D a t as he e t , V e rs io n 2 .

9, 25 M a r 20 1 3

®
CoolSET -F3
( J i tte r Ve r s i on )
I CE3 B0 3 65 J
I CE3 B0 5 65 J
I CE3 B1 5 65 J
I CE3 B2 0 65 J

O f f - Li ne S M P S C ur re nt Mo de
C on t ro ll er w it h in t e gr at e d 6 50 V
C oo lM O S ® a nd S t a rt u p c e l l
(f r eq ue nc y j it t er Mo de ) in D I P - 8

Po we r M a n ag e m e n t & Su p p ly

N e v e r s t o p t h i n k i n g .
CoolSET®-F3
ICE3Bxx65J
Revision History: 2013-03-25 Datasheet Version 2.9
Previous Version: 2.8
Page Subjects (major changes since last revision)
Revised typo (F3)
15 Revised max. limit for VFB, V SOFTS and V CS.

For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or
the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://
www.infineon.com

CoolMOS ®, CoolSET® are trademarks of Infineon Technologies AG.

Edition 2013-03-25
Published by
Infineon Technologies AG,
81726 Munich, Germany,
© 2013 Infineon Technologies AG.
All Rights Reserved.

Legal disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.

Information
For further information on technology, delivery terms and conditions and prices, please contact your nearest
Infineon Technologies Office (www.infineon.com).

Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
 CoolSET®-F3
ICE3Bxx65J

Off-Line SMPS Current Mode Controller with

integrated 650V CoolMOS® and Startup cell
(frequency jitter Mode) in DIP-8
Product Highlights
• Active Burst Mode to reach the lowest Standby Power
Requirements < 100mW
• Adjustable Blanking Window for High Load Jumps to PG-DIP-8
increase Reliability
• Frequency Jittering for Low EMI
• Pb-free lead plating, RoHS compilant
Features Description
• 650V Avalanche Rugged CoolMOS ® with built in The CoolSET®-F3(Jitter version) meets the requirements
switchable Startup Cell for Off-Line Battery Adapters and low cost SMPS for the
• Active Burst Mode for lowest Standby Power lower power range. By use of a BiCMOS technology a wide
@ light load controlled by Feedback Signal VCC range up to 26V is provided. This covers the changes
• Fast Load Jump Response in Active Burst Mode in the auxiliary supply voltage if a CV/CC regulation is
• 67 kHz fixed Switching Frequency implemented on the secondary side. Furthermore an Active
• Auto Restart Mode for Over temperature Burst Mode is integrated to fullfill the lowest Standby Power
Detection Requirements <100mW at no load and Vin = 270VAC. As
• Auto Restart Mode for Overvoltage Detection during Active Burst Mode the controller is always active
• Auto Restart Mode for Overload and Open Loop there is an immediate response on load jumps possible
• Auto Restart Mode for VCC Undervoltage without any black out in the SMPS. In Active Burst Mode
• User defined Soft Start the ripple of the output voltage can be reduced <1%.
• Minimum of external Components required Furthermore Auto Restart Mode is entered in case of
• Max Duty Cycle 75% Overtemperature, VCC Overvoltage, Output Open loop or
• Overall Tolerance of Current Limiting < ±5% Overload and VCC Undervoltage. By means of the internal
• Internal Leading Edge Blanking precise peak current limitation, the dimension of the
• BiCMOS technology provides wide VCC Range transformer and the secondary diode can be lowered which
• Frequency Jittering for Low EMI leads to more cost efficiency.

Typical Application
+

Snubber
Converter
C Bulk DC Output
85 ... 270 VAC
-

C VCC
VCC Drain
Startup Cell
Power M anagement

PWM Controller
Current Mode
CS
P recise Low Tolerance Peak
Current Limitation Depl. CoolMOS™ R Sense

FB
Active Burst Mode
GND C ontrol
U nit SoftS
Auto Restart Mode
CoolSET™ -F3 C SoftS
(Jitter Version)

Type Package Marking VDS FOSC RDSon1) 230VAC ±15% 2) 85-265 VAC2)
ICE3B0365J PG-DIP-8 ICE3B0365J 650V 67kHz 6.45W 22W 10W
ICE3B0565J PG-DIP-8 ICE3B0565J 650V 67kHz 4.70W 25W 12W
ICE3B1565J PG-DIP-8 ICE3B1565J 650V 67kHz 1.70W 42W 20W
ICE3B2065J PG-DIP-8 ICE3B2065J 650V 67kHz 0.92W 57W 28W
1)
typ @ T=25°C
2)
Calculated maximum input power rating at T a=75°C, Tj=125°C and without copper area as heat sink
Version 2.9 3 25 Mar 2013
 CoolSET®-F3
ICE3Bxx65J

Table of Contents Page

1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 Pin Configuration with PG-DIP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.3 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.4 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4.2 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.5 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.5.1 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.5.2 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.6.1 Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.6.2 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.6.2.1 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.6.2.2 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.6.2.3 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.6.3 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.3.1 Auto Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3.1 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3.2 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.3 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.4 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.5 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3.6 CoolMOS® Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5 Temperature derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
8 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .26

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 CoolSET®-F3
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1 Pin Configuration and Functionality

1.1 Pin Configuration with PG-DIP-8 1.2 Pin Functionality
SoftS (Soft Start, Auto Restart & Frequency
Jittering Control)
Pin Symbol Function The SoftS pin combines the function of Soft Start
during Start Up and error detection for Auto Restart
1 SoftS Soft-Start Mode. These functions are implemented and can be
2 FB Feedback adjusted by means of an external capacitor at SoftS to
ground. This capacitor also provides an adjustable
3 CS Current Sense/ blanking window for high load jumps, before the IC
650V1) CoolMOS® Source enters into Auto Restart Mode. Furthermore this pin is
also used to control the period of frequency jittering
4 Drain 650V1) CoolMOS® Drain during normal load.
5 Drain 650V1) CoolMOS® Drain
FB (Feedback)
6 N.C. Not Connected
The information about the regulation is provided by the
7 VCC Controller Supply Voltage FB Pin to the internal Protection Unit and to the internal
8 GND Controller Ground PWM-Comparator to control the duty cycle. The FB-
Signal controls in case of light load the Active Burst
1) Mode of the controller.
at Tj = 110°C

CS (Current Sense)
The Current Sense pin senses the voltage developed
on the series resistor inserted in the source of the
Package PG-DIP-8 integrated CoolMOS®. If CS reaches the internal
threshold of the Current Limit Comparator, the Driver
output is immediately switched off. Furthermore the
current information is provided for the PWM-
SoftS 1 8 GND Comparator to realize the Current Mode.

Drain (Drain of integrated CoolMOS®)

Pin Drain is the connection to the Drain of the internal
FB 2 7 VCC CoolMOSTM.

VCC (Power supply)

CS 3 6 N.C The VCC pin is the positive supply of the IC. The
operating range is between 10.3V and 26V.

GND (Ground)
Drain 4 5 Drain The GND pin is the ground of the controller.

Figure 1 Pin Configuration PG-DIP-8(top view)

Note: Pin 4 and 5 are shorted within the DIP
package.

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 CoolSET®-F3
ICE3Bxx65J

2 Representative Blockdiagram

Figure 2 Representative Blockdiagram

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 CoolSET®-F3
ICE3Bxx65J

3 Functional Description
All values which are used in the functional description 3.2 Power Management
are typical values. For calculating the worst cases the
min/max values which can be found in section 4
Electrical Characteristics have to be considered.
Drain VCC

3.1 Introduction Startup Cell

®
CoolSET -F3 Jitter version is the further development
of the CoolSET®-F2 to meet the requirements for the
lowest Standby Power at minimum load and no load
conditions. A new fully integrated Standby Power
concept is implemented into the IC in order to keep the Power Management
application design easy. Compared to CoolSET®-F2 no
further external parts are needed to achieve the lowest Undervoltage Lockout
Internal Bias
Standby Power. An intelligent Active Burst Mode is 18V
used for this Standby Mode. After entering this mode
10.3
there is still a full control of the power conversion by the
secondary side via the same optocoupler that is used
for the normal PWM control. The response on load
jumps is optimized. The voltage ripple on Vout is 5V
minimized. Vout is further on well controlled in this Voltage
Power-Down Reset Reference
mode.
The usually external connected RC-filter in the
feedback line after the optocoupler is integrated in the
IC to reduce the external part count. Auto Restart
Mode
Furthermore a high voltage Startup Cell is integrated
into the IC which is switched off once the Undervoltage Active Burst
Lockout on-threshold of 18V is exceeded. This Startup T1 Mode
Cell is part of the integrated CoolMOS ®. The external
startup resistor is no longer necessary as this Startup
Cell is connected to the Drain. Power losses are
therefore reduced. This increases the efficiency under
light load conditions drastically.
SoftS
The Soft-Start capacitor is also used for providing an
adjustable blanking window for high load jumps. During
this time window the overload detection is disabled. Figure 3 Power Management
With this concept no further external components are The Undervoltage Lockout monitors the external
necessary to adjust the blanking window. supply voltage VVCC . When the SMPS is plugged to the
An Auto Restart Mode is implemented in the IC to main line the internal Startup Cell is biased and starts
reduce the average power conversion in the event of to charge the external capacitor CVCC which is
malfunction or unsafe operating condition in the SMPS connected to the VCC pin. The VCC charge current
system. This feature increases the system’s that is provided by the Startup Cell from the Drain pin is
robustness and safety which would otherwise lead to a 1.05mA. When VVCC exceeds the on-threshold
destruction of the SMPS. Once the malfunction is VCCon=18V, bias circuit is switched on. Then the
removed, normal operation is automatically initiated Startup Cell is switched off by the Undervoltage
after the next Start Up Phase. Lockout and therefore no power losses present due to
The internal precise peak current limitation reduces the the connection of the Startup Cell to the Drain voltage.
costs for the transformer and the secondary diode. The To avoid uncontrolled ringing at switch-on a hysteresis
influence of the change in the input voltage on the is implemented. The switch-off of the controller can
power limitation can be avoided together with the only take place after active mode was entered and
integrated Propagation Delay Compensation. VVCC falls below 10.3V.
Therefore the maximum power is nearly independent The maximum current consumption before the
on the input voltage which is required for wide range controller is activated is about 300uA.
SMPS. There is no need for an extra over-sizing of the
SMPS, e.g. the transformer or the secondary diode.

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 CoolSET®-F3
ICE3Bxx65J

When V VCC falls below the off-threshold VCCoff=10.3V resistor RSoftS determines the duty cycle until V SoftS
the bias circuit is switched off and the Power Down exceeds 3.1V.
reset let T1 discharging the soft-start capacitor C SoftS at When the Soft Start begins, CSoftS is immediately
pin SoftS. Thus it is ensured that at every startup cycle charged up to approx. 0.8V by T2. Therefore the Soft
the voltage ramp at pin SoftS starts at zero. Start Phase takes place between 0.8V and 3.1V.
The bias circuit is switched off if Auto Restart Mode is Above VSoftsS = 3.1V there is no longer duty cycle
entered. The current consumption is then reduced to limitation DCmax which is controlled by comparator C7
300uA. since comparator C2 blocks the gate G7 (see Figure
Once the malfunction condition is removed, this block 5).This maximum charge current in the very first stage
will then turn back on. The recovery from Auto Restart when VSoftS is below 0.8V, is limited to 0.9mA.
Mode does not require disconnecting the SMPS from
the AC line.
When Active Burst Mode is entered, some internal Bias VSoftS
is switched off in order to reduce the current
consumption to about 500uA while keeping a max. Startup Phase
comparator (which trigger if VFB has exceeded 3.61V) 4.0V
and the Soft Start capacitor clamped at 3.0 V as this is 3.1V
necessary in this mode.

0.8V
max. Soft Start Phase
3.3 Startup Phase

DCmax t
3.25k
5V
RSoftS
DC1
DC2

Freq Jitter T2
Charging T3
SoftS current IFJ
0.8V
Freq Jitter
t1 t2 t
Discharging
CSoftS current IFJ Freq Jitter Figure 5 Startup Phase
Control
By means of this extra charge stage, there is no delay
Soft Start in the beginning of the Startup Phase when there is still
Soft-Start
Comparator
no switching. Furthermore Soft Start is finished at 3.1V
to have faster the maximum power capability. The duty
Gate Driver
C7 & cycles DC1 and DC2 are depending on the mains and
the primary inductance of the transformer. The
G7
limitation of the primary current by DC2 is related to
VSoftS = 3.1V. But DC1 is related to a maximum primary
C2 current which is limited by the internal Current Limiting
3.1V with CS = 1V. Therefore the maximum Startup Phase
PWM OP
is divided into a Soft Start Phase until t1 and a phase
from t1 until t2 where maximum power is provided if
x3.2 CS demanded by the FB signal.
0.6V

Figure 4 Soft Start

At the beginning of the Startup Phase, the IC provides
a Soft Start duration whereby it controls the maximum
primary current by means of a duty cycle limitation. A
capacitor CSofts in combination with the internal pull up

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 CoolSET®-F3
ICE3Bxx65J

3.4 PWM Section 3.4.2 PWM-Latch FF1

The oscillator clock output provides a set pulse to the
PWM-Latch when initiating the internal CoolMOS®
0.75 PWM Section conduction. After setting the PWM-Latch can be reset
Oscillator by the PWM comparator, the Soft Start comparator or
the Current-Limit comparator. In case of resetting the
Duty driver is shut down immediately.
Cycle
max 3.4.3 Gate Driver
Clock The Gate Driver is a fast totem pole gate drive which is
designed to avoid cross conduction currents.
Frequency
Jitter The Gate Driver is active low at voltages below the
undervoltage lockout threshold VVCCoff.
Soft Start FF1
Comparator Gate Driver
1 S
R &
PWM G8 Q
Comparator G9 VCC

Current
Limiting PWM-Latch
1

SoftS Gate Gate

Depl. CoolMOS™

Figure 6 PWM Section

3.4.1 Oscillator and Jittering

Gate Driver
The oscillator generates a fixed frequency with
frequency jittering of ±4% from the fixed frequency
(which is ±2.7kHz from 67kHz) at a jittering period TFJ.
The switching frequency is fswitch = 67kHz. Figure 7 Gate Driver
A resistor, a capacitor and a current source and current
sink which determine the frequency are integrated. The
charging and discharging current of the implemented
oscillator capacitor are internally trimmed, in order to
achieve a very accurate switching frequency. The ratio
of controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of D max=0.75.
Once the Soft Start period is over and when the IC goes
into normal mode, the Soft Start capacitor will be
charged and discharged through internal current
source, IFJ to generate a triangular waveform with a
jittering period TFJ which is externally adjustable by the
Soft Start capacitor, CSoftS (See Figure 4).

TFJ = kFJ * CSoftS

where kFJ is a constant = 4 ms/uF

eg. TFJ = 4 ms if CSoftS = 1uF

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 CoolSET®-F3
ICE3Bxx65J

3.5 Current Limiting 3.5.1 Leading Edge Blanking

VSense
PWM Latch
FF1 Vcsth
tLEB = 220ns
Current Limiting

Propagation-Delay
Compensation t
Figure 9 Leading Edge Blanking
Vcsth
C10 Leading Each time when the integrated internal CoolMOS® is
Edge switched on a leading edge spike is generated due to
Blanking the primary-side capacitances and secondary-side
PWM-OP 220ns rectifier reverse recovery time. This spike can cause
& the gate drive to switch off unintentionally. To avoid a
G10 C12 premature termination of the switching pulse, this spike
0.32V is blanked out with a time constant of tLEB = 220ns.
During this time, the gate drive will not be switched off.
10k 1pF
Active Burst D1 3.5.2 Propagation Delay Compensation
Mode
In case of overcurrent detection, the switch-off of the
integrated internal CoolMOS® is delayed due to the
propagation delay of the circuit. This delay causes an
CS
overshoot of the peak current Ipeak which depends on
the ratio of dI/dt of the peak current (see Figure 10).
Figure 8 Current Limiting
There is a cycle by cycle Current Limiting realized by Signal2 Signal1
the Current-Limit comparator C10 to provide an ISense tPropagation Delay
overcurrent detection. The source current of the
Ipeak2 IOvershoot2
integrated CoolMOS ® is sensed via an external sense
resistor RSense . By means of RSense the source current Ipeak1
is transformed to a sense voltage V Sense which is fed ILimit
into the pin CS. If the voltage VSense exceeds the
internal threshold voltage V csth the comparator C10 IOvershoot1
immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation
is added to support the immediate shut down without
delay of the integrated internal CoolMOS ® in case of
Current Limiting. The influence of the AC input voltage t
on the maximum output power can thereby be avoided.
Figure 10 Current Limiting
To prevent the Current Limiting from distortions caused
by leading edge spikes a Leading Edge Blanking is The overshoot of Signal2 is bigger than of Signal1 due
integrated in the current sense path for the to the steeper rising waveform. This change in the
comparators C10, C12 and the PWM-OP. slope is depending on the AC input voltage.
The output of comparator C12 is activated by the Gate Propagation Delay Compensation is integrated to limit
G10 if Active Burst Mode is entered. Once activated the the overshoot dependency on dI/dt of the rising primary
current limiting is thereby reduced to 0.32V. This current. That means the propagation delay time
voltage level determines the power level when the between exceeding the current sense threshold Vcsth
Active Burst Mode is left if there is a higher power and the switch off of the integrated inernal CoolMOS®
demand. is compensated over temperature within a wide range.

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 CoolSET®-F3
ICE3Bxx65J

Current Limiting is now possible in a very accurate way. 3.6 Control Unit
E.g. Ipeak = 0.5A with RSense = 2. Without Propagation
Delay Compensation the current sense threshold is set The Control Unit contains the functions for Active Burst
to a static voltage level V csth=1V. A current ramp of Mode and Auto Restart Mode. The Active Burst Mode
dI/dt = 0.4A/µs, that means dV Sense/dt = 0.8V/µs, and a and the Auto Restart Mode are combined with an
propagation delay time of i.e. tPropagation Delay =180ns Adjustable Blanking Window which is depending on the
leads then to an Ipeak overshoot of 14.4%. By means of external Soft Start capacitor. By means of this
propagation delay compensation the overshoot is only Adjustable Blanking Window, the IC avoids entering
about 2% (see Figure 11). into these two modes accidentally. Furthermore it also
provides a certain time whereby the overload detection
is delayed. This delay is useful for applications which
with compensation without compensation normally works with a low current and occasionally
require a short duration of high current.
V
1,3

1,25
3.6.1 Adjustable Blanking Window
1,2
VSense

1,15

1,1

1,05
SoftS
5V
1 S3 RSoftS
0,95

0,9
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 V Frequency
dVSense s S2 Jitter
3.0V
dt
S1
Figure 11 Overcurrent Shutdown
The Propagation Delay Compensation is realized by
means of a dynamic threshold voltage V csth (see Figure
12). In case of a steeper slope the switch off of the
driver is earlier to compensate the delay. C3
4.0V
VOSC max. Duty Cycle
& Auto
4.5V
Restart
C4 Mode
G5

off time
Active
Burst
Mode
VSense Propagation Delay t
&
Vcsth FB
G6
C5
1.35V
Control Unit

Signal1 Signal2
t
Figure 13 Adjustable Blanking Window

Figure 12 Dynamic Voltage Threshold V csth VSoftS swings between 3.2V and 3.6V after the SMPS is
settled and S2 is on while S3 is off, this is due to the
frequency jittering function that is making use of the
Soft Start pin. If overload occurs VFB is exceeding 4.5V.
Auto Restart Mode can’t be entered as the gate G5 is
still blocked by the comparator C3. But after VFB has

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 CoolSET®-F3
ICE3Bxx65J

exceeded 4.5V the switch S2 is opened and S3 is The Active Burst Mode is located in the Control Unit.
closed. The external Soft Start capacitor can now be Figure 14 shows the related components.
charged further by the integrated pull up resistor R SoftS
via switch S3. The comparator C3 releases the gates 3.6.2.1 Entering Active Burst Mode
G5 and G6 once V Softs has exceeded 4.0V. Therefore The FB signal is always observed by the comparator
there is no entering of Auto Restart Mode possible C5 if the voltage level falls below 1.35V. In that case the
during this charging time of the external capacitor switch S1 and S2 is released which allows the
CSoftS. The same procedure happens to the external capacitor CSoftS to be charged via S3 starting from the
Soft Start capacitor if a low load condition is detected swinging voltage level between 3.2V and 3.6V in
by comparator C5 when VFB is falling below 1.35V. normal operating mode. If VSoftS exceeds 4.0V the
Only after V SoftS has exceeded 4.0V and V FB is still comparator C3 releases the gate G6 to enter the Active
below 1.35V Active Burst Mode is entered. Burst Mode. The time window that is generated by
combining the FB and SoftS signals with gate G6
3.6.2 Active Burst Mode avoids a sudden entering of the Active Burst Mode due
The controller provides Active Burst Mode for low load to large load jumps. This time window can be adjusted
conditions at V OUT. Active Burst Mode increases by the external capacitor CSoftS.
significantly the efficiency at light load conditions while After entering Active Burst Mode a burst flag is set and
supporting a low ripple on V OUT and fast response on the internal bias is switched off in order to reduce the
load jumps. During Active Burst Mode which is current consumption of the IC down to approx. 500uA.
controlled only by the FB signal the IC is always active Also, switch S1 is closed to clamped the Soft Start
and can therefore immediately response on fast voltage to 3.0V. In this Off State Phase the IC is no
changes at the FB signal. The Startup Cell is kept longer self supplied so that therefore CVCC has to
switched off to avoid increased power losses for the provide the VCC current (see Figure 15). Furthermore
self supply. gate G11 is then released to start the next burst cycle
once VFB has 3.0V exceeded.
It has to be ensured by the application that the VCC
SoftS
remains above the Undervoltage Lockout Level of
5V
S3 10.3V to avoid that the Startup Cell is accidentally
RSoftS
switched on. Otherwise power losses are significantly
increased. The minimum VCC level during Active Burst
Frequency
Jitter
Mode is depending on the load conditions and the
3.0V S2 application. The lowest VCC level is reached at no load
conditions at VOUT .
S1 Internal Bias
3.6.2.2 Working in Active Burst Mode
After entering the Active Burst Mode the FB voltage
Current
rises as VOUT starts to decrease due to the inactive
Limiting
PWM section. Comparator C6a observes the FB signal
C3 &
if the voltage level 3.61V is exceeded. In that case the
4.0V G10
internal circuit is again activated by the internal Bias to
4.5V start with switching. As now in Active Burst Mode the
C4
gate G10 is released the current limit is only 0.32V to
reduce the conduction losses and to avoid audible
noise. If the load at VOUT is still below the starting level
Active
for the Active Burst Mode the FB signal decreases
Burst
FB C5 & Mode down to 3.0V. At this level C6b deactivates again the
1.35V G6
internal circuit by switching off the internal Bias. The
gate G11 is released as after entering Active Burst
Mode the burst flag is set. If working in Active Burst
C6a Mode the FB voltage is changing like a saw tooth
3.61V between 3.0V and 3.61V (see figure 15).

& 3.6.2.3 Leaving Active Burst Mode

C6b G11 The FB voltage immediately increases if there is a high
3.0V load jump. This is observed by comparator C4. As the
Control Unit
current limit is ca. 32% during Active Burst Mode a
certain load jump is needed that FB can exceed 4.5V.
Figure 14 Active Burst Mode At this time C4 resets the Active Burst Mode which also

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blocks C12 by the gate G10. Maximum current can now 3.6.3 Protection Modes
be provided to stabilize V OUT. The IC provides several protection features that
increase the SMPS system’s robustness and safety.
The following table shows the possible system failures
and the corresponding protection modes.
VFB Entering Leaving
Active Burst Active Burst
Mode Mode VCC Overvoltage Auto Restart Mode I
4.5V
3.61V Over temperature Auto Restart Mode I
3.0V
Overload Auto Restart Mode II
1.35V
Open Loop Auto Restart Mode II
VSoftS t VCC Undervoltage Auto Restart Mode II
Blanking Window Short Optocoupler Auto Restart Mode II

4.0V
3.6V~ 3.6.3.1 Auto Restart Mode I
3.2V
3.0V

VCS t SoftS

Current limit level

1.0V C3
during Active Burst
Mode 4.0V Auto
0.32V
Restart
Mode
S
VVCC t &
R Q
UVLO G13
FF2
Spike
Blanking
8.0us
VCC
10.3V C13 &
20.5V
IVCC t
G12
Internal
C4
2mA Bias
4.5V
Thermal Shutdown
500uA Tj >140°C
Control Unit
VOUT t
Max. Ripple < 1%
FB

Figure 16 Auto Restart Mode I

The VCC voltage is observed by comparator C13 if
20.5V is exceeded. The output of C13 is combined with
both the output of C3 which checks for VSoftS < 4.0V and
the output of C4 which checks for VFB > 4.5V. Therefore
t the overvoltage detection can only be active during Soft
Start Phase (VSoftS < 4.0V) and when FB signal is
outside the operating range > 4.5V. This means any
Figure 15 Signals in Active Burst Mode

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small voltage overshoots of VVCC during normal This charging of the Soft Start capacitor from
operating cannot trigger the Auto Restart Mode I. 3.2V~3.6V to 4.0V defines a blanking window which
In Order to ensure system reliability and prevent any prevents the system from entering into Auto Restart
false activation, a blanking time is implemented before Mode II unintentionally during large load jumps. In this
the IC can enter into the Auto Restart Mode I. The event, FB will rise close to 5.0V for a short duration
output of the VCC overvoltage detection is fed into a before the loop regulates with FB less than 4.5V. This
spike blanking with a time constant of 8.0us. is the same blanking time window as for the Active
Burst Mode and can therefore be adjusted by the
The other fault detection which can result in the Auto
external CSoftS.
Restart Mode I and has this 8.0us blanking time is the
Overtemperature detection. This block checks for a In case of VCC undervoltage, ie. VCC falls below
junction temperature of higher than 140°C for 10.3V, the IC will be turned off with the Startup Cell
malfunction operation. charging VCC as described earlier in this section. Once
VCC is charged above 18V, the IC will start a new
Once Auto Restart Mode is entered, the internal bias is
startup cycle. The same procedure applies when the
switched off in order to reduce the current consumption
system is under Short Optocoupler fault condition, as it
of the IC as much as possible. In this mode, the
will lead to VCC undervoltage.
average current consumption is only 300uA as the only
working blocks are the reference block and the
Undervoltage Lockout(UVLO) which controls the
Startup Cell by switching on/off at V VCCon/VVCCoff.
As there is no longer a self supply by the auxiliary
winding, VCC starts to drop. The UVLO switches on the
integrated Startup Cell when VCC falls below 10.3V. It
will continue to charge VCC up to 18V whereby it is
switched off again and the IC enters into the Start Up
Phase.
As long as all fault conditions have been removed, the
IC will automatically power up as usual with switching
cycle at the GATE output after Soft Start duration. Thus
the name Auto Restart Mode.

3.6.3.2 Auto Restart Mode II

Internal
SoftS Bias

C3
4.0V

Auto
4.5V &
Restart
C4 Mode
G5
FB
Control Unit

Figure 17 Auto Restart Mode II

In case of Overload or Open Loop, FB exceeds 4.5V
which will be observed by C4. At this time, the external
Soft Start capacitor can now be charged further by the
integrated pull up resistor R SoftS via switch S3 (see
Figure 13). If V SoftS exceeds 4.0V which is observed by
C3, Auto Restart Mode II is entered as both inputs of
the gate G5 are high.

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4 Electrical Characteristics
Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are
not violated.

4.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7
(VCC) is discharged before assembling the application circuit.

Parameter Symbol Limit Values Unit Remarks

min. max.
Drain Source Voltage VDS - 650 V Tj = 110°C
Pulse drain current, ICE3B0365J ID_Puls1 - 1.6 A
tp limited by max.
ICE3B0565J ID_Puls2 - 2.3 A
Tj=150°C
ICE3B1565J ID_Puls3 - 6.1 A
ICE3B2065J ID_Puls4 - 10.3 A
Avalanche energy, ICE3B0365J EAR1 - 0.005 mJ
repetitive tAR limited
ICE3B0565J EAR2 - 0.01 mJ
by max. Tj=150°C1)
ICE3B1565J EAR3 - 0.15 mJ
ICE3B2065J EAR4 - 0.4 mJ
Avalanche current, ICE3B0365J IAR1 - 0.3 A
repetitive tAR limited
ICE3B0565J IAR2 - 0.5 A
by max. Tj=150°C1)
ICE3B1565J IAR3 - 1.5 A
ICE3B2065J IAR4 - 2.0 A
VCC Supply Voltage VVCC -0.3 27 V
FB Voltage VFB -0.3 5.5 V
SoftS Voltage VSoftS -0.3 5.5 V
CS Voltage VCS -0.3 5.5 V
Junction Temperature Tj -40 150 °C Controller & CoolMOS®
Storage Temperature TS -55 150 °C
Thermal Resistance RthJA - 90 K/W PG-DIP-8
Junction-Ambient
ESD Capability VESD - 2 kV Human body model2)
1)
Repetetive avalanche causes additional power losses that can be calculated as PAV=EAR* f
2)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kW series resistor)

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4.2 Operating Range

Note: Within the operating range the IC operates as described in the functional description.

Parameter Symbol Limit Values Unit Remarks

min. max.
VCC Supply Voltage VVCC V VCCoff 26 V
Junction Temperature of Controller TjCon -25 130 °C Max value limited due to
integrated thermal shut down
Junction Temperature of TJCoolMOS -25 150 °C
CoolMOS ®

4.3 Characteristics

4.3.1 Supply Section

Note: The electrical characteristics involve the spread of values guaranteed within the specified supply voltage
and junction temperature range TJ from – 25 oC to 130 oC. Typical values represent the median values,
which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Start Up Current IVCCstart - 300 450 mA V VCC = 17V
VCC Charge Current IVCCcharge1 - - 5.0 mA V VCC = 0V
IVCCcharge2 0.55 1.05 1.60 mA V VCC = 1V
IVCCcharge3 - 0.88 - mA V VCC = 17V
Leakage Current of IStartLeak - 0.2 50 mA V Drain= 450V
Start Up Cell & CoolMOS at T j = 100°C
Supply ICE3B0365J IVCCsup_ng1 - 1.7 2.5 mA Soft Start pin is open
Current with ICE3B0565J
Inactive Gate ICE3B1565J
ICE3B2065J IVCCsup_ng2 - 3.3 4.2 mA
Supply Current with Active Gate IVCCsup_g - 2.5 3.6 mA V SoftS = 3.0V
IFB = 0
Supply Current in IVCCrestart - 300 - mA IFB = 0
Auto Restart Mode ISofts = 0
with Inactive Gate
Supply Current in IVCCburst1 - 500 950 uA V FB = 2.5V
Active Burst Mode V SoftS = 3.0V
with Inactive Gate
IVCCburst2 - 500 950 uA V VCC = 11.5V
V FB = 2.5V
V SoftS = 3.0V
VCC Turn-On Threshold VVCCon 17.0 18.0 19.0 V
VCC Turn-Off Threshold VVCCoff 9.6 10.3 11.0 V
VCC Turn-On/Off Hysteresis VVCChys - 7.7 - V

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4.3.2 Internal Voltage Reference

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Trimmed Reference Voltage VREF 4.90 5.00 5.10 V measured at pin FB
IFB = 0

4.3.3 PWM Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Fixed Oscillator Frequency fOSC3 58 67 76 kHz
fOSC4 62 67 74.5 kHz Tj = 25°C
Frequency Jittering Range fdelta - ±2.7 - kHz Tj = 25°C
Max. Duty Cycle Dmax 0.70 0.75 0.80
Min. Duty Cycle Dmin 0 - - V FB < 0.3V
PWM-OP Gain AV 3.0 3.2 3.4
Max. Level of Voltage Ramp VMax-Ramp - 0.6 - V
VFB Operating Range Min Level VFBmin - 0.5 - V
VFB Operating Range Max level VFBmax - - 4.3 V CS=1V limited by
Comparator C41)
Feedback Pull-Up Resistor RFB 9 14 22 kW
Soft-Start Pull-Up Resistor RSoftS 30 45 62 kW
1)
This parameter is not subject to production test - verified by design/characterization

4.3.4 Control Unit

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Deactivation Level for SoftS VSoftSC2 2.98 3.10 3.22 V V FB = 5V
Comparator C7 by C2
Clamped V SoftS Voltage during VSoftSclmp_bm 2.88 3.00 3.12 V
Burst Mode
Activation Limit of VSoftSC3 3.85 4.00 4.15 V V FB = 5V
Comparator C3
SoftS Startup Current ISoftSstart - 0.9 - mA V SoftS = 0V
Over Load & Open Loop VFBC4 4.33 4.50 4.67 V V SoftS = 4.5V
Detection Limit for
Comparator C4
Active Burst Mode Level for VFBC5 1.23 1.35 1.43 V V SoftS = 4.5V
Comparator C5
Active Burst Mode Level for VFBC6a 3.48 3.61 3.76 V After Active Burst
Comparator C6a Mode is entered

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Active Burst Mode Level for VFBC6b 2.88 3.00 3.12 V After Active Burst
Comparator C6b Mode is entered
Overvoltage Detection Limit VVCCOVP 19.5 20.5 21.5 V V FB = 5V, VSoftS = 3V
1)
Thermal Shutdown TjSD 130 140 150 °C
Spike Blanking tSpike - 8.0 - ms
1)
The parameter is not subject to production test - verified by design/characterization

Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP

4.3.5 Current Limiting

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Peak Current Limitation (incl. Vcsth 1.01 1.06 1.11 V dVsense / dt = 0.6V/ms
Propagation Delay Time)
(see Figure 11)
Peak Current Limitation during VCS2 0.27 0.32 0.37 V
Active Burst Mode
Leading Edge Blanking tLEB - 220 - ns V SoftS = 3.0V
CS Input Bias Current ICSbias -1.0 -0.2 0 µA V CS = 0V

4.3.6 CoolMOS® Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Drain Source Breakdown V(BR)DSS 600 - - V Tj = 25°C
Voltage 650 - - V Tj = 110°C
Drain Source ICE3B0365J RDSon1 - 6.45 7.50 W Tj = 25°C
On-Resistance - 13.70 17.00 W Tj = 125°C1)
at ID = 0.3A
ICE3B0565J RDSon2 - 4.70 5.44 W Tj = 25°C
- 10.00 12.50 W Tj = 125°C1)
at ID = 0.5A
ICE3B1565J RDSon3 - 1.70 1.96 W Tj = 25°C
- 3.57 4.12 W Tj = 125°C1)
at ID = 1.5A
ICE3B2065J RDSon4 - 0.92 1.05 W Tj = 25°C
- 1.93 2.22 W Tj = 125°C1)
at ID = 2.0A
Effective output ICE3B0365J Co(er)1 - 3.65 - pF V DS = 0V to 480V
capacitance,
energy related ICE3B0565J Co(er)2 - 4.75 - pF
ICE3B1565J Co(er)3 - 11.63 - pF
ICE3B2065J Co(er)4 - 21 - pF

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Rise Time trise - 302) - ns

Fall Time tfall - 302) - ns
1)
The parameter is not subject to production test - verified by design/characterization
2)
Measured in a Typical Flyback Converter Application

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5 Temperature derating curve

Figure 18 Safe Operating area ( SOA ) curve for ICE3B0365J

Figure 19 Safe Operating area ( SOA ) curve for ICE3B0565J

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Figure 20 Safe Operating area ( SOA ) curve for ICE3B1565J

Figure 21 Safe Operating area ( SOA ) curve for ICE3B2065J

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Figure 22 SOA temperature derating coefficient curve

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6 Outline Dimension

PG-DIP-8
(Plastic Dual In-Line Outline)

Figure 23 PG-DIP-8 ( Pb-free lead plating Platic Dual-in-Line Outline )

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7 Marking

Marking

Figure 24 Marking for ICE3B0365J

Marking

Figure 25 Marking for ICE3B0565J

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Marking

Figure 26 Marking for ICE3B1565J

Marking

Figure 27 Marking for ICE3B2065J

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Schematic for recommended PCB layout

8 Schematic for recommended PCB layout

Figure 28 Schematic for recommended PCB layout

General guideline for PCB layout design using F3 CoolSET (refer to Figure 26):
1. “Star Ground “at bulk capacitor ground, C11:
“Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11
separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device
effectively. The primary DC grounds include the followings.
a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.
b. DC ground of the current sense resistor, R12
c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of
IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground.
d. DC ground from bridge rectifier, BR1
e. DC ground from the bridging Y-capacitor, C4
2. High voltage traces clearance:
High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.
a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm
b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm
3. Filter capacitor close to the controller ground:
Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin
as possible so as to reduce the switching noise coupled into the controller.

Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 26):
1. Add spark gap
Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated
charge during surge test through the sharp point of the saw-tooth plate.
a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:
Gap separation is around 1.5mm (no safety concern)

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Schematic for recommended PCB layout

b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:

These 2 Spark Gaps can be used when the lightning surge requirement is >6KV.
230Vac input voltage application, the gap separation is around 5.5mm
115Vac input voltage application, the gap separation is around 3mm
2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input
3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:
The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET and
reduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148.
The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the
sensitive components such as the primary controller, IC11.

Version 2.9 27 25 Mar 2013

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