Objective: "CMOS 0.25 Micron Technology Inverter Characteristics and Layout in Microwind"

Lab#03
“CMOS 0.25 micron Technology Inverter Characteristics and

Layout in Microwind”
Student Name: M.Sharjeel Arif Roll No: 17ES24
Lab Instructor Signatures: Date:
1. Objective
In this lab students will design and implement a CMOS Inverter. Different design
Parameter’s effects like transistor sizing, supply voltages etc well be analyzed and delay,
area, power and currents will be observed. This lab assumed that students are familiar
with MicroWind and Lambda based design rules. The tool used in this lab is MicroWind.
The goals for this Lab are:
• Design of CMOS Inverter and transistor sizing.
• Layout Design using the tool.
• Gate delay, area, power and current analysis and the effects of transistor sizing on these
parameters.
2. Theory
2.1 MOSFET
The Metal Oxide Semiconductor Field Effect Transistor is very important part of Digital
Integrated Circuits. It is mostly used as switch in digital design. MOSFET is a four
terminal device. The voltage applied to the gate terminal determine the current flow
between drain and source terminals. The body/substrate of the transistor is the fourth
terminal. Mostly the fourth terminal (body/substrate) of the device is connected to dc
supply that is identical for all devices of the same type (GND fro nMOS and Vdd for
pMOS). Usually this terminal is not shown on the schematics
2.2 nMOS
The nMOS transistor consists of n+ drain and source diffusion regions, which are
embedded in a p-type substrate. The electrons in the channel beneath the gate between
source and drain terminal are responsible for the current flow.
2.3 pMOS
The pMOS transistor consists of p+ drain and source diffusion regions, which are
embedded in an n-type substrate. The holes in the channel beneath the gate between
source and drain terminal are responsible for the current flow.
2.4 CMOS
CMOS Inverter/NOT gate is considered to be the heart of VLSI circuits, based on the
understanding of NOT gate we can extend it easily to NAND and NOR gates which are
VLSI Design
the basic building blocks of more complex circuits e.g. multipliers and microprocessors.
As per discussion and design on white board in the Lab, a NOT gate can be implemented
using two FETs i.e. a pFET and an nFET both connected in series, in which Vdd is
supplied to pFET and nFET is grounded, input x is applied to the gate terminals of both
and the output is obtained at node y.
3. Design/ Diagram/Circuit
Symbol, Truth Table and CMOS circuit of NOT Gate
VDD
X Y
X Y
X Y
0 1
1 0
Gnd
Figure 3.1 Inverter Symbol
4. Lab Instructions
a. Open MicroWind and select the foundry cmos025.

b. Save the design as “Save as” as “Lab04”, and save the design frequently during
the lab session.
c. Draw the layout of nMOS using MOS Generator
d. Draw the layout of pMOS using MOS Generator by setting the appropriate width
of pMOS
e. Connect the two transistors using Medal 1as per diagram.
f. Draw the rails of Vdd and Gnd above and below.
g. Connect the n well with Vdd.
h. Add input and output to your design.
i. Save the layout.
j. Apply design rule checker.
k. Simulate the design using run Command.
l. Analyze configuration delay, gate delay, current, power, and midpoint voltage.
m. Repeat the design for different values
VLSI Design
Figure 3.2 Inverter Symbol in MicroWind
Figure 3.3 Running the Simulation 1

VLSI Design

Task: Design the layout of CMOS NAND gate using the Microwind tool.
NAND Gate
As per discussion and design on white board in the Lab, a NAND gate can be
implemented using four FETS i.e. two pFETs and two nFETs as the inputs of the gate is
two. pFETs are connected in parallel while nFETs are connected in series, Vdd is
supplied to the parallel combination of pFETs while the series combination of nFETs is
grounded. Inputs a & b are applied to the gate terminals of all FETs, and the output f is
obtained from the common junction of these series and parallel combinations as
illustrated in NAND circuit under the heading of Design Diagram / Circuit.
Symbol, Truth Table and CMOS circuit of NAND Gate

Vdd
a a b f
f a b
b 0 0 1
0 1 1 f
1 0 1
1 1 0 a

Objective: "CMOS 0.25 Micron Technology Inverter Characteristics and Layout in Microwind"

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Lab#03

“CMOS 0.25 micron Technology Inverter Characteristics and

Lab Instructor Signatures: Date:

Symbol, Truth Table and CMOS circuit of NOT Gate

a. Open MicroWind and select the foundry cmos025.

Figure 3.2 Inverter Symbol in MicroWind

Figure 3.3 Running the Simulation 1

Figure 3.4 Running the Simulation 2

Figure 3.5 Running the Simulation 3

Symbol, Truth Table and CMOS circuit of NAND Gate

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