Lab#02

“Introduction to MicroWind and Analysis of MOSFETs and different gates

implementation”

Student Name: M. Sharjeel Arif Roll No: 17ES24

Lab Instructor Signatures: Date:

1. Objective

In this lab students will be introduced to a Layout based EDA tool “MicroWind” and
the introduction will be accompanied with analysis of MOS transistors. The tool used
in this lab is MicroWind. The goals for this Lab are:
 Familiarity and Hands on Example using the tool.
 Layout Design using the tool.
 Study of MOSFET Characteristics.
 Analog Simulation of MOSFETs.

2. Theory

2.1. MOSFET
The Metal Oxide Semiconductor Field Effect Transistor is very important part of Digital
Integrated Circuits. It is mostly used as switch in digital design. MOSFET is a four
terminal device. The voltage applied to the gate terminal determine the current flow
between drain and source terminals. The body/substrate of the transistor is the fourth
terminal. Mostly the fourth terminal (body/substrate) of the device is connected to dc
supply that is identical for all devices of the same type (GND fro nMOS and Vdd for
pMOS). Usually this terminal is not shown on the schematics.

2.2. nMOS
The nMOS transistor consists of n+ drain and source diffusion regions, which are
embedded in a p-type substrate. The electrons in the channel beneath the gate between
source and drain terminal are responsible for the current flow.

2.3. pMOS
The pMOS transistor consists of p+ drain and source diffusion regions, which are
embedded in an n-type substrate. The holes in the channel beneath the gate between
source and drain terminal are responsible for the current flow.

2.4. CMOS
The CMOS (Complementary MOS) consist of both p-type and n-type MOS. The
advantage of CMOS is its low power design due to its Static behavior.

3. Design/ Diagram/Circuit
VLSI Design 12

OUT

IN

GND

Figure 2.1 NMOS Symbol

4. Lab Instructions

a) Open the Microwind2 by double clicking it located in the installed directory of

dsch2-7

The following screen will be appeared

Figure 2.2 Main Window MicroWind

b) Select the foundry using the command File > Select Foundry
VLSI Design 13

Figure 2.3 Select Foundry Window in MicroWind

c) Select 0.25-micron process by selecting “cmos025.tec” file. Click Open tab to

continue.

Figure 2.4 Foundry Selection Window MicroWind

d) Save the design as “Lab02” using the command File > Save as.
e) Create an nMOS by using the nMOS generator button in the Palate
VLSI Design 14

Figure 2.4 Layout Generator MicroWind

You can set the width and length of MOS by typing in the fields Width MOS and
Length MOS either in micron or in lambda units as indicated in the above figure.

f) Click on Generate Device Tab to generate the device.

Figure 2.5 NMOS Symbol in MicroWind

g) Apply the voltages and output node using the symbol buttons Vdd, Gnd, Add a
Pulse, and Visible node in the Palate menu, as indicated in the following
figure. You can use the Stretch/Move command button for these actions.
VLSI Design 15

Figure 2.5 Applying Input to NMOS

h) Click on the Run Tab on the Tool bar menu to start the simulation or using the
command Simulate > Run Simulation.

Figure 2.6 Timing Diagram in MicroWind

i) Now apply the Vdd to the n+ diffusion or drain terminal instead of Vss, run the
Simulation again
VLSI Design 16

Figure 2.7 NMOS in MicroWind

Figure 2.8 Analysis of NMOS in MicroWind

Analyze the simulation waveform, use different values of voltages for Vdd by double
clicking on it and set the voltage level. Now we will make the above schematics.

j) Now increase the width of nMOS either by using the stretch command for the
previous layout, by generating again the nMOS with significantly (5 to 10 times
more) increased width, or by using manual layout from the Palate menu. In the
below figure it is 50 (lambda) or 6.250µ m, and run the simulation again, analyze
the effect of width on the propagation delay.
VLSI Design 17

Figure 2.9 Changed Width of NMOS MicroWind

Figure 2.10 Response of NMOS after changing its width

Similarly the nMOS can be analyzed using different widths and different input
voltages.

k) Save the design.

 VLSI Design 18

The characteristics of the pMOS are similar to the nMOS. Design the pMOS Layout
and analyzed in the similar way as nMOS Explore the Simulation Graphs. Explore
different device parameters and the commands in the drop down menus.

4. Simulation Anlysis (Include in your Lab Report)

SR. Width of Drain term Input Propagation Output Current
# nMOS voltage Voltage Delay voltage ID
Level Level
1 10  V 2.5v
SS
2 0.5v
3 1.5v
4 5.5v
5 V 2.5v
DD
6 0.5v
7 1.5v
8 5.5v
9 50  V 2.5v
SS
10 0.5v
11 1.5v
12 5.5v
13 V 2.5v
DD
14 0.5v
15 1.5v
16 5.5v

NOTE:Draw the graph of the above table and add the graph in your lab report.

Discuss the Effects of width design parameter of the MOS devices on their behavior.

If during the design phase of the MOSFET device, the electrical and physical parameters which characterize the
MOSFET device as: the substrate doping concentration (NA), the threshold voltage (Vt), the body body-effect
coefficient (γ), the process transconductance parameter (k ’ n), the channel width (W), the channel length (L), the
gate-oxide thickness (tox) and the channel length modulation coefficient (λ) are controlled and implemented by
the selected technology process, the MOSFET device can be designed by requested performance by the device
designer, depending to the operation conditions.

When the threshold voltage (Vt0) and the gate oxide thickness (tox) of the MOSFET are smaller, the current-
voltage characteristic will shift to larger values of drain current, as result of increasing of the characteristic slope
compared to larger values, for same drain-to-source voltage