Ug903 Vivado Using Constraints
Ug903 Vivado Using Constraints
User Guide
Using Constraints
Chapter 1: Introduction
Migrating From UCF Constraints to XDC Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
About XDC Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Introduction
There are key differences between Xilinx Design Constraints (XDC) and User Constraints File
(UCF) constraints. XDC constraints are based on the standard Synopsys Design Constraints
(SDC) format. SDC has been in use and evolving for more than 20 years, making it the most
popular and proven format for describing design constraints.
VIDEO: For training videos on input delay, see the Vivado Design Suite QuickTake Video:
Migrating UCF Constraints to XDC.
If you are familiar with UCF but new to XDC, see the "Differences Between XDC and UCF
Constraints" section in the Migrating UCF Constraints to XDC chapter of the ISE to Vivado
Design Suite Migration Guide (UG911) [Ref 1]. That chapter also describes how to convert
existing UCF files to XDC as a starting point for creating XDC constraints.
IMPORTANT: XDC has fundamental differences from UCF that must be understood in order to properly
constrain a design. The UCF to XDC conversion utility is not a replacement for properly understanding
and creating XDC constraints. Each XDC constraint is described in this User Guide.
• They are not simple strings, but are commands that follow the Tcl semantic.
• They can be interpreted like any other Tcl command by the Vivado Tcl interpreter.
• They are read in and parsed sequentially the same as other Tcl commands.
You can enter XDC constraints in several ways, at different points in the flow.
To load the XDC file in memory: (1) use the read_xdc command; or (2) add it to one of
your project constraints sets. XDC files accept the following built-in Tcl commands only:
set, list, and expr.
To execute the Tcl script: (1) run the source command; or (2) add the Tcl script to one
of your project constraints sets.
IMPORTANT: The Vivado Design Suite allows you to mix XDC files and Tcl scripts in the same
constraints set. Modified constraints are saved back to their original location only if they originally
came from an XDC file, and not from a Tcl script. A constraint generated by a Tcl script cannot be
interactively modified. For more information, see Chapter 2, Constraints Methodology.
To validate the syntax or impact of a particular constraint after loading your design in
memory, use the Tcl console and the Vivado Design Suite reporting features. This is
particularly powerful for analyzing and debugging timing constraints and physical
constraints.
Constraints Methodology
Because the Xilinx ® Vivado ® Integrated Design Environment (IDE) synthesis and
implementation algorithms are timing-driven, you must create proper timing constraints.
Over-constraining or under-constraining your design makes timing closure difficult. You
must use reasonable constraints that correspond to your application requirements.
RECOMMENDED: Xilinx recommends that you separate timing constraints and physical constraints by
saving them into two distinct files. You can also keep the constraints specific to a certain module in a
separate file.
Project Flows
You can add your Xilinx Design Constraints (XDC) files to a constraints set during the
creation of a new project, or later, from the Vivado IDE menus.
Figure 2-1 shows two constraint sets in a project:, Single or Multi XDC
IMPORTANT: If your project contains an IP that uses its own constraints, the corresponding constraint
file does not appear in the constraints set. Instead, it is listed along with the IP source files.
You can also add Tcl scripts to your constraints set. Tcl scripts and XDC files are loaded in
the same sequence as displayed in the Vivado IDE (if they belong to the same
PROCESSING_ORDER group) or as reported by the command report_compile_order
-constraints.
An XDC file or a Tcl script can be used in several constraints sets if needed. For more
information on how to create and add constraint files and constraints sets to your project,
see Working with Constraints in the Vivado Design Suite User Guide: System-Level Design
Entry (UG895) [Ref 2].
Non-Project Flows
In Non-Project Mode, you must read each file individually before executing the compilation
commands.
The example script below shows how to use one or more XDC files for synthesis and
implementation.
Example Script
read_verilog [glob src/*.v]
read_xdc wave_gen_timing.xdc
read_xdc wave_gen_pins.xdc
synth_design -top wave_gen -part xc7k325tffg900-2
opt_design
place_design
route_design
IMPORTANT: The DONT_TOUCH attribute does not obey the properties of USED_IN_SYNTHESIS and
USED_IN_IMPLEMENTATION. If you use DONT_TOUCH properties in the synthesis XDC, it is propagated
to implementation regardless of the value of USED_IN_IMPLEMENTATION.
For more information about the DONT_TOUCH attribute, refer to RTL Attributes, page 56.
When running the Vivado IDE in Non-Project Mode, you can read in the constraints directly
between any steps of the flow. The properties USED_IN_SYNTHESIS and
USED_IN_IMPLEMENTATION do not matter in this mode.
The following compilation Tcl script shows how to read two XDC files for different steps of
the flow:
TIP: The constraints read in after synthesis are applied in addition to the constraints read in before
synthesis.
The Vivado IDE provides full visibility into your design. To validate your constraints step by
step:
Start with the clock definitions. The clocks must be created before they can be used by any
subsequent constraints. Any reference to a clock before it has been declared results in an
error and the corresponding constraint is ignored. This is true within an individual
constraint file, as well as across all the XDC files (or Tcl scripts) in your design.
The order of the constraint files matters. You must be sure that the constraints in each file
do not rely on the constraints of another file. If this is the case, you must read the file that
contains the constraint dependencies last. If two constraint files have interdependencies,
you must either:
• Merge them manually into one file that contains the proper sequence, or
• Divide the files into several separate files, and order them correctly.
IMPORTANT: You must verify that the final sequence stored in the constraint files still works as
expected. If you must modify the sequence, you must modify it by directly editing the constraint files.
This is especially important for timing constraints.
For example, in Figure 2-3, the file wave_gen_pin.xdc was moved to before the file
wave_gen_timing.xdc by using drag and drop.
X-Ref Target - Figure 2-3
Figure 2-3: Changing XDC File Order in the Vivado IDE Example
In Non-Project Mode, the sequence of the read_xdc calls determines the order in which the
constraint files are evaluated.
For example, Figure 2-4 shows that one of the IP cores in the project comes with an XDC
file.
X-Ref Target - Figure 2-4
By default, IP XDC files are read in before the user XDC files. Processing it in this way allows
an IP to create a clock object that can be referenced in the XDC. It also allows you to
overwrite physical constraints set by an IP core because the user constraints are evaluated
after the IP. There is an exception to this order for the IP cores that have a dependency on
clock objects being created by the user or by another IP (for example, get_clocks
-of_objects [get_ports clka]). In this case, the IP XDC is read after the user files.
This behavior is controlled by the PROCESSING_ORDER property, set for each XDC file:
An IP XDC will have its PROCESSING_ORDER property set to either EARLY or LATE. For user
XDC (or Tcl) files that belong to the same PROCESSING_ORDER group, their relative order
displayed in the Vivado IDE determines their read sequence. The order within the group can
be modified by moving the files in the Vivado IDE constraints set, or by using the
reorder_files command.
For IP XDC files that belong to the same PROCESSING_ORDER group, the order is
determined by import or creation sequence of the IP cores. This order cannot be changed
after the project has been created.
Finally, the relative order between user groups and IP XDC PROCESSING_ORDER groups are
as follows:
For the example shown in Figure •, page 8, the equivalent Tcl command is:
The same mechanism applies to Tcl scripts. In Non-Project Mode, the sequence of the
read_xdc and source commands determines the order of the constraint files.
If you use the native IP cores that come with a constraint file, the IP XDC files are loaded
after your files, in the same sequence as the IP cores are listed in the IP Sources window,
unless the file PROCESSING_ORDER properties are set to LATE. For example, Figure 2-6
shows that one of the project IP cores comes with an XDC file.
X-Ref Target - Figure 2-6
When you open your design, the log file shows that the IP XDC file was loaded last:
Unlike with the User XDC files, you cannot directly change the read order of the IP XDC files
that belong to the same PROCESSING_ORDER group. If you must modify the order, do the
following:
Entering Constraints
The Vivado IDE provides several ways to enter constraints. Unless you directly edit the XDC
file in a text editor, you must open a design database (elaborated, synthesized or
implemented) in order to access the constraints windows in the Vivado IDE.
Before you can run synthesis or implementation, you must save the constraints in memory
back to an XDC file that belongs to the project. The Vivado IDE prompts you to save your
constraints whenever necessary.
• Saves all new constraints to the XDC file marked target in the constraints set
associated with your design.
• Saves all edited constraints back to the XDC file from which they originated.
Note: The constraints management system preserves the original XDC files format as much as
possible.
• The modified constraints replace the original constraints in their original file.
• The new constraints are appended to the file marked as target.
• All manual edits in the XDC files are overwritten.
In case of a conflict when saving the constraints, you are prompted to choose among:
Constraints creation is iterative. You can use IDE editors in some cases, and hand edit the
constraint files in others.
,OAD YOUR DESIGN IN MEMORY
6IVADO
$ATABASE
5SE 6IVADO )$% EDITORS %DIT 8$# FILES IN 4EXT %DITOR
!NALYZE YOUR DESIGN
$EVICE0HYSICAL4IMING 3AVE YOUR 8$# FILES
SCHEMATICS$EVICE2EPORTS
/THERS OR 4CL #ONSOLE 2ELOAD YOUR DESIGN
.EED MORE
9%3 '5) /PTION 9%3 (AND %DIT /PTION
CONSTRAINTS
./
#LOSE YOUR DESIGN 2UN COMPILATION
'5) /PTION SAVE CHANGES TO 8$# FILES NEW OR EXISTING
(AND %DIT /PTION DO NOTHING OR DISCARD ANY CHANGES
8
If you switch between the two options, you must first save your constraints or reload your
design, to ensure that the constraints in memory are properly synchronized with the XDC
files.
Pin Assignment
To create and edit existing top-level ports placement when using the RTL Analysis,
Synthesis, or Implementation views:
For more information on Pin Assignment, see this link in the Vivado Design Suite User Guide:
I/O and Clock Planning (UG899) [Ref 3].
For more information on Clock Resources Assignment, see this link in the Vivado Design
Suite User Guide: I/O and Clock Planning (UG899) [Ref 3].
Floorplanning
To create and edit Pblocks when using the RTL Analysis, Synthesis, or Implementation views:
For more information on Floorplanning, see this link in the Vivado Design Suite User Guide:
Design Analysis and Closure Techniques (UG906) [Ref 4].
• Clocks
° Primary clocks
° Generated clocks
° Forwarded clocks
° Input delays
° Output delays
° Combinatorial delays
• Clock domain crossings
During each step, you can accept the recommended constraints or modify the list by
checking/unchecking each of the proposed constraints. However, unchecking
recommended constraints early in the wizard can prevent the identification of other
missing constraints in subsequent steps. For example, if you decide to skip the creation of
a clock, the wizard will not identify and recommend any constraints that refer to this clock
or its auto-derived clocks.
The final page of the wizard provides a summary of the constraints that will be created. You
can click on each individual hyperlink to see the constraints details, or visualize the new
constraints in the Timing Constraints Editor after exiting the wizard.
You can also elect to generate the following recommended reports upon clicking Finish to
verify that the design is completely and properly constrained:
• Create Timing Summary report: Timing slack is reported with the new constraints, in
addition to a check_timing report. Timing violations will likely display if the period or
I/O delay constraints that you entered are too difficult.
• Create Check Timing report: This report identifies missing or inappropriate
constraints.
• Create DRC Report using only Timing Checks: this report identifies missing or
inappropriate constraints.
IMPORTANT: The newly added constraints are automatically saved to the Target XDC file
unless you click Cancel. You can edit or delete the new constraints in the Timing Constraints
Editor after exiting the wizard.
The Timing Constraint Wizard does not recommend a constraint if it introduces unsafe
timing analysis. Also, the wizard does not fix inappropriate constraints that already existed
when loading the design in memory. Nevertheless, some invalid constraints might become
valid after creating all the missing clocks when using Vivado Design Suite in project mode;
for more details, see Constraints Processing Order and Invalid Constraints, below. Also, after
using the wizard, if check_timing or report_drc still flag some constraints issues, it is
usually due to a constraint problem that already existed in the source XDC files. You must
address these problems directly instead of using the wizard to resolve them.
• Project mode: You must specify a target XDC file with its processing order set to
NORMAL before launching the Timing Constraints wizard. The target XDC file must
belong to the Constraints Set of the design open in memory and currently selected. The
position of the target XDC file among the other XDC files matters because it specifies
where the recommended constraints will be applied and saved later. Also, the wizard
tries to re-apply any invalid constraint that belongs to XDC files parsed after the target
XDC file in order to provide the most complete and accurate recommendations.
For example, consider the netlist from synth_1 run open in memory with the
Constraints Set constr_1. This Constraints Set contains three XDC files in the
following sequence: a.xdc, b.xdc, and c.xdc. If you choose b.xdc as the target XDC
file and each file contains an invalid constraint, the Timing Constraints wizard applies
the recommended clocks, then re-applies the invalid constraints from c.xdc before
proceeding to the next step and discovering other missing constraints.
• Non-project or Design Check Point (DCP) modes: You cannot specify a target XDC
file in these modes, so the Timing Constraints wizard recommends and applies new
constraints at the last position of the constraints sequence. This is equivalent to
entering new constraints in the Tcl Console or via the Timing Constraints Editor. In
these modes, the wizard does not attempt to re-apply invalid constraints. If the new
constraints need to be applied earlier in the overall constraints sequence in order to
resolve constraints dependencies or precedence issues, you must edit the constraints
sequence manually.
You can review the updated timing constraints sequence using the Timing Constraints
Editor.
Only the following features are available while the Timing Constraints wizard is open:
Most pages of the wizard have buttons to generate and access the clock network report
in order to visualize the clock topologies, their source point, and the shared segments
for some of the clocks.
Figure 2-11: Report Clock Networks and View Clock Network Buttons
Refer to the Vivado Design Suite User Guide: Design Analysis and Closure Techniques
(UG906) [Ref 4] for more details about the clock network report.
The Find and Find In Files dialog boxes are available from the Edit menu. You can use
these dialog boxes to retrieve some information about the design while entering the
constraints in the wizard.
You can select design objects in the main Vivado IDE window and visualize them in
schematics. All schematics features are available. Only the last step of the Timing
Constraints wizard, Asynchronous Clock Domain Crossings, supports convenient
schematics cross-probing when selecting one or several entries in the Timing Paths tab.
Refer to the Vivado Design Suite User Guide: Using the Vivado IDE (UG893) [Ref 6] for
more info on using schematics.
Each page of the wizard includes a tab that shows the existing constraints of the same
type as recommended by the step. This is convenient for quickly reviewing the details of
constraints already created in the XDC files. For a complete view of all timing constraints
in memory, the Timing Constraints Editor shows the full sequence of constraints,
organized by XDC file, including scoping information. It also displays the invalid
constraints.
• Uncheck the constraints you do not want to create, using one of the following
methods:
° Remove each constraint from the list, one at a time, by unchecking each line.
° Remove all constraints by unchecking the upper left check box of the table.
Alternatively, you can use the context menu of the selected lines, as shown in
Figure 2-12:
X-Ref Target - Figure 2-12
In Figure 2-13, clock1a, clocka2 and clock4 are unchecked and will be skipped.
X-Ref Target - Figure 2-13
• Enter the missing values by clicking on the cells that show undefined (for example, the
Frequency or Period value for clock3a in Figure 2-13).
You can edit several constraints at the same time by selecting the corresponding rows
and clicking the edit icon, as shown in Figure 2-14.
X-Ref Target - Figure 2-14
Editing multiple constraints at a time is particularly helpful for input and output delay
constraints.
When all the checked recommended constraints have been reviewed and completed, click
Next to proceed to the next page. Any entries that you missed prevent the wizard from
moving to the next step.
You can use the Back button to revisit a page. If you edit any constraint on a previous page
and click Next, the wizard re-analyzes the design and recommends new constraints
accordingly. In most cases, the previously recommended constraints not affected by the
change are reinstated. If you only view a previous page without modifying any of its
recommended constraints, the wizard does not re-run any analysis, which usually saves
runtime.
IMPORTANT: You cannot use the Timing Constraints wizard to edit existing timing
constraints. Instead, you must use the Timing Constraints Editor.
Two categories of clocks are identified by the wizard, as shown in Figure 2-16.
X-Ref Target - Figure 2-16
• The primary clocks needed for computing the timing slack for
setup/hold/recovery/removal checks appear in the Recommended Constraints table.
• The clocks only needed for performing pulse width checks (min_period,
max_period, max_skew, min_low_pulse_width, and min_high_pulse_width)
appear in the Constraints For Pulse Width Check Only table. By default, these clocks
are unchecked because they are only used for reporting purposes and do not influence
the implementation tools quality of result.
The wizard automatically identifies the proper clock source point for the constraint. It
corresponds to the clock tree root where the clock signal physically enters the design. In
most cases, the clock source point is an input clock port, and in some special cases it is the
output of a primitive that does not have a timing arc. For example, in 7 series devices, the
wizard identifies missing primary clocks on the output of GT_CHANNEL primitives. For
UltraScale™ devices, the Vivado Design Suite is able to auto-derive the GT_CHANNEL
output clocks based on the incoming clock characteristics and the GT_CHANNEL
configuration and connectivity. Consequently, the wizard recommends primary clocks
located upstream from the GT_CHANNEL cells on the design boundary.
Generated Clocks
The Timing Constraints wizard recommends the creation of a generated clock on the output
of a sequential cell when it drives the clock pins of other sequential cells either directly or
through some glue logic. Unlike PLL or MMCM, user logic cannot multiply the frequency of
the master clock, so the wizard only offers the option to specify a division coefficient, as
shown in Figure 2-17.
X-Ref Target - Figure 2-17
When several master clocks reach the generated clock source point, the wizard creates all
the corresponding generated clocks, using unique names and clear reference to individual
master clocks. Figure 2-17 illustrates the scenario where two clocks (clock6 and clock7)
reach the sequential cell FD7. Consequently two generated clock constraints are
recommended: invWire and invWire_1.
Forwarded Clocks
The Timing Constraints wizard recommends generated clock constraints on output ports
that are driven by double data-rate registers with constant inputs. Based on the input
constant connectivity, the generated clock phase is adjusted to either positive (0 degree
phase shift) or inverted (180 degree phase shift). The master clock used in the constraint is
the clock that reaches the clock pin of the double data-rate register. See the Source Clock
column of the Recommended Constraints table in Figure 2-18.
X-Ref Target - Figure 2-18
For the UltraScale device family, the ODDR and ODDRE1 primitives are automatically
retargeted to OSERDESE3 with the property ODDR_MODE=TRUE. The wizard recognizes the
topology shown in Figure 2-20, where OSERDESE3/D[0] is connected to 1 and
OSERDESE3/D[4] is connected to 0 (no phase-shift).
The Timing Constraints wizard analyzes the feedback loop connectivity of the MMCM and
PLL cells present in the design. External delay constraints (min and max) are recommended
when the CLKFBIN and CLKFBOUT pins are connected to the design ports through IO
buffers and the MMCM or PLL property COMPENSATION=EXTERNAL. Figure 2-21 illustrates
the recommended External Delay constraints.
X-Ref Target - Figure 2-21
Figure 2-22 illustrates a typical MMCM with external feedback path circuit.
X-Ref Target - Figure 2-22
In the current Vivado release, the Timing Constraints wizard cannot recommend external
delay constraints when there is a sequential cell in the feedback path, such as ODDR, which
is used for generating a forwarded clock. In this case, you must create the external delay
constraints manually or using the Timing Constraints Editor after exiting the wizard.
Input Delays
The Timing Constraints wizard analyzes all paths from input ports to identify their
destination clock inside the design and their active edges. Based on this information, the
wizard recommends basic system synchronous input delay constraints that are based on the
XDC templates available in the Vivado IDE (see XDC Templates, page 54 for templates). The
waveform associated with the selected template is displayed at the bottom of the window
in the Waveform tab when you select a constraint entry in the Recommended Constraints
table.
Figure 2-23, page 33 shows an example of several input constraints proposed by the wizard
and partially edited by the user.
° System (for System Synchronous interface): use this setting when the data is
launched and captured by different clock edges that are 1 period or ½ period apart.
° Source (for Source Synchronous interface): use this setting when the data is
launched and captured by the same clock edge.
• Alignment describes the data transition alignment with respect to the active clock
edge.
• Data Rate and Edge describes the active clock edges constrained by the template. The
default value recommended by the wizard is based on the active clock edges of the
capturing sequential cell.
° Single Rise: use this setting for cases where only the rising clock edges launch the
data outside the FPGA device.
° Single Fall: use this setting for cases where only the falling clock edges launch the
data outside the FPGA device.
° Dual: use this setting for cases where both rising and falling clock edges launch the
data outside the FPGA device.
The recommended clock is usually the board clock related to the input path sequential cell.
When the input path internal clock is an MMCM or PLL generated clock, the board clock
that drives the MMCM or PLL is used as the input constraint reference clock. The only
exceptions exist when the internal clock waveform and the board clock waveform are not
identical, such as the following scenarios:
The input constraint references a virtual clock that has the same waveform as the
internal clock so that the setup analysis is performed with a 1 cycle path requirement.
The virtual clock is automatically created.
The wizard uses a virtual clock as the reference clock. The virtual clock is automatically
created with the same waveform as the board clock. In addition, the wizard also
specifies a multicycle path constraint between the virtual clock and the internal clock to
adjust the default analysis to 1 period + the amount of phase-shift for setup. The
combination of the virtual clock and the multicycle path constraint provides simpler
constraints for the Vivado timer to handle and can only affect input ports that reference
to the virtual clock.
Note that for a negative phase-shift, the virtual clock and the multicycle path constraint
are not needed because the default setup path requirement is 1-cycle minus the amount
of phase-shift.
The wizard does not allow you to change the reference clock selected for the constraint. To
do so, you must manually edit the XDC files or use the Timing Constraints Editor after
exiting the wizard.
After you select the proper template, enter the delay parameter values in the Delay
Parameters panel located on the right hand side of the wizard and then click Apply to
validate the entries.
The input delay equations are displayed below the delay parameter fields and on some of
the template waveforms. Figure 2-24 shows the Delay Parameters panel for the DDR System
Synchronous interface template.
X-Ref Target - Figure 2-24
To accelerate the delay parameter entry task, you can select and edit several constraints
with same clock and same template at once.
After the constraints have been completed and applied, you can review their corresponding
Tcl syntax in the Tcl Command Preview tab or you can click Next to proceed to the next step.
TIP: The Timing Constraints wizard skips input ports with a false path constraint. This is particularly
useful for skipping asynchronous resets that usually do not have a known phase relationship with any
clock of the design. The false path constraint can only be created outside the wizard.
Output Delays
Similar to the Input delays step, the Timing Constraints wizard analyzes the paths to all
output ports to identify their source clocks inside the design and their active edges. The
template selection rules are the same as described in Input Delays, page 32. Figure 2-25,
page 36 shows an example of several output constraints proposed by the wizard and
partially edited by the user.
• Synchronous describes the nature of the clock-data relationship (see Input Delays,
page 32 for more details).
• Alignment describes the data transition alignment with respect to the active clock
edge.
° Setup/Hold: use this setting when the template delay parameters are specified
based on the data valid window timing characteristics outside the FPGA device.
° Skew (Source Synchronous only): use this setting when the template delay
parameters are specified based on the skew requirements on the output pin of the
FPGA.
• Data Rate and Edge describes the active clock edges constrained by the template (see
Input Delays, page 32 for more details).
Like for recommended input delay constraints, the reference clock is the board clock for
most cases, except in the following cases:
• The board clock and the output path internal clock have different clock periods.
The output constraint references a virtual clock that has the same waveform as the
internal clock so that the setup analysis is performed with a 1-cycle path requirement.
The virtual clock is automatically created.
• The output path internal clock has a negative phase-shift compared to the board clock.
The wizard uses a virtual clock as the reference clock. The virtual clock is automatically
created with the same waveform as the board clock. In addition, the wizard also
specifies a multicycle path constraint between the virtual clock and the internal clock to
adjust the default analysis to 1 period + the amount of phase-shift for setup. The
combination of the virtual clock and the multicycle path constraint provides simpler
constraints for the Vivado timer to handle and can only affect output ports that
reference to the virtual clock.
Note that for a positive phase-shift, the virtual clock and the multicycle path constraint
are not needed because the default setup path requirement is 1 cycle minus the amount
of phase-shift.
• A forwarded clock has been identified for timing the output path based on the shared
clocking connectivity.
The forwarded clock must have been created during the third step of the wizard
"Forwarded Clocks", or else the board clock or a virtual clock will be used as the output
delay constraint reference clock.
Figure 2-26 shows a basic example of an output source synchronous path along with its
forwarded clock for the 7 series family. Both ODDR instances are connected to the same
clock net (highlighted in blue). The ssco generated clock is already defined on the ssco
output port.
Figure 2-26: Example of a Source Synchronous Output Path with its Forwarded Clock
• Figure 2-27 shows the corresponding constraints in the wizard.
X-Ref Target - Figure 2-27
Figure 2-27: Recommended Source Synchronous Output Path Delay Constraint with a
Forwarded Clock
After you select the proper template, you must enter the delay parameters values. To
accelerate the delay parameter entry task, you can select and edit several constraints with
same clock and same template at once. After the constraints have been completed and
applied, you can review their corresponding Tcl syntax in the Tcl Command Preview tab or
you can click Next to proceed to the next step.
TIP: The Timing Constraints wizard skips output ports with a false path constraint. The false path
constraint can only be created outside the wizard.
Combinatorial Delays
Some paths propagate directly from input ports to output ports without being captured
inside the device by a sequential cell. If an input port is connected to both an output port
and a sequential cell, the Timing Constraints wizard does not recommend combinational
constraints between the input/output port pair, because the input port should have been
constrained during the Input Delay step. For the combinational paths, the wizard
recommends to define a virtual clock along with input and output delays on the design
ports as shown in Figure 2-28.
X-Ref Target - Figure 2-28
The virtual clock period must be modified so that it is greater than the largest
combinational delay constraint across all constrained combinational paths. Figure 2-29
shows the delay entries needed per input/output ports pair.
X-Ref Target - Figure 2-29
None of the input and output delay constraints override existing ones. If a given port has
multiple delay constraints with respect to the same clock, the smallest value of all
constraints is used by Vivado Timing during hold analysis, and the largest one during setup
analysis.
After all delay entries have been filled, you can click Next to proceed to the next step.
TIP: Alternatively, you can constrain combinational paths using the set_max_delay and
set_min_delay commands outside the Timing Constraints wizard.
Physically exclusive clocks are clocks that are defined on the same source point and
propagate on the same clock tree. Figure 2-30 shows an example where two primary clocks
are defined on the same input port.
X-Ref Target - Figure 2-30
While their overlap is convenient for timing several application modes with one design and
constraint database, these clocks and their children generated clocks should never be timed
together. The Timing Constraints wizard identifies such clocks and recommends a clock
groups constraint to prevent unnecessary timing analysis on the clock domain crossing
paths, as shown in Figure 2-31.
X-Ref Target - Figure 2-31
Logically exclusive clocks are clocks that are defined on different source points but share
part of their clock tree due to a multiplexer or other combinational logic. The Timing
Constraints wizard identifies such clocks and recommends a clock groups constraint
directly on them when they do not have timing paths between each other except for the
logic connected to their shared clock tree. Figure 2-32 shows an example of two clocks,
clkA and clkB, which are defined on different input ports and start overlapping on the
output of a BUFGMUX.
X-Ref Target - Figure 2-32
The Timing Constraints wizard identifies logically exclusive clocks that have timing paths
between each other elsewhere than just on the logic connected to the shared clock tree.
Figure 2-33 shows an example where clkA and clkB have a shared clock tree portion, and
also have a timing path from the shared clock tree to clkA only.
X-Ref Target - Figure 2-33
Figure 2-33: Example of a Design with Logically Exclusive Clocks with Interaction
Because only the clock domain crossing paths of the shared clock tree must be ignored, the
wizard recommends to create generated clocks that are copies of clkA and clkB but that
only exist on the shared clock tree. The clock groups constraint is applied to the generated
clocks only, so that the paths outside the logic of the shared clock tree can still be normally
timed. Figure 2-34 illustrates the wizard recommended constraints for the example above.
Figure 2-34: Recommended Constraints for Logically Exclusive Clocks with Interaction
Asynchronous Clock Domain Crossings
The Timing Constraints wizard analyzes the topology of clock domain crossing (CDC) paths
between asynchronous clocks and recommends clock groups or false path constraints
whenever it is safe to do so.
Asynchronous clocks are clocks with no known phase relationship, which typically happens
when they do not share the same primary clock or do not have a common period. For this
reason, slack computation on asynchronous CDC paths is not accurate and cannot be
trusted. Due to potentially large skew between asynchronous clocks, the timing
quality-of-result can be heavily impacted and prevent proper timing closure if any of the
asynchronous CDC paths is timed. You are responsible for adding timing exceptions on
these paths, such as set_clock_groups, set_false_path, or set_max_delay
-datapath_only to either completely ignore timing analysis or just ignore the clock skew
and uncertainty. Also, the design must implement proper CDC circuitry to prevent
metastability.
In Vivado, the wizard only identifies flip-flop-based synchronizers for synchronous data and
asynchronous reset. For an example of such synchronizers, see this link in the Vivado Design
Suite User Guide: Design Analysis and Closure Techniques (UG906) [Ref 4]. Figure 2-35 shows
an example of the recommended and non-recommended constraints tables.
• Source Clock: this is the clock of the CDC paths start points identified by the wizard.
• Destination Clock: this is the clock of the CDC paths endpoints identified by the
wizard.
• Constraint: this column shows either the dominant timing exception or the
characteristics of the clock relationship when there is no exception.
° In the Recommended Constraints table, the wizard anticipates that the constraints
will be created and displays the new constraint:
- asynch (clock groups) for the cases where it is safe to ignore timing in both
directions, in which case a set_clock_groups constraint is created
- asynch (false path) when it is only safe to ignore the paths in one direction, in
which case a set_false_path constraint is created
The table entries contain cross-probing links whenever applicable. When you click on a
number, the corresponding CDC paths are listed in the Paths tab at the bottom of the
window. You can select one or several CDC paths and click on the Schematic (F4) button to
display the logic of the path(s) in the main Vivado window.
The Timing Constraints wizard provides a table with constraints that are not enabled by
default because they are not recommended for one of the following reasons:
You can decide to activate any of these constraints when working on an early version of the
design, and then revisit the CDC paths and their constraints later when finalizing your
design.
Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to
true in order to preserve the synchronizer cells through any logic optimization during
synthesis and implementation, and to optimize their placement for best Mean Time Before
Failure (MTBF) statistics. For any clock group constraints that are enabled in both tables
(either by default or by the user), the wizard sets to true any missing ASYNC_REG property.
The Timing Constraints wizard does not recognize some valid CDC topologies that are not
based on simple synchronizers. The report_cdc command provides a powerful and more
comprehensive view of the CDC paths that need structural correction in order to become
safe. Refer to this link in the Vivado Design Suite User Guide: Design Analysis and Closure
Techniques (UG906) [Ref 4] for detailed information about report_cdc.
For the cases where the wizard does not recommend a constraint due to the presence of
some set_max_delay -datapath_only, the other CDC paths that are normally timed
must be reviewed individually and possibly ignored by additional false path constraints. The
creation of point-to-point false path constraints must be done in the XDC file, in the Tcl
Console, or in the Timing Constraints Editor after exiting the wizard.
Constraints Summary
The final page of the Timing Constraints wizard summarizes the new constraints that will be
applied and saved at the end of the Target XDC file when you click Finish. Click each
hyperlink to see the details of the constraints. Figure 2-36 below shows an example of the
Constraints Summary page.
X-Ref Target - Figure 2-36
You can open the Timing Constraints window using one of the following three options, as
shown in Figure 2-37:
Figure 2-37: Multiple Methods for Opening the Timing Constraints Window
The Timing Constraints editor displays the timing constraints in memory, in either:
Some of the constraints cannot be edited from this window. They are marked with the XDC
No Edit icon .
• Source File: The name of the XDC file or Tcl script the constraint comes from
• Scoped Cell: The name of the current instance when the constraint was applied. This
name usually corresponds to an IP instance which is delivered with dedicated
constraints. For more information, see Constraints Scoping, page 64.
A new constraint of the selected type can be created by double clicking the last line of the
spreadsheet. The corresponding constraint creation dialog opens and lets you fill in the
details of the new constraint. Click OK to apply the constraint in memory and close the
window. A new line in the spreadsheet shows the new constraint information.
You can edit any existing constraint by modifying the values directly in the spreadsheet.
After you have finished editing, click Apply to apply the modified constraints in memory.
IMPORTANT: Applying a new or modified constraint does not save it in the XDC file. You must click
Save Constraints to save it.
IMPORTANT: IP constraints cannot be edited or deleted. In order to modify a constraint delivered with
an IP, you must: (1) disable the corresponding IP XDC file; (2) copy the constraint to your XDC file; and
(3) edit the constraint as desired.
To create a new constraint, double click the name of the target constraint. A dialog box
allows you to specify the value for each option. When you click OK, the tool:
All Constraints
The bottom of the window displays the complete list of constraints loaded in memory, in
the same sequence as they were applied. The constraints are grouped in accordance with
the XDC file or the Tcl script from which they originated. When an XDC file is scoped to a
particular hierarchical cell, the cell name is displayed next to the file name.
X-Ref Target - Figure 2-41
You can expand and collapse the constraints by the associated source file, or completely by
clicking the two corresponding button on the left side of the panel.
X-Ref Target - Figure 2-42
TIP: The collapsed view provides a compact overview of which constraints file are loaded in memory,
and where the scoping mechanism is used. The same information is available through the
report_compile_order -constraints command.
De-select the Group by Source icon to switch the view to a table in which the source
constraint file and the scoped cell information appears in the two right columns.
When saving the constraints, the new constraints are saved at the end of the XDC file
marked as target. If there is no target XDC file in the constraint set associated with the
design in memory, or if there is only a Tcl script in the constraint set, you are prompted to
specify where to save the constraints.
Regularly save your constraints. Click Save, or select File > Save Constraints.
IMPORTANT: New and modified constraints cannot be saved back to a Tcl script.
CAUTION! Do not enter new constraints in the Tcl Console if any constraints in the Timing Constraints
editor have not yet been applied. The final constraints order in the editor can become different from the
constraints order in memory. In order to avoid any confusion, you must re-apply all constraints each
time you edit an existing constraint.
XDC Templates
You can access XDC templates by selecting Window > Language Templates.
X-Ref Target - Figure 2-45
° Clock definitions
° Jitter
° Input/output delay
° Exceptions
• Physical constraints
• Configuration constraints
You must verify that all necessary values have been filled instead of using the default
values.
X-Ref Target - Figure 2-46
Xilinx® FPGA devices include many logic features that can be used in many different ways.
Your constraints are needed to guide the synthesis engine towards a solution that meets all
the design requirements at the end of implementation.
There are four categories of constraints for the Vivado IDE synthesis:
• RTL Attributes
• Timing Constraints
• Physical and Configuration Constraints
• Elaborated Design Constraints
RTL Attributes
RTL attributes must be written in the RTL files. They usually correspond to directives related
to the mapping style of certain part of the logic, as well as preserving certain registers and
nets, or controlling the design hierarchy in the final netlist.
For more information, see this link in the Vivado Design Suite User Guide: Synthesis (UG901)
[Ref 7].
IMPORTANT: The DONT_TOUCH attribute does not obey the properties of USED_IN_SYNTHESIS and
USED_IN_IMPLEMENTATION. If you use DONT_TOUCH properties in the synthesis XDC, it is
propagated to implementation regardless of the value of USED_IN_IMPLEMENTATION.
Timing Constraints
Timing constraints must be passed to the synthesis engine by means of one or more XDC
files. Only the following constraints related to setup analysis have any real impact on
synthesis results:
• create_clock
• create_generated_clock
• set_input_delay
• set_output_delay
• set_clock_groups
• set_false_path
• set_max_delay
• set_multicycle_path
At this point in the flow, the net delay modeling is still not very accurate. The main goal is
to obtain a synthesized netlist which meets timing, or fail by a small amount, before starting
implementation. In many cases, you will have to go through several XDC and RTL
modification iterations before you can reach this state.
The RTL-based XDC creation iteration is shown in Figure 2-47, page 58. It is based on the
utilization of the Elaborated design to find the object names in your design that you want
to constrain for synthesis.
You must use the Tcl Console to validate the syntax of the XDC commands before saving
them in the XDC files. With the elaborated design, you can create constraints, query clocks,
and query design objects, but you cannot run any timing report command.
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Some RTL names are modified or lost during the creation of the elaborated design.
Following are the most common cases:
By default, the register name is based on the signal name in the RTL, plus the _reg suffix.
For example, for a signal defined as follows in VHDL and Verilog, the instance name
generated during the elaboration is wbDataForInputReg_reg:
Figure 2-48 shows the schematic of the register, and its pins. It is possible to define a
constraint on the register instance or its pins.
X-Ref Target - Figure 2-48
By default, the register name is based on the signal name in the RTL, plus the _reg suffix.
You can only query and constrain individual bits of the multi-bit register in your XDC
commands.
For example, for a signal defined as follows in VHDL and Verilog, the instance names
generated during the elaboration are loadState_reg[0], loadState_reg[1], and
loadState_reg[2]:
Figure 2-49 shows the schematic of the register. The multi-bit register appears as a vector
of single-bit registers. The vector is represented in a compact way whenever possible in the
schematics. Each individual bit can also be displayed separately.
X-Ref Target - Figure 2-49
You can only constrain each register individually or as a group by using the following
patterns:
IMPORTANT: You cannot query the multi-bit register, or more generally any multi-bit instance, by
using the following pattern: loadState_reg[2:0]
Because the names above also correspond to the names in the post-synthesis netlist, any
constraint based on them will most probably work for implementation as well.
Some registers or nets in the RTL sources can disappear in the elaborated design (or
synthesized design) for various reasons. For example, memory block, DSP or shift register
inference requires absorbing several design objects into one resource. Instead of using
these objects to define constraints, try to find other connected registers or nets that you
can use.
Hierarchical Names
Unless you plan to force Vivado synthesis to keep the complete hierarchy of your design,
some or all levels of the hierarchy can be flattened during synthesis. For more information,
see the flatten_hierarchy information available by going to this link in the Vivado
Design Suite User Guide: Synthesis (UG901) [Ref 7].
RECOMMENDED: Use fully resolved hierarchical names in your synthesis constraints. They are more
likely to be matching the final netlist names regardless of the hierarchy transformations.
For example, consider the following register located in a sub-level of the design.
During synthesis (assuming no special optimization is performed on this register), you can
get either flat or hierarchical name depending on the tool options or the design structure.
inst_A/inst_B/control_reg (F)
inst_A/inst_B/control_reg (H)
There is no obvious difference because the / character is also used to mark flattened
hierarchy levels. You will notice the difference when querying the object in memory. The
following commands will return the netlist object for F but not H:
In order to avoid problems related to hierarchical names, Xilinx recommends that you:
% get_cells inst_A/inst_B/*_reg
% get_cells inst_*/inst_B/control_reg
CAUTION! (1) Do not attach constraints to hierarchical pins during synthesis for the same reason as
explained above for hierarchical cells. (2) Do not attach constraints to nets connecting combinatorial
logic operators. They will likely be merged into a LUT and disappear from the netlist.
RECOMMENDED: Regularly save your XDC files after editing, and reload the Elaborated design in order
to make sure the constraints in memory and the constraints in the XDC files are the same. After
running synthesis, load the synthesized design with the same synthesis XDC in memory, and run timing
analysis by using the timing summary report.
1. Find the new XDC syntax that applies to the synthesized netlist.
2. Save the constraints in a new XDC file to be used during implementation only.
3. Move the synthesis constraints that can no longer be applied to a separate XDC file that
will be used for synthesis only.
In some cases, the object names in the synthesized netlist are different from the names in
the elaborated design. If this is the case, you must recreate some constraints with the
corrected names, and save them in an implementation-only XDC file.
After the tool can properly load all the XDC files, you can run timing analysis in order to:
You can use the same base constraints as during synthesis, and create a second XDC file to
store all new constraints specific to implementation. You can choose to save physical and
configuration constraints in a separate XDC file.
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RECOMMENDED: Revisit the RTL to reduce the number of logic levels on the violating paths and to
clean up the clock trees in order to use dedicated clock resources and minimize the skew between
related clocks. You can also add synthesis attributes and use different synthesis options.
For more information, see this link in the Vivado Design Suite User Guide: Synthesis (UG901)
[Ref 7], or this link in the Vivado Design Suite User Guide: Implementation (UG904) [Ref 8].
Constraints Scoping
The constraints from a particular XDC file can be optionally scoped to a specific module, to
specific cells of your design, or both, if needed. This is convenient for creating and applying
constraints to a sub-level of your design without having any information about the
top-level. It also prevents constraints from being applied outside the target hierarchical cell.
By default, all the IP cores from the Vivado IP Catalog generated within a Vivado project use
this mechanism to load their constraints in memory.
• SCOPED_TO_REF: This property takes the name of a module (or entity). The constraints
are applied to ALL instances of the specified module (or entity) only,
• SCOPED_TO_CELLS: This property takes a list of hierarchical cell names. The constraints
are scoped and applied to each hierarchical cell individually,
• SCOPED_TO_REF + SCOPED_TO_CELLS: If BOTH these properties are specified, the
constraints are applied to each cell of the SCOPED_TO_CELLS list, located inside the
module (or entity) specified by SCOPED_TO_REF.
These properties are automatically set by Vivado for IP cores added to your RTL project by
means of the IP Catalog.
Following are three equivalent Tcl examples to use the scoping properties on
uart_tx_ctl.xdc. The same values can be set in the Properties windows of the XDC file
in the Vivado IDE.
When using Vivado in Non-Project Mode, you can use the read_xdc command with the
-ref and -cells options to achieve the same result:
The only exceptions are with timing clock objects and netlist ports:
° The port names to be used with get_ports are the port names of the scoped
instance interface, not the top-level port names.
° If there is any leaf cell, including IO and clock buffers, between the scoped instance
port and the top-level ports, the get_ports command becomes a get_pins
command and returns the hierarchical scoped instance pin.
The XDC scoping mechanism is used for reading all Vivado IP constraint files. Figure 2-52,
page 67, and Figure 2-53, page 67, show the two examples of how the get_ports
commands are treated when reading in the IP-level XDC using this methodology.
In Figure 2-52, page 67, the I/O buffer is instantiated inside the IP and the IP interface pin
is directly connected to a top-level port (regardless of the hierarchy). When the XDC for the
IP is applied, the argument of the get_ports command is automatically replaced with the
top-level port.
This enables setting physical properties such as a LOC or IOSTANDARD at the IP level and
having them be placed on the top-level port where they need to be. This is accomplished
without the IP knowing the name of the top-level ports of the design.
X-Ref Target - Figure 2-52
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In Figure 2-53, the IP does not contain an I/O buffer, so the synthesis engine infers one
between the IP interface pin and the top-level port. Consequently, the get_ports is
converted to a get_pins of the IP interface pin (for example, a hierarchical pin) when the
XDC is applied.
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This capability is very useful for creating constraints on the interface of an IP or a sub-level
module without knowing the names of the top-level design.
If the scoped XDC file includes constraints that can only be applied to top-level ports but
the IP instance is not directly connected to top-level ports, the Vivado XDC reader will
return errors. For example, the following constraints can only be applied to top-level ports,
and not hierarchical pins of your design:
• set_input_delay/set_output_delay
• set_property IOSTANDARD
Similarly, you can develop constraints for a sub-module of your design, and use the same
scoping mechanism as IP cores by setting the SCOPED_TO_REF/SCOPED_TO_CELLS XDC file
properties appropriately in a project flow, or use the read_xdc -ref/-cells command
in Non-Project Mode.
• Cell/net/pin objects queries are limited to the scoped instance and its sub-levels:
° The NAME property of the object shows the full hierarchical path of the object
relative to the top-level and not just the scoped instance. If you use the -filter
option of the get_* commands on the NAME property, you must use the glob
string match operator and provide a pattern which starts with a *. For example:
get_nets -hierarchical -filter {NAME =~ *clk}
° all_inputs, all_outputs
• Clock commands are not scoped and will return all timing clocks of your design.
° get_clocks, all_clocks
• Top-level and local clock objects can be queried by probing the netlist with
get_clocks -of_objects.
For example, consider the case in which a false path constraint is defined in the IP XDC
between two clocks that come into the IP. The IP includes proper circuitry for asynchronous
clock boundaries, but perhaps not for the rest of the design. This is a problem if the two
clocks are related and must be timed together in the rest of the design in order to have
proper hardware functionality.
Also, as discussed in Chapter 6, XDC Precedence, a timing exception defined in the IP XDC
file can have higher precedence than top-level constraints and can override them, which is
undesired. To avoid this situation, Xilinx recommends that you apply the constraints to
netlist objects local to the IP. In the case of a false path between two global clocks, the false
path must be applied from a group of startpoint cells inside the IP to another group of
endpoint cells inside the IP as well. This technique is referred to as point-to-point
exceptions instead of global exceptions.
° Defined on a port directly connected to an input buffer instantiated inside the IP.
° Defined on a driver pin located inside the IP (for example, GTX output).
• Query top-level clocks with the get_clocks -of_objects command instead of
redefining these clocks locally.
• Specify input and output delay only if the port is directly connected to the top-level
port and the I/O buffer is instantiated inside the IP.
• Do not define timing exceptions between two clocks that are not bounded to the IP.
Defining Clocks
About Clocks
In digital designs, clocks represent the time reference for reliably transferring data from
register to register. The Xilinx ® Vivado ® Integrated Design Environment (IDE) timing engine
uses the clock characteristics to compute timing path requirements and report the design
timing margin by means of the slack computation.
For more information, see this link in the Vivado Design Suite User Guide: Design Analysis
and Closure Techniques (UG906) [Ref 4].
Clocks must be properly defined in order to get the maximum timing path coverage with
the best accuracy. The following characteristics define a clock:
• It is defined on the driver pin or port of its tree root, which is called the source point.
• Its edges are described by the combination of the period and the waveform properties.
• The period is specified in nanoseconds. It corresponds to the time over which the
waveform repeats.
• The waveform is the list of rising edge and falling edge absolute times, in nanoseconds,
within the clock period. The list must contain an even number of values. The first value
always corresponds to the first rising edge. Unless specified otherwise, the duty cycle
defaults to 50% and the phase shift to 0ns.
As shown in Figure 3-1, the clock Clk0 has a 10ns period, a 50% duty cycle and 0ns phase.
The clock Clk1 has 8ns period, 75% duty cycle and a 2ns phase shift.
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Propagated Clocks
The period and waveform properties represent the ideal characteristics of a clock. When
entering the FPGA device and propagating through the clock tree, the clock edges are
delayed and become subject to variations induced by noise and hardware behavior. These
characteristics are called clock network latency and clock uncertainty.
By default, the Vivado IDE always treats clocks as propagated clocks, that is, non-ideal, in
order to provide an accurate slack value which includes clock tree insertion delay and
uncertainty.
They can also be generated by special primitives called Clock Modifying Blocks, such as:
• MMCM
• PLL
• BUFR
They can also be transformed by regular cells such as LUTs and registers.
The following sections describe how to best define clocks based on where they originate.
Primary Clocks
A primary clock is a board clock that enters the design through:
• An input port, or
• A gigabit transceiver output pin (for example, a recovered clock)
A primary clock must be attached to a netlist object. This netlist object represents the point
in the design from which all the clock edges originate and propagate downstream on the
clock tree. In other words, the source point of a primary clock defines the time zero used by
the Vivado IDE when computing the clock latency and uncertainty used in the slack
equation.
IMPORTANT: The Vivado IDE ignores all clock tree delays coming from cells located upstream from the
point at which the primary clock is defined. If you define a primary clock on a pin in the middle of the
design, only part of its latency is used for timing analysis. This can be a problem if this clock
communicates with other related clocks in the design, because the skew, and consequently the slack,
value between the clocks can be inaccurate.
Primary clocks must be defined first, because other timing constraints often refer to them.
As shown in Figure 3-2, the board clock enters the device through the port sysclk, then
propagates through an input buffer and a clock buffer before reaching the path registers.
RECOMMENDED: Define the board clock on the input port, not on the output of the clock buffer.
Similar to sysclk, a board clock devclk enters the device through the port ClkIn.
Corresponding XDC:
Figure 3-3 shows a transceiver gt0, which recovers the clock rxclk from a high speed link on
the board. The clock rxclk has a 3.33ns period, a 50% duty cycle and is routed to an MMCM,
which generates several compensated clocks for the design.
When defining rxclk on the output driver pin of GT0, all the generated clocks driven by the
MMCM have a common source point, which is gt0/RXOUTCLK. The slack computation on
paths between them uses the proper clock latency and uncertainty values.
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Virtual Clocks
A virtual clock is a clock that is not physically attached to any netlist element in the design.
A virtual clock is commonly used to specify input and output delay constraints in one of the
following situations:
• The external device I/O reference clock is not one of the design clocks.
• The FPGA I/O paths are related to an internally generated clock that cannot be properly
timed against the board clock from which it is derived.
Note: This happens when the ratio between the two periods is not an integer. which leads to a
very tight and unrealistic timing path requirement.
• You want to specify different jitter and latency only for the clock related to the I/O
delay constraints without modifying the internal clocks characteristics.
For example, the clock clk_virt has a period of 10ns and is not attached to any netlist
object. The [<objects>] argument is not specified. The -name option is mandatory in such
cases.
The virtual clocks must be defined before being used by the input and output delay
constraints.
Generated Clocks
This section discusses generated clocks and includes:
Generated clocks are associated with a master clock. The create_generated_clock command
considers the start point of the master clock. The master clock can be:
• A primary clock
• Another generated clock
Generated clock properties are directly derived from their master clock. Instead of
specifying their period or waveform, you must describe how the modifying circuitry
transforms the master clock.
The relationship between a master clock and a generated clock can be:
RECOMMENDED: Define all primary clocks first. They are needed for defining the generated clocks.
Specify the master clock using the -source option. This indicates a pin or port in the design
through which the master clock propagates. It is common to use the master clock source
point or the input clock pin of generated clock source cell.
IMPORTANT: The -source option accepts only a pin or port netlist object. It does not accept clock
objects.
The primary clock clkin has a period of 10ns. It is divided by 2 by the register REGA which
drives other registers clock pin. The corresponding generated clock is called clkdiv2.
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Instead of using the -divide_by option, you can use the -edges option to directly describe
the waveform of the generated clock based on the edges of the master clock. The argument
is a list of master clock edge indexes used for defining the position in time of the generated
clock edges, starting with the rising clock edge.
The following example is equivalent to the generated clock defined in Example One: Simple
Division by 2.
Example Three: Duty Cycle Change and Phase Shift with -edges and -edge_shift Options
Each edge of the generated clock waveform can also be individually shifted by a positive or
negative value by using the -edge_shift option. Use this option only if a phase shift is
needed.
The -edge_shift option cannot be used at the same time as any of the following:
• -divide_by
• -multiply_by
• -invert
Consider the master clock clkin with a 10ns period and a 50% duty cycle. It reaches the cell
mmcm0 which generates a clock with a 25% duty cycle, shifted by 90 degrees. The generated
clock definition refers to the master clock edges 1, 2, and 3. These edges respectively occur
at 0ns, 5ns, and 10ns. To obtain the desired waveform, shift the first and the third edges by
2.5ns.
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Example Four: Using Both -divide_by and -multiply_by at the Same Time
The Vivado IDE allows you to specify both -divide_by and -multiply_by at the same time.
This is an extension to standard Synopsys Design Constraints (SDC) support. This is
particularly convenient for manually defining clocks generated by MMCM or PLL instances,
although Xilinx recommends that you let the engine create these constraints automatically.
Consider the mmcm0 cell as in Example Three: Duty Cycle Change and Phase Shift with
-edges and -edge_shift Options above, and assume that it multiplies the frequency of the
master clock by 4/3. The corresponding generated clock definition is:
If you create a generated clock constraint on the output of an MMCM or PLL, it is better to
verify that the waveform definition matches the configuration of the MMCM or PLL.
The master clock clkin drives the input CLKIN of the MMCME2 instance clkip/mmcm0. The
name of the auto-generated clock is cpuClk and its definition point is
clkip/mmcm0/CLKOUT.
X-Ref Target - Figure 3-6
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Name Conflicts
In case of name conflict between two auto-generated clocks, the Vivado IDE adds unique
suffixes to differentiate them, such as:
• usrclk
• usrclk_1
• usrclk_2
• ...
The arguments that must be specified are the new generated clock name and the source
object of the generated clock. The -source and -master parameters must be used only
when more than one clock propagates through the source pin in order to remove any
ambiguity.
Limitations
• Auto-derived clocks can only be renamed at the pin where they originate, such as at
the output of the Clock Modifying blocks (PLL, MMCM, ...). For example, an
auto-derived clock cannot be renamed at the output of a BUFG even though it
propagates through it.
• Primary clocks or user-defined generated clocks cannot be renamed. Only auto-derived
clocks can be renamed with this mechanism.
• A generated clock cannot be renamed if any constraint references the generated clock
prior to its definition. This can occur when constraints using clock queries are located
before the auto-derived name constraint:
° get_clocks clockName
If some timing constraints do reference the generated clock, the constraints must be
re-organized so that the renaming of the auto-derived clock happens before the clock is
referenced
An error is returned if the tool cannot rename the generated clock. The master clock must
also exist at the time the renaming is done.
For example, below is an abstract of report_clocks for the generated clock at the
output pins of an MMCM:
====================================================
Generated Clocks
====================================================
The three commands below illustrate the command line options that must be specified to
rename the three auto-derived clocks at the output of the MMCM:
create_generated_clock -name clk_rx [get_pins
clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKOUT0]
create_generated_clock -name clk_tx [get_pins
clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKOUT1]
create_generated_clock -name clkfbout [get_pins
clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKFBOUT]
Clock Groups
This section discusses Clock Groups and includes:
Use the schematic viewer or the Clock Networks Report to visualize the topology of the
clock trees, and determine which clocks must not be timed together. You can also use the
Clock Interactions Report to review the existing constraints between two clocks, and
determine whether they share the same primary clock -- that is, they have a known phase
relationship -- or identify the clocks with no common period (unexpandable).
CAUTION! Ignoring timing analysis between two clocks does not mean that the paths between them
will work properly in hardware. In order to prevent metastability, you must verify that these paths have
proper re-synchronization circuitry, or asynchronous data transfer protocols.
Clock Categories
This section discusses the following Clock Categories:
• Synchronous Clocks
• Asynchronous Clocks
• Unexpandable Clocks
Synchronous Clocks
Two clocks are synchronous when their relative phase is predictable. This is usually the case
when their tree originates from the same root in the netlist, and when they have a common
period.
For example, a generated clock and its master clock that have a period ratio of 2 are
synchronous because they propagate through the same netlist resources up to the
generated clock source point, and have a common period of 2 cycles. They can be safely
timed together.
Asynchronous Clocks
Two clocks are asynchronous when it is impossible to determine their relative phase.
For example, two clocks generated by separate oscillators on the board and entering the
FPGA device by means of different input ports have no known phase relationship. They
must therefore be treated as asynchronous. If they were generated by the same oscillator
on the board, this would not be true.
In most cases, primary clocks can be treated as asynchronous. When associated with their
respective generated clocks, they form asynchronous clock groups.
Unexpandable Clocks
Two clocks are not expandable when the timing engine cannot determine their common
period over 1000 cycles. In this case, the worst setup relationship over the 1000 cycles is
used during timing analysis, but the timing engine cannot ensure this is the most
pessimistic case.
This is typically the case between two clocks with an odd fractional period ratio. For
example, consider two clocks, clk0 and clk1, generated by two MMCMs that share the
same primary clock:
Their rising clock edges do not realign within 1000 cycles. The timing engine uses a setup
path requirement of 0.01ns on the timing paths between the two clocks. Even if the two
clocks have a known phase relationship at their clock tree root, their waveforms do not
allow safe timing analysis between them.
As with asynchronous clocks, the slack computation appears normally, but the value cannot
be trusted. For this reason, unexpandable clocks are often assimilated to asynchronous
clocks. Both clock categories must be treated the same way for constraining and
clock-domain crossing circuitry.
IMPORTANT: The set_clock_groups command has higher priority over the regular timing
exceptions. If you need to constrain and report some paths between asynchronous clocks, you must use
the timing exceptions only, and not set_clock_groups .
If the name of the generated clocks cannot be predicted in advance, use get_clocks
-include_generated_clocks to dynamically retrieve them. The -include_generated_clocks
option is an SDC extension.
Because these cells are combinatorial cells, the Vivado IDE propagates all incoming clocks
to the output. With the Vivado IDE, several timing clocks can exist on a clock tree at the
same time, which is convenient for reporting on all the operation modes at once, but is not
possible in hardware.
Such clocks are called exclusive clocks. Constrain them as such by using the options of
set_clock_groups:
• -logically_exclusive, or
• -physically_exclusive
An MMCM instance generates clk0 and clk1 which are connected to the BUFGMUX instance
clkmux. The output of clkmux drives the design clock tree.
By default, the Vivado IDE analyzes paths between clk0 and clk1 even though both clocks
share the same clock tree and cannot exist at the same time.
You must enter the following constraint to disable the analysis between the two clocks:
The following options are equivalent in the context of Xilinx FPGA devices:
• -physically_exclusive
• -logically_exclusive
The physically and logically labels refer to various signal integrity analysis (crosstalk) modes
in ASIC technologies which is not needed for Xilinx FPGA devices.
Clock Latency
After propagating on the board and inside the FPGA device, the clock edges arrive at their
destination with a certain delay. This delay is typically represented by:
• The source latency (delay before the clock source point, usually, outside the device)
• The network latency
The delay introduced by the network latency (also called insertion delay) is either:
For Xilinx FPGA devices, use the set_clock_latency command primarily to specify the
clock latency outside the device.
set_clock_latency Example
# Minimum source latency value for clock sysClk (for both Slow and Fast corners)
set_clock_latency -source -early 0.2 [get_clocks sysClk]
# Maximum source latency value for clock sysClk (for both Slow and Fast corners)
set_clock_latency -source -late 0.5 [get_clocks sysClk]
Clock Uncertainty
Clock Jitter
For ASIC devices, clock jitter is usually represented with the clock uncertainty characteristic.
However, for Xilinx FPGA devices, the jitter properties are predictable. They can be
automatically computed by the timing analysis engine, or be specified separately.
Input Jitter
Input jitter is the difference between successive clock edges with respect to variation from
the nominal or ideal clock arrival times.
Use the set_input_jitter command to specify input jitter for each primary clock
individually. You cannot specify the input jitter on a generated clock directly. The Vivado IDE
timing engine automatically computes the jitter that a generated clock inherits from its
master clock.
• For the case in which the generated clock is driven by a MMCM or a PLL, the input jitter
is replaced with a computed discrete jitter.
• For the case the generated clock is created by a combinatorial or sequential cell, the
generated clock jitter is the same as its master clock jitter.
System Jitter
Use the set_system_jitter command to set only one value for the whole design, that
is, all the clocks.
• set_input_delay
• set_output_delay
Input Delay
The set_input_delay command specifies the input path delay on an input port relative
to a clock edge at the interface of the design.
VIDEO: For training videos on input delay, see the Vivado Design Suite QuickTake Video: Setting
Input Delay.
When considering the application board, the input delay represents the phase difference
between:
a. The data propagating from an external chip through the board to an input package
pin of the FPGA device, and
b. The relative reference board clock.
Consequently, the input delay value can be positive or negative, depending on the clock
and data relative phase at the interface of the device.
RECOMMENDED: When using a virtual clock, use the same waveform as the design clock related to the
input ports inside the design. This way, the timing path requirement is realistic. Using a virtual clock is
convenient for modeling different jitter or source latency scenarios without modifying the design clock.
If neither is used, the input delay value applies to both min and max.
Do not confuse the -clock_fall option with the -rise and -fall options. These options
refer to the data edge and not to the clock edge.
This option is commonly used to constrain an input port relative to more than one clock
edge, as, for example, DDR interfaces.
You can apply an input delay constraint only to input or bi-directional ports, excluding clock
input ports, which are automatically ignored. You cannot apply an input delay constraint to
an internal pin.
This example defines an input delay relative to a previously defined sysClk for both min
and max analysis.
This example defines an input delay relative to a previously defined virtual clock.
This example defines a different input delay value for min analysis and max analysis relative
to sysClk.
This example creates constraints from data launched by both rising and falling edges of the
clk_ddr clock outside the device to the data input of the internal flip-flop that is sensitive to
both rising and falling clock edges.
Additional Examples
For additional examples, refer to Xilinx Answer Record 59893 [Ref 13].
Output Delay
The set_output_delay command specifies the output path delay of an output port
relative to a clock edge at the interface of the design.
VIDEO: For training videos on output delay, see the Vivado Design Suite QuickTake Video: Setting
Output Delay.
When considering the application board, this delay represents the phase difference between:
a. The data propagating from the output package pin of the FPGA device, through the
board to another device, and
b. The relative reference board clock.
The output delay value can be positive or negative, depending on the clock and data
relative phase outside the FPGA device.
RECOMMENDED: When using a virtual clock, use the same waveform as the design clock related to the
output ports inside the design. This way, the timing path requirement is realistic. Using a virtual clock
is convenient for modeling jitter or source latency scenarios without modifying the design clock.
Do not confuse the -clock_fall option with the -rise and -fall options. These
options refer to the data edge, not the clock edge.
The same is true for a min output delay constraint. This option is commonly used to
constrain an output port relative to more than one clock edge, as, for example, rising and
falling edges in DDR interfaces, or when the output port is connected to several devices
that use different clocks.
IMPORTANT: You can apply an output delay constraint only to output or bi-directional ports. You
cannot apply an output delay constraint to an internal pin.
This example defines an output delay relative to a previously defined sysClk for both min
and max analysis.
This example defines an output delay relative to a previously defined virtual clock.
This example specifies output delay value relative to a DDR clock with different values for
min (hold) and max (setup) analysis.
This example creates constraints from data launched by both rising and falling edges of the
clk_ddr clock outside the device to the data output of the internal flip-flop sensitive to
both rising and falling clock edges.
Timing Exceptions
The Xilinx ® Vivado® Integrated Design Environment (IDE) supports the timing exceptions
commands shown in Table 5-1, Timing Exceptions Commands.
Multicycle Paths
The Multicycle Path constraint allows you to modify the setup and hold relationships
determined by the timer, based on the design clock waveforms. By default, the Vivado IDE
timing engine performs a single-cycle analysis. This analysis can be too restrictive, and can
be inappropriate for certain logic paths.
The most common example is the logical path that requires more than one clock cycle for
the data to stabilize at the endpoint. If the control circuitry of the path startpoint and
endpoint allows it, Xilinx recommends that you use the Multicycle Path constraint to relax
the setup requirement.
The hold requirement might still maintain the original relationship, depending on your
intent. This helps the timing-driven algorithms to focus on other paths that have tighter
requirements and that are challenging. It can also help in reducing runtime.
set_multicycle_path Syntax
The syntax of the set_multicycle_path command with the basic options is:
You must specify the <path_multiplier>. The default values used by the timer are:
The hold relationship is tied to the setup relationship. Use the following formula to retrieve
the number of hold cycles for most common cases:
• By default, the setup path multiplier is defined with respect to the destination clock. To
modify the setup requirement with respect to the source clock, use the -start
option.
• Similarly, the hold path multiplier is defined with respect to the source clock. To modify
the hold requirement with respect to the destination clock, use the -end option.
Note: For a definition of the relevant terms, see this link in the Vivado Design Suite User Guide:
Design Analysis and Closure Techniques (UG906) [Ref 4] .
IMPORTANT: There are two hold relationships for each setup relationship. (1) The first hold
relationship ensures that the setup launch edge is not captured by the edge arriving before the active
capture edge. (2) The second hold relationship ensures that the edge after the active launch edge is not
captured by the active capture edge. The timing analysis tool calculates both hold relationships but
only the most restrictive is kept during analysis and reporting. See Figure 5-1.
IMPORTANT: The -start and -end options have no apparent effect when applying a Multicycle
Path constraint on paths clocked by the same clock or clocked by two identical clocks (that is, when the
clocks have the same waveform with or without a phase shift).
Table 5-2, Active Launch and Capture Edges, summarizes how the active launch and capture
edges are affected by the -end and -start options.
Table 5-2: Active Launch and Capture Edges
Source Clock (-start) Destination Clock (-end)
Moves the launch edge Moves the capture edge
Setup <---- (backward) ----> (forward) (default)
IMPORTANT: The -setup option of the set_multicycle_path command does not only
modify the setup relationship. It also affects the hold relationships which are always tied to the setup
relationships. If the hold relationship is to be restored back to its original position, another
set_multicycle_path specification would be needed with -hold .
Note: A Multicycle constraint can be set on a single path, on multiple paths, or even between two
clocks.
The following sections cover the common Multicycle Path constraint scenarios and illustrate
the impact of the setup and hold multipliers and the -start and -end options on the
timing path requirement.
The default Setup and Hold relationships that are resolved by the Static Timing Analysis
(STA) tool are shown in Figure 5-3.
X-Ref Target - Figure 5-3
• Setup check
TDatapath(max) < TCLK(t=Period) - TSetup
• Hold check:
TDatapath(min) > TCLK(t=0) + THold
This link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques
(UG906) [Ref 4] describes how the hold relationships are derived from the setup
relationships. When modifying the setup relationship, the hold relationships are also
modified to follow the changes in the setup launch and capture edges.
IMPORTANT: If the new hold requirements become too aggressive, it will likely result in difficult timing
closure. It is the your responsibility to relax the hold requirement assuming it is safe for the design.
In the same example as Figure 5-4, after moving the setup check to the second capture
edge, the hold check is automatically moved to the first capture edge (that is, one clock
period before the setup check).
Figure 5-5 shows how both the setup and hold relationships have changed when only the
setup path multiplier has been defined with the Multicycle Path constraint.
X-Ref Target - Figure 5-5
Holding the data in the data0_reg for one cycle is not needed for this path to be
functional due to the clock enable. In this case, Xilinx recommends changing the hold
relationship back to the original, which is between the same launch and capture edges. To
do so, you must add a second Multicycle Path constraint that modifies the hold check only:
The -end option is used with set_multicycle -hold command because the edges of
the capture clock must be moved backward.
Note: Because the launch and capture clocks have the same waveforms, the -end option is
optional. Moving the capture edges backward result in the same hold relationship as moving the
launch edges forward. To simplify the expressions, the -end option has been removed from the next
two examples.
Figure 5-6 shows the updated setup and hold relationships after applying both Multicycle
Path constraints.
X-Ref Target - Figure 5-6
To summarize this example, the following constraints are necessary to properly define a
multicycle path of two (2) between data0_reg/C and data1_reg/D:
For a multicycle with a setup multiplier of four (4), the constraints are:
By default, the setup multiplier is applied against the capture clock. This results in moving
the edge on the capture clock forward. The setup capture edge comes after five clock
periods instead of just one. Because no hold multiplier has been specified, the edge of the
capture clock used for the hold check stays the edge that arrives one cycle before the active
edge used for the setup check.
The edges on the launch clock do not change for the setup and hold relationships.
X-Ref Target - Figure 5-8
With a four-cycle hold requirement, the timing-driven implementation tools usually have to
insert a large amount of delay in the datapath in order to meet hold timing in both Slow and
Fast timing corners. This results in unnecessary area and power consumption. For this
reason, it is important to relax the hold requirement when possible.
In this example design, the clock enable signal provides the safety to not have to hold the
data in the data0_reg for four cycles without risking metastability. Example Two: Setup=5
/ Hold=4 describes how the hold requirement can be relaxed.
By default, the setup multiplier is applied against the destination clock, which in this case
results in moving the capture edge forward to the fifth cycle instead of the first cycle.
Accordingly, by default, the hold check follows the setup check.
On specifying the second command, the hold multiplier is applied against the source clock,
which in this case results in moving the launch edge forward to the fourth cycle.
X-Ref Target - Figure 5-9
Because both source and destination clocks have the same waveforms, and are
phase-aligned, Figure 5-9 is equivalent to Figure 5-10.
X-Ref Target - Figure 5-10
IMPORTANT: In general, within a clock domain or between two clocks with the same waveform, when
a setup multiplier of N is defined, define a hold multiplier of N-1 (most common case) as shown below:
For example, assume that: (1) the two clocks CLK1 and CLK2 have the same waveform; and
(2) CLK2 is shifted by +0.3ns.
The setup relationship is calculated by the timing engine by: (1) looking at all the edges on
both waveforms; and (2) selecting the two edges on the launch and capture clocks that
result in the stricter constraint.
Because of the clocks phase-shift, the setup and hold relationships used by the timing
engine might not be those expected. See Figure 5-12.
X-Ref Target - Figure 5-12
In this example, the setup constraint due to the phase-shift is 0.3ns. This makes it almost
impossible to achieve timing closure. On the other hand, the hold check is -3.7ns, which is
too lenient.
The setup and hold edges must be adjusted to match your intent. This is done by adding a
Multicycle constraint with a setup multiplier of two (2):
This results in moving the capture edge for the setup requirement forward by one cycle. The
default edge for the hold is derived from the setup requirement. It does not need to be
specified.
X-Ref Target - Figure 5-13
Figure 5-13: Default Scenario of Positive Phase-Shift: Setup 2 (-end), Hold Moved Accordingly
In the case of negative phase-shift, as shown in Figure 5-14, between the two clock
domains, the launch and capture edges used for the setup and hold checks are similar to
those from the previous section (single clock domain, no phase-shift).
X-Ref Target - Figure 5-14
For example, assume that: (1) CLK2 is three times the frequency of CLK1; and (2) a clock
enable signal on the receiving registers allows a Multicycle constraint to be set between
both clocks. See Figure 5-16.
X-Ref Target - Figure 5-16
The setup and hold relationships that are resolved by the STA tool when no multicycle is
applied are shown in Figure 5-17.
X-Ref Target - Figure 5-17
The consequence of the setup multiplier is to move the edge of the capture clock used for
setup check forward by two (2) cycles (that is, 3-1 cycles). Because no hold multiplier has
been specified, the hold relationship is derived by the tool from the setup launch and
capture edges. The launch clock active edge is not modified by the Multicycle constraint.
The setup and hold relationships after the multicycle are shown in Figure 5-18.
X-Ref Target - Figure 5-18
There is no need to hold the data in the launch registers for one cycle of CLK2 for this path
to be functional. Doing so adds unnecessary logic, which increases area and consumes
power.
Because the receiving registers have a clock enable signal, it is safe to relax the hold
requirement without risks of metastability.
TIP: If-end is not specified with set_multicycle_path -hold, then the launch clock edge is
instead moved forward. This does not result in the intended hold requirement.
As in the Example One: Setup=3 / Hold Moved Accordingly, the setup multiplier moves the
edge of the capture clock used for setup check forward by two (2) cycles (that is, 3-1 cycles).
The setup and hold relationships after the two Multicycle constraints are shown in
Figure 5-19.
X-Ref Target - Figure 5-19
IMPORTANT: For a SLOW-to-FAST clock domain crossing, when a setup multiplier of N is defined,
define a hold multiplier of N-1 against the capture clock (-end ) (most common case) as shown in the
following code example:
In the next example, the launch clock CLK1 is the fast clock. The capture clock CLK2 is the
slow clock. Assume that CLK1 is three (3) times the frequency of CLK2. See Figure 5-21.
X-Ref Target - Figure 5-21
The setup and hold relationships that are resolved by the STA tool when no multicycle is
applied are shown in Figure 5-22.
X-Ref Target - Figure 5-22
The consequence of the defining the setup multiplier against the launch clock (-start) is
to move the edge of the launch clock used for setup check backward by two (2) cycles (that
is, 3-1 cycles). However, because a hold multiplier is defined against the launch clock
(default -start option with -hold) the edge of the launch clock that is used for the hold
relationship is moved forward by two (2) cycles.
For both setup and hold checks, the capture clock edge does not change. See Figure 5-23.
X-Ref Target - Figure 5-23
IMPORTANT: For a FAST-to-SLOW clock domain crossing, define a setup multiplier of N against the
launch clock (-start ) with a hold multiplier of N-1 (most common case). See the following example:
Note: The get_clocks command has been omitted in Table 5-3 to simplify the expressions.
False Paths
A false path is a path that topologically exists in the design but either: (1) is not functional;
or (2) does not need to be timed. Consequently, the false paths should be ignored during
timing analysis.
Vivado
VIDEO: For training videos on the advanced timing exceptions, including false paths, see the
Design Suite QuickTake Video: Advanced Timing Exceptions - False Path, Min-Max Delay
and Set_Case_Analysis.
• Clock domain crossings in which double synchronizer logic has been added
• Registers that might be written once at power up
• Reset or test logic
• Ignore paths between the write and asynchronous read clocks of an asynchronous
distributed RAM (when applicable)
Figure 5-24 shows an example of a non-functional path. Because both multiplexers are driven
by the same select signal, the path from Q to D does not exist, and should be defined as a
false path.
X-Ref Target - Figure 5-24
TIP: Use a Multicycle constraint in place of a False Path constraint when: (1) your intent is only to relax
the timing requirements on a synchronous path; but (2) the path still must be timed, verified and
optimized.
• Decrease Runtime
When false paths have been removed from the timing analysis, the tool does not need
to time or optimize those non-functional paths. Having non-functional paths visible to
the timing and optimization engines can result in a large runtime penalty.
Removing false paths can greatly enhance the Quality of Results (QOR). The quality of
the synthesized, placed, and optimized design is greatly impacted by the timing issues
that the tool tries to solve.
If some non-functional paths have timing violations, the tool might try to fix those paths
instead of working on the real functional paths. Not only might the design unnecessarily
increase in size (such as logic cloning), but the tool might skip fixing real issues because
non-functional paths have larger violations that overshadow other real violations. The
best results are always achieved with a realistic set of constraints.
False paths are defined inside the tool with the Xilinx Design Constraints (XDC) command
set_false_path:
There are additional options to the command to fine tune the path specification. For
detailed information about all supported command line options, see the Vivado Design
Suite Tcl Command Reference Guide (UG835) [Ref 9].
• The list of nodes for the -from option should be a list of valid startpoints. A valid
startpoint is a clock object, a clock pin of a sequential element, or an input (or inout)
primary port. Multiple elements can be provided.
• The list of nodes for the -to option should be a list of valid endpoints. A valid endpoint
is a clock object, an output (or inout) primary port, or a sequential element input data
pin. Multiple elements can be provided.
• The list of nodes for the -through option should be a list of valid pins or ports.
Multiple elements can be provided.
CAUTION! Be careful when using -through option without -from and -to because it removes
from timing analysis any path going through this list of pins or ports. Be especially careful when the
timing constraints are designed for an IP or a sub-block, but then used in a different context or a larger
project. Many more paths than expected could be removed when -through is used alone.
The order of the -through option is important. See the following examples.
The following example removes the timing paths from the reset port to all the registers:
The following example disables the timing paths between two asynchronous clock domains
(for example, from clock CLKA to clock CLKB):
The previous example disables the paths from clock CLKA to clock CLKB. Paths from clock
CLKB to clock CLKA are not disabled. Accordingly, disabling all the paths between the two
clock domains in either direction requires two set_false_path commands:
IMPORTANT: Although the previous two set_false_path examples perform what is intended, when two
or more clock domains are asynchronous and the paths between those clock domains should be
disabled in either direction, Xilinx recommends using the set_clock_groups command instead:
In the non-functional path example shown in Figure 5-24, page 111, the false path can be set
using the -through option instead of using the -from or -to option. See Figure 5-25.
X-Ref Target - Figure 5-25
This ensures that all the paths going through the path shown above are selected without
needing to find specific patterns for the startpoints and endpoints.
Note: The order of the -through option is important. In the above example, the order ensures
that the false paths go through pin MUX1/a0 first and then pin MUX2/a1 .
Another common example is with asynchronous dual-ports distributed RAM. The write
operations are synchronous to the clock RAM but the read operations can be asynchronous
when permitted by the design. In this case, it is safe to false paths the timing paths between
the write and the read clocks.
• Define a false path from the write registers before the RAM to the registers after the
RAM receiving the read clock:
set_false_path -from [get_cells <write_registers>] -to [get_cells <read_registers>]
set_false_path -from [get_cells -hier -filter {REF_NAME =~ RAM* && IS_SEQUENTIAL &&
NAME =~ *char_fifo*}]
Figure 5-26 illustrates the way the distributed RAM is driven in the WAVE (HDL) example
project.
X-Ref Target - Figure 5-26
Min/Max Delays
You can override a maximum delay or a minimum delay for a path:
• Use the Maximum Delay constraint to override the default setup (or recovery)
requirement on a path.
• Use the Minimum Delay constraint to override the default hold (or removal)
requirement.
VIDEO: For training videos on the advanced timing exceptions, including min-man delays, see the
Vivado Design Suite QuickTake Video: Advanced Timing Exceptions - False Path, Min-Max Delay and
Set_Case_Analysis.
Additional command options are available to fine tune the path specification. For more
information about the supported command line options, see the Vivado Design Suite Tcl
Command Reference Guide (UG835) [Ref 9].
By default, the timing engine includes the clock skew inside the slack computation.
The -datapath_only option can be used to remove the clock skew from the slack
computation. The -datapath_only option is supported only by the set_max_delay
command, and requires the -from option.
Table 5-4, Differences Between Max Delay Constraint With and Without -datapath_only,
summarizes the impact of -datapath_only in the behavior of set_max_delay
constraint.
The common behavior for the path delay calculation of set_max_delay with or without
-datapath_only is:
• Input delay is included in the path delay calculation when the path starts on an input
port and that a set_input_delay has been specified on the port
• Output delay is included in the path delay calculation when the path ends on an output
port and that a set_output_delay has been specified on the port
• The data pin setup time is included in the path delay calculation when the path ends on
the data pin of a sequential element.
Table 5-4: Differences Between Max Delay Constraint With and Without -datapath_only
set_max_delay set_max_delay -datapath_only
Path delay calculation Skew included when the constraint starts Skew never included.
on the clock pin of a sequential element
or ends on the data pin of a sequential
element.
Hold Requirement Untouched False-ed path
-from Option Optional Mandatory
Note: Using the -datapath_only option with set_max_delay results in the hold
requirement being false-ed path on that/those path(s) (some internal set_false_path -hold constraints
are generated).
Similarly, setting a Minimum Delay constraint on a path does not modify the default setup
(or recovery) check.
If a path has only, for example, a max delay requirement, the path can be constrained with
a combination of set_max_delay and set_false_path commands. See the following
example:
The above example sets a 5ns setup requirement for the path starting on FD1/C and ending
on FD2/D. There is no minimum requirement due to the set_false_path command.
For the same reason, the output logic between the last level of registers and the output
ports is typically constrained with the set_output_delay command. However, the
set_max_delay command and the set_min_delay command are typically used to
constrain pure combinational path between primary input ports and primary output port
(in-to-out I/O paths).
For example, timing paths between two asynchronous clock domains can be disabled with
the set_clock_groups command (recommended) or the set_false_path command
(not recommended). This assumes that you have properly designed the inter-clock domains
with, for instance, a double registers synchronizer or a FIFO. However, you must still ensure
that the path delay between the two clock domains is not unnecessarily high.
If a maximum delay must be specified for some or for all the paths between two clock
domains, then you must use the command set_max_delay -datapath_only to
constrain those paths. In this case, set_clock_groups cannot be used to define the two
clock domains as asynchronous, as it supersedes the set_max_delay constraint in terms
of constraint priority. Other cross clock domains paths must then be constrained with a
combination of set_false_path or set_max_delay constraints.
Path Segmentation
Unlike other XDC constraints, the set_max_delay command and the set_min_delay
command can accept, in the case of -from and -to options, a list of invalid startpoints or
endpoints respectively.
When an invalid startpoint is specified, the timing engine breaks the timing arcs going
through the node so that the node does become a valid startpoint.
If the constraint is applied to FD1/Q, the timing engine breaks the timing arc C->Q to make
the pin Q a valid startpoint:
Note: Because of Path Segmentation, no clock insertion delay is used for the launch clock for paths
starting from FD1/Q. This can potentially result in large skew because the clock skew of the endpoints
is still taken into account. See Figure 5-29 .
X-Ref Target - Figure 5-29
CAUTION! Path segmentation can have unexpected consequences. Avoid path segmentation
altogether, or use it very carefully.
After path segmentation, there is no default hold requirement on the path. Assuming the
-datapath_only option has not been specified, use the set_min_delay command to set a
hold requirement on the path if necessary.
Because of the risks, a critical warning is issued when a path segmentation occurs.
If you targeted the output FD1/Q as the startpoint in order to avoid taking the clock skew
into account, Xilinx recommends using the -datapath_only option. Instead, see the
following example:
In the same way, when an invalid endpoint is specified, the timing engine breaks the timing
arcs after the node so that the node does become a valid endpoint.
In the following example, the max delay is specified on LUTA/O, which is not a valid
endpoint:
To make LUTA/O an endpoint, the timing arc after LUTA/O is broken. As a result, all timing
paths going through LUTA/O are impacted for both setup and hold. For the path starting
on REGA/C and ending on LUTA/O, only the insertion delay of the launch clock is taken into
account. This can result in very large skew.
Because path segmentation breaks timing arcs in the design, it can have unexpected
consequences. The broken timing arcs impact all the timing paths going through those
nodes.
In the following example, a max delay has been set between LUTA/O and REGB/D:
Scenario 1
set_max_delay <ns> -datapath_only -from <instance> -to <instance>
In this scenario, instance names are provided for -from/-to. The set_max_delay
constraint is always overridden by set_clock_groups -asynchronous, because
Vivado always selects valid startpoints when an instance is provided.
Scenario 2
set_max_delay <ns> -datapath_only -from <pin> -to <pin | instance>
In this scenario, if the pin name provided with -from results in path segmentation, then
that particular set_max_delay constraint is not overriden by set_clock_groups
-asynchronous. The reason behind is that the path segmentation forces the path starting
on the pin name to no longer being considered launched by the first clock domain. As a
result, this path is no longer covered by the set_clock_groups constraints and the
set_max_delay constraint get applied.
Case Analysis
In some designs, certain signals have a constant value in specific modes. For instance, in
functional modes, the test signals do not toggle and are therefore tied either to VDD or VSS
depending on their active level. This also applies to signals that do not toggle after the
design has been powered up. In the same way, today's designs have multiple functional
modes and some signals that are active in some of the functional modes might be inactive
in other modes.
To help reduce the analysis space, runtime and memory consumption, it is important to let
the Static Timing Engine know about the signals that have a constant value. This is also
critical to ensure that non-functional and irrelevant paths are not reported.
VIDEO: For training videos on the advanced timing exceptions, including set_case_analysis, see
the Vivado Design Suite QuickTake Video: Advanced Timing Exceptions - False Path, Min-Max Delay
and Set_Case_Analysis.
When the values ris(e)(ing) or fall(ing) are specified, this means that the given
pins or ports should only be considered for timing analysis with the specified transition. The
other transition is disabled.
A case value can be set on a port, a pin of a leaf cell, or a pin of a hierarchical module.
In the example below, two clocks are created on the input pins of the multiplexer clock_sel
but only clk_2 is propagated through the output pin after setting the constant value on the
selection pin S.
X-Ref Target - Figure 5-32
Note: Setting a case value on a pin results in disabling timing analysis through that pin. This means
that timing paths through that pin are not reported.
Some timing arcs are automatically disabled by the timer to handle specific cases. For
instance, combinational feedback loops are not recommended and cannot be properly
timed. The timer breaks such loops by disabling one of the timing arcs inside the loop.
Another example is a case analysis set on a MUX. By default, all the data inputs of a MUX are
propagated to the output port but when a case analysis is set on the select signals, only one
data input port gets propagated to the output port. This is done by the timer by breaking
timing arcs from the other data input ports to the output port.
The set_disable_timing command gives you the ability to manually break cell timing
arcs in the design. You can, for example, decide which timing arc(s) of a combinational
feedback loop should be disabled to break the loop instead of letting the tool make this
determination.
Also, suppose that multiple clocks arrive on a LUT input pins but only one clock should be
propagated to the LUT output port. This scenario can be handled by breaking the timing
arcs associated to the clocks that should not propagate.
There is also a scenario involving LUTRAM that can be quite frequent. Inside the LUTRAM,
there is physical path from WCLK pin to the output O pin between the write and read clocks.
However, LUTRAM-base asynchronous FIFO are designed in such way that this CDC path
WCLK->O cannot happen by construction. Nevertheless, this timing arc is enabled and can
result is the timer reporting paths through this WCLK->O timing arc. This arc can also
trigger some TIMING-10 DRC violations. In such case, the user should disable the WCLK->O
arc so that those paths are not timed and reported and that they do not trigger invalid DRC
violations. This timing arc is automatically disabled in the current implementation of the
Xilinx LUTRAM-based FIFO.
Note: After a timing arc is disabled, no timing path will be reported by the timer through this arc.
You should be very careful to not disable any valid timing arc. This might result is masking some
timing violations and/or timing problems that could result in the design failing in hardware.
Only pin names and not Vivado objects can be provided to the -from and -to command
line options. The pin names should also match pin names from the library cell, not design
pin names. For example:
The above command disables the WCLK->O timing arcs for all the LUTRAM-based
asynchronous FIFOs inst_fifo_gen/ gdm.dm/gpr1.dout_i_reg[*].
The command line options -from and -to are optional. If -from is not specified, then all
the timing arcs ending on the pin specified with -to are being disabled. In the same way if
-to is not specified, then all the timing arcs starting on the pin specified with -from are
being disabled. If neither -from nor -to are specified, then all the timing arcs of the cells
specified in the command are disabled.
You can use the command report_disable_timing to list all the timing arcs that have
been automatically disabled by the timer as well as manually disabled by the user. Be careful
as the list can be very large. Use the -file command line option to save the result in a file.
XDC Precedence
In this example, the second clock definition overrides the first clock definition because:
Exceptions Priority
If constraints overlap (for example, if several timing exceptions are applied to the same
path), the priority from highest to lowest is:
In addition, for the same type of exception, the more specific the constraint, the higher the
precedence. Depending on the filtering options and the type of objects used in the
constraint, you can modify the specificity of a constraint.
The precedence rule for the filters, from highest to lowest, is:
In this example, the first constraint overrides the second constraint for the paths from clk1
to clk2.
The number of -through options used in an exception does not affect the precedence. The
timing engine uses the tightest constraint.
Both exceptions are kept by the timing engine. The more challenging constraint is used for
timing analysis. In this example, the 4ns max delay constraint will be used even for paths
going through the pin inst1/I3.
RECOMMENDED: You must avoid using several timing exceptions on the same paths, so that the timing
analysis results are not dependent on priority rules, and it is easier to validate the effect of your
constraints.
If a string instead of an object is passed to the constraint, the Tcl interpreter uses the
following sequence to determine which object matches the string:
1. port
2. pin
3. cell
4. net
The search is not exhaustive. As soon as objects of a certain type match the string pattern,
they are returned, even though objects of another type down the list might also match the
same pattern.
Physical Constraints
Critical Warning
Critical Warnings are issued for invalid constraints in XDC files, including those applied to
objects that cannot be found in the design.
For property definition and usage, see the Vivado Design Suite Properties Reference Guide
(UG912) [Ref 10].
RECOMMENDED: Xilinx highly recommends that you review all Critical Warnings to ensure that the
design is properly constrained. Invalid constraints result in errors when applied interactively.
Netlist Constraints
Netlist constraints are set on netlist objects such as ports, pins, nets or cells, to require the
compilation tool to handle them in special way.
IMPORTANT: Be sure that you understand the impact of using these constraints. They might result in
increased design area, reduced design performance, or both.
• CLOCK_DEDICATED_ROUTE
• MARK_DEBUG
• DONT_TOUCH
• LOCK_PINS
CLOCK_DEDICATED_ROUTE
Set CLOCK_DEDICATED_ROUTE on a net to indicate how the clock signal is expected to be
routed.
MARK_DEBUG
Set MARK_DEBUG on a net in the RTL to preserve it and make it visible in the netlist. This
allows it to be connected to the logic debug tools at any point in the compilation flow.
For more information, see this link in the Vivado Design Suite User Guide: Programming and
Debugging (UG908) [Ref 11].
DONT_TOUCH
Set DONT_TOUCH on a leaf cell, hierarchical cell, or net object to preserve it during netlist
optimizations. DONT_TOUCH is most commonly used to:
Sometimes it is best to manually replicate logic, such as a high-fanout driver that spans
a wide area. Adding DONT_TOUCH to the manually replicated drivers (as well as the
original) prevents synthesis and implementation from optimizing these cells.
TIP: Avoid using DONT_TOUCH on hierarchical cells for implementation as Vivado IDE
implementation does not flatten logical hierarchy. Use KEEP_HIERARCHY in synthesis to maintain
logical hierarchy for applying XDC constraints.
LOCK_PINS
LOCK_PINS is a cell property used to specify the mapping between logical LUT inputs (I0, I1,
I2, …) and LUT physical input pins (A6, A5, A4, …).
A common use is to force timing-critical LUT inputs to be mapped to the fastest A6 and A5
physical LUT inputs.
I/O Constraints
I/O constraints configure:
• Ports
• Cells connected to ports
• I/O standard
• I/O location
The Vivado Integrated Design Environment (IDE) supports many of the same I/O constraints
as the Integrated Software Environment (ISE®) Design Suite. The following list of I/O
properties is not exhaustive.
° For a complete list of I/O properties, more information on I/O port and I/O cell
properties, and coding examples with proper syntax, see the Vivado Design Suite
Properties Reference Guide (UG912) [Ref 10].
Note: All properties are applied to port objects unless otherwise stated.
° For more information on the application and methodology behind these properties,
see the device SelectIO documents, for example 7 Series FPGAs SelectIO Resources
User Guide (UG471) [Ref 12].
• DRIVE
Sets the output buffer drive strength (in mA), available with certain I/O standards only.
• IOSTANDARD
• SLEW
Sets the slew rate (the rate of transition) behavior of a device output.
• IN_TERM
Sets the configuration of the input termination resistance for an input port
• DIFF_TERM
Turns on or off the 100 ohm differential termination for primitives such as
IBUFDS_DIFF_OUT.
• KEEPER
• PULLTYPE
Applies a weak logic low or high level on a tri-stateable output or bidirectional port to
prevent it from floating.
• DCI_CASCADE
Defines a set of master and slave banks. The DCI reference voltage is chained from the
master bank to the slaves. DCI_CASACDE is set on IOBANK objects.
• INTERNAL_VREF
Frees the Vref pins of an I/O Bank and uses an internally generated Vref instead.
INTERNAL_VREF is set on IOBANK objects
• IODELAY_GROUP
Groups a set of IDELAY and IODELAY cells with an IDELAYCTRL to enable automatic
replication and placement of IDELAYCTRL in a design.
• IOB
Tells the placer to try to place FFs in I/O Logic instead of the fabric slice.
IMPORTANT: There are notable differences between the ISE Design Suite and the Vivado Design Suite
in the handling of IOB. The Vivado tool allows IOB to be set on both ports and on register cells
connected to ports. If conflicting values are set on a port and its register, the value on the register
prevails. The Vivado tool uses only the values TRUE and FALSE. The value FORCE is interpreted as TRUE,
and the value AUTO is ignored. Unlike ISE, if a setting of IOB true cannot be honored, the Vivado tool
generates a critical warning, not an error.
Placement Constraints
Placement constraints are applied to cells to control their locations within the device. The
Vivado Integrated Design Environment (IDE) supports many of the same placement
constraints as the Integrated Software Environment (ISE) Design Suite and the PlanAhead™
tool.
• LUTNM
A unique string name applied to two LUTs to control their placement on a single LUT
site.
Unlike HLUTNM, LUTNM can be used to combine LUTs that belong to different
hierarchical cells.
• HLUTNM
A unique string name applied to two LUTs in the same hierarchy to control their
placement on a single LUT site.
• PROHIBIT
• PBLOCK
PBLOCK is a read-only cell property that is the name of the Pblock to which the cell is
assigned. Cell Pblock membership can be changed only by using the XDC Tcl commands
add_cells_to_pblock and remove_cells_from_pblock.
• PACKAGE_PIN
Specifies the location of a design port on a pin of the target device package.
• LOC
• BEL
Places a logical element from the netlist to a specific BEL within a slice on the device.
Placement Types
There are two types of placement in the tools:
• Fixed Placement
• Unfixed Placement
Fixed Placement
Fixed placement is placement specified by the user through:
• Hand placement, or
• An XDC constraint
• Using either of the following on a cell object of the design loaded in memory:
° IS_LOC_FIXED
° IS_BEL_FIXED
Unfixed Placement
Unfixed placement is a placement performed by the implementation tools. By setting the
placement as fixed, the implementation cannot move the constrained cells during the next
iteration or during an incremental run. A fixed placement is saved in the XDC file, where it
appears as a simple LOC or BEL constraint.
• IS_LOC_FIXED
• IS_BEL_FIXED
Place a LUT in the C5LUT BEL position within a slice and fix its BEL assignment.
Locate input bus registers in ILOGIC cells for shorter input delay.
Combine two small LUTs into a single LUT6_2 that uses both O5 and O6 outputs.
Prevent the placer from using the first column of block RAMs.
Routing Constraints
Routing constraints are applied to net objects to control their routing resources.
Fixed Routing
Fixed Routing is the mechanism for locking down routing, similar to Directed Routing in
ISE®. Locking down a net routing resources involves three net properties. See Table 7-1,
Net Properties.
To guarantee that a net routing can be fixed, all of its cells must also be fixed in advance.
Following is an example of a fully-fixed route. The example takes the design in Figure 7-1,
Simple Design to Illustrate Routing Constraints, and creates the constraints to fix the
routing of the net netA (selected in blue).
X-Ref Target - Figure 7-1
You can query the routing information of any net after loading the implemented design in
memory:
The routing is defined as a series of relative routing node names with fanout denoted using
embedded curly braces. The routing is fixed by setting the following property on the net:
To back-annotate the constraints in your XDC file for future runs, the placement of all the
cells connected to the fixed net must also be preserved. You can query this information by
selecting the cells in the schematics or device view, and look at their LOC/BEL property
values in the Properties window. Or you can query those values directly from the Tcl
console:
Because fixed routes are often timing-critical, LUT pins mapping must also be captured in
the LOCK_PINS property of the LUT to prevent the router from swapping pins.
Again, you can query the site pin of each logical pin from the Tcl console:
The complete XDC constraints required to fix the routing of net netA are:
If you are using interactive Tcl commands instead of XDC, several placement constraints can
be specified at once with the place_cell command, as shown below:
For more information on place_cell, see the Vivado Design Suite Tcl Command Reference
Guide (UG835) [Ref 9].
Configuration Constraints
Configuration constraints are global constraints for bitstream generation that are applied
to the current design. This includes constraints such as the configuration mode.
For a list of bitstream generation properties and definitions, see this link in the Vivado
Design Suite User Guide: Programming and Debugging (UG908) [Ref 11].
• FF
• LUT
• DSP
• RAM
RPMs are primarily used to place small groups of logic close together in order to:
• Each element of the set is placed in relation to the other elements of the set by Relative
Location (RLOC) constraints.
• Logic elements with RLOC constraints and common set names are associated in an
RPM.
TIP: You can use the create_macro and update_macro commands to define macro objects in the
Vivado Design Suite, that act like RPMs within the design. Refer to the Vivado Design Suite Tcl
Command Reference (UG835) [Ref 9] for more information on these commands.
For more information on U_SET, HU_SET, and RLOC constraints, see the Vivado Design Suite
Properties Reference Manual (UG912) [Ref 10].
Creating an RPM
To create an RPM:
The grouping occurs by using an H_SET constraint that is implicitly defined by the
combination of the design hierarchy and the RLOC constraint.
All design elements with RLOC constraints in a single block of the design hierarchy are
considered to be in the same H_SET unless they are tagged with another set constraint, such
as U_SET or HU_SET.
Design elements tagged with a U_SET constraint can be primitive or non-primitive symbols.
All cells with the same hierarchically qualified set_name are members of the same set.
U_SET Example
(* U_SET = "uset0", RLOC = "X0Y0" *) FD my_reg (.C(clk), .D(d0), .Q(q0));
HU_SET Example
(* HU_SET = "huset0", RLOC = "X0Y0" *) FD other_reg (.C(clk), .D(d1), .Q(q1));
RPM sets must be embedded as properties in HDL source files. After synthesis, RPM related
properties appear on netlist objects as read only properties for use by the Xilinx Vivado®
Integrated Design Environment (IDE) placer.
TIP: RPMs can be placed and locked down by dragging from the Physical Constraints to the Device
window. The RPMs are moved as a single shape instead of cell-by-cell.
To specify the RLOC property, use either of two different grid coordinate systems:
RLOC=XmYn
where
The relative grid is a standard rectangular grid in which each grid element is the same size.
For example, the following Verilog code example results in an eight-slice-high column with
an FD cell in each slice:
Because the cells can occupy sites of various sizes, the RPM_GRID system uses absolute
RPM_GRID coordinates. The RPM_GRID values are visible in the Site Properties window of
the Vivado Integrated Design Environment (IDE) when a specific site is selected. The
coordinates can also be queried with Tcl commands using the RPM_X and RPM_Y site
properties.
As long as at least one cell has the RPM_GRID property equal to GRID, the RPM_GRID
coordinate system is used.
Although the RPM_GRID coordinates are absolute based on the target device, they define
the relative placement of the elements of an RPM set.
During implementation, the RPM set can be placed at any suitable location on the device.
• Are stored as RPM_X and RPM_Y properties on device sites in the Vivado tool.
• Can be queried using get_property.
Because the RPM_GRID coordinates must be extracted from the target device, you will
probably need to:
• Iterate on the design to find the right RPM_GRID values after synthesis.
• Add the coordinates as properties in the RTL source files.
• Resynthesize the netlist before placement.
The following example shows a hierarchical RPM that is fixed using RLOC_ORIGIN. RLOC
constraints are assigned to the RPM register cells to create a two-up-by-three-across
placement pattern.
In Verilog:
The RPM is instantiated into the design three times with an RLOC on each cell:
TIP: Although RPMs control the relative placement of logic elements, they do not insure that specific
routing resources are used to connect the logic from one implementation to the next.
For more information on controlling the routing used, see Routing Constraints, page 135.
XDC Macros
XDC macros enable assignment of relative placement to cells after synthesis. Macros have
many characteristics similar to RPMs, but are design objects that can be modified
interactively using XDC and Tcl. Macros are created from leaf cells that are grouped
together with relative placement constraints.
While RPMs are managed in HDL code, macros are managed using XDC constraints. RPMs
cannot be automatically converted to macros. Similarly, macros cannot be automatically
annotated to HDL code. Unlike macros, RPMs are not objects, and the XDC macro
commands cannot be used on RPMs.
Specifying Macros
Use the following XDC Tcl commands to specify macros:
• create_macro
• update_macro
• delete_macros
• get_macros
create_macro
The create_macro command creates a new macro object.
Macro names must be unique. Attempting to create a macro with the same name as an
existing macro generates an error.
create_macro Syntax
create_macro <name>
create_macro Example
create_macro m0
TIP: To ensure LUT-FF alignment, specify the BEL location when creating your macro.
update_macro
The update_macro command adds leaf cells and relative placements (RLOCs) to the
macro.
The RLOC has identical syntax and functionality as the RPM RLOC attribute. All cells must be
specified at once. No partial or incremental definition is allowed.
update_macro Syntax
update_macro [-absolute_grid] <macro name> <cell-RLOC list>
where
• -absolute_grid: A switch to choose the Absolute Grid for mixing slice and non-slice
sites.
° The X-Y values are the site properties RPM_X and RPM_Y.
° All macro cells and RLOCs must be specified at once. It is not possible to build a
macro in steps.
The following (update_macro Example Two) does the same, with slightly different syntax.
delete_macros
The delete_macros command deletes the specified macros.
delete_macros Syntax
delete_macros <pattern>
delete_macros Example
delete_macros m1
get_macros
The get_macros command returns macro objects in a design.
get_macros Syntax
get_macros [pattern]
With no arguments, the get_macros command returns all macros in the design. When
macro names are specified, the command returns the corresponding macro objects.
get_macros Examples
The get_macros command can be used with other object commands. Examples:
% create_macro m1
% update_macro m1 {u2/sr0 X0Y0 u2/sr1 X0Y1}
% get_cells -of [get_macros m1]
u2/sr0 u2/sr1
% get_macros -of [get_cells u2]
m1
The following command returns all macros that are fully contained within the cells.
Managing Macros
Macros are stored as XDC constraints. By definition, they are Tcl commands. This allows the
macros to be used in both XDC constraint files and Tcl scripts, and used interactively.
Macros are written using the write_xdc command. Macros are read using the read_xdc
command. The -cell option can be used to limit scope to particular cells.
The -cell option is particularly useful for applying a relative placement from one macro to
similar instances in different hierarchies.
% write_xdc constrs.xdc
% create_macro m0
% update_macro m0 {reg0 X0Y0 reg1 X0Y1}
% write_xdc -cell inst_0 inst_0.xdc
Read the XDC constraints including the macro m0 from cell inst_0, and apply it to inst_1
and inst_2:
TIP: When a macro is read and applied to another cell using the -cell option, the new macro name
must be unique. The cell name is applied as a prefix to the macro name to create a unique macro name.
In Example Four, two new unique macros were created: inst_1_m0 and inst_2_m0.
Macro Properties
Macro objects have the following properties:
• ABSOLUTE_GRID
• CLASS
• NAME
• RLOCS
ABSOLUTE_GRID
Boolean property that reflects whether or not the RLOCs are using the default grid system
or the Absolute Grid system.
The default is false. If update_macro is used with -absolute_grid, then the property is
true.
The Absolute Grid uses coordinates that align with site RPM_X and RPM_Y properties to
allow creating macros from cells placed at different site types.
CLASS
NAME
Name of the macro object, either the name used by create_macro, or the macro name
prefixed by the cell hierarchy when using read_xdc -cell.
RLOCS
String containing the list of macro cells and their RLOC properties in the same format used
by the update_macro command.
RLOCS Example
The following simple example illustrates the relative placement derived from macro RLOCs.
The macro consists of a pair of SRL >FF >FF circuits that are to be arranged in a 2x2 pattern.
See Figure 8-3, Schematic of Example Circuit, page 152.
X-Ref Target - Figure 8-3
To create the desired relative placement, the cells are assigned RLOCs as follows:
srl[0] X0Y0
regs0[0] X0Y0
regs1[0] X1Y0
srl[1] X0Y1
regs0[1] X0Y1
regs1[1] X1Y1
create_macro m0
update_macro m0 {srl[0] X0Y0 regs0[0] X0Y0 regs1[0] X1Y0 srl[1] X0Y1 regs0[1] X0Y1
regs1[1] X1Y1}
The macro can be automatically placed by the placer or manually placed as a set. The macro
placement appears as shown in Figure 8-4, Placement of the Macro Example, page 153.
X-Ref Target - Figure 8-4
The macro contains SRLs which are based on LUTRAMs, and which can be placed only in
SLICEM type slices. This places slight restrictions on the possible locations of the macro. The
macro can be located only where a SLICEL column is to the right of a SLICEM column.
CAUTION! Too many densely packed slices in proximity can cause congestion, which reduces routability
and can negatively impact performance.
The absolute grid (also known as the RPM grid) is an absolute coordinate system that
defines the coordinates of a site based on its location within the device. The absolute grid
also considers the sizes of sites: RAM and DSP blocks have wider spacing than slices. The
absolute grid is illustrated in Figure 8-5, Example Circuit for Absolute Grid, page 154.
In this example, there are cells from three different types to group into a macro using the
absolute grid. The example consists of an input data path from input ports, through two
stages of registers, then block RAMs. This is illustrated in the schematic in Figure 8-5,
Example Circuit for Absolute Grid, page 154.
X-Ref Target - Figure 8-5
The macro creation requires a list of cells and their relative locations (RLOCs) using the
absolute grid. When creating the macro, it might be difficult to visualize the relative
placement of absolute grid macros.
RECOMMENDED: Place the cells temporarily into absolute locations in the device, then derive the
absolute grid RLOC values of each cell.
The cells are first manually placed and arranged in their desired locations as shown in
Figure 8-6, Manually Placed Cells for an Absolute Grid Macro, page 155.
X-Ref Target - Figure 8-6
Although the absolute grid specifies absolute locations, the resulting macro can be placed
at any location within the device that can accommodate the relative placement of the
macro. In this example, the relative locations are specified using the lower-left hand corner
as the point of reference.
However, the absolute grid locations specify only relative placement, not absolute
placement. That allows the macro to be located anywhere in the device that maintains the
relative placement.
Because the example is somewhat complex, consisting of ILOGIC, slices, and block RAM, the
macro locations are somewhat restricted but can be placed at any of the three locations
highlighted in orange in Figure 8-7, Three Possible Locations for the XDC Macro, page 156.
Selecting the site (not the cell) displays the following values of 33 for RPM_X and 0 for
RPM_Y (Figure 8-8). These are the absolute grid coordinates. The corresponding RLOC value
is X33Y0.
X-Ref Target - Figure 8-8
The same method is applied to determine the absolute RLOC of a slice (Figure 8-9). The
cells within this slice have an RLOC of X31Y0.
X-Ref Target - Figure 8-9
There are two commands used to create the macro, with a name m0:
create_macro m0
update_macro m0 -absolute_grid <cell0 rloc0 cell1 rloc1 cell2 rloc2 … cellN rlocN>
If the macro contains many cells as it does in this example, Tcl can be used to simply
building and specifying the cell-rloc list required by update_macro. Given a placed cell,
the absolute grid RLOC can be determined using the following Tcl proc getAbsRLOC:
proc getAbsRLOC {cell} {
set site [get_sites -of [get_cells $cell]]
set X [get_property RPM_X $site]
set Y [get_property RPM_Y $site]
return "X${X}Y${Y}"
}
Example: assign the variable rloc to the string value of a block RAM cell RLOC
% set rloc [getAbsRLOC $ram0]
X33Y0
The Tcl dict command can be used to build a dictionary (associative array) of cells and
absolute grid RLOCs for the update_macro command. A Tcl associative array is a series of
key-value pairs. The cells and RLOCs can be arranged as such as series using the dict
command. The array keys are the macro cell objects. The array values are the cell RLOCs.
This helps to automate the process of creating macros with many cells. The following
example uses the absolute grid, but the method can be applied to the normal grid as well.
Assuming $cells is the list of macro cells, and each cell of $cells has been placed to form
the desired macro pattern, the following Tcl proc creates a list of cell-RLOC pairs for the
update_macro command.
proc buildRLOCList {cells} {
set rlocs [dict create] ; # initialize dictionary called rlocs
foreach cell $cells {
# dictionary key is cell, value is absolute RLOC
dict set rlocs $cell [getAbsRLOC $cell]
}
return $rlocs
}
If there are many macro cells and macro cells buried in hierarchy, specifying the explicit list
of cell-RLOC pairs can become complicated and error prone. The creation and management
of XDC macros can be made simpler using Tcl.
[-top_net_of_hierarchical_group]
[-segments]
[-boundary_type arg]
get_pins get_pins
[-hierarchical] [-hierarchical]
[-hsc separator] [-hsc arg]
[-regexp] [-regexp]
[-nocase] [-nocase]
-of_objects objects [-of_objects args]
patterns [patterns]
[-leaf]
[-filter arg]
[-match_style arg]
get_ports get_ports
[-regexp] [-regexp]
[-nocase] [-nocase]
patterns [patterns]
[-filter arg]
[-of_objects args]
[-match_style arg]
set_case_analysis set_case_analysis
value value
port_or_pin_list objects
• set_clock_gating_check
• set_clock_transition
• set_ideal_latency
• set_ideal_network
• set_ideal_transition
• set_max_fanout
Note: Maximum fanout is controlled by the MAX_FANOUT attribute during synthesis.
• set_drive
• set_driving_cell
• set_fanout_load
• set_input_transition
• set_max_area
• set_max_capacitance
• set_max_transition
• set_min_capacitance
• set_port_fanout_number
• set_resistance
• set_timing_derate
• set_voltage
• set_wire_load_min_block_size
• set_wire_load_mode
• set_wire_load_model
• set_wire_load_selection_group
• create_voltage_area
• set_level_shifter_strategy
• set_level_shifter_threshold
• set_max_dynamic_power
• set_max_leakage_power
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.
Solution Centers
See the Xilinx Solution Centers for support on devices, software tools, and intellectual
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troubleshooting tips.
References
Vivado Design Suite User and Reference Guides
The following Vivado® Design Suite guides are referenced in this document.
11. Vivado Design Suite User Guide: Programming and Debugging (UG908)
12. 7 Series FPGAs SelectIO Resources User Guide (UG471)
Training Resources
Xilinx provides a variety of training courses and QuickTake videos to help you learn more
about the concepts presented in this document. Use these links to explore related training
resources:
1. Vivado Design Suite QuickTake Video: Advanced Clock Constraints and Analysis
2. Vivado Design Suite QuickTake Video: Advanced Timing Exceptions - False Path,
Min-Max Delay and Set_Case_Analysis
3. Vivado Design Suite QuickTake Video: Setting Input Delay
4. Vivado Design Suite QuickTake Video: Setting Output Delay
5. Vivado Design Suite QuickTake Video: Migrating UCF Constraints to XDC
6. Vivado Design Suite QuickTake Video Tutorials