Appendix I

Synthesizable and Non-Synthesizable

Verilog Constructs

The list of synthesizable and non-synthesizable Verilog constructs is tabu-lated in the following
Table
Verilog Used for Synthesizable Non-Synthesizable
Constructs construct Construct
module The code inside the module and Yes No
the endmodule consists of the
declarations and functionality of
the design
Instantiation If the module is synthesizable Yes No
then the instantiation is also
synthesizable
initial Used in the test benches No Yes
always Procedural block with the reg Yes No
type assignment on LHS side.
The block is sensitive to the
events
assign Continuous assignment with Yes No
wire data type for modeling the
combinational logic
primitives UDP’s are non-synthesizable Yes No
whereas other Verilog primitives
are synthesizable
force and These are used in test benches No Yes
release and non-synthesizable
delays Used in the test benches and No Yes
synthesis tool ignores the delays
fork and join Used during simulation No Yes
ports Used to indicate the direction, Yes No
input, output and inout. The
input is used at the top module
parameter Used to make the design more Yes No
generic
time Not supported for the synthesis No Yes
(continued)

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400 Appendix I: Synthesizable and Non-Synthesizable Verilog Constructs

(continued)
real Not supported for synthesis No Yes
functions and Both are synthesizable. Provided Yes No
task that the task does not have the
timing constructs
loop The for loop is synthesizable and Yes No
used for the multiple iterations.
Verilog Used for arithmetic, bitwise, Yes No
Operators unary, logical, relational etc are
synthesizable
Blocking and Used to describe the Yes No
non-blocking combinational and sequential
assignments design functionality respectively
if-else, case, These are used to describe the Yes No
casex, casez design functionality depending
on the priority and parallel
hardware requirements
Compiler Used during synthesis Yes No
directives
(‘ifdef,‘undef,
‘define)
Bits and part It is synthesizable and used for Yes No
select the bit or part select
Appendix II
Xilinx Spartan Devices

• Xilinx Spartan 3 Devices

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V. Taraate, Digital Logic Design Using Verilog,
DOI 10.1007/978-81-322-2791-5
402 Appendix II: Xilinx Spartan Devices

• Spartan 3 Family Architecture

• Xilinx Spartan 3 Package information for Part no XC3S400-4PQ208C

Appendix II: Xilinx Spartan Devices 403

For more information please use the following link http://www.xilinx.com/support/

documentation/data_sheets/ds099.pdf.

• Xilinx FPGA Spartan 3E Devices

• Xilinx Spartan 3E Architecture

404 Appendix II: Xilinx Spartan Devices

• Xilinx Spartan 3E package information

For more information please use the following link http://www.xilinx.com/support/

documentation/data_sheets/ds312.pdf.
Appendix III
Design For Testability

The Design For Testability (DFT) and its necessity is discussed in summarized

In the practical ASIC design, the DFT is used to find out various kinds of faults in
the design. For FPGA designs this step is excluded. The necessity of DFT is for
early detection of the faults in the design using scan chain insertions. The func-
tional abstraction of defects is called as fault and the abstraction of the fault is the
system level error. Physical testing is carried out after manufacturing of chip to
understand the fabrication-related issues or faults.
The defects in the design can be physical or electrical. Physical defects are due to
silicon or defective oxide. Electrical defects are short, open, transistor defects and
changes in the threshold voltage.
Few of the faults in the design are following
1. Stuck at faults: Stuck at one or Stuck at zero
2. Memory faults or pattern-sensitive faults
3. Bridging faults
4. Cross point faults
5. Delay faults
Testing process is the process of test pattern generation, test pattern application
and output evaluation.
Generally, the test flow includes the following:
1. Identify the target faults
2. Test generation
3. Fault Simulation
4. Testability
5. DFT

• Design For Testability (DFT)

The DFT is required to reduce the defect level in the design. Consider the
following design; in this design it is not possible to give the test input so design
is not testable. The DFT uses the concept of controllability and observabilty.
The key steps are

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406 Appendix III: Design For Testability

1. RTL design
2. Simulation
3. Synthesis
4. Insert scan chain
5. Layout
If every data input of the register need to be forced to the known value during the
test, then the design is controllable.
Observability indicates the ability to observe the node at primary output. The
de-sign needs to be controllable and observable.
As shown in the following design, the design input of comb_logic1 is control-
lable and the output from comb_logic3 is observable. But comb_logic1 and
comb_logic2 are not observable. So for detection of faults, it is essential to make
comb_logic1, comb_logic2, and comb_logic3 controllable as well as observable.

comb_l comb_l comb_l

ogic1 ogic2 ogic3

clk

• The basic DFT techniques are: Ad-HOC DFT and Structured DFT. The struc-
tured DFT includes the scan-based DFT which is again classified as MUX -
based DFT and level–sensitive, element-based DFT. An-other structured DFT
technique is MBIST and LBIST. JTAG is used for boundary scan.
Basic MUX-based technique is described below.
• MUX-based scan cell
The MUX-based scan cell is shown below and it has additional inputs as
Test_data, Scan_en. The MUX is inserted at the input of the D flip-flop and
during testing Scan_en=1 the D input is Test_data. During normal operation, the
Scan_en=0 and Data_in can pass through the combinational logic to the D input.
Thus, the following cell works both in the test and normal modes. The clk can
be scan_clk during the test mode.
Appendix III: Design For Testability 407

Data_in comb_l Q_out

ogic2
D
Test_data

Scan _en

clk

• MUX-based scan chain:

Normally used method is insertion of scan by using MUX logic. MUX-based
scan cell shown in the above figure is used to replace the sequential elements
from the design. Depending on the requirements the design team decides
whether to use partial scan method or full scan method.
In the partial scan method few of the sequential elements are replaced by the
MUX based scan cell. In the full scan method, all the sequential elements are
re-placed by the MUX-based scan cell.
Due to scan insertion, the area and timing of the design has significant impact.
Scan insertion increases the area of the design and due to added MUX-based
logic even it affects on the timing of the design. The following example shows
the scan chain using MUX-based scan cells.
Most of the time, the partial scan is recommended if area and timing is the
constraint but this reduces overall fault coverage. If full scan is used then it
increases area and has significant impact on timing but this improves overall
fault coverage.

comb_
Data_in comb_
logic2
logic1
D D comb_

Test_data logic3

Scan _en

clk
408 Appendix III: Design For Testability

• Scan Design rules

Following are few of the scan design rules need to be considered:

1. Generated clocks in the design: There should not be generated clocks in the
design as they are not controllable
2. Combinational feedback loop: There should not be any combinational loop in
the design as it creates issues in the timing analysis and hence it is essential to
break the combinational loop
3. Gated clocks: Gated clocks need to be avoided as they are not controllable
4. Asynchronous Control signals: There should not be any internally generated
asynchronous control signals
5. Do not mix the positive and negative edge triggered flip-flops
6. Avoid use of latches in the design
7. If shift registers are used then do not replace them by using scan enabled flip-
flops but only ensure the enable control
8. Do not use the clock input as data
9. Bypass the memories during DFT
Index

Symbols Area utilization, 98

#0delay assignments, 80 Arithmetic logic unit (ALU), 172
$display, 229 Arithmetic operations, 11, 39
$finish, 229 ASIC chip designs, 2
$monitor, 80, 229 ASIC design, 197
$strobe, 80 ASIC library, 389
1 line to 2 or (1:2) decoder, 61 ASIC porting, 383
14 nanometer (nm), 261 Asynchronous, 322
100 K gates, 300 Asynchronous counters, 138
2 line to 4 or (2:4) decoder, 66 Asynchronous design, 249
2:1 MUX, 54 Asynchronous path, 295
20 nanometer (nm), 261 Asynchronous pulse generator, 169, 248
4 line to 16 or (4:16) decoder, 67 Asynchronous reset, 109, 156, 157
4:1 MUX, 57 Asynchronous reset ‘reset_n’, 200
40 nanometer (nm), 261 Attribute, 308
50% duty cycle, 266
B
A Barrel shifter, 192
Acknowledgment or notification, 329 Basic cell or base cell, 257
Active, 80 Baud rate control block., 396
Active event queue, 80 Begin-end, 150
Active power, 364 Behavior, 9
Adders, 38 Behavioral, 7
Addition, 179 Bidirectional, 10
AHB, 386 Bidirectional IO, 395
Algorithms, 386 Bidirectional shift register, 130
Altera, 242 Binary counter, 114
ALU, 392 Binary encoding, 244
ALU architecture, 172 Binary-to-Gray, 49, 342
always, 11, 222, 369 Bit-stream, 238
Analyze, 264 Bitwise operations, 16
AND, 173 Blocking (=), 10, 80, 217
AND logic, 32 Blocking assignments, 146, 243
Antifuse, 234 Block level, 389
Arbiters, 172, 391 Bluetooth, 382
Architecture, 3, 237, 259, 289 Boolean algebra, 2
Area, 369 Bottom-up, 3, 300
Area minimization, 30 BRAM, 235
Area optimization, 246 Buses, 397

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410 Index

C Constraints, 260
Cadence RTL Compiler, 259 Continuous assignment, 82, 92
Capture flip-flop, 282 Control and timing unit, 392
case, 57, 369 Control path, 165, 392
case construct, 92 Control signals, 325
case-endcase, 57, 93 Coverage goals, 388
Case equality, 97 CPLD, 230
Case inequality, 97 CPU, 256
Cell library, 263 create_clock, 265, 287
Characterize, 312 Cumulative delay, 160
Check_design, 265, 318 Current simulation time, 80
Check_timing, 318 Current_state, 198
Checker, 187, 228 Cycle accurate, 187
Chip level, 389 Cycles, 390
CLB, 232, 235 Cycle stealing, 154
clk initalization, 229
clk generator, 229 D
Clock balancing, 370 Data arrival time, 278, 281
Clock buffer, 370 Database, 263
Clock definitions, 286 Data buffers, 396
Clock domain, 161 Data integrity, 322
Clock domain crossing (CDC), 250, 322 Data path, 280, 364, 392
Clocked-based logic, 104 Data path synchronizer, 340
Clocked logic, 192 Data propagation, 390
Clock gating, 251, 363, 364, 366, 390 Data rate, 258
Clock gating structure, 161 Data required time, 281
Clocking boundary, 341 DCM, 235, 242
Clock path group, 285 DDR, 241
Clock skew, 242, 387 DDR II, 382
Clock to ‘q’ delay, 280 DDR III, 382
Clock tree, 363, 364, 387 Dead zone code, 273
Clock tree synthesis, 260 Debug, 303
CMOS, 360 Decoder, 58
CMOS logic, 2 Decrement, 179
Code converters, 49 default, 93, 217, 369
Coding guidelines, 79 Defining hierarchy, 390
Combinational logic, 10, 27 Delay operators, 185
Combinational loop, 245 Deserializer, 391
Combinational path, 286 Design compiler, 263
Combinational path group, 284 Design constraints, 5, 300
Combinational shifters, 192 Design environment, 302
Comparators, 46 Design implementation, 252
Compile, 267 Design object, 264, 301
Compile-characterize, 302 Design partitioning, 274, 306, 346, 386
Compiler, 314 Design performance, 79, 162, 163, 386
Computational blocks, 386 Design rule constraints, 300
Concentration and replication, 18 Design rule library, 261
Concurrent, 10 Design rules, 302
Concurrent execution, 161 Design specification, 257
Conditional assignments, 55 DesignWare, 262
Configuration data, 239 Device utilization summary, 239
Consolidated control signal, 334 DFT, 259, 389
Constant folding, 272 DFT friendly RTL, 390
Constants, 10 Differential IOs, 387
Index 411

Different phases, 324 FPGA, 230, 382

DLL, 239, 242 FPGA designs, 228
DMA controller, 391 FPGA prototyping, 382
DRC violations, 315 Frequency synthesis, 242
Drivers, 228 FSM, 197, 244, 314
Drive strength, 302 FSM coding, 200
DSP, 192, 382 FSM control, 340
DSP algorithms, 389 Full adder, 39, 98, 181
DSP blocks, 235 Full-case, 174
DSP filtering, 389 Full-case statement, 91
DUV, 226 Full-custom, 256
Dynamic, 278 Full subtractors, 41
Dynamic power, 251, 360 Functional and timing proven., 386
Dynamic voltage and frequency scaling, 365 Functional design specifications, 3
Functionality, 257
E Functional model, 3
EDA, 238, 387 Functional simulation, 238
EDA tool, 4, 300, 364 Functions, 172, 184
Edge triggered, 107
EDIF, 238 G
Efficient synthesis, 215 Gated clock, 161
Effort level, 252 Gate level netlist, 3, 260, 278, 303
Efforts levels, 267 GDSII, 360
Eight-bit parameterized counter, 130 GDSII file, 261
Elaborate, 264 General purpose, 387
Empty and full flag, 341 Geometric, 260
Enable, 67, 104 Glitches, 111, 157, 199
Encoder, 68 Glitches or hazards, 343
Encoding, 174, 291 Glitch free, 216, 244
Encounter from Cadence., 261 Global clock buffers, 247
End point, 284 Glue logic, 274, 306
Equality operators, 11 Gray counter, 123, 210, 342
Ethernet, 382 Gray encoding, 341
Even parity, 187 Gray-to-binary, 50, 341
Events, 390 group, 307
Exclusive OR, 34 group_path, 310

F H
Fabrication techniques, 258 Half adder, 38
False path, 295, 327 Half subtractor, 41
Fast debugging, 215 Handshaking, 338
Faults, 263 Handshaking mechanism, 391
Feasibility study, 385 Handshaking signals, 329
FFT, 386 Hazards, 111, 390
FIFO, 386, 396 HDL, 370
FIFO memory buffer, 338, 345 Hierarchical design, 302
FIR, 386 Hierarchies, 290
Flash memory, 233 High impedance, 11
Flip-flop, 103, 107 High speed, 257
Floor planning, 260 High-speed interfaces, 241
Four as to one MUX, 56 High speed IOs, 387
FPD, 230 Hold, 160
412 Index

Hold time, 260 Library models, 366

Hold time violations, 278, 346 Link library, 263
Hold violation, 280, 315 Linting tool, 250
Load, 302
I Logical equality, 97
I2C, 382 Logical flattening, 309
IC Compiler from Synopsys, 261 Logical inequality, 97
IEEE 1364-2005, 80 Logical operators, 11
IEEE 1801, 371 Logic capacity, 232
if-else, 57, 369 Logic cells, 238
if-else construct, 92 Logic density, 232
IIR, 386 Logic duplication, 246, 291
Inactive, 80 Logic gates, 27
Increment, 179 Longer runtime, 305
Incremental compilation, 309 Loss of correlation, 347
initial, 11, 220, 222 LUTs, 239
Input and output delay, 267
Input argument, 185 M
Input register path group, 284 Macrocells, 238
Input string, 185 Macros, 258
Input to reg path, 284 Map, 262
Instantiation, 8 Map_effort, 309
Instruction register and decoder logic, 392 Master mode, 233
Inter-assignment delays, 222 Master-slave flip-flops, 368
Interconnect, 232 Maximum area, 257
Interface, 258 Maximum operating frequency, 280
Internally generated clock, 157 Mealy, 198
Intra-assignment delays, 224 Mealy level to pulse, 200
IO blocks (IOB), 235, 238 Memory storage element, 107
IO high performance standards, 235 Metastability, 248, 324
IO interfaces, 387 Micro-architecture, 3, 172, 259, 289, 300, 388
IPs, 258, 382 Microprocessors, 256
Isolation, 371 Minimization techniques, 27
Isolation cell, 365, 371, 390 Minimum bus width, 369
Isolation control, 371 The min, max corner analysis, 287
Min or max, 267
J Missing ‘else’ clause, 95
Johnson counter, 127 Modeling levels, 390
Monitor, 80, 228
L Moore, Gordon, 2, 198
Latch-based designs, 163 Multibit adders and subtractors, 44
Latches, 103, 217 Multi-bit signals, 338
Late arrival, 332 Multi-Cycle Path (MCP), 295, 331, 343
Late arrival signal, 291 Multi phase clock, 165
Latency, 249, 297, 327, 340, 360 Multiple “always” block, 150
Launch flip-flop, 282 Multiple Vth, 364
Layout, 257 Multiple clock domain, 163
Leakage current, 360 Multiple clocks, 274
Legal converging, 329 Multiple control signals, 332
Level shifter, 371, 374, 390 Multiple Driver Assignment, 102
Level synchronizers, 325 Multiple driver error, 102
Level-to-pulse, 329 Multiple drivers, 245
Level triggered, 154 Multiple power domain, 382
Libraries, 5, 302 Multiplex decoding, 390
Index 413

Multiplex encoding, 292 Parentheses, 273

Multiplexers, 53, 98, 367 Parity checker, 189
Multiplier, 235, 386 Parity detectors, 48
MUX, 53 Parity generator, 187
MUX Synchronizer, 331 Partitioning of design, 172
Path groups, 315
N Performance, 232
NAND logic, 33 Performance constraints, 257
NBA, 80 Performance improvement, 177
NBA queue, 88, 150 Phase Shifting, 242
Negative clock skew, 283 Photo lithography, 261
Negative edge, 104 Physical verification, 261
Negative level sensitive D latch, 106 Pipelined design, 391
Nested if-else, 244 Pipelined processor, 389
Netlist, 238 Pipelined register, 163
Nets, 308 Pipelined stage, 313
Next_state, 198 Pipelining, 154, 161, 177, 290, 390
Next state logic, 199 PIPO registers, 132
Nonblocking, 10, 217, 243 PLA, 230
Non-blocking (<=), 80 Place and route, 252, 389
Non-blocking assignments, 80, 150, 189 PLL, 242, 382
Nonconverging, 328 Port interfaces, 306
Nonsynthesizable, 219 Ports, 308
Non-synthesizable constructs, 11 Positive clock skew, 282
NOR logic, 28 Positive edge, 104
Positive level sensitive latch, 104
O Positive slack, 290
Odd parity, 187 The post-synthesis verification, 246
One-hot encoding, 212, 244 Power, 184, 238, 259
Opcode, 172 Power compiler, 366
Operand, 181 Power domains, 371
Operand Isolations, 364 Power gating, 365
Optimization, 5, 184 Power management, 363
Optimization constraints, 300 Power planning, 260
Optimize, 262 Power rails, 371
Optimized netlist, 263 Power Shut-Off (PSO), 365
OR, 173 Power state tables, 371
OR logic, 28 Power switches, 371
Oscillatory behavior, 85 Pre layout STA, 260
Output register path, 284 Prime Time, 278
Output to reg path, 284 Priorities, 308
Priority encoders, 69
P The priority encoding, 292
Packaging, 258 Priority logic, 57, 92, 157
Packets, 386 Procedural assignments, 83
Parallel and multiplexing logic, 173 Procedural Block “always”, 146
Parallel execution, 386 Process, 302
Parallel input parallel output logic., 132 Processing algorithms, 389
Parallelism, 391 Process node, 360
Parallel logic, 57, 157 Processor, 392
Parameterized binary and gray counter, 123 Program and stack pointer, 392
Parameters, 10 Program Language Interface (PLI), 11
Parasitic (RC), 260 Programmable interconnects, 238
Parasitic capacitance, 361 Programmable logic devices (PLD), 230, 382
414 Index

Programmable Switch, 232 S

PROM, 230 SATA, 382
Propagation delay, 280, 313 Scan insertions, 263
Protocol, 172, 386, 391 SDC, 287, 295, 327
Prototype, 230, 382 Sdc commands, 300
Pulse stretcher, 329 SDF, 246
Pulse synchronizers, 330 Search_path, 263
Semiconductor, 383
R Semi-custom, 256
Race around conditions, 87 Sensitivity, 10
Race condition, 85 Sensitivity list, 81, 245
RAM, 140 Sequence detector, 212
Random test, 388 Sequential, 10
Read, 264 Sequential logic, 10, 103
Readability, 79, 198 Serial data, 396
Read empty logic, 352 Serializer, 391
Read synchronization, 352 Set_clock_latency, 287
Reduction operators, 19 Set_clock_uncertainty, 287
References, 308 Set_dont_touch, 305
Reg, 83 Set_input_delay, 287, 288
Register balancing, 290, 291, 313, 390 Set_output_delay, 287
Register duplications, 290 Set and reset, 370
Register retiming, 390 Set-don’t_touch_network, 369
Registered inputs and outputs, 174 Setup, 160
Register logic, 199 Setup time, 278
Register output logic, 160 Setup violation, 310
Register-to-register path, 174 Shift operators, 20
Register-to-register timing path, 313 Shift register, 127, 130, 146, 240
Reg to reg path, 284 Short-circuit power, 362
Relational operator, 18 Sign operands, 13
Report_constraints, 315 Silicon wafer, 257
Report_constraints_all, 315 Simulation, 220
Report_timing, 310 Simulation and synthesis mismatch., 90
Reset deassertion, 109, 346 Simulator, 5, 390
Reset recovery, 157 Single port RAM, 241
Reset synchronizer, 346 Skew, 266, 334
Reset tree, 156 Slack, 279, 310
Resource sharing, 47, 98, 174, 246 Slave mode, 233
Retention, 371 Slowest path in the design, 154
Retention cell, 373, 390 SOC, 172, 359, 382
Retention control, 373 SOC components, 391
Reusability, 79 SOC design, 228
Ring counter, 125, 226 SOC validation, 387
Ripple counter, 140 SPI, 382
Robust verification, 390 SPLD, 230
ROM, 140 SRAM, 233
Round robin, 393 SRAM memory cell, 233
RTL, 3, 259, 306 SRPG, 366
RTL code, 9 STA, 238, 278
RTL design, 284, 358 Standard cell, 256, 360
RTL synthesis, 3 State encoding, 215
Index 415

State machines, 274 Three-procedural block FSM, 200

State register, 199 Throughput, 360, 386
State transition, 200 Time borrowing, 154
State transition table, 210 Time budgeting, 154
Static, 278, 397 Time control, 185
Stratified event queue, 80 Time to market, 257
Stratified event queuing, 146 Timing analysis, 198, 277, 303
Stray capacitance, 361 Timing analyzer, 286
Structural, 7 Timing closure, 278
Structural design, 7 Timing goals, 286
Structured ASIC, 232 Timing issues, 247
Stuck at fault coverage, 389 The timing optimization, 308
Subroutine, 184 Timing or area, 238
Subtraction, 179 Timing parameters, 287
Subtractors, 41 Timing paths, 260
Switches, 371 Timing performance, 238
Switching activity, 362 Timing proven IPs, 383
Switching power, 161 Timing sequence, 327
Switch level design, 3 Timing summary, 315
Symbol_library, 263 Timing violation, 160, 174, 260, 280
Synchronization, 156, 391 Toggle flip-flop, 200
Synchronization failure, 324 Toggle synchronizer, 330
Synchronized asynchronous resets, 250 Too tight constraints, 278
Synchronizers, 274 Top-down, 3, 300
Synchronous, 114, 198 Top level, 274
Synchronous design, 114, 248, 286 Transactions, 390
Synchronous reset, 111, 157 Transistor, 2
Synopsys, 367 Transitions in the state diagram, 217
Synopsys_dc.setup, 263 Translate, 262
Synopsys DC, 300 Transport and inertial, 390
Synopsys Design Compiler, 259 Tri-state, 37, 102, 240
Synopsys PT, 278, 300 Two-level synchronizer, 250
Synthesis, 199, 238, 259, 387 Two stage level synchronizer, 109, 157
Synthesizable, 7
Synthesizable constructs, 392 U
Synthesizable RTL, 383 UART, 382, 396
Synthesized logic, 200 Unified Power Format (UPF), 370, 389
Synthesizer, 259 Unintended latches, 88
System C, 388 Unintentional combinational loops, 85
System Verilog, 388 Universal logic, 35, 55
Unknown, 11
T USB, 382
Target library, 262 User constraints, 315
Task, 172, 184
Technology constraints, 258 V
Technology library, 262 Vendor-specific power formats, 370
Temperature, 302 Verification, 259, 343
Testability, 260 Verification methodologies, 5
Testbench, 5, 219, 390 Verification planning, 388
Test plan, 388 Verilog, 2
Test vectors, 388 Verilog IEEE standards, 6
Three-bit down counter, 118 Verilog RTL, 3
Three-bit up counter, 114 Video decoders, 386
Three-bit up-down counter, 120 Virtex, 239
416 Index

Virtual clock, 266 Write full logic, 352

Voltage, 302 Write synchronization, 352
Voltage level, 374
X
W Xilinx, 242
Weight factor, 310 XILINX Spartan, 239
Wire, 82 XNOR, 34
Working directory, 263 XOR, 34, 173
Write command, 267 XOR logic, 55