INSTR F311: Electronic Instruments and Instrumentation Technology

Digital meters

BITS Pilani Dr. Sujan Yenuganti (office no: 5699 - O)

[email protected]
Pilani Campus
 Asynchronous counter

2-bit asynchronous binary counter

 The CLK is applied to the clock input (C) of the first flip flop (FF0), which will be always the LSB.

 The second flip flop FF1 is triggered by the Q0 output of FF0.

BITS Pilani, Pilani Campus
 Contd..

 Both the flip flops inputs are made

HIGH and are assumed to be
initially reset (Q LOW).

 The positive going edge of the 1st

clock pulse causes Q0 output of FF0
to go HIGH. At the same time Q0
output goes LOW and has no effect
on FF1.
J K Q(t+1)
 The positive going edge of the 2nd 0 0 Q(t) (no change)
clock pulse causes Q0 to go LOW.
0 1 0 (reset)
Output Q0 goes HIGH and triggers
FF1, causing Q1 to go HIGH. 1 0 1 (set)
1 1 Q’(t) (compliment)

BITS Pilani, Pilani Campus

 Contd..

4-bit asynchronous binary counter

BITS Pilani, Pilani Campus

 Contd..

Negative edge triggered flip flops

BITS Pilani, Pilani Campus

Clock pulse Q3 Q2 Q1 Q0

Initial state 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0  When the clock input goes high to

7 0 1 1 1
low, the flip flop toggles it output.
8 1 0 0 0
 Otherwise there is no change in state
9 1 0 0 1 at the output.
10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

16 0 0 0 0
 Decade counter

 The Modulus of a counter is the number of unique states which the counter will sequence.

 The maximum no of states of a counter is 2n, where n is the number of flip flops in the counter.

 A counter can be designed to have less than 2n states. This type of sequences are called truncated
sequences.

 One common counter with truncated sequence is Mod-10 counter, which is generally called as decade
counter.

 In these counters it is necessary to force the counter to truncate and recycle before going through all
possible states.

BITS Pilani, Pilani Campus

Clock pulse Q3 Q2 Q1 Q0

Initial state 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0 0 0 0 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

16 0 0 0 0
Decade counter

Mod 10 counter or decade counter

BITS Pilani, Pilani Campus

 Synchronous counter

Clock pulse Q1 Q0 J1 K1
Initial state 0 0 0 x
1 0 1 1 x
2 1 0 x 0
3 1 1 x 1
4 0 0

J1  Q0 K1  Q0

Q(t) Q(t+1) J K
2 bit synchronous binary counter 0 0 0 X
Excitation table
0 1 1 X
1 0 X 1
1 1 X 0
BITS Pilani, Pilani Campus
 Contd..
Clock pulse Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

Initial state 0 0 0 1 1

1 0 0 1 1 1

2 0 1 0 1 1

3 0 1 1 1 1

4 1 0 0 1 1
Excitation table
5 1 0 1 1 1

6 1 1 0 1 1 Q(t) Q(t+1) J K
7 1 1 1 1 1
0 0 0 X
8 0 0 0 1 1
0 1 1 X
1 0 X 1
J0  1 K0  1 J1  Q0 K1  Q0 1 1 X 0
J 2  Q1Q0 K 2  Q1Q0
BITS Pilani, Pilani Campus
 Contd..

3-bit synchronous binary counter J 3  Q2 Q1Q0

K 3  Q2 Q1Q0

4-bit synchronous binary counter

BITS Pilani, Pilani Campus

 Contd..

Mod 10 counter or decade counter J 3  Q3Q0  Q2 Q1Q0

_ _
J0  1 K 0  1 J1  Q0 Q3 K1  Q0 Q3 J 2  Q1Q0 K 2  Q1Q0 K 3  Q3Q0  Q2 Q1Q0

BITS Pilani, Pilani Campus

 3 digit display

 The system consists of three decade counters, BCD

to seven segment drivers and displays and one flip
flop which indicates only 1 when it is in set
condition.

 The first nine input pulses will be counted by the

first decade counter and displayed.

 On the tenth pulse, the first counter goes to 0 and

pulse output from the this counter triggers the second
decade counter.
Scale of 2000 counter
 The second counter will display now 1 and the
complete display will be 010.

BITS Pilani, Pilani Campus

 Contd..

 The next nine input pulses cause the first counter to go from 0 to 9
again, so that the compete display reads 019 on the 19th pulse.

 The 20th input pulse causes the first decade counter to display 0 once
again.

 At this time a pulse is given to the second counter from the first one.

 The 100th pulse will make the first and second decade counters to
display 0.

 At this time a pulse is given to the third counter from the second one.

 On the 1000th pulse, all the decade counters will display 000, and a
pulse is emitted from the third counter which triggers the flip flop
and turns on the display 1.
BITS Pilani, Pilani Campus
Linear ramp ADC

 Counting register, a linear ramp generator,

clock generator, AND gate and a voltage
comparator.

 The analog input voltage (Vin) is applied to

the comparator non inverting terminal.

 The ramp generator output (VR) is given to

the comparator inverting terminal.

 The comparator output (V1) and the clock

generator output are given as two inputs to
the AND gate.

BITS Pilani, Pilani Campus

 Contd..

 When VR is less than Vin then V1 remains high. The

moment when VR is equal to Vin then V1 goes low.

 V1 remains high during the time t1, the clock pulses

pass through the AND gate to the counting register.
At the end of t1, V1 goes low so that no more clock
pulses are passed through the AND gate.

 The time duration t1 for which the comparator output

is high is directly proportional to input voltage Vin.

BITS Pilani, Pilani Campus

 Waveform

 The register indicates the digital equivalent of the

clock pulses counted during t1 which is
equivalent to the analog input voltage.

 At the end of t2 , the negative going edge of the

ramp waveform resets the register to its zero
condition and ready for another cycle of A to D
conversion.

BITS Pilani, Pilani Campus

Digital ramp ADC

 A modified version of linear ramp ADC, here the

ramp generator is replaced by a DAC.

 The output wave form of DAC is a stair case,

incremented by each clock pulse passed to the
register.

 A rectangular wave control input is used to cycle

the entire system through the conversion process.

BITS Pilani, Pilani Campus

 Contd..

 The leading edge of the control input pulse resets

the register to zero at the start of the conversion
cycle, and also applies a high input voltage to one of
the three input AND gate.

 At this instant, the analog input is greater than the

DAC output, and so the comparator output is high,
thus allowing the AND gate to pass the clock pulses
to the counting register.

BITS Pilani, Pilani Campus

 Contd..

 When the register output is digital equivalent of the

analog input, this causes the comparator output to
switch to low and no clock pulses are passed to the
register and counting ceases.

 This condition is maintained for time t2 until the

control input switches to high again.

BITS Pilani, Pilani Campus

Ramp type DVM

 Two comparators: input and ground

comparator.

 A sampled rate multivibrator, a ramp

generator, Gate, Oscillator or clock generator
and a counter.

BITS Pilani, Pilani Campus

 Contd..

 At the start of the measurement cycle, a ramp voltage is

generated (counter reset to zero and the sampled rate
MV gives a pulse which initiates the ramp generation)

 The ramp voltage is continuously compared with the

input voltage to be measured. At the instant when these
voltages are equal, the input comparator generates the
start pulse, which opens the gate.

 The ramp continues until the second comparator senses

the ramp voltage has reached zero value. When the
ramp voltage reaches zero, the ground comparator
generates the stop pulse which closes the gate.

BITS Pilani, Pilani Campus

 Contd..

 The time duration of the gate opening is

proportional to the input voltage value.

 In the time interval between start and stop pulses,

the gate opens and the counter counts the pulses
from the oscillator.

 The magnitude of the count indicates the

magnitude of the input voltage applied.

BITS Pilani, Pilani Campus

 Dual slope Integrating type DVM

 An integrator, a comparator, counter and a control logic which operates the switches S to connect input
analog voltage and reference input voltage.
BITS Pilani, Pilani Campus
 Contd..

 At the start of the conversion process, the counter is reset and switch S is connected to input voltage VA

 The capacitor begins to charge and as soon as the integrator output goes below zero, the comparator
changes its state to high and the control logic allows the clock pulses to be counter by the counter.

 At the end of the fixed count interval (T1), the count is set at zero and the switch S is shifted to the
reference voltage VREF of opposite polarity.

 The integrator output voltage increases at a fixed rate until it rises above the comparator reference voltage,
(T2) at which the control logic receives a signal (the comparator output) to stop the count.

 The pulses counted by the counter during T2 has a direct relation with the input voltage VA.

BITS Pilani, Pilani Campus

Waveform
t
V At V AT1

1 V0  
V0   V A dt  
RC RC RC
0
t
1
V0  inital voltage 
RC 
(VREF )dt
0

V AT1 VREF t
V0 (t )   
RC RC

V AT1 VREF T2
0 
RC RC

BITS Pilani, Pilani Campus

Successive approximation type DVM

 SAR, ring counter, a comparator, DAC with

a reference voltage and a gate.

 When Vin is less than Vout then comparator

output is negative and it resets a particular
bit in SAR to low(0).

 The moment when Vin is greater than Vout

then comparator output is positive and it sets
a particular bit in SAR to high(1).

BITS Pilani, Pilani Campus

Microprocessor based ramp
type DVM

 A multiplexer having three inputs (1, 2 and 3)

and a comparator with two inputs (1 and 2).

 The input 1 of the comparator can be

consecutively connected to the inputs 1, 2 and 3
of the multiplexer, depending on the command
from the microprocessor.

 During the resting period of the

microprocessor, it signals to the ramp generator
to generate ramp voltage whose duration is Tr
and amplitude Vm

BITS Pilani, Pilani Campus

 Contd..

 When a conversion command arrives at the microprocessor at time ts, the μp connects the input 1 of the multiplexer
(ground) to the input 1 of the comparator and pauses until another ramp wave starts.

 The moment when the input 2 voltage coming from the ramp generator becomes equal to the input 1 of the comparator, it
sends a signal to μp that the ramp voltage is zero and the μp measures this time interval as t1.

 At the same time, a command from the μp causes the comparator input 1 to be connected to input 2 (unknown voltage Vx)
of the multiplexer.

 At an instant when the ramp voltage is equal to the unknown voltage, the comparator sends a signal to μp and the μp
measures this time interval as t2.

 At the same time, a command from the μp causes the comparator input 1 to be connected to input 3 (reference voltage
Vfs) of the multiplexer.

 At an instant when the ramp voltage is equal to the reference voltage, the comparator sends a signal to μp and the μp
measures this time interval as t3.

BITS Pilani, Pilani Campus