TIMERS AND COUNTERS

1. What is the counting rate of a machine cycle in correlation to the oscillator

frequency for timers?

a. 1 / 10
b. 1 / 12
c. 1 / 15
d. 1 / 20

ANSWER: b. 1 / 12

2. Which special function register play a vital role in the timer/counter mode
selection process by allocating the bits in it? 

a. TMOD
b. TCON
c. SCON
d. PCON 

ANSWER: a. TMOD

3. How many machine cycle/s is / are executed by the counters in 8051 in order
to detect '1' to '0' transition at the external pin?

a. One
b. Two
c. Four
d. Eight

ANSWER: b. Two

4. Which bit must be set in TCON register in order to start the 'Timer 0' while
operating in 'Mode 0'?

a. TR0
b. TF0
c. IT0
d. IE0

ANSWER: a. TR0

5. Who controls the timer1 especially when it is configured as a timer in

mode'0',where gate and TR1 bits are attributed to be '1” in TMOD register ?

a. TR1
b. External input at (INT1)
c. TF1
d. All of the above 
ANSWER: b. External input at (INT1)

6. Which timer mode exhibit the necessity to generate the interrupt by setting
EA bit in IE enhancing the program counter to jump to another vector
location? 

a. Mode 0
b. Mode 1
c. Mode 2 
d. Mode 3
ANSWER: b. Mode 1

7. Consider the below generated program segment for initializing Timer 1 in

Mode 1 operation :

MOV SP, # 54 H 
MOV TMOD ,# 0010 0000 C
SET C ET1
SETC TR0 
SJMP $

Which among the below mentioned program segments represent the correct
code ?

a. MOV SP, # 54 H 
MOV TCON ,# 0010 0000 C 
SETC ET1
SETC TR0 
SJMP $

b. MOV SP, # 54H 

MOV TMOD ,# 0010 0000 C
SETC ET0 
SETC TR0 
SJMP $

c. MOV SP, # 54 H 
MOV TMOD ,# 0010 0000 C
SETC ET1
SETC TR1
SETC EA
SJMP $ 

d. MOV SP, # 54 H 
MOV TMOD ,# 0010 0000 C
SETC ET0
SETC TR1
SETC EA
SJMP $

ANSWER: (c) MOV SP, # 54 H 

MOV TMOD ,# 0010 0000 C
SETC ET1
SETC TR1
SETC EA
SJMP $

8. What is the maximum delay generated by the 12 MHz clock frequency in

accordance to an auto-reload mode (Mode 2 ) operation of the timer?

a. 125 μ s
b. 250 μ s
c. 256 μ s
d. 1200 μ s

ANSWER: c. 256 μ s

9. Which among the below mentioned sequence of program instructions

represent the correct chronological order for the generation of 2kHz square
wave frequency?

1. MOV TMOD, 0000 0010 B

2. MOV TL0, # 06H
3. MOV TH0, # 06H
4. SETB TR0 
5. CPL p1.0 
6. ORG 0000H

a. 6, 5, 2, 4, 1, 3
b. 6, 1, 3, 2, 4, 5
c. 6, 5, 4, 3, 2, 1
d. 6, 2, 4, 5, 1, 3

ANSWER: b. 6, 1, 3,2, 4, 5

10. What is the clock source for the timers?

a) some external crystal applied to the micro-controller for executing the timer
b) from the crystal applied to the micro-controller
c) through the software
d) through programming
View Answer
Answer: b
Explanation: Timer’s clock source is the crystal that is applied to the
controller.
11. What is the frequency of the clock that is being used as the clock source
for the timer?
a) some externally applied frequency f’
b) controller’s crystal frequency f
c) controller’s crystal frequency /12
d) externally applied frequency/12
Answer: c
Explanation: The frequency of the clock source for the timer is equal to
f/12( where f is frequency of the crystal ).

12. What is the function of the TMOD register?

a) TMOD register is used to set different timer’s or counter’s to their appropriate
modes
b) TMOD register is used to load the count of the timer.
c) Is the destination or the final register where the result is obtained after the
operation of the timer
d) Is used to interrupt the timer
Answer: a
Explanation: TMOD register is used to set different timer’s or counter’s to their
appropriate modes so that it tells the user that what mode is being used when
operating any timer or counter.

13. What is the maximum delay that can be generated with the crystal
frequency of 22MHz?
a) 2978.9 sec
b) 0.011 msec
c) 11.63 sec
d) 2.97 msec
Answer: d
Explanation: For generating the maximum delay we have to multiply the
maximum number of counts with the time period required to execute one
machine cycle (65536*1/22MHz).

14. Auto reload mode is allowed in which mode of the timer?

a) Mode 0
b) Mode 1
c) Mode 2
d) Mode 3
Answer: c
Explanation: Auto reload is allowed in the Mode 2 of the timer because here in
this mode, we don’t need to load the count again and again in the register.

15. Find out the roll over value for the timer in Mode 0, Mode 1 and Mode 2?
a) 00FFH,0FFFH,FFFFH
b) 1FFFH,0FFFH,FFFFH
c) 1FFFH,FFFFH,00FFH
d) 1FFFH,00FFH,FFFFH
Answer: c
Explanation: For Mode 0 13 bit value is used so 1FFFH is chosen to be the roll
over value. Similarly for Mode 1 FFFFH and for Mode 2 FFH is the roll over
value for the timers and counter.

16. What steps are followed when we need to turn on any timer?
a) load the count, start the timer, keep monitoring it, stop the timer
b) load the TMOD register, load the count, start the timer, keep monitoring it, stop
the timer
c) load the TMOD register, start the timer,load the count, keep monitoring it, stop the
timer
d) none of the mentioned
Answer: b
Explanation: When any timer is to turn on, then firstly we have to load the
TMOD register and the count. Then timer is to get started. After then, we need
to monitor the timer properly and then when the roll over condition arises then
timer is to be stopped.

17. If Timer 0 is to be used as a counter, then at what particular pin clock pulse
need to be applied?
a) P3.3
b) P3.4
c) P3.5
d) P3.6
Answer: b
Explanation: If Timer 0 is to be used as a counter, then a pulse has to be
applied at P3.4 and if it is for Timer 1 then the clock pulse has to be applied at
the pin P3.5.

18. In the instruction “MOV TH1,#-3”, what is the value that is being loaded in
the TH1 register ?
a) 0xFCH
b) 0xFBH
c) 0xFDH
d) 0xFEH
Answer: a
Explanation: Hex value that is being loaded in the TH1 register is the two’s
complement of the value being loaded in it.

19. TF1, TR1, TF0, TR0 bits are of which register?

a) TMOD
b) SCON
c) TCON
d) SMOD
Answer: c
Explanation: These bits are of TCON register. It tells us about the overflow flag
bit and the run control bit.

SERIAL COMMUNICATION
1. Why is it not necessary to specify the baud rate to be equal to the number of
bits per second?

A. Because each bit is preceded by a start bit & followed by one stop bit
B. Because each byte is preceded by a start byte & followed by one stop byte
C. Because each byte is preceded by a start bit & followed by one stop bit
D. Because each bit is preceded by a start byte &followed by one stop byte

ANSWER: C. Because each byte is preceded by a start bit & followed by one
stop bit

2. Which factor/s is/are supposed to have the equal values at both phases of
transmission and reception levels with an intimation of error-free serial
communication?

a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above
ANSWER: d. All of the above

3. Which bits exhibit and signify the termination phase of the character
transmission and reception in SCON special function register?

a. Control bits
b. Status bits
c. Both a & b
d. None of the above

ANSWER: b. Status bits

4. Which two bits are supposed to be analyzed / tested for unity value (1) in
SCON for the reception of byte in mode 1 serial communication ?

a. RI & TI
b. REN & RB8
c. RI & REN
d. TI & RB8
ANSWER: c. RI & REN

5. What is the bit transmitting or receiving capability of mode 1 in serial

communication?

a. 8 bits
b. 10 bits
c. 11 bits
d. 12 bits

ANSWER: b. 10 bits

6. Which pin in the shift register mode (Mode 0) of serial communication allow
the data transmission as well as reception?

a. TXD
b. RXD
c. RB8
d. REN

ANSWER: b. RXD

7. How is the baud rate determined on the basis of system clock frequency (f sc)
in accordance to mode '0' of serial communication?

a. (oscillator frequency) / 12
b. [2SMOD / 32] x (oscillator frequency) / [12 x (256 – (TH1) ] 
c. [2SMOD / 64] x (oscillator frequency) 
d. 2SMOD / 32 x (Timer 1 overflow rate) 

ANSWER: a. (oscillator frequency) / 12

8. Which serial modes possess the potential to support the multi-processor

type of communication?

a. Modes 0 & 1
b. Modes 1 & 2
c. Modes 2 & 3
d. All of the above

ANSWER: c. Modes 2 & 3

9. How does it become possible for 9th bit to differentiate the address byte from
the data byte during the data transmission process in multiprocessor
communication?

a. By recognizing 9th bit as '1' for address byte & '0' for data byte
b. By recognizing 9th bit as '0' for address byte & '1' for data byte
c. By recognizing 9th bit as '1' for address as well as data bytes
d. By recognizing 9th bit as '0' for address as well as data bytes 

ANSWER: a. By recognizing 9th bit as '1' for address byte & '0' for data byte

10. Which byte has the capability to interrupt the slave when SM2 bit is
assigned to be '1' after the initialization process in the multiprocessor mode of
communication?

a. Address byte
b. Data byte
c. Both a & b
d. None of the above

ANSWER: a. Address byte

11. Which devices are specifically being used for converting serial to parallel
and from parallel to serial respectively?
a) timers
b) counters
c) registers
d) serial communication
Answer: c
Explanation: Some registers like parallel in serial out and serial in parallel out
are used to convert serial data into parallel and vice versa respectively.

12. What is the difference between UART and USART communication?

a) they are the names of the same particular thing, just the difference of A and S is
there in it
b) one uses asynchronous means of communication and the other uses
synchronous means of communication
c) one uses asynchronous means of communication and the other uses
asynchronous and synchronous means of communication
d) one uses angular means of the communication and the other uses linear means of
communication
Answer: c
Explanation: UART stands for Universal Asynchronous receiver-transmitter
and USART stands for Universal Synchronous and Asynchronous receiver-
transmitter.

13. Which of the following best describes the use of framing in asynchronous
means of communication?
a) it binds the data properly
b) it tells us about the start and stop of the data to be transmitted or received
c) it is used for error checking
d) it is used for flow control
Answer: b
Explanation: In data framing in asynchronous means of communication, the
data is packed between the start and the stop bit. This is done so as to tell the
other computer about the start and the end of the data.

14. Which of the following signal control the flow of data?

a) RTS
b) DTR
c) Both of the mentioned
d) None of the mentioned
Answer: a
Explanation: RTS is a request to send control signal which is a control for the
flow of data. On the other hand DTR is a Data Terminal Ready control signal
which tells about the current status of the DTE.

15. Which of the following is the logic level understood by the micro-
controller/micro-processor?
a) TTL logic level
b) RS232 logic level
c) None of the mentioned
d) Both of the mentioned
Answer: a
Explanation: TTL logic or the transistor transistor logic level is the logic that is
understood by the micro-controllers/microprocessors.

16. What is null modem connection?

a) no data transmission
b) no MAX232
c) the RxD of one is the TxD for the other
d) no serial communication
Answer: c
Explanation: In null modem connection the RxD of one is the TxD for the other.

17. Which of the following best states the reason that why baud rate is
mentioned in serial communication?
a) to know about the no of bits being transmitted per second
b) to make the two devices compatible with each other, so that the transmission
becomes easy and error free
c) to use Timer 1
d) for wasting memory
Answer: b
Explanation: To make two devices compatible with each other baud rate is
mentioned in the serial communication so that the transmission becomes easy
and error free.

18. With what frequency UART operates (where f denoted the crystal
frequency)?
a) f/12
b) f/32
c) f/144
d) f/384
Answer: d
Explanation: UART frequency is the crystal frequency f/12 divided by 32 that
comes out to be f/384.

19. What is the function of SCON register?

a) to control SBUF and SMOD registers
b) to program the start bit, stop bit, and data bits of framing
c) none of the mentioned
d) both of the mentioned
Answer: b
Explanation: SCON register is mainly used for programming the start bits, stop
bits and data bits of framing. As it consists of bits like RB8, TB8, SM0, SM1,
SM2 etc.

20. What should be done if we want to double the baud rate?

a) change a bit of the TMOD register
b) change a bit of the PCON register
c) change a bit of the SCON register
d) change a bit of the SBUF register
Answer: b
Explanation: PCON register consists of SMOD bit as its D7 bit, so if we set this
bit then the baud rate gets doubled.

21. The serial communication is

a) cheaper communication
b) requires less number of conductors
c) slow process of communication
d) all of the mentioned
Answer: d
Explanation: The serial communication requires less number of conductors
and thus it is cheaper. It is slow as the bits are transmitted one by one along
with start, stop and parity bits.

22. The serial communication is used for

a) short distance communication
b) long distance communication
c) short and long distance communication
d) communication for a certain range of distance
Answer: b
Explanation: Serial communication is more popular for communication over
longer distances as it requires less number of conductors.

23. The mcs 51 architecture supports

a) serial transmission and reception
b) simultaneous transmission and reception
c) transmission and reception of data using serial communication interface
d) all of the mentioned
Answer: d
Explanation: The mcs 51 architecture supports simultaneous transmission and
reception of binary data byte by byte i.e. full duplex mode of communication. It
supports serial transmission and reception of data using standard serial
communication interface and baud rates.

24. The number of bits transmitted or received per second is defined as

a) transmission rate
b) reception rate
c) transceiver rate
d) baud rate
Answer: d
Explanation: Here, baud rate can be defined as the number of bits transmitted
or received per second.

25. The task of converting the byte into serial form and transmitting it bit by bit
along with start, stop and parity bits is carried out by
a) reception unit
b) serial communication unit
c) transmission unit
d) all of the mentioned
Answer: c
Explanation: the serial communication unit consists of transmission unit and
reception unit. The task of converting the byte into serial form and transmitting
it bit by bit along with start, stop and parity bits is carried out by transmission
unit.

26. The transmission unit does not require assistance from processor if once a
byte for transmission is written to
a) SCON register
b) SBUF register
c) SFR address
d) Any of the mentioned
Answer: b
Explanation: once a byte for transmission is written to the serial buffer(SBUF)
register, the transmission unit does not require assistance from processor.

27. The common unit shared by the receiver unit and transmission unit of
serial communication unit is
a) SCON(Serial Port Control) Register
b) SBUF(Serial Buffer) register
c) 8-bit serial data interface
d) All of the mentioned
Answer: d
Explanation: The transmission unit and receiver unit both are controlled by
using a common SCON(Serial Port Control) Register. Also both units share a
common serial buffer(SBUF) register which is a common 8-bit serial data
interface.

28. During serial reception, the buffer that receives serial bits and converts to
a byte is
a) receive buffer 0
b) receive buffer 1
c) receive buffer 2
d) none
Answer: b
Explanation: During serial reception, the receive buffer 1 receives serial bits
and converts to a byte, it then transfers the received parallel byte in receive
buffer 2.

29. If SM0=1, SM1=0, then the transceiver selected is

a) 8-bit synchronous
b) 9-bit synchronous
c) 8-bit asynchronous
d) 9-bit asynchronous
Answer: d
Explanation: If SM0=1, SM1=0, then the 9-bit asynchronous transceiver is
selected.

30. If the microcontroller is expected to communicate in multiprocessor

system, then the required condition is
a) SM0 is set
b) SM1 is set
c) SM2 is set
d) REN is set
Answer: c
Explanation: The bit, SM2 is set if the microcontroller is expected to
communicate in multiprocessor system.

31. In mode 2, the baud rate depends only on

a) SMOD bit
b) SCON bit
c) Oscillator clock frequency
d) SMOD bit and oscillator clock frequency
Answer: d
Explanation: In mode 2, the baud rate depends only on SMOD bit and oscillator
clock frequency.

32. The mode that offers the most secured parity enabled data communication
at lower baud rates is
a) mode 2
b) mode 1
c) mode 0
d) all of the mentioned
Answer: a
Explanation: The mode 3 offers the most secured parity enabled data
communication at lower baud rates of mode 1.

INTERRUPT PROGRAMMING

1. Match the following:

A. ISS --------------------------------------- 1. Monitors the status of interrupt pin 

B. IER --------------------------------------- 2. Allows the termination of ISS 
C. RETI ------------------------------------- 3. MCS-51 Interrupts Initialization 
D. INTO ------------------------------------ 4. Occurrence of high to low transition level

a. A-1, B-2, C-3, D-4

b. A-3, B-2, C-4, D-1 
c. A-1, B-3, C-2, D-4 
d. A-4, B-3, C-2, D-1

ANSWER: c. A-1, B-3, C-2, D-4

2. What kind of triggering configuration of external interrupt intimate the signal

to stay low until the generation of subsequent interrupt? 

a. Edge - Triggering
b. Level Triggering
c. Both a & b
d. None of the above

ANSWER: b. Level Triggering

3. Which among the below mentioned reasons is / are responsible for the
generation of Serial Port Interrupt?

A. Overflow of timer/counter 1
B. High to low transition on pin INT1
C. High to low transition on pin INT0
D. Setting of either TI or RI flag

a. A & B 
b. Only B 
c. C& D
d. Only D

ANSWER: d. Only D
4. How does the processor respond to an occurrence of the interrupt?

a. By Interrupt Service Subroutine

b. By Interrupt Status Subroutine
c. By Interrupt Structure Subroutine
d. By Interrupt System Subroutine

ANSWER: a. By Interrupt Service Subroutine

5. Which address / location in the program memory is supposed to get

occupied when CPU jump and execute instantaneously during the occurrence
of an interrupt? 

a. Scalar
b. Vector
c. Register
d. All of the above

ANSWER: b. Vector

6. Which location specify the storage / loading of vector address during the
interrupt generation? 

a. Stack Pointer
b. Program Counter
c. Data Pointer
d. All of the above

ANSWER: b. Program Counter

7. The external interrupts of 8051 can be enabled by

a) 4 LSBs of TCON register
b) Interrupt enable
c) priority register
d) all of the mentioned
Answer: d
Explanation: The external interrupts namely INT0 (active low) and INT1 (active
low) can be enabled and programmed using the least significant four bits of
TCON register and the Interrupt enable and priority registers.

8. The bits that control the external interrupts are

a) ET0 and ET1
b) ET1 and ET2
c) EX0 and EX1
d) EX1 and EX2
Answer: c
Explanation: The bits, EX0 and EX1 individually control the external interrupts,
INT0(active low) and INT1(active low). If INT0 (active low) and INT1 (active low)
interrupts are to be enabled then the bits EX0 and EX1 must be set
respectively.

9. EA bit is used to
a) enable or disable external interrupts
b) enable or disable internal interrupts
c) enable or disable all the interrupts
d) none of the mentioned
Answer: c
Explanation: Using EA bit, all the interrupts can be enabled or disabled. Using
the individual respective bit, the respective interrupt can be enabled or
disabled.

10. The number of priority levels that each interrupt of 8051 have is
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: Each interrupt level of 8051 can have two levels of priority namely
level 0 and level 1. Level 1 is considered as a higher priority level compared to
level 0.

11. The priority level of interrupt of 8051 for which SI(serial interrupt) interrupt
is programmed is
a) level 0
b) level 1
c) level 0 or level 1
d) none
Answer: b
Explanation: SI interrupt is programmed for level 1 priority.

12. The interrupt bit that when set works at level 1, and otherwise at level 0 is
a) PT1
b) PT0
c) PX1
d) All of the mentioned
Answer: d
Explanation: The bits, PT1, PT0, PX0 and PX1 when set, work at level 1,
otherwise at level 0.

13. All the interrupts at level 1 are polled in the second clock cycle of the
a) forth T state
b) fifth T state
c) third T state
d) none
Answer: b
Explanation: All the interrupts at level 1 are polled or sensed in the second
clock cycle of the fifth T state or 9th clock cycle out of 12 clock cycles. Then
all the interrupts at level 0 are also polled in the same cycle.

14. The minimum duration of the active low interrupt pulse for being sensed
without being lost must be
a) greater than one machine cycle
b) equal to one machine cycle
c) greater than 2 machine cycles
d) equal to 2 machine cycles
Answer: b
Explanation: The minimum duration of the active low interrupt pulse should be
equal to the duration of one machine cycle for being sensed, else it will be
lost.

15. If two interrupts, of higher priority and lower priority occur simultaneously,
then the service provided is for
a) interrupt of lower priority
b) interrupt of higher priority
c) lower & higher priority interrupts
d) none of the mentioned
Answer: b
Explanation: If two interrupts, occur simultaneously, then the one with higher
priority level and early polling sequence will receive service. The other one
with lower priority may get lost there, as there is no mechanism for storing the
interrupt requests.

16. For an interrupt to be guaranteed served it should have duration of

a) one machine cycle
b) three machine cycles
c) two machine cycles
d) four machine cycles
Answer: c
Explanation: For an interrupt to be guaranteed served it should have duration
of two machine cycles.

17. The service to an interrupt will be delayed if it appears during the execution
of
a) RETI instruction
b) Instruction that writes to IE register
c) Instruction that writes to IP register
d) All of the mentioned
Answer: d
Explanation: The service to an interrupt will be delayed if it appears during the
execution of RETI instruction or the instruction that writes to IE/IP registers.

18. When any interrupt is enabled, then where the pointer moves does
immediately after this interrupt has occurred?
a) to the next instruction which is to be executed
b) to the first instruction of ISR
c) to the first location of the memory called the interrupt vector table
d) to the end of the program
Answer: c
Explanation: When any interrupt is enabled, then it goes to the vector table
where the address of the ISR is placed.

19. What are the contents of the IE register, when the interrupt of the memory
location 0x00 is caused?
a) 0xFFH
b) 0x00H
c) 0x10H
d) 0xF0H
Answer: b
Explanation: When interrupt of 0x00 is caused (the reset interrupt) then all the
other interrupts will be disabled or the contents of the IE register becomes
null.

20. After RETI instruction is executed then the pointer will move to which
location in the program?
a) next interrupt of the interrupt vector table
b) next instruction of the program after the IE instruction
c) next instruction after the RETI in the memory
d) none of the mentioned
Answer: b
Explanation: When the RETI instruction is executed, it will execute the
instruction present at the top of the stack (which is the PC’s value i.e after the
interrupt enable instruction).

21. Which pin of the external hardware is said to exhibit INT0 interrupt?
a) pin no 10
b) pin no 11
c) pin no 12
d) pin no 13
Answer: c
Explanation: INT0 interrupt is caused when pin no 12 in the hardware of the
8051 controller is enabled with a low levelled pulse.

22. Which bit of the IE register is used to enable TxD/RxD interrupt?

a) IE.D5
b) IE.D2
c) IE.D3
d) IE.D4
Answer: d
Explanation: IE.D4 is used to enable RS interrupt or the serial communication
interrupt.

23. Which of the following combination is the best to enable the external
hardware interrupt 0 of the IE register (assuming initially all bits of the IE
register are zero)?
a) EX0=1
b) EA=1
c) any of the mentioned
d) both of the mentioned
Answer: d
Explanation: For executing the EX0 interrupt, the EX0 and EA bits of the IE
register should be set. EA is set to enable all the interrupts and EX0 is set to
enable the external hardware interrupt 0 interrupt and mask the other enabled
interrupts.

24. Why normally LJMP instructions are the topmost lines of the ISR?
a) so as to jump to some other location where there is a wider space of memory
available to write the codes
b) so as to avoid overwriting of other interrupt instructions
c) both of the mentioned
d) none of the mentioned
Answer: c
Explanation: There is a small space of memory present in the vector table
between two different interrupts so in order to avoid overwriting of other
interrupts we normally jump to other locations where a wide range of space is
available.

25. Which register is used to make the pulse a level or an edge triggered
pulse?
a) TCON
b) IE
c) IPR
d) SCON
Answer: a
Explanation: TCON register is used to make any pulse level or edge triggered
one.

26. What is the disadvantage of a level triggered pulse?

a) a constant pulse is to be maintained for a greater span of time
b) difficult to analyse its effects
c) it is difficult to produce
d) another interrupt may be caused, if the signal is still low before the completion of
the last instruction
Answer: d
Explanation: In a level triggered pulse, if the signal does not becomes high
before the last instruction of the ISR, then the same interrupt will be caused
again, so monitoring of pulse is required for a level triggered pulse.

27. What is the correct order of priority that is set after a controller gets reset?
a) TxD/RxD > T1 > T0 >EX1 > EX0
b) TxD/RxD < T1 < T0<EX1 < EX0
c) EX0 > T0 > EX1 >T1> TxD/RxD
d) EX0 < T0 < EX1 < T1 < TxD/RxD
Answer: c
Explanation: EX0 >T0 > EX1> T1>TxD/RxD. This is the correct order of priority
that is set after a controller gets reset.