Lost in Translation Solving Common Issues in High Speed Design PDF
Lost in Translation Solving Common Issues in High Speed Design PDF
Lost in Translation Solving Common Issues in High Speed Design PDF
Technically speaking, when the path delay of a signal is long, compared to the rise-time of the
conducted signal, it’s considered high-speed. Practically every design today has some aspect
of high-speed behavior involved, which is why, as a PCB Design Engineer, it is more important
than ever to be able to diagnose and correct the issues the signals may present.
THE COST
OF HIGH-SPEED PROBLEMS
Not only will you save time and money, you will also find a smoother
work flow overall.
Identifying and resolving your high-speed design issues will ultimately allow you and your
team to move through to the layout and manufacturing stages faster, with fewer errors to
be fixed in each round. A faster process will result in increased overall production value, and
ultimately aid in the growth of your product.
NOISE & TIMING
TYPICAL ROOT CAUSES
The first problem many designers face is signal noise. Considered to be anything undesired
or not intended, signal noise is often detected as anything “extra” in your signal waves
that degrade the quality. Digital signals ultimately need to be defined as ones and zeros, so
when there are extra bits, the clarity is confused and muddy. Additionally, signal noise also
promotes electro-magnetic radiation (EMI) effects. Such affects will damage signal integrity
with emissions and crosstalk.
Impedance Mismatches
Issue: Impedance values are not consistent.
Impact: Consistent impedance is very important for signal quality. Each segmented entity
within a signal trace can have drastic changes in impedance values and, if not consistent,
cause a variety of problems. Symptoms may manifest as signal ringing, delays associated with
overshoot and undershoot, and reflections that reduce signal quality. Impedance mismatching
can also affect the timing of your signals. When a signal must overcome a specified amount of
delay, it will impact your timing margin.
Fix: There are several ways to correct the mismatches. First, locate and move problematic
segments. You may also need to resize the trace widths or alter the stack-up directions. These
solutions are easy to manage early in the design cycle, but become costly if the design has
progressed too far.
COUPLING
NOISE ISSUE #2
Coupling Errors
Issue: The proximity of two signal traces to one another.
Impact: Coupling issues are a function of signal “edge” speed and the proximity of each
signal trace to one another. Most issues occur within the rise and fall rates of your signal
transmissions. Fast signals are the aggressors and can victimize any adjacent trace. Long
parallel runs are the easiest victims and will cause false switching points and unwanted noise.
The stack-up can also affect coupling issues in cases of thicker dielectric layers and different
materials than the norm.
Fix: If the trace-to-trace spacing is too narrow, you must move one of the traces. With too long
of a parallel routing length, disrupt the parallelism. In stack-up cases, you may need to alter
the stack-up. Lastly, when the signal edges are too fast for the board design techniques, slow
down the signal edges where possible. Many of these issues will also have costly fixes when
found in later stages of the design and/or manufacturing process.
RETURN-PATH DELAY
NOISE ISSUE #3
Return-Path Delay
Issue: Discontinuities in a return path.
Impact: Important for good signal quality, discontinuities can affect trace impedance and
cause delay. Signal currents will use the path of least resistance to return to the source, so
issues such as split planes will create gaps and return path discontinuities, degrading the
signal and diminishing the quality. These complications in turn prevent smooth current flow
and effectively lengthen the return path. Additionally, they will generate unwanted radiated
signal emission from your board (EMI).
Fix: In simple cases, you may add more reference planes. The best option would be to move
power and ground planes around to avoid breaks under the signal paths. Alter the signal
paths to avoid discontinuities and create a smooth flow.
TIMING IS KEY
A ROOT CAUSE
Solving the impedance-related problems should be a top priority, as they are a primary cause
of timing issues. Minimizing them may result in board alterations, so it is important to catch
these errors as early in the process as possible. Next, make sure to measure the entire delay
path for accumulated delay, which can often require taking pin and z-axis delays into account.
Lastly, resolve any phase issues with differential clocking signals, as these can lead to severe
timing problems by distorting reference clocks.
RULES OF THUMB
ARE NO GUARANTEE
Design cycles have many steps, and when problems occur early on, they
are often compounded through to the end and result in costly re-spins.
When critical decisions need to be changed late in the process, it can have a ripple effect
throughout the design. Having a working high-speed design management system in place will
ensure a smooth process with minimal delays.
REAL-TIME DESIGN
IS A SAFE BET
Still want more information? Check out our High-Speed Design page or
contact us at [email protected] for inquiries.