Viper26: Fixed Frequency Viper Plus Family
Viper26: Fixed Frequency Viper Plus Family
Features
■ 800 V avalanche rugged power section
■ PWM operation with frequency jittering for low
EMI
SO16 narrow DIP-7
■ Operating frequency: SO-16
– 60 kHz for L type Description
– 115 kHz for H type
The device is an off-line converter with an 800 V
■ Standby power < 50 mW at 265 VAC avalanche ruggedness power section, a PWM
■ Limiting current with adjustable set point controller, user defined overcurrent limit,
■ On-board soft-start protection against feedback network
disconnection, hysteretic thermal protection, soft
■ Safe auto-restart after a fault condition start up and safe auto restart after any fault
■ Hysteretic thermal shutdown condition.
Advance frequency jittering reduces EMI filter
Application cost. Burst mode operation and the devices very
low consumption both help to meet the standard
■ Auxiliary power supply for appliances set by energy saving regulations.
■ Power metering
■ LED drivers Figure 1. Typical topology (VOUT ≤VDDCSon)
■
DC Input Voltage DC Output Voltage
SMPS for set-top boxes, DVD players and
recorders
-
DRAIN COMP
VIPER26
GND VDD LIM FB
VIPER26LN
DIP-7 Tube
VIPER26HN
VIPER26HD Tube
VIPER26HDTR Tape and reel
SO16 narrow
VIPER26LD Tube
VIPER26LDTR Tape and reel
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 Typical circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
10 Soft start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1 Block diagram
2 Typical power
VIPER26 18 W 20 W 10 W 12 W
1. Typical continuous power in non ventilated enclosed adapter measured at 50 ° C ambient.
2. Maximum practical continuous power in an open frame design at 50 ° C ambient, with adequate heat
sinking.
3 Pin settings
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Note: The copper area for heat dissipation has to be designed under the DRAIN pins.
4 Electrical data
IDRAIN = 1 mA,
VBVDSS Break-down voltage 800 V
VCOMP = GND, TJ = 25 °C
VDRAIN = max rating,
IOFF OFF state drain current 60 µA
VCOMP = GND
Voltage
Current
Error amplifier
Current limitation
IDlim Drain current limitation ILIM = -10 µA, VCOMP = 3.3 V, TJ = 25 °C 0.66 0.7 0.74 A
tSS Soft-start time 8.5 ms
TON_MIN Minimum turn ON time 480 ns
IDlim_bm Burst mode current limitation VCOMP = VCOMPL 145 mA
Overload
Oscillator section
VIPER26L 54 60 66 kHz
FOSC Switching frequency
VIPER26H 103 115 127 kHz
FOSC = 60 kHz ±4 kHz
FD Modulation depth
FOSC = 115 kHz ±8 kHz
FM Modulation frequency 230 Hz
DMAX Maximum duty cycle 70 80 %
Thermal shutdown
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Figure 14. Power MOSFET on-resistance vs TJ Figure 15. Power MOSFET break down voltage
vs TJ
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VDDCSon
VDDoff
IDRAIN time
time
TJ
TSD
TSD - THYST
time
Normal operation Shut down after over temperature Normal operation
6 Typical circuits
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7 Power section
The power section is implemented with an n-channel power MOSFET with a breakdown
voltage of 800 V min. and a typical RDS(on) of 7 Ω. It includes a SenseFET structure to allow
a virtually lossless current sensing and the thermal sensor.
The gate driver of the power MOSFET is designed to supply a controlled gate current during
both turn-ON and turn-OFF in order to minimize common mode EMI. During UVLO
conditions, an internal pull-down circuit holds the gate low in order to ensure that the power
MOSFET cannot be turned ON accidentally.
The high voltage current generator is supplied by the DRAIN pin. At the first start up of the
converter, it is enabled when the voltage across the input bulk capacitor reaches the
VDRAIN_START threshold, sourcing the IDDch1 current (see Table 7 on page 6); as the VDD
voltage reaches the VDDon start-up threshold, the power section starts switching and the
high voltage current generator is turned OFF. The VIPer26 is powered by the external
source. After the start-up, the auxiliary winding or the diode connected to the output voltage
have to power the VDD capacitor with voltage higher than VDDCSon threshold (see Table 7
on page 6). During the switching, the internal current source is disabled and the
consumptions are minimized. In case of fault the switching is stopped and the device is self
biased by the internal high voltage current source; it is activated between the levels VDDCSon
and VDDon delivering the current IDDch2 to the VDD capacitor during the MOSFET off time,
see Figure 22 on page 13.
At converter power-down, the VDD voltage drops and the converter activity stops as it falls
below VDDoff threshold (see Table 7 on page 6).
VDDCSon
VDDoff
VDRAIN time
IDD time
IDDch2
IDDch1
time
Power-on Normal operation Power-off
9 Oscillator
The switching frequency is internally fixed at 60 kHz (VIPER26LN or LD) or 115 kHz
(VIPER26HN or HD).
In both cases the switching frequency is modulated by approximately ±4 kHz (60 kHz
version) or ±8 kHz (115 kHz version) at 230 Hz (typical) rate, so that the resulting spread-
spectrum action distributes the energy of each harmonic of the switching frequency over a
number of sideband harmonics having the same energy on the whole but smaller
amplitudes.
10 Soft start-up
During the converters' start-up phase, the soft-start function progressively increases the
cycle-by-cycle drain current limit, up to the default value IDlim. By this way the drain current is
further limited and the output voltage is progressively increased reducing the stress on the
secondary diode. The soft-start time is internally fixed to tSS, see typical value on Table 8 on
page 7, and the function is activated for any attempt of converter start-up and after a fault
event.
This function helps prevent transformers' saturation during start-up and short-circuit.
The VIPer26 includes a current mode PWM controller: cycle by cycle the drain current is
sensed through the integrated resistor RSENSE and the voltage is applied to the non
inverting input of the PWM comparator, see Figure 2 on page 3. As soon as the sensed
voltage is equal to the voltage derived from the COMP pin, the power MOSFET is switched
OFF.
In parallel with the PWM operations, the comparator OCP, see Figure 2 on page 3, checks
the level of the drain current and switch OFF the power MOSFET in case the current is
higher than the threshold IDlim, see Table 8 on page 7.
The level of the drain current limit, IDlim, can be reduced depending from the sunk current
from the pin LIM. The resistor RLIM, between LIM and GND pins, fixes the current sunk and
than the level of the current limit, IDlim, see Figure 13 on page 9.
When the LIM pin is left open or if the RLIM has an high value (i.e. > 80 kΩ) the current limit
is fixed to its default value, IDlim, as reported on Table 8 on page 7.
The device can be used both in non-isolated and in isolated topology. In case of non-
isolated topology, the feedback signal from the output voltage is applied directly to the FB
pin as inverting input of the internal error amplifier having the reference voltage, VREF_FB,
see the Table 8 on page 7.
The output of the error amplifier sources and sinks the current, ICOMP, respectively to and
from the compensation network connected on the COMP pin. This signal is then compared,
in the PWM comparator, with the signal coming from the SenseFET; the power MOSFET is
switched off when the two values are the same on cycle by cycle basis. See the Figure 2 on
page 3 and the Figure 23 on page 15.
When the power supply output voltage is equal to the error amplifier reference voltage,
VREF_FB, a single resistor has to be connected from the output to the FB pin. For higher
output voltages the external resistor divider is needed. If the voltage on FB pin is
accidentally left floating, an internal pull-up protects the controller.
The output of the error amplifier is externally accessible through the COMP pin and it’s used
for the loop compensation: usually an RC network.
As reported on Figure 23 on page 15, in case of isolated power supply, the internal error
amplifier has to be disabled (FB pin shorted to GND). In this case an internal resistor is
connected between an internal reference voltage and the COMP pin, see the Figure 23 on
page 15. The current loop has to be closed on the COMP pin through the opto-transistor in
parallel with the compensation network. The VCOMP dynamics ranges is between VCOMPL
and VCOMPH as reported on Figure 24 on page 16.
When the voltage VCOMP drops below the voltage threshold VCOMPL, the converter enters
burst mode, see Section 13 on page 16.
When the voltage VCOMP rises above the VCOMPH threshold, the peak drain current will
reach its limit, as well as the deliverable output power
Without Isolation:
VREF
switch open & E/A enabled
RCOMP VCOMPL
With Isolation: PWM stop
+
switch closed & E/A disabled
-
VOUT SW
BUS
FB
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E/A
RH VREF_FB +
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13 Burst mode
When the voltage VCOMP drops below the threshold, VCOMPL, the power MOSFET is kept in
OFF state and the consumption is reduced to IDD0 current, as reported on Table 7 on
page 6. As reaction at the energy delivery stop, the VCOMP voltage increases and as soon
as it exceeds the threshold VCOMPL + VCOMPL_HYS, the converter starts switching again with
consumption level equal to IDD1 current. This ON-OFF operation mode, referred to as “burst
mode” and reported on Figure 25 on page 16, reduces the average frequency, which can go
down even to a few hundreds hertz, thus minimizing all frequency-related losses and
making it easier to comply with energy saving regulations. During the burst mode, the drain
current limit is reduced to the value IDlim_bm (reported on Table 8 on page 7) in order to
avoid the audible noise issue.
VCOMP
VCOMPL +VCOMPL_HYS
VCOMPL
time
IDD
IDD1
IDD0
IDRAIN time
IDlim_bm
time
Burst Mode
The overload protection is implemented in automatic way using the integrated up-down
counter. Every cycle, it is incremented or decremented depending if the current logic detects
the limit condition or not. The limit condition is the peak drain current, IDlim , reported on
Table 8 on page 7 or the one set by the user through the RLIM resistor, as reported in
Figure 13 on page 9.
After the reset of the counter, if the peak drain current is continuously equal to the level IDlim,
the counter will be incremented till the fixed time, tOVL, after that will be disabled the power
MOSFET switch ON. It will be activated again, through the soft start, after the tRESTART time,
see the Figure 26 on page 17 and the mentioned time values on Table 8 on page 7.
In case of overload or short-circuit event, the power MOSFET switching will be stopped after
a time that depends from the counter and that can be as maximum equal to tOVL. The
protection will occur in the same way until the overload condition is removed, see Figure 26
on page 17.
This protection ensures restart attempts of the converter with low repetition rate, so that it
works safely with extremely low power throughput and avoiding the IC overheating in case of
repeated overload events.
If the overload is removed before the protection tripping, the counter will be decremented
cycle by cycle down to zero and the IC will not be stopped.
VDDon
VDDCSon
IDRAIN time
IDlim_bm
In case the power supply is built in fly-back topology and the VIPer26 is supplied by an
auxiliary winding, as shown in Figure 27 on page 18 and Figure 28 on page 19, the
converter is protected against feedback loop failure or accidental disconnections of the
winding.
The following description is applicable for the schematics of Figure 27 on page 18 and
Figure 28 on page 19, respectively the non-isolated fly-back and the isolated fly-back.
If RH is opened or RL is shorted, the VIPer26 works at its drain current limitation. The output
voltage, VOUT, will increase and so the auxiliary voltage, VAUX, which is coupled with the
output through the secondary-to-auxiliary turns ratio.
As the auxiliary voltage increases up to the internal VDD active clamp, VDDclamp (the value is
reported on Table 8 on page 7) and the clamp current injected on VDD pin exceeds the
latch threshold, IDDol (the value is reported on Table 8 on page 7), a fault signal is internally
generated.
In order to distinguish an actual malfunction from a bad auxiliary winding design, both the
above conditions (drain current equal to the drain current limitation and current higher than
IDDol through VDD clamp) have to be verified to reveal the fault.
If RL is opened or RH is shorted, the output voltage, VOUT, will be clamped to the reference
voltage VREF_FB (in case of non isolated fly-back) or to the external TL voltage reference (in
case of isolated fly-back).
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17 Revision history
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