Aims and Objectives

‹ How to go about designing complex, high speed digital

systems (not just circuits)?
‹ How to use some of the modern CAD tools to help with the
E 3.05 design?
Digital System Design ‹ How to implement such designs using programmable logic
(e.g. FPGAs)?
‹ How to read data sheets and make sense of them?
Peter Cheung
‹ How do digital building blocks (such as memory chips,
Department of Electrical & Electronic Engineering
Imperial College London
processing elements, arithmetic circuits etc.) work?
‹ How to interface to processors and computers (from hardware
point of view)?
‹ How to deal with testing of complex systems?
‹ Have fun!
URL: www.ee.ic.ac.uk/pcheung/
E-mail: [email protected]

PYKC 3-Jan-08 E3.05 Digital System Design Topic 1 Slide 1 PYKC 3-Jan-08 E3.05 Digital System Design Topic 1 Slide 2

Course Syllabus Course Syllabus (1) – Programmable Logic

‹ The course syllabus is divided into five main sections: ‹ Technologies behind programmable logic
• Programmable Logic ‹ Programmable Logic architectures in general
• Arithmetic Circuits ‹ Complex Programmable Logic Devices (CPLDs)
• Data Encoding & communication ‹ Field Programmable Gate Arrays (FPGAs)
• Architectures
‹ Recent advances in FPGAs
• Testing
‹ Designing with FPGAs
‹ Design Flow, Design Tools, Design Libraries
‹ Future of programmable logic

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 Course Syllabus (3) – Data Encoding &
Course Syllabus (2) – Arithmetic Circuits
Communication

‹ Adders architectures ‹ Logic interface standards

‹ Multipliers circuits ‹ Clocking for high speed digital design
‹ Floating point arithmetic circuits ‹ Metastability issues
‹ Other computational building blocks ‹ Clock synchronisation
‹ Data encode and error correction
‹ On-chip and On-board communication

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Course Syllabus (4) – Hardware

Course Syllabus (5) – Digital Test
Architectures

‹ Parallel vs serial ‹ Modern packaging

‹ Systolic and other array architectures ‹ Board testing issues
‹ Distributed arithmetic ‹ JTAG Boundary Scan
‹ Cordic based architecture

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 Recommended Books Coursework

No perfect textbook for this course. Here are four reasonable possibilities:
‹ Best way to learn DSD is to do it!
‹ "Digital Design Principles and Practices", 4th Edition (Sept 2005), John F. Wakerly,
Prentice Hall.
‹ Unassessed coursework:
• This is a new edition of a well established textbook. It covers a significant portion of the • 2 to 8 lab exercises using DE2 Board (from Altera) to learn the system
materials taught on this course. At ~£45, this a bargain. Recommended purchase if you ‹ Assessed coursework:
have not already done so!
• Design of a cordic based processor to add ripple effect on an image
‹ “Contemporary Logic Design”, Gaetano Boriello, Randy H. Katz, August 2004,
• Work in pairs – one deliverable between the pair
Prentice Hall.
• Good coverage on finite state machines and computer architectures. (~£45) ‹ Deliverables:
‹ "High-Speed Digital Design - A handbook of black magic", Howard G. Johnson, • Working design and demonstrator
Prentice Hall, 1993; ISBN 0-13-395724-1 (£61). • Design document (effectively a no-nonsense report)
• The best practical guide to designing and building very high speed digital circuits. • Deadline: 1st day of the Summer Term
Expensive reference for your company to buy (not you).
‹ Quartus-II software has a web-edition that can be downloaded (free)
‹ “FPGA-based System Design”, Wayne Wolf, Prentice Hall, 2004, ISBN from Altera website after you register
0131424610 (£75)
• Contemporary book based on FPGA; possibly too expensive for what it covers ‹ Software also available on all Level 5 & Level 1 machines
‹ DE2 Boards available on Level 5 and Level 1 Labs

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Coursework – DE2 Board Coursework – Demo

‹ http://www.altera.com/education/univ/materials/boards/unv-de2-board.html ‹ This shows an example of the ripple video effect which is the goal of this
coursework

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 Levels of Design Abstractions

Design Design Descriptions Primitive Theoretical Techniques

Levels Components
Topic 1 Algorithmic Specifications Functional blocks Signal processing theory

High-level lang. 'black boxes' Control theory

Design Methodologies & Math. equations Sorting algorithm
Implementation Technologies Functional VHDL, Verilog Registers Automata theory
FSM language Counters Timing analysis
Peter Cheung C/Pascal ALU
Department of Electrical & Electronic Engineering
Imperial College London Logic Boolean equations Logic gates Boolean algebra
Truth tables Flip-flops K-map
Timing diagrams Boolean minimization

URL: www.ee.imperial.ac.uk/pcheung/ Circuit Circuit equations Transistors Linear/non-linear eq.

E-mail: [email protected] Transistor netlist Passive comp. Fourier analysis

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The Design Process The Design Process (cont’)

Specification ‹ Top-down design strategies

Preliminary High-level (behavioural) • Refine Specification successively
design simulation
• Decompose each component into small components
Functional
• Lowest-level primitive components
description Schematic/HDL capture • Over-sold methodology - only works with plenty of experience
Detail design Logic simulation
Timing analysis ‹ Bottom-up design strategies
• Build-up from primitive components
Design
description • Combined to form more complex components
Implementation Simulation
Optimisation Logic synthesis & • Risk wrong interpretation of specifications
Verification Optimisation
‹ Mixed strategies
Manufacturing
• Mostly top-down, but also bits of bottom-up
Boundary-scan • Reality: need to know both top level and bottom level
Testing Built-in testing constraints

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 Design Descriptions Design Tools
Hardware Description
Schematic capture
Languages

Good for multiple data flow Flexible & parameterisable

Give overview picture Excellent for optimisation & synthesis
Relates to hardware better Direct mapping to algorithms
Doesn't need to be good in computing Excellent for datapaths
High information density Readily interfaced to optimiser
Easy to handle and transmit
Back annotations possible
(electronically)
Mixed analogue/digital possible

Not good for algorithms Essentially serial representation

Not good for datapaths May not show overall picture
Doesn't interface well in optimiser Often need good programming skill
No good for synthesis software Divorce from physical hardware
Difficult to reuse Need special software
Not parameterisable

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A typical digital system Implementation Technologies

Digital Logic

Microprocessor RAM/ROM Buffer memories Progammable

Standard Logic ASICs Full Custom
Logic Devices

Microprocessor
SPLDs CPLDs FPGAs & RAM
Bus interface
Complex ASIC Glue Logic
circuits

TTL CMOS Gate Standard

74xx 4xxx Arrays Cells

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