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Useful Skew

The document discusses different approaches to clock tree design, including zero skew and balanced skew designs where insertion delays are equalized. It notes that while zero skew is traditionally used, it can be costly, and introducing intentional skew (useful skew) through P&R tools can help meet timing constraints with lower cost. An example is provided where a design with a timing violation sees the violation resolved by introducing a 2ns skew between registers, allowing one path's timing to borrow cycle time from another path without affecting its margin. P&R tools can enable useful skew optimization to intentionally skew the clock network and help meet timing goals.

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412 views2 pages

Useful Skew

The document discusses different approaches to clock tree design, including zero skew and balanced skew designs where insertion delays are equalized. It notes that while zero skew is traditionally used, it can be costly, and introducing intentional skew (useful skew) through P&R tools can help meet timing constraints with lower cost. An example is provided where a design with a timing violation sees the violation resolved by introducing a 2ns skew between registers, allowing one path's timing to borrow cycle time from another path without affecting its margin. P&R tools can enable useful skew optimization to intentionally skew the clock network and help meet timing goals.

Uploaded by

Pratik Pro
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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For clock trees, the traditional way is to go with zero skew or balanced skew.

For each of the sinks, the


insertion delay is kept to be equal so that each node receives the clock at the same time(or as close as
physically possible). Here, your clock design is completely independent of your data path design. You are
ensuring the clock signals come to each data sync point within a permissible variation, and the design
can theoretically be timing closed if the data paths also can meet the timing within a permissible range
of the clock signal.

However, meeting zero skew in some large designs can be unnecessarily costly. If clock skew is used
intentionally to meet timing then it is called useful skew. P&R tools can use useful skew as an
optimization option in CTS and other stage optimizations to leverage the clock signal in meeting timing,
with acceptable margins.

Let us first see an example of clock being skewed to meet timing.

Given below is a design with zero skew, but setup timing violation.

Let’s take the clock period of the circuit as 10ns, with 2ns insertion to delay to clock pin of each register.
Let’s also assume that the setup and hold times of the flops are zero for this example. The path1
combinational delay is 11ns and path2 combinational delay is 5ns.

The setup timing requirement of path 1 is:

2ns(clock path delay till FF1/CP) + 11ns < 2ns(clock path delay till FF2/CP)+10ns(clock period)

13ns < 12 ns --> Timing Violation

If we decide to keep the clock network intact, we need to fix this timing violation by reducing the
combinational path delay of Path1. However, path2 timing is met with considerable margin.

2ns+5ns < 2ns+10ns

So, ideally we could borrow some cycle time from path2, if no other paths are affected by it.

Let’s introduce some clock skew to do just that.

Now the setup timing requirement is

2ns(clock path delay till FF1/CP) + 11ns < 4ns(clock path delay till FF2/CP)+10ns(clock period)

13ns < 14ns --> Pass

However, now there is a clock skew of 2ns between these registers, and the Path2 timing has now
changed to:

4ns(clock path delay till FF2/CP)+5ns < 2ns+10ns

9ns < 12ns –-> Still not violated, even though margin is now less.

PnR tools when enabled 'useful skew' can change the clock network and introduce intentional skew to
meet timing with smaller cost. Some of the useful commands in Innovus tool are:

setOptMode –usefulSkew false

setOptMode -usefulSkew true -usefulSkewPreCTS true

setOptMode -usefulSkew true -usefulSkewPostCTS true

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