VHDL Introduction

VHDL stands for Very high-speed integrated circuit (VHSIC) Hardware Description Language. It is a
programming language used to model a digital system by dataflow, behavioral and structural style
of modeling. This language was first introduced in 1981 for the department of Defense (DoD)
under the VHSIC program.

Describing a Design

In VHDL an entity is used to describe a hardware module. An entity can be described using,

• Entity declaration
• Architecture
• Configuration
• Package declaration
• Package body

Entity Declaration

It defines the names, input output signals and modes of a hardware module.

The entity declaration describes the input and output of a design entity and parametric values.
The input and output I/O could be the I/O of an entity which is also the device level description-
I/O of a chip. It also can represent a schematic symbol which describe components connection to
the rest of the design.

Syntax −

entity entity_name is
Port declaration;
end entity_name;

An entity declaration should start with ‘entity’ and end with ‘end’ keywords. The direction will be
input, output or inout.

Ports

Each I/O signal in an entity declaration is referred as a port which is analogous to a pin in a
schematic symbol. The set of ports defined for the entity is referred as a part of declaration. Each
port has a mode which describes the direction in which data is transferred through the port. The
following modes are considered:-

in : data flows only into entity. Mode is used for clock input, control input and unidirectional data
inputs.

Out : - data flows only from source to output of entity. It is used for Count output.
Buffer : Internal feedback which is needed to declare port as mode buffer or declared a separate
signal for use within architecture body a port that is declared as mode buffer is similar to a port
that is declared as Mode out.

in/out : bidirectional declaration in which mode is out allows data flow into and out of the entity.

Example:-

Entity add4 is port (

a, b : in STD_logic_vector(3 down to 0)

C1 : in STD_logic

Sum : out STD_logic_vector(3 down to 0)

C0 : out STD_logic) ;

end add4;

The symbol equivalent is shown in figure

A(3:0) C1 sum(3:0)

B(3:0) CO

The entity declaration for add4 can be processed in VHDL software/compiler if it is written as
follows:

library ieee:

use ieee : std_logic_1164 all:

Entity add4 is port (

a, b : in STD_logic_vector(3 down to 0)

C1 : in STD_logic

Sum : out STD_logic_vector(3 down to 0)

C0 : out STD_logic) ;

end add4;
Architecture −

The architecture body describes the contents of an entity. There are three types of style used for
description of architecture body-behavioral description, dataflow description and structural
description.

Syntax −

architecture architecture_name of entity_name

architecture_declarative_part;

begin
Statements;
end architecture_name;

Here, we should specify the entity name for which we are writing the architecture body. The
architecture statements should be inside the ‘begin’ and ‘énd’ keyword. Architecture declarative
part may contain variables, constants, or component declaration.

Behavioral Modeling

In this modeling style, the behavior of an entity as set of statements is executed sequentially in the
specified order. Only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are
sequential.

Rather than specifying the structure or netlist of a circuit, the designs are specified with a set of
statements that model function or behaviour of entity or port of entity.

Architecture body uses an algorithm to describe the design function.

Sequential statements are used to model the function of devices used in the circuit.

PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code that are executed
sequentially.

However, as a whole, any of these blocks is still concurrent with any other statements placed
outside it.

One important aspect of behavior code is that it is not limited to sequential logic. Indeed, with it,
we can build sequential circuits as well as combinational circuits.

The behavior statements are IF, WAIT, CASE, and LOOP. VARIABLES are also restricted and
they are supposed to be used in sequential code only. VARIABLE can never be global, so its value
cannot be passed out directly.
Example:

library ieee:

use ieee : std_logic_1164 all:

Entity eqcomp4 is port (

a, b : in STD_logic_vector(3 down to 0)

equals : out STD_logic) ;

end eqcomp4;

architecture behavioural of eqcomp4 is

begin

comp process(a, b)

Begin

If a = b, then

equals <= 1

else

equals <= 0

end if

end process comp

end behavioral
Data Flow Modeling
In this modeling style, the flow of data through the entity is expressed using concurrent (parallel)
signal. The concurrent statements in VHDL are WHEN and GENERATE.

Data flow style specified how data will be transform from signal to signal and input to output
without the use of sequential statements.

The difference between behaviour style and data flow style is that one uses process and other uses
how data will flow.

In the data flow descriptions conditional statement when-else or selected signal assignment (with-
select-when) statements rather than algorithms statement are used for representing simple
equations.

Besides them, assignments using only operators (AND, NOT, +, *, all, etc.) can also be used to
construct code.

Finally, a special kind of assignment, called BLOCK, can also be employed in this kind of code.

In concurrent code, the following can be used −

• Operators
• The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
• The GENERATE statement;
• The BLOCK statement

Library ieee:
use ieee : std_logic_1164 all:

Entity eqcomp4 is port (

a, b : in STD_logic_vector(3 down to 0)
equals : out STD_logic) ;
end eqcomp4;

architecture dataflow of eqcomp4 is

begin
equals <= 1 when a=b else 0;
end dataflow

We can describe the same comparator using Boolean equation in datalow:

Architecture bool of eqcomp4 is
Begin
Equals <= not a(0) xor b(0) and not a(1) xor b(1) and not a(2) xor b(2) and not a(3) xor b(3)
end bool;
Structural Modeling
• In this modeling, an entity is described as a set of interconnected components. A component
instantiation statement is a concurrent statement. Therefore, the order of these statements is not
important. The structural style of modeling describes only an interconnection of components
(viewed as black boxes), without implying any behavior of the components themselves nor of
the entity that they collectively represent.
• it consists of VHDL netlists. These netlists are very much like schematic netlist: components
are instantiated and connected together with signals.
• To instantiate a component is to place it in a hierarchical design.
• An instantiation is either an act of placing a component or an instance of a component in
structural design in hierarchy in which separate entity declaration and multiple architectural
bodies are used.
• In Structural modeling, architecture body is composed of two parts − the declarative part
(before the keyword begin) and the statement part (after the keyword begin).
Library ieee:
use ieee : std_logic_1164 all:
Entity eqcomp4 is port (
a, b : in STD_logic_vector(3 down to 0)
equals : out STD_logic) ;
end eqcomp4;

use work.gatepkg.all;
architecture structure of eqcomp4 is
signal x : std_logic_vector(0 to 3)
begin
n0 : xnor port map (a(0), b(0), x(0));
n1 : xnor port map (a(1), b(1), x(1));
n2 : xnor port map (a(2), b(2), x(2));
n3 : xnor port map (a(3), b(3), x(3));
end structure;

• In the above example, separate entity declaration and architecture body pairs are created for
the and4, xnor2 and eqcomp4 design entities.
• The structural design methodology is often used to decomposed a design into manageable
units and is also used to attain higher degree of control over synthesis than other
architectures.
Logic Operation – AND GATE

X Y Z
0 0 0
0 1 0
1 0 0
1 1 1

VHDL code for 2 input AND gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and2 is Port ( X : in std_logic;

Y : in std_logic;
Z : out std_logic);
end and2;

architecture and11 of and2 is

begin
Z <= X AND Y;
end and11;

Waveforms
Logic Operation – OR Gate

X Y Z
0 0 0
0 1 1
1 0 1
1 1 1

VHDL code for 2 input OR gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity OR2 is Port ( X : in std_logic;

Y : in std_logic;
Z : out std_logic);
end OR2;

architecture or11 of OR2 is

begin
Z <= X OR Y;
end or11;

Waveforms
Logic Operation – NOT Gate

X Y
0 1
1 0
VHDL code for NOT gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity NOT1 is Port ( X : in std_logic;

Z : out std_logic);
end NOT1;

architecture NOT11 of NOT1 is

begin
Z<= NOT X;
end NOT11;
Logic Operation – NAND Gate

X Y z
0 0 1
0 1 1
1 0 1
1 1 0

VHDL code for 2 input NAND gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity nand2 is Port ( X : in std_logic;

Y : in std_logic;
Z : out std_logic);
end nand2;

architecture nand11 of nand2 is

begin
Z <= X NAND Y;
end nand11;

Waveforms
Logic Operation – NOR Gate

X Y z
0 0 1
0 1 0
1 0 0
1 1 0

VHDL code for 2 input NOR gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity NOR2 is Port ( X : in std_logic;

Y : in std_logic;
Z : out std_logic);
end NOR2;

architecture nor11 of NOR2 is

begin
Z<=X NOR Y;
end nor11;

Waveforms
Logic Operation – XOR Gate

X Y Z
0 0 1
0 1 1
1 0 1
1 1 0

VHDL code for 2 input XOR gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity XOR2 is Port ( X : in std_logic;

Y : in std_logic;
Z : out std_logic);
end XOR2;

architecture xor11 of XOR2 is

begin
Z <= X XOR Y;
end xor11;

Waveforms
Logic Operation – X-NOR Gate

X Y Z
0 0 1
0 1 1
1 0 1
1 1 0

VHDL code for 2 input XNOR gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity XNOR2 is Port ( X : in std_logic;

Y : in std_logic;
Z : out std_logic);
end XNOR2;

architecture xnor11 of XNOR2 is

begin
Z<=not (X XOR Y);
end xnor11;

Waveforms
VHDL Programming Combinational Circuits
VHDL code for Half Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ha1 is
Port ( A : in std_logic;
B : in std_logic;
SUM : out std_logic;
CARRY : out std_logic);
end ha1;

architecture ha11 of ha1 is

begin
SUM<=A xor B;
CARRY<= A and B;
end ha11;

Waveforms

VHDL code for Full Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fa is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fa;

architecture fa1 of fa is
begin
sum<= a xor b xor c;
carry<=(a and b)or(b and c)or(c and a);
end fa1;
VHDL code for full adder using structural method

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FAdder is
Port ( FA, FB, FC : in STD_LOGIC;
FS, FCA : out STD_LOGIC);
end FAdder;

architecture structural of FAdder is

component ha1 is Port ( A, B : in STD_LOGIC;

SUM, CARRY : out STD_LOGIC);
end component;

component OR2 is Port ( X,Y: in STD_LOGIC;

Z: out STD_LOGIC);
end component;

SIGNAL S0, S1, S2 : STD_LOGIC;

begin
U1:ha1 PORT MAP(A=>FA,B=>FB,SUM=>S0,CARRY=>S1);
MAP(A=>FA,B=>FB,S
U2:ha1 PORT MAP(A=>S0,B=>FC,S
MAP(A=>S0,B=>FC,SUM=>FS,CARRY=>S2);
U3:OR2 PORT MAP(X=>S2,Y=>S1,Z=>FCA);
end structural;

Waveforms
VHDL Code for a Half-Subtractor
Half
Library ieee;
use ieee.std_logic_1164.all;

entity half_sub is
port(a,c:in STD_LOGIC;
STD_LOGIC
d,b:out STD_LOGIC);
STD_LOGIC
end half_sub;

architecture data of half_sub is

begin
d<= a xor c;
b<= (a and (not c));
end data;

Waveforms

VHDL Code for a Full Subtractor

Library ieee;
use ieee.std_logic_1164.all;

entity full_sub is
port(a,b,c:in STD_LOGIC; sub,borrow:out STD_LOGIC);
STD_LOGIC
end full_sub;

architecture data of full_sub is

begin
sub<= a xor b xor c;
borrow <= ((b xor c) and (not a)) or (b and c);
end data;

Waveforms
VHDL code for 2x1 Multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux21 is
Port ( A : in std_logic;
B : in std_logic;
SEL : in std_logic;
X : out std_logic);
end mux21;

architecture mx of mux21
m is

begin
process(A,B,SEL)
begin
case SEL is
when "0"=>
X <= A;
when "1"=>
X <= B;
end case;
end process;
end mx;

VHDL Code for a 4X1 Multiplexer

Library ieee;
use ieee.std_logic_1164.all;

entity mux is
port(S1,S0,D0,D1,D2,D3:in
S1,S0,D0,D1,D2,D3:in STD_LOGIC;
Y:out STD_LOGIC);
);
end mux;

architecture data of mux is

begin
Y<= (not S0 and not S1 and D0) or
(S0 and not S1 and D1) or
(not S0 and S1 and D2) or
(S0 and S1 and D3);
end data;

Waveforms
VHDL Code for a Demultiplexer
Library ieee;
use ieee.std_logic_1164.all;

entity demux is
port(S1,S0,D:in STD_LOGIC;
STD_LOGIC
Y0,Y1,Y2,Y3:out STD_LOGIC);
end demux;

architecture data of demux is

begin
Y0<= ((Not S0) and (Not S1) and D);
Y1<= ((Not S0) and S1 and D);
Y2<= (S0 and (Not S1) and D);
Y3<= (S0 and S1 and D);
end data;

Waveforms

VHDL Code for a 8 x 3 Encoder

library ieee;
use ieee.std_logic_1164.all;

entity enc is
port(i0,i1,i2,i3,i4,i5,i6,i7:in STD_LOGIC;
o0,o1,o2: out STD_LOGIC);
STD_LOGIC
end enc;

architecture ENCO of enc is

begin
o0<=i4 or i5 or i6 or i7;
o1<=i2 or i3 or i6 or i7;
o2<=i1 or i3 or i5 or i7;
end ENCO;

Waveforms
VHDL Code for a 3 x 8 Decoder
library ieee;
use ieee.std_logic_1164.all;

entity dec is
port(i0,i1,i2:in STD_LOGIC;
STD_LOGIC
o0,o1,o2,o3,o4,o5,o6,o7: out STD_LOGIC);
end dec;

architecture vcgandhi of dec is

begin
o0<=(not i0) and (not i1) and (not i2);
o1<=(not i0) and (not i1) and i2;
o2<=(not i0) and i1 and (not i2);
o3<=(not i0) and i1 and i2;
o4<=i0 and (not i1) and (not i2);
o5<=i0 and (not i1) and i2;
o6<=i0 and i1 and (not i2);
o7<=i0 and i1 and i2;
end vcgandhi;

Waveforms
VHDL Code – 4 bit Parallel adder
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity pa is
port(a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
ca : out STD_LOGIC;
sum : out STD_LOGIC_VECTOR(3 downto 0)
);
end pa;

architecture vcgandhi of pa is
Component fa is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
ca : out STD_LOGIC
);
end component;
signal s : std_logic_vector (2 downto 0);
signal temp: std_logic;
begin
temp<='0';
u0 : fa port map (a(0),b(0),temp,sum(0),s(0));
u1 : fa port map (a(1),b(1),s(0),sum(1),s(1));
u2 : fa port map (a(2),b(2),s(1),sum(2),s(2));
ue : fa port map (a(3),b(3),s(2),sum(3),ca);
3),b(3),s(2),sum(3),ca);
end vcgandhi;

Waveforms
VHDL Code – 4 bit Parity Checker
library ieee;
use ieee.std_logic_1164.all;

entity parity_checker is
port (a0,a1,a2,a3 : in std_logic;
p : out std_logic);
end parity_checker;

architecture vcgandhi of parity_checker is

begin
p <= (((a0 xor a1) xor a2) xor a3);
end vcgandhi;

Waveforms

VHDL Code – 4 bit Parity Generator

library ieee;
use ieee.std_logic_1164.all;

entity paritygen is
port (a0, a1, a2, a3: in std_logic;
std_logic
p_odd, p_even: out std_logic);
end paritygen;

architecture vcgandhi of paritygen is

begin
process (a0, a1, a2, a3)

if (a0 ='0' and a1 ='0' and a2 ='0' and a3 =’0’)

then odd_out <= "0";
even_out <= "0";
else
p_odd
dd <= (((a0 xor a1) xor a2) xor a3);
p_even <= not(((a0 xor a1) xor a2) xor a3);
end vcgandhi

Waveforms
VHDL
HDL Programming for Sequential Circuits
S-R Latch

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity S_R_latch_top is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
Q : out STD_LOGIC);
end S_R_latch_top;

architecture Behavioral of S_R_latch_top is

signal notQ : STD_LOGIC;
begin

Q <= R nor notQ;

notQ <= S nor Q;

end Behavioral;

Waveforms
VHDL Code for a D Latch
library ieee; Waveforms
use ieee.std_logic_1164.all;

entity DL is
port(d:in STD_LOGIC;
q,qbar:buffer STD_LOGIC);
end DL;

architecture DLL of DL is
signal s1,r1:bit;
begin
q<= d nand qbar;
qbar<= d nand q;
end DLL;

VHDL Code for an SR Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity srflip is
port(r, s, clk : in STD_LOGIC;
STD_LOGIC
q, qbar : buffer STD_LOGIC);
STD_LOGIC
end srflip;

architecture SRFF of srflip is

signal s1,r1:bit;
begin
s1<=s nand clk;
r1<=r nand clk;
q<= s1 nand qbar;
qbar<= r1 nand q;
end SRFF;

Waveforms
VHDL code for a JK Flip Flop
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity jk is
port(
j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC);
end jk;

architecture jkff1 of jk is
begin
jkff : process (j,k,clk,reset) is
variable
iable m : std_logic := '0';

begin
if (reset = '1') then
m : = '0';
elsif (rising_edge (clk)) then
if (j/ = k) then
m : = j;
elsif (j = '1' and k = '1') then
m : = not m;
end if;
end if;

q <= m;
qb <= not m;
end process jkff;
end jkff1;

Waveforms
VHDL Code for a D Flip Flop
Library ieee;
use ieee.std_logic_1164.all;

entity dflip is
port(d,clk:in STD_LOGIC;
STD_LOGIC
q,qbar:buffer STD_LOGIC);
STD_LOGIC
end dflip;

architecture dff of dflip is

signal d1,d2: STD_LOGIC;
STD_LOGIC
begin
d1 <=d nand clk;
d2 <=(not d) nand clk;
q <= d1 nand qbar;
qbar<= d2 nand q;
end dff;

Waveforms
VHDL Code for a T Flip Flop
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Toggle_flip_flop is
port(
t : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end Toggle_flip_flop;

architecture tff1 of Toggle_flip_flop is

begin
tff : process (t,clk,reset) is
variable m : std_logic : = '0';

begin
if (reset = '1') then
m : = '0';
elsif (rising_edge (clk)) then
if (t = '1') then
m : = not m;
end if;
end if;
dout < = m;
end process tff;
end tff1;

Waveforms
VHDL Code for a 4 - bit Up Counter
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
Clock, CLR : in std_logic;
port(Clock,
Q : out std_logic_vector(3 downto 0)
);
end counter;

architecture upcounter of counter is

signal tmp: std_logic_vector(3 downto 0);
begin
process (Clock, CLR)

begin
if (CLR = '1') then
tmp < = "0000";
elsif (Clock'event and Clock = '1') then
tmp
mp <= tmp + 1;
end if;
end process;
Q <= tmp;
end upcounter;

Waveforms
VHDL Code for a 4-bit
4 Down Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dcounter is
port(Clock, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end dcounter;

architecture downcounter of dcounter is

signal tmp: std_logic_vector(3 downto 0);

begin
process (Clock, CLR)
begin
if (CLR = '1') then
tmp <= "1111";
elsif (Clock'event and Clock = '1') then
tmp <= tmp - 1;
end if;
end process;
Q <= tmp;
end downcounter;

Waveforms
Shift Registers in VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shift_register_top is
Port ( CLK : in STD_LOGIC;
D : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR(7 downto 0));
end shift_register_top;

architecture Behavioral of shift_register_top is

signal shift_reg : STD_LOGIC_VECTOR(7 downto 0) := X"00";
begin

-- shift register
process (clock_div(4))
begin
if (CLK'event and CLK = '1') then
t
shift_reg(7) <= D;
shift_reg(6) <= shift_reg(7);
shift_reg(5) <= shift_reg(6);
shift_reg(4) <= shift_reg(5);
shift_reg(3) <= shift_reg(4);
shift_reg(2) <= shift_reg(3);
shift_reg(1) <= shift_reg(2);
shift_reg(0) <= shift_reg(1);
end if;
end process;

-- hook up the shift register bits to the LEDs

LED <= shift_reg;

end Behavioral;
//=====================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shift_register2 is
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0));
end shift_register2;

architecture Behavioral of shift_register2 is

signal clock_div : STD_LOGIC_VECTOR(4 downto 0);
signal shift_reg : STD_LOGIC_VECTOR(7 downto 0) := X"00";
begin

-- clock divider
process (CLK)
begin
if (CLK'event and CLK = '1') then
clock_div <= clock_div + '1';
end if;
end process;

-- shift register
process (clock_div(4))
begin
if (clock_div(4)'event and clock_div(4) = '1') then
shift_reg(6 downto 0) <= shift_reg(7 downto 1);
shift_reg(7) <= D;
end if;
end process;

-- hook up the shift register bits to the LEDs

LED <= shift_reg;
end Behavioral;