ADVANCED INFORMATION Data Sheet No.

PD60108B

IR2157
FULLY INTEGRATED BALLAST CONTROL IC
Features
• Thermal overload protection
• Programmable preheat time & frequency • Programmable deadtime
• Programmable ignition ramp • Integrated 600V level-shifting gate driver
• Protection from failure-to-strike • Internal 15.6V zener clamp diode on VCC
• Lamp filament sensing & protection • True micropower startup (150uA)
• Protection from operation below resonance • Latch immunity protection on all leads
• Protection from low-line condition & automatic • ESD protection on all leads
restart (mimics a magnetic ballast)
Description Packages
The IR2157 is a fully integrated, fully protected 600V ballast control IC designed to
drive virtually all types of rapid start fluorescent lamp ballasts. Externally program-
mable features such as preheat time & frequency, ignition ramp characteristics, and
running mode operating frequency provide a high degree of flexibility for the ballast 16 Lead SOIC
design engineer. Comprehensive protection features such as protection from failure (narrow body)
of a lamp to strike, filament failures, low dc bus conditions, thermal overload, or lamp
failure during normal operation, as well as an automatic restart function, have been
included in the design. The heart of this control IC is a variable frequency oscillator
with externally programmmable deadtime. Precise control of a 50% duty cycle is
accomplished using a T-flip-flop. The IR2157 is available in both 16 pin DIP and 16
pin narrow body SOIC packages.
16 Lead PDIP
Typical Connection
+ Rectified AC Line

+ VBUS
R2
R1 R Supply

VDC HO
1 16 Q1
C1 R GHS C BLOCK L RES
CPH VS
2 15
IR2157

C PH C BS
RPH VB
3 14
C SNUBBER
C IGN R PH
RT N/C
4 13 D BOOT
RT R SNUBBER
R RUN
RUN VCC
5 12
C START R START C VCC C RES
CT COM D1
6 11
D2
CT R DT DT LO
7 10 Q2
R GLS
SD CS R4
8 9
C2 R3
R CS

R5

V B U S return

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IR2157

Power Turned On

UVLO Mode
1/
2 -Bridge Off
I Q C C ≅ 1 5 0 µA
C PH = 0V
Oscillator Off

VCC > 11.4V ( U V + ) VCC < 9.5V

SD > 2.0V (VCC Fault or Power Down)
and
(Lamp Removal)
VDC > 5.1V ( B u s O K ) or
or
and VDC < 3.0V
VCC < 9.5V (dc Bus/ac Line Fault or Powe
SD < 1.7V ( L a m p O K )
(Power Turned Off)
and or
T J < 175C ( T jmax ) SD > 2.0V
(Lamp Fault or Lamp Remova

FAULT Mode T J > 175C PREHEAT Mode

Fault Latch Set (Over-Temperature) 1
1 / 2-Bridge @ f PH
/ 2 -Bridge Off
C P H Charging @ I PH = 1 µA
I Q C C ≅ 1 5 0 µA
RPH = 0V
CPH = 0V
RUN = Open Circuit
VCC = 15.6V
CS Disabled
Oscillator Off

CPH > 4.0V

(End of PREHEAT Mode)
CS > 1.0V
(Failure to Strike Lamp
or Hard Switching)
or IGNITION RAMP Mode
T J > 175C
f PH ramps to f MIN
(Over-Temperature)
C P H Charging @ I PH = 1 µA
RPH = Open Circuit
RUN = Open Circuit
CS 1V Threshold Enabled

CS > 1.0V
(Over-Current or Hard Switching) CPH > 5.1V
or (End of IGNITION RAMP)
CS < 0.2V
(No-Load or Below Resonance)
or RUN Mode
T J > 175C f MIN Ramps to f R UN
(Over-Temperature)
C P H Charges to 7.6V Clamp
RPH = Open Circuit
RUN = 0V
CS 0.2V Threshold Enabled

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IR2157

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and
power dissipation ratings are measured under board mounted and still air conditions.

Symbol Definition Min. Max. Units

VB High side floating supply voltage -0.3 625
VS High side floating supply offset voltage VB - 25 VB + 0.3
V
VHO High side floating output voltage VS - 0.3 VB + 0.3
VLO Low side output voltage -0.3 VCC + 0.3
IOMAX Maximum allowable output current due to miller effect -500 500
mA
IRT RT pin current -5 5
VCT CT pin voltage -0.3 VCC + 0.3 V
ICPH CPH pin current -5 5 mA
VRPH RPH pin voltage -0.3 VCC + 0.3
VRUN RUN pin voltage -0.3 VCC + 0.3
VDT Deadtime pin voltage -0.3 5.5 V
VCS Current sense pin voltage -0.3 5.5
VSD Shutdown pin voltage -0.3 5.5
ICC Supply current (note 1) — 20 mA
dV/dt Allowable offset voltage slew rate -50 50 V/ns
PD Package power dissipation @ TA ≤ +25°C (16 lead PDIP) — 1.60
(16 lead SOIC) — 1.25
RthJA Thermal resistance, junction to ambient (16 lead PDIP) — 75
°C/W
(16 lead SOIC) — 100
TJ Junction temperature -55 150
TS Storage temperature -55 150 °C
TL Lead temperature (soldering, 10 seconds) — 300

Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown
voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source
greater than the VCLAMP specified in the Electrical Characteristics section.

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IR2157

Recommended Operating Conditions

For proper operation the device should be used within the recommended conditions.

Symbol Definition Min. Max. Units

VBs High side floating supply voltage V CC - 0.7 VCLAMP
VS Steady state high side floating supply offset voltage -3.0 600 V
VCC Supply voltage VCCUV+ VCLAMP
ICC Supply current note 2 10 mA
VDC VDC lead voltage 0 VCC V
CT CT lead capacitance 220 — pF
RDT Deadtime resistance 1.0 — kΩ
IRT RT lead current (note 3) -500 -50 uA
IRPH RPH lead current (note 3) 0 450 uA
IRUN RUN lead current (note 3) 0 450 uA
ISD Shutdown lead current -1 1 mA
ICS Current sense lead current -1 1 mA
o
TJ Junction temperature -40 125 C

Electrical Characteristics
VCC = VBS = VBIAS = 15V +/- 0.25V, RT = 40.0kΩ, CT = 470 pF, RPH and RUN leads no connection, VCPH = 0.0V, RDT =
6.1kΩ, VCS = 0.5V, VSD = 0.0V, CL = 1000pF, TA = 25oC unless otherwise specified.

Supply Characteristics
Symbol Definition Min. Typ. Max. Units Test Conditions
VCCUV+ VCC supply undervoltage positive going — 11.4 — VCC rising from 0V
threshold
VCCUV- VCC supply undervoltage positive going — 9.6 — V VCC falling from 15V
threshold
VHYSTUV VCC supply undervoltage lockout hysteresis — 1.8 —
IQCCUV UVLO mode quiescent current — 150 — VCC= 10V rising
IQCCFLT Fault-mode quiescent current (undervoltage — 200 — µA
lockout, shutdown, over-current, over-temp)
IQCC Quiescent VCC supply current — 3.8 — RT no connection, CT
connected to COM
mA
IQCC50K VCC supply current, f= 50kHz — 4.5 — RT =36kΩ, RDT =
5.6kΩ, CT=220pF
VCLAMP VCC zener clamp voltage — 15.6 — V I CC = 10mA

Note 2: Enough current should be supplied into the VCC lead to keep the internal 15.6V zener clamp diode on this lead
regulating its voltage.
Note 3: Due to the fact that the RT input is a voltage-controlled current source, the total RT pin current is sum of all of
the parallel current sources connected to that pin. For optimum oscillator current mirror performance, this total
current should be kept between 50mA and 500mA. During the preheat mode, the total current flowing out of
the RT pin consists of the RPH pin current plus the current due to the RT resistor. During the run mode, the
total RT pin current consists of the RUN pin current plus the the current due to the RT resistor.
4

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IR2157

Electrical Characteristics (cont.)

Floating Supply Characteristics
Symbol Definition Min. Typ. Max. Units Test Conditions
IQBS0 Quiescent VBS supply current — 0 — VHO = VS
µA
IQBS1 Quiescent VBS supply current — 30 — VHO = VB
VBSMIN Minimum required VBS voltage for proper — 4 5 V
HO functionality
ILK Offset supply leakage current — — 50 µA VB = VS = 600V

Oscillator I/O Characteristics

Symbol Definition Min. Typ. Max. Units Test Conditions
fosc Oscillator frequency — 30 — RT = 32kΩ, RDT =
6.1kΩ, CT=470pF
kHz
— 100 — RT = 6.1kΩ, RDT =
6.1kΩ, CT=470pF
df/dV Oscillator frequency voltage stability — 0.5 — %/V VCCUV+ < VCC < 15V
df/dT Oscillator frequency temperature stability — 0.02 — %/C -40oC < Tj < 125oC
d Oscillator duty cycle — 50 — %
VCT+ Upper CT ramp voltage threshold — 4.0 —
V
VCT- Lower CT ramp voltage threshold — 2.0 —
VCTFLT Fault-mode CT pin voltage — 0 — mV SD = 5V, CS = 2V,
or Tj > TSD
VRT RT pin voltage — 2.0 — V
VRTFLT Fault-mode RT pin voltage — 0 — SD = 5V, CS = 2V,
mV
or Tj > TSD
tdlo LO output deadtime — 2.0 —
µsec
toho HO output deadtime — 2.0 —
dtd/dV Deadtime voltage stability — 0.5 — %/V VCCUV+ < VCC < 15V
dtd/dT Deadtime temperature stability — 0.02 — %/C -40oC < Tj < 125oC

Preheat Characteristics
Symbol Definition Min. Typ. Max. Units Test Conditions
ICPH CPH pin charging current — 1.0 — µA VCPH = 0V
VCPHIGN CPH pin lgnition mode threshold voltage — 4.0 —
VCPHRUN CPH pin run mode threshold voltage — 5.15 — V
VCPHCLMP CPH pin clamp voltage — 7.6 — ICPH = 1mA
VCPHFLT Fault-mode CPH pin voltage — 0 — mV SD = 5V, CS = 2V,
or Tj > TSD

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IR2157

Electrical Characteristics (cont.)

RPH Characteristics
Symbol Definition Min. Typ. Max. Units Test Conditions
IRPHLK Open circuit RPH pin leakage current — 0.1 — µA VRPH = 5V,VRPH = 5V
VRPHFLT Fault-mode RPH pin voltage — 0 — mV SD = 5V, CS = 2V,
or Tj > TSD

RUN Characteristics
Symbol Definition Min. Typ. Max. Units Test Conditions
IRUNLK Open circuit RUN pin leakage current — 0.1 — µA VRUN = 5V
VRUNFLT Fault-mode RUN pin voltage — 0 — mV SD = 5V, CS = 2V,
or Tj > TSD

Protection Circuitry Characteristics

Symbol Definition Min. Typ. Max. Units Test Conditions
VSDTH+ Rising shutdown pin threshold voltage — 2.0 — V
VSDHYS Shutdown pin threshold hysteresis — 150 — mV
VCSTH+ Over-current sense threshold voltage — 1.0 —
VCSTH- Under-current sense threshold voltage — 0.2 — V
TCS Over-current sense propogation delay — 160 — nsec Delay from CS to LO
or HO
VDC+ Low VBUS /rectified line input upper threshold — 5.15 —
V
VDC- Low VBUS /rectified line input lower threshold — 3.0 —
o
TSD Thermal shutdown junction temperature — 175 — C

Gate Driver Output Characteristics

Symbol Definition Min. Typ. Max. Units Test Conditions
VOL Low-level output voltage — 0 100 Io = 0
mV
VOH High level output voltage — 0 100 VBIAS - VO, Io = 0
tr Turn-on rise time — 85 150
nsec
tf Turn-off fall time — 45 100

Note 4: When the IC senses an overtemperature condition (Tj > 175ºC), the IC is latched off. In order to reset this Fault
Latch, the SD pin must be cycled high and then low, or the VCC supply to the IC must be cycled below the
falling undervoltage lockout threshold (VCCUV-).

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IR2157

Lead Assignments & Definitions

Lead # Symbol Description
1 VDC DC bus sensing input 1 16
VDC HO
2 CPH Preheat timing capacitor
3 RPH Preheat frequency resistor & ignition capacitor CPH 2 15 VS
4 RT Oscillator timing resistor

IR2157
5 RUN Run frequency resistor RPH 3 14 VB
6 CT Oscillator timing capacitor
7 DT Deadtime programming RT 4 13 N/C
8 SD Shutdown input
9 CS Current sensing input RUN 5 12 VCC
10 LO Low-side gate driver output
CT 6 11 COM
11 COM IC Power & signal ground
12 VCC Logic & low-side gate driver supply 7 10
DT LO
13 N/C Unused
14 VB High-side gate driver floating supply SD 8 9 CS
15 VS High voltage floating return
16 HO High-side gate driver output

Functional Block Diagram

3.0V
14 VB
VDC 1
S Q
PULSE
LEVEL
R Q FILTER & 16 HO
5.1V
SHIFT
LATCH

1.0uA
15 VS
CPH 2

7.6V
5.1V

S Q T Q
4.0V 12 VCC
4.0V R1
R Q
RPH 3 2.0V R2 Q
10 LO
I RT
15.6V
RT 4
2.0V 11 COM

RUN 5

I CT = I RT
Q D 0.2V

CT 6 CLK 9 CS
Q S
Q R
Q R
DT 7
1.0V

SD 8
UNDER- OVER-
2.0V
VOLTAGE TEMP
DETECT DETECT

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IR2157

16 Lead SOIC (narrow body) 01-3064 00

16 Lead PDIP 01-3065 00

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IR2157

Description of Operation & Component Selection Tips

Supply Bypassing and PC Board Layout Connecting the IC Ground (COM) to the
Rules Power Ground
Component selection and placement on the pc Both the low power control circuitry and low side
board is extremely important when using power gate driver output stage grounds return to this pin
control ICs VCC should be bypassed to COM as close within the IC. The COM pin should be connected to
to the IC terminals as possible with a low ESR/ESL the bottom terminal of the current sense resistor in
capacitor, as shown in Figure 1 below. the source of the low side power MOSFET using an
individual pc board trace, as shown in Figure 2. In
addition, the ground return path of the timing
components and VCC decoupling capacitor should
pin 1
C B O O T (surface mount)
be connected directly to the IC COM pin, and not via
separate traces or jumpers to other ground traces on
IR2157

the board.
D Boot (surface mount)

C VCC (through hole)

IR2157 pin 1

C VCC (surface mount)

C VCC (surface mount)

Figure 1: Supply bypassing PCB layout example timing

C VCC (through hole)
components

R C S (through hole)

A rule of thumb for the value of this bypass capacitor

is to keep its minimum value at least 2500 times the V B U S return

value of the total input capacitance (Ciss) of the

power transistors being driven. This decoupling
capacitor can be split between a higher valued Figure 2: COM pin connection PCB layout example
electrolytic type and a lower valued ceramic type
connected in parallel, although a good quality
electrolytic (e.g., 10mF) placed immediately adjacent These connection technique prevents high current
to the VCC and COM terminals will work well. ground loops from interfering with sensitive timing
component operation, and allows the entire control
In a typical application circuit, the supply voltage to circuit to reject common-mode noise due to output
the IC is normally derived by means of a high value switching.
startup resistor (1/4W) from the rectified line voltage,
in combination with a charge pump from the output
of the half-bridge. With this type of supply
arrangement, the internal 15.6V zener clamp diode
from VCC to COM will determine the steady state IC
supply voltage.

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IR2157

The Control Sequence & Timing The heart of this controller is an oscillator which
resembles those found in many popular PWM voltage
Component Selection
regulator ICs. In its simplest form, this oscillator
consists of a timing resistor and capacitor connected
The IR2157 uses the following control sequence
to ground. The voltage across the timing capacitor
(Figure 3) to drive rapid start fluorescent lamps.
CT is a sawtooth, where the rising portion of the ramp
is determined by the current in the RT pin, and the
falling portion of the ramp is determined by an external
f Start
deadtime resistor RDT. The oscillograph in Figure 4
illustrates the relationship between the oscillator
frequency

fP H capacitor waveform and the gate driver outputs.

fR u n

f min

5V

V CPH

2V
V RPH

2V

V RUN

Preheat mode Ignition R u n m o d e

Ramp
mode

Figure 3: IR2157 control sequence

Figure 4
The control sequence used in the IR2157 allows
the Run Mode operating frequency of the ballast to
be higher than the ignition frequency (i.e., fstart > The deadtime can be programmed by means of the
fph > frun > fign). This control sequence is external RDT resistor, given a certain range of CT
recommended for lamp types where the ignition capacitor values, using the graph shown in Figure 5.
frequency is too close to the run frequency to ensure
proper lamp striking for all production resonant LC The RT input is a voltage-controlled current source,
component tolerances (please note that it is possible where the voltage is regulated to be approximately
to use the IR2157 in systems where fstart > fph > 2.0V. In order to maintain proper linearity between
fign > frun, simply by leaving the RUN pin open). the RT pin current and the CT capacitor charging
current, the value of the RT pin current should be
Six pins in the IC are used to control the Startup, kept between 50µA and 500µA. The RT pin can
Preheat, Ignition Ramp, and Run modes of also be used as a feedback point for closed loop
operation, and to allow ballast and lamp engineers control.
the flexibility to optimize their designs for virtually
any lamp type.

10

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 ADVANCED INFORMATION
IR2157
During the Startup Mode, the operating frequency is
10 determined by the parallel combination of RPH,
RSTART , and RT , combined with the values of
CSTART, CT and RDT , as shown in Figure 6. This
frequency is normally chosen to ensure that the
instantaneous voltage across the lamp during the
tDEAD first few cycles of operation does not exceed the
(usec) strike potential of the lamp. As the voltage across
CT = 220 pF
CSTART charges up to the RT pin voltage, the output
1
CT = 470 pF frequency exponentially decays to the preheat
CT = 1 nF
frequency.

During the Preheat Mode, the operating frequency

is determined by the parallel combination of RPH
and RT , combined with the value of CT and RDT .
This frequency, along with the Preheat Time, is
normally chosen to ensure that adequate heating of
0.1
the lamp filaments occurs. Typically, a 4.5:1 ratio of
1 10 100
RDT (Kohms)

Figure 5: Deadtime versus RDT

CPH 1.0uA

2
C PH 7.6V

5.1V

S Q
4.0V
4.0V R1
RPH
3 2.0V R2 Q

C IGN R PH
RT IRT

4
RT 2.0V
R RUN RUN
5
C START R START

CT ICT = IRT

6
CT R DT DT
7 UNDER-
VOLTAGE
DETECT

Figure 6: Oscillator section block diagram with external component connection

11

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IR2157

the hot filament-to-cold filament resistance is desired The following graphs, Figures 8 and 9, illustrate the
for maximum lamp life, as shown in Figure 7 relationship between the effective RT resistance (i.e.,
the parallel combination of resistors which programs
the CT capacitor charging current) and the operating
frequency.

150

FREQ
(KHz)
CT=220pF,RDT=11K
CT=470pF,RDT=6.2K
100 CT=1nF,RDT=3K

50

Figure 7: Lamp filament voltage during the

preheat, ignition ramp and run modes.
0
0 5 10 15 20 25 30 35 40
RT (K ohms)
The Preheat Time is programmed by means of the
preheat capacitor, CPH, an internal 1mA current Figure 8: fosc versus effective RT (tDEAD = 2.0 usec)
source, and an internal threshold on the CPH pin of
4.0V, according to the following formula:

tPH = 4E6 ⋅ CPH, or 250

CPH = 250E- 9 ⋅ tPH

At the end of the Preheat Time, the internal, open- 200

drain transistor holding the RPH pin to ground turns CT=220pF, RDT=5.6K
off, and the voltage on this pin charges exponentially CT=470pF, RDT=2.7K
CT=1nF, RDT=1.2K
up to the RT pin potential. During this Ignition Ramp 150
FREQ
Mode, the output frequency exponentially decays to (KHz)
a minimum value. The rate of decay of this frequency
is a function of the RPH * CPH time constant. Because 100
the Ignition Ramp Mode ends when the voltage on
the CPH pin reaches 5.15V, the ignition ramp is
always 1/4th as long as the preheat time. 50
When the CPH pin reaches 5.15V, an open-drain
transistor on the RUN pin turns on, and the external
RRUN resistor is then in parallel with the RT resistor. 0
The Run Mode operating frequency is therefore a 0 5 10 15 20 25 30 35 40
RT (K ohms)
function of the parallel combination of RRUN and
RT , and this means that the operating power of the
Figure 9: fosc versus effective RT (tDEAD = 1.0 usec)
lamp can be programmed by means of RRUN .
12

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IR2157

Lamp Protection & Automatic Restart Circuitry Operation

Three pins on the IR2157 are used for protection, as shown in Figure 10 below. These are VDC (dc bus
monitor), SD (unlatched shutdown), and CS (latched shutdown).

+ V BUS

R2 VDC 3.0V

1
S Q

R Q
5.1V
R1 C1
from oscillator
section
CPH 1.0uA T Q
2 R Q
7.6V

5.1V Q2

4.0V

R4
Q D 0.2V CS
CLK 9
DT
from lamp Q S
Q R R3
7
lower cathode Q R

R5 R CS
1.0V
SD
8
UNDER- OVER-
2.0V
VOLTAGE TEMP
C2 DETECT DETECT

Figure 10: Lamp protection & automatic restart circuitry block diagram with external component connection.

Sensing the DC Bus Voltage

The first of these protection pins senses the voltage pump off of the output of the half-bridge). In this
on the DC bus by means of an external resistor case, the voltage on the VDC pin will shut the oscillator
divider and an internal comparator with hysteresis. off, thereby protecting the power transistors from
When power is first supplied to the IC at system potentially hazardous hard switching. Approximately
startup, 3 conditions are required before oscillation 2V of hysteresis has been designed into the internal
is initiated: 1.) the voltage on the VCC pin must comparator sensing the VDC pin, in order to account
exceed the rising undervoltage lockout threshold for variations in the dc bus voltage under varying
(11.5V), 2.) the voltage at the VDC pin must exceed load conditions. When the dc bus recovers, the chip
5.1V, and 3.) the voltage on the SD pin must be below restarts from the beginning of the control sequence,
approximately 1.85V. If a low dc bus condition occurs as shown in timing diagram 11 below.
during normal operation, or if power to the ballast is
shut off, the dc bus will collapse prior to the VCC of
the chip (assuming the VCC is derived from a charge

13

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IR2157

rectified
AC line + VB U S

VDC HO
1 16 Q1
5 RGHS
CPH VS
VDC 2 15 CBLOCK LRES

IR2157
3 RPH VB
3 14 C BOOT R SUPPLY
RSNUBBER
RT N/C
4 13
D BOOT D1 CS N U B B E R
RUN VCC
5 12
4 CRES
CT COM CVCC
6 11
D2
CT DT LO
7 10 Q2
R GLS
SD CS
8 9
R3 R4
8 C2 RCS

CPH R5

V B U S return

15

LO Figure 12: Lamp presence detection circuit

connection (shaded area)

15

HO-VS

SD
RUN mode Low VDC Restart

Figure 11: VDC pin fault and auto restart CT

CPH
Lamp Presence Detection and
Automatic Restart
15

The second protection pin, SD, is used for both LO

unlatched shutdown and automatic restart functions.
The SD pin would normally be connected to an
external circuit which senses the presence of the
15
lamp (or lamps), as shown in Figure 12.
HO-VS

When the SD pin exceeds 2.0V (approximately

150mV of hysteresis is included to increase noise
RUN mode SD mode Restart
immunity), signaling either a lamp fault or lamp
removal, the oscillator is disabled, both gate driver
Figure 13: SD pin fault and auto restart
outputs are pulled low, and the chip is put into the
micropower mode. Since a lamp fault would normally
lead to a lamp exchange, when a new lamp is conditions a reset signal would restart the chip from
inserted into the fixture, the SD pin would be pulled the beginning of the control sequence, as shown in
back to near the ground potential. Under these the timing diagram in Figure 13.
14

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IR2157

Thus, for a lamp removal and replacement, the ballast and under-resonance conditions, there is a negative-
automatically restarts the lamp in the proper manner, going threshold of 0.2V which is enabled at the onset
maximizing lamp life and minimizing stress on the of the run mode. The sensing of this 0.2V threshold
power MOSFETs or IGBTs. The SD pin contains an is synchronized with the falling edge of the LO output.
internal 7.5V zener diode clamp, thereby reducing
the number of external components required. Figures 15, 16 and 17 are oscillographs of fault
conditions. Figure 15 shows a failure of the lamp to
Half-Bridge Current Sensing and strike, Figure 16 shows a hard switching condition
Protection and Figure 17 shows an under-current condition.

The third pin used for protection is the CS pin, which

is normally connected to a resistor in the source of
the lower power MOSFET, as shown in Figure 14.

The CS pin is used to sense fault conditions such a

failure of a lamp to strike, over-current during normal
operation, hard switching, no load, and operation
below resonance. If any one of these conditions is
sensed, the fault latch is set, the oscillator is disabled,
the gate driver outputs go low, and the chip is put
into the micropower mode. The CS pin performs its
sensing functions on a cycle-by-cycle basis in order
to maximize ballast reliability. failure-to-strike, and
For the over-current, hard switching fault conditions,
the 1V, positive-going CS threshold is enabled at
the end of the preheat time. For the under-current
Figure 15: Lamp failure to strike
rectified
AC line +V B U S

VDC HO
1 16 Q1
R GHS
CPH VS
2 15
IR2157

1
RPH VB / 2 Bridge output
3 14 CBOOT R SUPPLY
R SNUBBER
RT N/C
4 13
DBOOT D1 C SNUBBER
RUN VCC
5 12
CT COM C VCC
6 11
D2
DT LO
7 10 Q2
R GLS
SD CS
8 9
R3
R CS

V B U S return

Figure 14: Half-bridge current sensing circuit

connection (shaded area) Figure 16: Hard switching condition

15

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IR2157

Recovery from such a fault condition is accomplished

by cycling either SD pin or the VCC pin. When a
lamp is removed, the SD pin goes high, the fault
latch is reset, and the chip is held off in an unlatched
state. Lamp replacement causes the SD pin to go
low again, reinitiating the startup sequence. The
fault latch can also be reset by the undervoltage
lockout signal, if VCC falls below the lower
undervoltage threshold.

Bootstrap Supply Considerations

Power is normally supplied to the high-side circuitry
by means of a simple charge pump from VCC, as
shown in Figure 19 below.

rectified
AC line +V B U S

VDC HO
Figure 17: Operation below resonance 1 16
R GHS
Q1
CPH VS
2 15
IR2157

1
RPH VB / 2 Bridge output
3 14 CBOOT R SUPPLY
RSNUBBER
RT N/C
4 13
DBOOT D1 CSNUBBER
RUN VCC
5 12
CT COM C VCC
6 11
D2
DT LO
7 10 Q2
R GLS
SD CS
8 9
R3
R CS

V B U S return

Figure 19: Typical bootstrap supply connection

with VCC charge pump from half-bridge output
(shaded area)

A high voltage, fast recovery diode DBOOT (the so-

called bootstrap diode) is connected between VCC
(anode) and VB (cathode), and a capacitor CBOOT
(the so-called bootstrap capacitor) is connected
between the VB and VS pins. During half-bridge
switching, when MOSFET Q2 is on and Q1 is off, the
bootstrap capacitor CBOOT is charged from the VCC
Figure 18: Auto restart for lamp replacement decoupling capacitor, through the bootstrap diode
DBOOT, and through Q2. Alternately, when Q2 is off
and Q1 is on, the bootstrap diode is reverse-biased,
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 ADVANCED INFORMATION
IR2157

and the bootstrap capacitor (which ‘floats’ on the

pin 1
source of the upper power MOSFET) serves as the
C B O O T (surface mount)
power supply to the upper gate driver CMOS circuitry.
Since the quiescent current in this CMOS circuitry is

IR2157
very low (typically 45mA in the on-state), the majority
D Boot (surface mount)
of the drop in the VBS voltage when Q1 is on occurs
due to the transfer of charge from the bootstrap
capacitor to the gate of the power MOSFET. C VCC (through hole)

C VCC (surface mount)

VB should be bypassed to VS as close as possible
to the pins of the IC with a low ESR/ESL capacitor. A
PCB layout example is shown in figure 20. A rule of
Figure 20: Supply bypassing PCB layout example
thumb for the value of this capacitor is to keep its
minimum value at least 50 times the value of the total
input capacitance (Ciss) of the MOSFET or IGBT being
driven. In addition, the VS pin should be connected
directly to the high side power MOSFET source.

Characteristic Curves
0.15
100

0.125 T = -25
T = 25C
10
T = 75C
0.1 T = 125C
Iqcc
(mA)
1
Iqcc 0.075
(mA)
0.1
0.05

0.01 0.025

0
0.001 0 2 4 6 8 10 12
0 2 4 6 8 10 12 14 16 VCC (volts)
VCC (volts)
Figure 22: I QCC versus V CC and temperature
Figure 21: IQCC versus VCC (VCC < VCC+)

4 30

25

T = -25
3.5 T = 25C
20
T = 75C
Iqcc
T = 125C
(mA)
Iqcc
(mA) 15

3 T = -25 10
T = 25C
T = 75C
T = 125C 5

2.5 0
11.5 12.5 13.5 14.5 14.5 15 15.5 16 16.5
VCC (volts) VCC (volts)

Figure 23: IQCC versus VCC and temperature Figure 24: VCLAMP versus I QCC and temperature
(VCC > VCC+)

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 ADVANCED INFORMATION
IR2157

80
12

70 T = -25C
11.5 T = 25C
60 T = 75C
Vccuv+ T = 125C
11
50
Vccuv
(V)
Iqbs1
10.5 40
(uA)

30
10
Vccuv- 20

9.5
10

9 0
-25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 18 20
Temperature (C) VBS (volts)

Figure 25: VCCUV+ and VCCUV- versus temperature Figure 26: IQBS1 versus VBS

54 210

T = -25C
53.75 207.5
T = 25C
T = 75C
53.5 205
T = 125C

53.25 202.5

fOSC fOSC
53 200
(KHz) (KHz)

52.75 197.5

T = -25C
52.5 195
T = 25C
T = 75C
52.25 192.5
T = 125C

52 190
11 11.5 12 12.5 13 13.5 14 14.5 15 11 11.5 12 12.5 13 13.5 14 14.5 15
VCC (volts) VCC (volts)

Figure 27: fOSC versus VCC and temperature Figure 28: fOSC versus VCC and temperature
(RT=330kΩ, CT=300pF) (RT=6.2kΩ, CT=300pF)

1000 80
T = -25C T = -25C
990
T = 25C T = 25C
T = 75C 70
980 T = 75C
T = 125C T = 125C
970
60
960

tDEAD
950 50
(nsec)
tfall
940 (nsec)
40
930

920
30
910

900 20
11 11.5 12 12.5 13 13.5 14 14.5 15 11 11.5 12 12.5 13 13.5 14 14.5 15
VCC (volts) VCC (volts)

Figure 29: tDEAD versus VCC and temperature Figure 30: tfall versus VCC and temperature

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IR2157

160 1.1
T = -25C
T = 25C T = -25C
140 T = 75C T = 25C
1.08
T = 125C T = 75C
T = 125C
120
1.06

trise CS+
100 (volts)
(nsec)
1.04

80

1.02
60

40 1
11 11.5 12 12.5 13 13.5 14 14.5 15 11 11.5 12 12.5 13 13.5 14 14.5 15
VCC (volts) VCC (volts)

Figure 31: trise versus VCC and temperature Figure 32: CS+ threshold versus VCC and temperature

0.235 2.15

T = -25C T = -25C
0.23
T = 25C 2.125 T = 25C
T = 75C T = 75C
0.225 T = 125C T = 125C
2.1
SD+
0.22 (volts)
CS-
(volts) 2.075

0.215

2.05
0.21

2.025
0.205

0.2 2
11 11.5 12 12.5 13 13.5 14 14.5 15 11 11.5 12 12.5 13 13.5 14 14.5 15
VCC (volts) VCC (volts)

Figure 33: CS- threshold versus VCC and temperature Figure 34: SD+ threshold versus VCC and temperature

0.25 5.4
T = -25C
T = -25C
T = 25C 5.35
0.225 T = 25C
T = 75C
T = 75C
T = 125C
5.3 T = 125C
0.2
SD 5.25
hysterisis VDC+
(volts) (volts)
0.175 5.2

5.15
0.15

5.1

0.125
5.05

0.1 5
11 11.5 12 12.5 13 13.5 14 14.5 15 11 11.5 12 12.5 13 13.5 14 14.5 15
VCC (volts) VCC (volts)

Figure 35: SD hysterisis versus VCC and temperature Figure 36: VDC+ threshold versus VCC and temperature

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 ADVANCED INFORMATION
IR2157

3.3 4.15

T = -25C T = -25C
T = 25C T = 25C
3.25
4.1 T = 75C
T = 75C
T = 125C T = 125C

3.2
4.05

VDC- VCPHIGN
3.15 (volts)
(volts)
4

3.1

3.95
3.05

3.9
3 11 11.5 12 12.5 13 13.5 14 14.5 15
11 11.5 12 12.5 13 13.5 14 14.5 15 VCC (volts)
VCC (volts)
Figure 38: VCPHIGN threshold versus VCC and
Figure 37: VDC- threshold versus VCC and temperature temperature

5.25 1.2

T= -25C 1.15
5.2 T= 25C
T= 75C 1.1
T= 125C
5.15 1.05
VCPHRUN
ICPH
(volts) 1
(uA)
5.1
0.95

0.9 T = -25C
5.05
T = 25C
T = 75C
0.85
T = 125C
5
11 11.5 12 12.5 13 13.5 14 14.5 15 0.8
VCC (volts) 11 11.5 12 12.5 13 13.5 14 14.5 15
VCC (volts)
Figure 39: VCPHRUN threshold versus VCC and
temperature Figure 40: ICPH versus V CC and temperature

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http://www.irf.com/ Data and specifications subject to change without notice. 3/1/99
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