2552 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO.

6, NOVEMBER 2007

Small-Signal Discrete-Time Modeling of Digitally Controlled PWM Converters

Dragan Maksimovic, Senior Member, IEEE, and Regan Zane, Senior Member, IEEE

Abstract—The letter presents an exact small-signal discrete-time and the converter states at a particular instant during a switching
model for digitally controlled pulsewidth modulated (PWM) dc–dc period (e.g., at a beginning of the switch on-time [3], [4]). There-
converters operating in constant frequency continuous conduc- fore, these models are not directly applicable to digitally con-
tion mode (CCM) with a single effective A/D sampling instant
per switching period. The model, which is based on well-known trolled converters where the A/D sampling instants can occur
approaches to discrete-time modeling and the standard -trans- at any time during a switching period. To address this problem,
form, takes into account sampling, modulator effects and delays a frequency-domain approach based on Laplace-domain modu-
in the control loop, and is well suited for direct digital design of lator modeling [13] and the modified -transform has been de-
digital compensators. The letter presents general results valid scribed in [10]. This approach results in an exact discrete-time
for any CCM converter with leading or trailing edge PWM.
Specific examples, including approximate closed-form expressions model that correctly takes into account sampling, modulator ef-
for control-to-output transfer functions are given for buck and fects and delays in the digital control loop. However, according
boost converters. The model is verified in simulation using an to [10], the approach is straightforwardly applicable only to
independent system identification approach. buck-type converters.
Index Terms—DC–DC converter, digital control, discrete-time The purpose of this letter is to show how the well-known dis-
model, pulsewidth modulation (PWM) converter, small-signal crete-time modeling [1]–[4] can be extended to take into ac-
model. count the sampling, modulator effects and delays in a digitally
controlled converter. The result is an exact small-signal dis-
I. INTRODUCTION crete-time model applicable to any constant-frequency PWM
converter. Section II describes the modeling approach. Model
examples and verification results are presented in Section III.
D ISCRETE-TIME modeling of dc–dc switching converters
has had a long history of contributions, starting from [1].
Effects of sampling due to the pulse-width modulator in the con-
Conclusions are given in Section IV.

text of averaged small-signal models and standard analog con- II. DISCRETE-TIME MODELING WITH DIGITAL
trollers were discussed in [2]. Extensions of discrete-time mod- CONTROLLER SAMPLING AND DELAYS
eling have included generalizations to various analog control Fig. 1(a) shows a dc–dc converter (e.g., a buck converter) with
techniques including constraint modulations [3], [4], as well as digital voltage-mode control. In the discussion, without loss of
applications to computer-aided modeling and simulations [5], generality, a sensing gain of 1 is assumed together with
[6]. Exact continuous-time small-signal converter models have a constant-frequency trailing-edge PWM having an equivalent
been developed based on a combination of discrete-time models saw-tooth amplitude 1. The converter operates in contin-
and the concept of equivalent hold [7]. Recently, the growing in- uous-conduction mode. In each state of the switch (1 or 2), the
terest in practical digital control for high-frequency dc–dc con- converter circuit is linear, time-invariant, with the corresponding
verters has prompted renewed interest in discrete-time analysis state-space description
and modeling [8]–[12] to facilitate direct digital compensator
design. In a digitally controlled constant-frequency pulsewidth
modulated (PWM) converter, an example of which is shown in (1)
Fig. 1(a), the output voltage error is sampled by an A/D con-
verter. A discrete-time compensator computes a duty-cycle con- where is the vector of converter states (e.g., inductor current
trol signal for a digital pulse-width modulator (DPWM). Dis- and capacitor voltage, ). We assume the input voltage
crete-time models suitable for sampling rates lower than the is constant, since the primary interest is in the control-to-
switching frequency have been discussed in [8]. Sampling rates output responses.
equal to or even exceeding the switching frequency are now The A/D converter samples the output voltage error at the
practical, with dynamic performance dependent on control-loop sampling rate equal to the switching frequency . The error
delays [10]–[12]. As noted in [10], the previously derived dis- signal samples are processed by a discrete-time compensator
crete-time models describe the behavior of the control variable . The compensator output samples control the switch
duty cycle via a digital pulse-width modulator (DPWM). This
modulator can be viewed as a D/A converter including a sample-
Manuscript received May 10, 2007; revised June 19, 2007. This work was and-hold followed by signal sampling at the modulated edge [2].
supported through the Colorado Power Electronics Center. Recommended for
publication by Associate Editor R. Teodorescu.
It is important to note that there are two samplers in the feed-
The authors are with the Colorado Power Electronics Center, Electrical back loop: A/D sampling of the error voltage, and the modulator
and Computer Engineering Department, University of Colorado, Boulder, CO sampling. As a result, the system small-signal model does not
80309-0425 USA (e-mail: [email protected]; [email protected]). include a sample-and-hold. Instead, the relationship between the
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org. small-signal perturbations of the voltage error signal and the
Digital Object Identifier 10.1109/TPEL.2007.909776 duty-cycle includes a delay between the A/D sampling
0885-8993/$25.00 © 2007 IEEE
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2553

, the derivation of is not necessary. We simply pro-

ceed with the discrete-time model derivation according to the
waveforms shown in Fig. 1(c). These waveforms are shown for
the specific case of trailing edge modulation and the A/D sam-
pling in interval 2 . The small-signal dis-
crete-time model can be written as

(2)

where the matrix and vector coefficients can be solved by propa-

gating the effect of each perturbation during the converter switch
states according to (1) and Fig. 1(c). Consider first the effect of
only a perturbation 1 of the states. Starting from the A/D
sampling at 1 , the perturbation 1 propagates
through switch state 2 for , state 1 for , and fi-
nally state 2 for . Therefore, the resulting perturbation
after one period is given by

(3)

where is the steady-state duty ratio. Next, consider only the

effect of perturbation in the duty cycle. The initial per-
turbation in the states occurs at the modulation edge of the
PWM output signal and can be found from (1) as linear exten-
sions of the previous and next switch states

(4)

where are the steady-state states at the PWM sampling

instant, . The perturbation then propagates
through the system over the remaining part of the switching
period, which is in switch state 2 for . The resulting
matrix and vector coefficients for the model (2) are given in
Table I, where and

(5)
Fig. 1. (a) Switching dc–dc converter with digital voltage-mode control. (b)
Small-signal model of the digitally controlled dc–dc converter. (c) Waveforms
illustrating discrete-time model derivation for the digitally controlled dc–dc The output state-space equation can be added according to (1)
converter with A/D sampling during interval 2. as follows:

(6)
at and the modulator sampling at , as shown in
Fig. 1(b), and illustrated by the waveforms in Fig. 1(c). The Note that is the state-to-output matrix in the subinterval
total delay in the control loop includes the A/D conversion when the A/D sampling occurs [interval in the case of the
time, the computation delay (i.e., the time it takes to compute the timing diagram in Fig. 1(c)]. Finally, the standard -transform
duty-cycle control signal ), as well as the modulator delay of (2) and (6) gives the desired discrete-time control-to-output
(i.e., the time between the update of and the switch transi- transfer functions.
tion from state 1 to state 2). In the discussion that follows, we as- Although a buck converter is shown in Fig. 1(a), the results
sume that the total delay is shorter than the switching period , in Table I are valid for any PWM converter that can be defined
0 . Inclusion of the delay in the discrete-time model by the state-space description in (1). In addition, although the
presented here is the key extension compared to the models in waveforms in Fig. 1(c) and the discussion above are based on
[1]–[4]. trailing-edge modulation and A/D sampling in interval 2, ex-
As shown in the model of Fig. 1(b), the samples af- tensions to other modulation types or other sampling times are
fect the converter state perturbations through the equivalent simple. The results in Table I cover both leading- and trailing-
hold which models the converter responses between the edge modulation with A/D sampling in either interval 1 or 2.
samples, leading to exact continuous-time models [7]. Since the All that is required to derive an exact discrete-time model of
digital control system only operates on the values of the state a digitally controlled PWM converter in CCM is to define the
variables or the outputs sampled at the A/D sampling instants state-space description in the form of (1). Component losses,
2554 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

TABLE I
DISCRETE-TIME SMALL-SIGNAL MODEL PARAMETERS FOR TRAILING AND LEADING EDGE PWM CONVERTERS IN CCM

input filters and other converter elements can all be accounted for , . The model (2), (6) and Table I then
for in the state-space description. The small-signal model is then simplify to
obtained from (2) and (6) according to the coefficients in Table I.
Such models can be easily defined in matrix-based tools such as (13)
MATLAB and used for direct digital controller design. Exten- (14)
sions to modeling converters in discontinuous conduction mode (15)
are not difficult.
Examples of direct digital design of proportional, integral, (16)
derivative (PID) and higher-order compensators, as well as ex-
Approximate expansions of the matrix exponentials in (14)
perimental verifications of digitally controlled converters based
and (15), such as or the alternatives proposed in
on the discrete-time model presented in this letter have been dis-
[17], can be employed to obtain an approximate closed-form an-
cussed in [14]–[16].
alytical discrete-time model. Using the approximation
III. MODEL EXAMPLE AND VERIFICATION , the standard -transform of (13) and (16) yields the
control-to-output transfer function in closed form
As an example, consider the buck converter of Fig. 1(a) with
trailing edge PWM and: 5 H, 25 m , 5 F,
(17)
16 m , 1 , 10 V, 1 V, 0.2,
1 1 MHz. In the buck converter, ,
, 0, , 0. The coefficients in (1) where the numerator and denominator polynomials in (17) are
are given by shown in Table II. Results are shown for the ideal (no losses)
buck converter and the ideal boost converter with A/D sampling
(7) in interval 1 or in interval 2. Further discussions related to boost
or flyback converters with capacitor ESR can be found in [16].
Note in all cases that the zeros of the discrete-time control-to-
(8) output voltage transfer functions depend on the total delay in
the control loop, while the poles are not affected by the delay.
(9) For the nonideal buck converter, it is also interesting to note that
the capacitor ESR does not add another zero. Rather, it just shifts
(10) the zero in the direction opposite to the effect of . Fig. 2 shows
the magnitude and phase responses of for the buck con-
Note that only the output voltage is used in (10) since verter with the parameters defined earlier at the nominal
the primary interest is in solving the control-to-output voltage 16 m for 0, 0.5 , and . The delay effects,
transfer function. Additional outputs could be easily defined which are clearly visible, especially in the phase responses, must
based on the desired transfer function (e.g., inductor current). be taken into account in the design of high-performance digital
The description of (7)–(10) can then be used to define the exact controllers.
small-signal model according to (2), (6), and Table I in a soft- The model results are also shown in Fig. 3 at 0.5
ware tool such as MATLAB. In addition, approximate closed- and compared to an independent method of frequency response
form expressions can be derived to gain insight into the effects identification. The comparison was generated by performing
of system parameters, including the control loop delay . a switching level time-domain simulation in Simulink and in-
As an example, in order to simplify the analysis, losses are jecting perturbation signals on the steady-state duty cycle for
neglected except for the dominant effect of the capacitor ESR, cross-correlation based system identification, as described in
, in (9). Resulting simplified equations for and are [18]. The simulation was performed using the buck converter
given by parameters defined above, a delay element to adjust according
to Fig. 1 (interval 2 sampling) and no quantization in the PWM
(11) or output signal sampling. The samples (dots) obtained through
transient identification are exact matches to the small-signal
(12) model (17), as shown in Fig. 3.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 2555

TABLE II
POLYNOMIALS FOR APPROXIMATE BUCK AND BOOST CLOSED-FORM CONTROL-TO-OUTPUT TRANSFER FUNCTIONS (TRAILING EDGE PWM)

Fig. 2. Magnitude and phase responses of G z

( ) for the digitally-controlled Fig. 3. Comparison of model-based G z ( ) (line) to identification results
buck converter example operating atf R
= 1 MHz, = 16 m
, for three (dots) for the digitally-controlled buck converter example operating at f =
t t
values of the total delay : t T t T
= 0, = 0.5 , = . 1 MHz, t T R
= 0.5 , = 16 m
.

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