NI R Series Multifunction RIO User Manual
NI R Series Multifunction RIO User Manual
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ni.com/manuals
June 2009
370489G-01
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on ni.com/legal for more information about National Instruments trademarks.
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Patents
For patents covering National Instruments products/technology, refer to the appropriate location: Help»Patents in your software,
the patents.txt file on your media, or the National Instruments Patent Notice at ni.com/patents.
Chapter 1
Introduction
About the Reconfigurable I/O Device ...........................................................................1-1
Using PXI with CompactPCI.........................................................................................1-2
Overview of Reconfigurable I/O ...................................................................................1-3
Reconfigurable I/O Concept............................................................................1-3
Flexible Functionality .......................................................................1-4
User-Defined I/O Resources .............................................................1-4
Device-Embedded Logic and Processing .........................................1-4
Reconfigurable I/O Architecture .....................................................................1-5
Reconfigurable I/O Applications.....................................................................1-6
Software Development ..................................................................................................1-6
LabVIEW FPGA Module................................................................................1-6
LabVIEW Real-Time Module.........................................................................1-7
Cables and Accessories..................................................................................................1-8
Custom Cabling .............................................................................................................1-9
Chapter 2
Hardware Overview of the NI 78xxR
NI 7811R Overview.......................................................................................................2-3
NI 7813R Overview.......................................................................................................2-3
NI 7830R Overview.......................................................................................................2-3
NI 7831R/7833R Overview ...........................................................................................2-4
NI 784xR Overview.......................................................................................................2-4
NI 785xR Overview.......................................................................................................2-4
Analog Input (NI 783xR/784xR/785xR Only)..............................................................2-4
Input Modes.....................................................................................................2-5
Input Range .....................................................................................................2-5
Connecting Analog Input Signals ..................................................................................2-6
Chapter 3
Calibration (NI 783xR/784xR/785xR Only)
Loading Calibration Constants ...................................................................................... 3-1
Self-Calibration ............................................................................................................. 3-1
External Calibration....................................................................................................... 3-2
Appendix A
Connecting I/O Signals
Appendix B
Using the SCB-68 Shielded Connector Block
Appendix C
Technical Support and Professional Services
Glossary
Conventions
The following conventions appear in this manual:
NI 78xxR NI 781xR, 783xR, NI 784xR, and NI 785xR refer to all PCI, PCI Express,
and PXI R Series devices.
Related Documentation
The following documents contain information that you may find helpful as
you use this help file. Your documentation needs may vary depending on
the hardware and software you use for your application.
Note Most R Series manuals are available as PDFs. You must have Adobe Reader with
Search and Accessibility 5.0.5 or later installed to view the PDFs. Refer to the Adobe
Systems Incorporated Web site at www.adobe.com to download Adobe Reader. Refer to
ni.com/manuals for updated documentation resources.
Software Documentation
• LabVIEW FPGA documentation
– Getting Started with LabVIEW FPGA 8.x—This KnowledgeBase,
available at ni.com/kb, provides links to the top resources that
can be used to assist in getting started with programming in
LabVIEW FPGA.
– FPGA Module book in the LabVIEW Help—Select Help»Search
the LabVIEW Help in LabVIEW to view the LabVIEW Help.
Browse the FPGA Module book in the Contents tab for
information about using the FPGA Module to create VIs that run
on the NI 78xxR device.
– LabVIEW FPGA Module Release and Upgrade Notes—Contains
information about installing the LabVIEW FPGA Module,
describes new features, and provides upgrade information.
To access this document, refer to ni.com/manuals. In
LabVIEW 8.0 or later, you can also view the LabVIEW Manuals
directory that contains this document by selecting Start»
All Programs»National Instruments»LabVIEW»LabVIEW
Manuals.
• LabVIEW Real-Time documentation
– Getting Started with the LabVIEW Real-Time Module—Provides
exercises to teach you how to develop a real-time project and VIs,
from setting up RT targets to building, debugging, and deploying
real-time applications. This document provides references to the
LabVIEW Help and other Real-Time Module documents for more
information as you create the real-time application. To access this
document, refer to ni.com/manuals. In LabVIEW 8.0 or later,
you can also view the LabVIEW Manuals directory that contains
this document by selecting Start»All Programs»National
Instruments»LabVIEW»LabVIEW Manuals.
– Real-Time Module book in the LabVIEW Help—Select Help»
Search the LabVIEW Help in LabVIEW to view the LabVIEW
Help. Browse the Real-Time Module book in the Contents tab
for information about how to build deterministic applications
using the LabVIEW Real-Time Module.
– LabVIEW Real-Time Module Release and Upgrade
Notes—Includes information about system requirements,
installation, configuration, new features and changes, and
compatibility issues for the LabVIEW Real-Time Module.
To access this document, refer to ni.com/manuals. In
LabVIEW 8.0 or later, you can also view the LabVIEW Manuals
Device-Specific Documentation
• Getting Started with R Series Multifunction RIO—This document
explains how to install and configure NI 781xR/783xR/784xR/785xR,
and contains a tutorial that demonstrates how to begin taking a
measurement using LabVIEW FPGA. This document is available at
ni.com/manuals.
• NI R Series Multifunction RIO Specifications—Lists the specifications
of the NI 781xR/783xR/784xR/785xR R Series devices. This
document is available at ni.com/manuals.
Additional Resources
The following documents contain information you might find helpful:
• NI Developer Zone tutorial, Field Wiring and Noise Considerations
for Analog Signals, at ni.com/zone
• PICMG CompactPCI 2.0 R3.0
• PXI Hardware Specification Revision 2.1
• PXI Software Specification Revision 2.1
• National Instruments Example Finder—LabVIEW contains an
extensive library of VIs and example programs for use with R Series
devices. To access the NI Example Finder, open LabVIEW and select
Help»Find Examples, then select Hardware Input and Output»
R Series.
• LabVIEW FPGA IPNet—Offers resources for browsing,
understanding, and downloading LabVIEW FPGA functions or IP
(Intellectual Property). Use this resource to acquire IP that you need
for your application, download examples to help learn programming
techniques, and explore the depth of IP offered by the LabVIEW
FPGA platform. To access the LabVIEW FPGA IPNet, visit
ni.com/ipnet.
instrument (VI) to the FPGA. Using the FPGA Module, you can
graphically design the timing and functionality of the R Series device.
If you only have LabVIEW but not the FPGA Module, you cannot create
new FPGA VIs, but you can create VIs that run on Windows or a LabVIEW
Real-Time (RT) target to control existing FPGA VIs.
The NI 78xxR uses the Real-Time System Integration (RTSI) bus to easily
synchronize several measurement functions to a common trigger or timing
event. R Series PCI devices access the RTSI bus through a RTSI cable
connected between devices. R Series PXI devices access the RTSI bus
through the PXI trigger lines implemented on the PXI backplane.
Caution Damage can result if the J2 lines are driven by the sub-bus.
Flexible Functionality
Flexible functionality allows the NI 78xxR to match individual application
requirements and to mimic the functionality of fixed I/O devices. For
example, you can configure an R Series device in one application for
three 32-bit quadrature encoders and then reconfigure the R Series device
in another application for eight 16-bit event counters.
You also can use the R Series device with the LabVIEW Real-Time
Module in timing and triggering applications, such as control and
hardware-in-the-loop (HIL) simulations. For example, you can configure
the R Series device for a single timed loop in one application and then
reconfigure the device in another application for four independent timed
loops with separate I/O resources.
Bus Interface
Software accesses the R Series device through the bus interface, and the
FPGA connects the bus interface and the fixed I/O to make possible timing,
triggering, processing, and custom I/O measurements using the LabVIEW
FPGA Module.
The FPGA logic provides timing, triggering, processing, and custom I/O
measurements. Each fixed I/O resource used by the application uses a small
portion of the FPGA logic that controls the fixed I/O resource. The bus
interface also uses a small portion of the FPGA logic to provide software
access to the device.
You can place useful applications in the FPGA. How much FPGA space
your application requires depends on your need for I/O recovery, I/O, and
logic algorithms.
The FPGA does not retain the VI when the R Series device is powered off,
so you must reload the VI each time you power on the device. You can load
the VI from onboard Flash memory or from software over the bus interface.
One advantage to using Flash memory is that the VI can start executing
almost immediately after power up, instead of waiting for the computer to
completely boot and load the FPGA VI. Refer to the LabVIEW Help for
more information about how to store your VI in Flash memory.
Software Development
You can use LabVIEW with the LabVIEW FPGA Module to program the
NI 78xxR. To develop real-time applications that control the NI 78xxR, use
LabVIEW with the LabVIEW Real-Time Module.
Use the FPGA Interface functions when you target LabVIEW for Windows
or an RT target to create host VIs that wait for interrupts and control the
FPGA by reading and writing the FPGA VI running on the R Series device.
Note If you use the R Series device without the FPGA Module, you can use the RIO
Device Setup utility, available by selecting Start»All Programs»National Instruments»
NI-RIO»RIO Device Setup to download precomplied FPGA VIs to the Flash memory of
the R Series device. This utility installs with NI-RIO. You also can use the utility to
configure the analog input mode, to synchronize the clock on the R Series device to the
PXI clock (for NI PXI-78xxR only), and to configure when the VI loads from Flash
memory. For more information about using the RIO Device Setup utility, refer to the
RIO Device Setup Help, found at Start»All Programs»National Instruments»NI-RIO»
RIO Device Setup Help.
Custom Cabling
NI offers a variety of cables for connecting signals to the NI 78xxR. If you
need to develop a custom cable, a nonterminated shielded cable is available
from NI. The SHC68-NT-S connects to the NI 78xxR VHDCI connectors
on one end of the cable. The other end of the cable is not terminated. This
cable ships with a wire list identifying the wires that correspond to each
NI 78xxR pin. You can use this cable to quickly connect the NI 78xxR
signals that you need to the connector of your choice. Refer to Appendix A,
Connecting I/O Signals, for the NI 78xxR connector pinouts.
Figure 2-1 shows a block diagram for the NI 781xR. Figure 2-2 shows a
block diagram for the NI 7830R. Figure 2-3 shows a block diagram for the
NI 7831R/7833R/784xR/785xR.
PCI/PXI/CompactPCI Bus
Connector 0 (DIO)
User-Configurable Control
Bus
Digital I/O (40) FPGA on Data/Address/Control
Interface
RIO Devices Address/Data
Connector 1 (DIO)
RTSI Bus
Calibration
Input Mux DACs Configuration Flash
AI+ +
Control Memory
16-Bit
Configuration
Instrumentation
AI– Ampliflier ADC
–
PCI/PXI/CompactPCI Bus
x4 Channels
Connector 0 (MIO)
RTSI/PXI Triggers
Digital I/O (40)
PXI Local Bus (NI PXI-7830R only)
RTSI Bus
Calibration
Input Mux DACs Configuration Flash
AI+ Control Memory
+
Configuration
Instrumentation 16-Bit
AI– Amplifier ADC
PCI/PXI/CompactPCI Bus
–
x8 Channels
Connector 0 (MIO)
RTSI/PXI Triggers
Digital I/O (40)
RTSI Bus
Connector 2 (DIO)
NI 7811R Overview
The NI 7811R has 160 bidirectional DIO lines and a Virtex-II XC2V1000
FPGA.
NI 7813R Overview
The NI 7813R has 160 bidirectional DIO lines and a Virtex-II XC2V3000
FPGA.
NI 7830R Overview
The NI 7830R has four independent, 16-bit AI channels; four independent,
16-bit AO channels; 56 bidirectional DIO lines that you can configure
individually for input or output; and a Virtex-II XC2V1000 FPGA.
NI 7831R/7833R Overview
The NI 7831R/7833R each have eight independent, 16-bit AI channels;
eight independent, 16-bit AO channels; 96 bidirectional DIO lines that you
can configure individually for input or output; and a Virtex-II XC2V3000
FPGA.
NI 784xR Overview
The NI 784xR each have eight independent, 16-bit AI channels;
eight independent, 16-bit AO channels; and 96 bidirectional DIO lines that
you can configure individually for input or output. The NI PXI-7841R has
a Virtex-5 LX30 FPGA, and the NI PXI-7842R has a Virtex-5 LX50
FPGA.
NI 785xR Overview
The NI 785xR each have eight independent, 16-bit AI channels;
eight independent, 16-bit AO channels; and 96 bidirectional DIO lines that
you can configure individually for input or output. The NI PXI-7851R has
a Virtex-5 LX30 FPGA, the NI PXI-7852R has a Virtex-5 LX50 FPGA,
the NI PXI-7853R has a Virtex-5 LX85 FPGA, and the NI PXI-7854R has
a Virtex-5 LX110 FPGA.
Input Modes
The NI 783xR/784xR/785xR input mode is software configurable. The
input channels support three input modes—differential (DIFF), referenced
single ended (RSE), and nonreferenced single ended (NRSE). The selected
input mode applies to all the input channels. Table 2-2 describes the three
input modes.
Input Range
The NI 783xR/784xR/785xR AI range is fixed at ±10 V.
Caution Exceeding the differential and common-mode input ranges distorts the
input signals. Exceeding the maximum input voltage rating can damage the
NI 783xR/784xR/785xR and the computer. NI is not liable for any damage resulting from
such signal connections. The maximum input voltage ratings are listed in Table A-2,
NI 78xxR I/O Signal Summary.
AIGND is a common AI signal that is routed directly to the ground tie point
on the NI 783xR/784xR/785xR. You can use this signal for a general analog
ground tie point to the NI 783xR/784xR/785xR if necessary.
Vin+ +
Instrumentation
+
Amplifier
Vm Measured
Voltage
–
Vin– –
Vm = [Vin+ – Vin–]
You must reference all signals to ground either at the source device or at the
NI 783xR/784xR/785xR. If you have a floating source, reference the signal
to ground by using RSE input mode or the DIFF input mode with bias
resistors. Refer to the Differential Connections for Nonreferenced or
Floating Signal Sources section of this chapter for more information about
these input modes. If you have a grounded source, do not reference the
signal to AIGND. You can avoid this reference by using DIFF or NRSE
input modes.
Input Modes
The following sections discuss single-ended and differential measurements
and considerations for measuring both floating and ground-referenced
signal sources.
Figure 2-5 summarizes the recommended input mode for both types of
signal sources.
Examples Examples
• Ungrounded Thermocouples • Plug-in Instruments with
Input • Signal Conditioning with Nonisolated Outputs
Isolated Outputs
• Battery Devices
AI<i>(+) AI<i>(+)
+ +
+ V + V
– 1 AI<i>(–) – 1 AI<i>(–)
– –
Differential
(DIFF)
AIGND<i> AIGND<i>
NOT RECOMMENDED
AI<i> AI
+ +
+ V + V
– 1 AIGND<i> – 1
Single-Ended— – –
+ Vg –
Ground
Referenced
(RSE) AIGND
AI<i> AI<i>
+ +
+ V + V
– 1 AISENSE – 1 AISENSE
– –
Single-Ended—
Nonreferenced
AIGND<i>
(NRSE)
AIGND<i>
Use differential input connections for any channel that meets any of the
following conditions:
• The input signal is low level (less than 1 V).
• The leads connecting the signal to the NI 783xR/784xR/785xR are
greater than 3 m (10 ft).
• The input signal requires a separate ground-reference point or return
signal.
• The signal leads travel through noisy environments.
AI+ +
Ground- + AI–
Referenced Instrumentation
Signal Vs Amplifier +
Source – Measured
– Vm
Voltage
–
Common-
Mode +
Noise and Vcm
Ground – AISENSE
Potential
AIGND
I/O Connector
With this connection type, the instrumentation amplifier rejects both the
common-mode noise in the signal and the ground potential difference
between the signal source and the NI 783xR/784xR/785xR ground, shown
as Vcm in Figure 2-6. In addition, the instrumentation amplifier can reject
common-mode noise pickup in the leads connecting the signal sources to
the device. The instrumentation amplifier can reject common-mode signals
when V+in and V– in (input signals) are both within their specified input
ranges. Refer to the NI R Series Multifunction RIO Specifications, available
at ni.com/manuals, for more information about input ranges.
AI+ +
Bias
Floating + Resistors AI–
(see text) Instrumentation
Signal Vs Amplifier +
Source – Measured
– Vm
Voltage
–
Bias
Current
Return
Paths
AISENSE
AIGND
I/O Connector
Figure 2-7 shows two bias resistors connected in parallel with the signal
leads of a floating signal source. If you do not use the resistors and the
source is truly floating, the source might not remain within the
common-mode signal range of the instrumentation amplifier, causing
erroneous readings. You must reference the source to AIGND by
connecting the positive side of the signal to the positive input of the
instrumentation amplifier and connecting the negative side of the signal to
AIGND and to the negative input of the instrumentation amplifier without
resistors. This connection works well for DC-coupled sources with low
source impedance, less than 100 Ω.
For larger source impedances, this connection leaves the differential signal
path significantly out of balance. Noise that couples electrostatically onto
the positive line does not couple onto the negative line because it is
connected to ground. Hence, this noise appears as a differential-mode
signal instead of a common-mode signal, and the instrumentation amplifier
does not reject it. In this case, instead of directly connecting the negative
You can fully balance the signal path by connecting another resistor of the
same value between the positive input and AIGND, as shown in Figure 2-7.
This fully balanced input mode offers slightly better noise rejection but has
the disadvantage of loading down the source with the series combination
(sum) of the two resistors. If, for example, the source impedance is 2 kΩ
and each of the two resistors is 100 kΩ, the resistors load down the source
with 200 kΩ and produce a –1% gain error.
You can use single-ended input connections for any input signal that meets
the following conditions:
• The input signal is high-level (>1 V).
• The leads connecting the signal to the NI 783xR/784xR/785xR are less
than 3 m (10 ft).
• The input signal can share a common reference point with other
signals.
Use DIFF input connections for greater signal integrity for any input signal
that does not meet the preceding conditions.
AI+ +
AI– Instrumentation
Amplifier +
– Vm Measured
Floating + Voltage
–
Signal Vs
Source –
AISENSE
AIGND
I/O Connector
AI+ +
Ground- + AI–
Referenced Instrumentation
Vs Amplifier +
Signal
Source – Measured
– Vm
Voltage
–
Common-
Mode +
Noise and Vcm
Ground – AISENSE
Potential
AIGND
I/O Connector
NRSE Input Mode Selected
Analog Output
The bipolar output range of the NI 783xR/784xR/785xR AO channels is
fixed at ±10 V. Some applications require that the AO channels power on
to known voltage levels. To set the power-on levels, you can configure the
NI 783xR/784xR/785xR to load and run a VI when the system powers on.
The VI can set the AO channels to the desired voltage levels. The VI
interprets data written to the DAC in two’s complement format. Table 2-3
shows the ideal AO voltage generated for a given input code.
Note If your VI does not set the output value for an AO channel, then the AO channel
voltage output will be undefined.
AO <0..n> are the AO channels. AOGND is the ground reference signal for
the AO channels.
AO0
Channel 0
+
Load
VOUT 0
– AOGND0
NI 783xR/784xR/785xR
Digital I/O
You can configure the NI 78xxR DIO lines individually for either input or
output. When the system powers on, the DIO lines are at high impedance.
To set another power-on state, you can configure the NI 78xxR to load a VI
when the system powers on. The VI can then set the DIO lines to any
power-on state.
NI 7830R has one RMIO and one RDIO connector for a total of 56 DIO
lines. The NI 7831R/7833R/784xR/785xR has one RMIO and two RDIO
connectors for a total of 96 DIO lines.
Caution Exceeding the maximum input voltage ratings, listed in Table A-2, NI 78xxR I/O
Signal Summary, can damage the NI 78xxR and the computer. NI is not liable for any
damage resulting from such signal connections.
Caution Do not short the DIO lines of the NI 78xxR directly to power or to ground. Doing
so can damage the NI 78xxR by causing excessive current to flow through the DIO lines.
LED
TTL or
DGND +5 V
LVCMOS*
Compatible
Devices
DIO<4..7>
5 V CMOS †
+5 V
Switch
DGND
I/O Connector
NI 783xR/784xR/785xR
*3.3 V CMOS
†Use a pull-up resistor when driving 5 V CMOS devices.
Figure 2-11 shows DIO<0..3> configured for digital input and DIO<4..7>
configured for digital output. Digital input applications include receiving
TTL, LVTTL, CMOS, or LVCMOS signals and sensing external device
states, such as the state of the switch shown in Figure 2-11. Digital output
applications include sending TTL or LVCMOS signals and driving external
devices, such as the LED shown in Figure 2-11.
SH68-C68-S
Shielded Cable Recommended Types
Device Digital Lines Signal Pairing of Digital Signals
NI 781xR DIO<0..27> DIO line paired All types—high-frequency or
with power low-frequency signals,
or ground edge-sensitive or
non-edge-sensitive signals
DIO<28..39> DIO line paired Static signals or
with another non-edge-sensitive,
DIO line low-frequency signals
NI 783xR, Connector 0, DIO<0..7>; DIO line paired All types—high-frequency or
NI 784xR, Connector 1, DIO<0..27>; with power low-frequency signals,
NI 785xR Connector 2, DIO<0..27> or ground edge-sensitive or
non-edge-sensitive signals
Connector 0, DIO<8..15>; DIO line paired Static signals or
Connector 1, DIO<28..39>; with another non-edge-sensitive,
Connector 2, DIO<28..39> DIO line low-frequency signals
You can use the RTSI trigger lines to synchronize the NI 78xxR to any other
device that supports RTSI triggers. On the NI PCI-781xR/783xR and
NI PCIe-784xR/785xR, the RTSI trigger lines are labeled
RTSI/RTSI<0..6> and RTSI/RTSI7. On the NI PXI-78xxR, the RTSI
trigger lines are labeled PXI/PXI_Trig<0..7>. In addition, the
NI PXI-78xxR can use the PXI star trigger line to send or receive triggers
from a device plugged into Slot 2 of the PXI chassis. The PXI star trigger
line on the NI PXI-78xxR is PXI/PXI_Star.
The NI 78xxR can configure each RTSI trigger line either as an input or an
output signal. Because each trigger line on the RTSI bus is connected in
parallel to all the other RTSI devices on the bus, only one device
should drive a particular RTSI trigger line at a time. For example, if
one NI PXI-78xxR is configured to send out a trigger pulse on
PXI/PXI_Trig0, the remaining devices on that PXI bus segment must have
PXI/PXI_Trig0 configured as an input.
Caution Do not drive the same RTSI trigger bus line with the NI 78xxR and another device
simultaneously. Such signal driving can damage both devices. NI is not liable for any
damage resulting from such signal driving.
The NI PXI-781xR/783xR can configure each PXI local bus line either as
an input or an output signal. Only one device can drive the same physical
local bus line at a time. For example, if the NI PXI-781xR/783xR is
configured to drive a signal on PXI/PXI_Lbr 0, the device in the slot
immediately to the right must have its PXI/PXI_Lbl 0 line configured as an
input.
Caution Do not drive the same PXI local bus line with the NI PXI-781xR/783xR and
another device simultaneously. Such signal driving can damage both devices. NI is not
liable for any damage resulting from such signal driving.
The NI PXI-781xR/783xR local bus lines are only compatible with 3.3 V
signaling LVTTL and LVCMOS levels.
Caution Do not enable the local bus lines on an adjacent device if the device drives
anything other than 0–3.3V LVTTL signal levels on the NI PXI-781xR/783xR. Enabling
the lines in this way can damage the NI PXI-781xR/783xR. NI is not liable for any damage
resulting from enabling such lines.
The left local bus lines from the left peripheral slot of a PXI backplane
(Slot 2) are routed to the star trigger lines of up to 13 other peripheral slots
in a two-segment PXI system. This configuration provides a dedicated,
delay-matched trigger signal between the first peripheral slot and the
other peripheral slots for precise trigger timing signals. For example—as
shown in Figure 2-12—an NI PXI-781xR/783xR in Slot 2 can send an
independent trigger signal to each device plugged into Slots <3..15> using
the PXI/PXI_Lbl<0..12>. Each device receives its trigger signal on its own
dedicated star trigger line.
Caution Do not configure the NI 781xR/783xR and another device to drive the same
physical star trigger line simultaneously. Such signal driving can damage the
NI 781xR/783xR and the other device. NI is not liable for any damage resulting from
such signal driving.
Trigger 0
Trigger 1
Trigger 2
Trigger 3
Trigger 0
Trigger 1
Trigger 2
Trigger 3
Trigger 0
Trigger 1
Trigger 2
Trigger 3
PXI_Star* PXI_Star PXI_Star
* A Slot 2 device ties the PXI_Star Line to the PXI 10 MHz clock
Refer to the PXI Hardware Specification Revision 2.1 and PXI Software
Specification Revision 2.1 at www.pxisa.org for more information about
PXI triggers.
NI PX
Recon I-7811R
figurab
le I/O
CONNECTOR 3 (DIO)
CONNECTOR 2 (DIO)
NI PX
ReconfiI-7831R
gurab
le I/O
CONNECTOR 2 (DIO)
ON ON
1 2 3 1 2 3
After completing this procedure, a VI stored in Flash memory does not load
to the FPGA at power-on. You can use software to configure the NI 78xxR,
if necessary. To return to the defaults of loading from Flash memory, repeat
the previous procedure but return SW1 to the OFF position in step 3. You
can use this switch to enable/disable the ability to load from Flash memory.
In addition to this switch, you must configure the NI 78xxR with the
software to autoload an FPGA VI.
Note When the NI 781xR/783xR is powered on with SW1 in the ON position, the analog
circuitry does not return properly calibrated data. Move the switch to the ON position only
while you are using software to reconfigure the NI 781xR/783xR for the desired power-up
behavior. Afterward, return SW1 to the OFF position.
+5 V Power Source
The +5 V terminals on the I/O connector supply +5 V referenced to DGND.
Use these terminals to power external circuitry.
Caution Never connect the +5 V power terminals to analog or digital ground or to any
other voltage source on the NI 78xxR device or any other device. Doing so can damage the
device and the computer. NI is not liable for damage resulting from such a connection.
3. Replace the blown fuse while referring to Figure 2-18 for the fuse
locations.
4. Reinstall the PCI, PCI Express, or PXI device into the computer or PXI
chassis.
However, you should install the disk drive power connector in either of the
following situations:
• You need more power than listed in the device specifications
• You are using an R Series accessory with no external power supply,
such as the cRIO-9151
Refer to the specifications document for your device for more information
about PCI Express power requirements and power limits.
Note The power available on the disk drive power connectors in a computer can vary. For
example, consider using a disk drive power connector that is not in the same power chain
as the hard drive.
2
1
4. Replace the computer cover, and plug in and power on the computer.
5. Use the NI 78xxR Calibration Utility to run a self-calibration on the
NI PCIe-784xR/785xR device. Refer to the Self-Calibration section of
Chapter 3, Calibration (NI 783xR/784xR/785xR Only), for more
information.
Note Connecting or disconnecting the disk drive power connector can affect the analog
performance of your device. To compensate for this, NI recommends that you
self-calibrate after connecting or disconnecting the disk drive power connector.
Self-Calibration
With self-calibration, the NI 783xR/784xR/785xR can internally measure
and correct almost all of its calibration-related errors without any external
signal connections. NI provides software to perform an self-calibration.
This internal self-calibration process, which generally takes less than
two minutes, is the preferred method of assuring accuracy in your
Note The NI 78xxR Calibration Utility does not support NI 781xR devices.
If you have NI-RIO installed, you can find the self-calibration utility at
Start»All Programs»National Instruments»NI-RIO»Calibrate 78xxR
Device. Device is the NI PXI-783xR/784xR/785xR or NI PCI-783xR
device.
External Calibration
An external calibration refers to calibrating your device with a known
external reference rather than relying on the onboard reference. The
NI 783xR/784xR/785xR has an onboard calibration reference to ensure
the accuracy of self-calibration. The reference voltage is measured at the
factory and stored in the Flash memory for subsequent self-calibrations.
Externally calibrate the device annually or more often if you use it at
extreme temperatures.
Figure A-1 shows the I/O connector pin assignments and locations for
NI PCI-7811R/7813R and NI PXI-7811R/7813R.
Figure A-2 shows the I/O connector pin assignments and locations
for NI PCI-7830R/7831R/7833R, NI PCIe-7841R/7842R/7851R/7852R,
and the NI PXI-7830R/7831R/7833R/7841R/7842R/7851R/7852R/
7853R/7854R.
CONNECTOR 3
CONNECTOR 0
(RDIO)
(RDIO)
DIO39 68 34 DIO38
DIO37 67 33 DIO36
66 32 DIO34 TERMINAL 68 TERMINAL 35
DIO35
DIO33 65 31 DIO32 TERMINAL 34 TERMINAL 1
DIO31 64 30 DIO30
DIO29 63 29 DIO28
DIO27 62 28 +5V
DIO26 61 27 +5V
DIO25 60 26 DGND
DIO24 59 25 DGND
DIO23 58 24 DGND
DIO22 57 23 DGND TERMINAL 1 TERMINAL 34
DIO21 56 22 DGND TERMINAL 35 TERMINAL 68
DIO20 55 21 DGND
DIO19 54 20 DGND
DIO18 53 19 DGND
DIO17 52 18 DGND
DIO16 51 17 DGND
DIO15 50 16 DGND
DIO14 49 15 DGND
DIO13 48 14 DGND TERMINAL 68 TERMINAL 35
DIO12 47 13 DGND
46 12 DGND TERMINAL 34 TERMINAL 1
DIO11
DIO10 45 11 DGND
DIO9 44 10 DGND
DIO8 43 9 DGND
DIO7 42 8 DGND
DIO6 41 7 DGND
DIO5 40 6 DGND
DIO4 39 5 DGND
TERMINAL 1 TERMINAL 34
DIO3 38 4 DGND
DIO2 37 3 DGND TERMINAL 35 TERMINAL 68
DIO1 36 2 DGND
DIO0 35 1 DGND
CONNECTOR 1
CONNECTOR 2
(RDIO)
(RDIO)
CONNECTOR 0
(RMIO)
DIO39 68 34 DIO38 AI0+ 68 34 AI0–
DIO37 67 33 DIO36 AIGND0 67 33 AIGND1
66 32 DIO34 TERMINAL 68
DIO35 AI1+ 66 32 AI1–
DIO33 65 31 DIO32 TERMINAL 34 AI2+ 65 31 AI2–
DIO31 64 30 DIO30 AIGND2 64 30 AIGND3
DIO29 63 29 DIO28 AI3+ 63 29 AI3–
DIO27 62 28 +5V AI4+1 62 28 AI4–1
DIO26 61 27 +5V AIGND4 61 27 AIGND5
DIO25 60 26 DGND AI5+1 60 26 AI5–1
DIO24 59 25 DGND AI6+1 59 25 AI6–1
DIO23 58 24 DGND AIGND6 58 24 AIGND7
DIO22 57 23 DGND TERMINAL 1 AI7+1 57 23 AI7–1
DIO21 56 22 DGND TERMINAL 35 AISENSE 56 22 No Connect
DIO20 55 21 DGND AO0 55 21 AOGND0
DIO19 54 20 DGND AO1 54 20 AOGND1
DIO18 53 19 DGND AO2 53 19 AOGND2
DIO17 52 18 DGND AO3 52 18 AOGND3
DIO16 51 17 DGND AO41 51 17 AOGND4
DIO15 50 16 DGND AO51 50 16 AOGND5
DIO14 49 15 DGND AO61 49 15 AOGND6
DIO13 48 14 DGND TERMINAL 68 TERMINAL 35 AO71 48 14 AOGND7
DIO12 47 13 DGND DIO15 47 13 DIO14
46 12 DGND TERMINAL 34 TERMINAL 1
DIO11 DIO13 46 12 DIO12
DIO10 45 11 DGND DIO11 45 11 DIO10
DIO9 44 10 DGND DIO9 44 10 DIO8
DIO8 43 9 DGND DIO7 43 9 DGND
DIO7 42 8 DGND DIO6 42 8 DGND
DIO6 41 7 DGND DIO5 41 7 DGND
DIO5 40 6 DGND DIO4 40 6 DGND
DIO4 39 5 DGND DIO3 39 5 DGND
TERMINAL 1 TERMINAL 34
DIO3 38 4 DGND DIO2 38 4 DGND
DIO2 37 3 DGND TERMINAL 35 TERMINAL 68 DIO1 37 3 DGND
DIO1 36 2 DGND DIO0 36 2 DGND
DIO0 35 1 DGND +5V 35 1 +5V
CONNECTOR 1
CONNECTOR 2
1 No
(RDIO)
To access the signals on the I/O connectors, you must connect a cable from
the I/O connector to a signal accessory. Plug the small VHDCI connector
end of the cable into the appropriate I/O connector and connect the other
end of the cable to the appropriate signal accessory.
+5V DGND Output +5 VDC Source—These pins supply 5 V from the computer
power supply. For more information on the +5V terminals,
refer to the +5 V Power Source section in Chapter 2,
Hardware Overview of the NI 78xxR.
AI<0..7>– AIGND Input Negative input for Analog Input channels 0 through 7.
AISENSE AIGND Input Analog Input Sense—This pin serves as the reference node
for AI <0..7> when the device is configured for NRSE mode.
AO<0..7> AOGND Output Analog Output channels 0 through 7. Each channel can
source or sink up to 2.5 mA.
DIO<0..15>
Connector 0
(NI 783xR/784xR/785xR)
DIO<0..39>
Connector <1..2>
(NI 783xR/784xR/785xR)
Caution Connections that exceed any of the maximum ratings of input or output signals
on the NI 78xxR can damage the NI 78xxR and the computer. Maximum input ratings for
each signal are in the Protection column of Table A-2. NI is not liable for any damage
resulting from such signal connections
+5V DO — — — — — —
AI<0..7>+ AI 10 GΩ in 42/35 — — — ±2 nA
parallel with
100 pF
AI<0..7>– AI 10 GΩ in 42/35 — — — ±2 nA
parallel with
100 pF
AIGND AO — — — — — —
AISENSE AI 10 GΩ in 42/35 — — — ±2 nA
parallel with
100 pF
AOGND AO — — — — — —
Figure A-3 shows the connector pinouts when using the NSC68-262650
cable.
No Connect 1 2 No Connect
No Connect 3 4 No Connect
No Connect 5 6 No Connect
No Connect 7 8 No Connect
No Connect 9 10 No Connect
No Connect 11 12 No Connect
No Connect 13 14 No Connect
No Connect 15 16 No Connect
DIO15 17 18 No Connect
DIO14 19 20 No Connect
DIO13 21 22 No Connect
DIO12 23 24 No Connect
AO0 1 2 No Connect AI0+ 1 2 AI0– DIO11 25 26 No Connect
AOGND0 3 4 No Connect AIGND0 3 4 AI1– DIO10 27 28 No Connect
AO1 5 6 AOGND1 AI1+ 5 6 AIGND1 DIO9 29 30 No Connect
AO2 7 8 No Connect AI2+ 7 8 AI2– DIO8 31 32 No Connect
AOGND2 9 10 No Connect AIGND2 9 10 AI3– DIO7 33 34 No Connect
AO3 11 12 AOGND3 AI3+ 11 12 AIGND3 DIO6 35 36 DGND
AO4 13 14 No Connect AI4+ 13 14 AI4– DIO5 37 38 DGND
AOGND4 15 16 No Connect AIGND4 15 16 AI5– DIO4 39 40 DGND
AO5 17 18 AOGND5 AI5+ 17 18 AIGND5 DIO3 41 42 DGND
AO6 19 20 No Connect AI6+ 19 20 AI6– DIO2 43 44 DGND
AOGND6 21 22 No Connect AIGND6 21 22 AI7– DIO1 45 46 DGND
AO7 23 24 AOGND7 AI7+ 23 24 AIGND7 DIO0 47 48 DGND
No Connect 25 26 No Connect AISENSE 25 26 No Connect +5V 49 50 DGND
You can plug each of these 50-pin headers directly into an 8-, 16-, 24-,
or 32-channel SSR backplane for digital signal conditioning. One of the
50-pin headers contains DIO<0..23> from the NI 78xxR RDIO connector.
These lines correspond to Slots <0..23> on an SSR backplane in sequential
order. The other 50-pin header contains DIO<24..39> from the NI 78xxR
RDIO connector. These lines correspond to Slots <0..15> on an SSR
backplane in sequential order. You can connect to an SSR backplane
containing a number of channels unequal to the number of lines on the
NSC68-5050 cable header. In this case, you have access only to the
channels that exist on both the SSR backplane and the NSC68-5050 cable
header you are using.
Figure A-4 shows the connector pinouts when using the NSC68-5050
cable.
The SCB-68 has 68 screw terminals for I/O signal connections. To use
the SCB-68 with the NI 78xxR, you must configure the SCB-68 as a
general-purpose connector block. Refer to Figure B-1 for the
general-purpose switch configuration.
S1
S2
S5 S4 S3
Figure B-1. General-Purpose Switch Configuration for the SCB-68 Terminal Block
After configuring the SCB-68 switches, you can connect the I/O signals to
the SCB-68 screw terminals. Refer to Appendix A, Connecting I/O Signals,
for the connector pin assignments for the NI 78xxR. After connecting
I/O signals to the SCB-68 screw terminals, you can connect the
SCB-68 to the with the SHC68-68-RMIO (for Connector 0 on the
NI 783xR/784xR/785xR) or SHC68-68-RDIO (Connector <0..3> on the
NI 781xR and Connector <1..2> on the NI 783xR/784xR/785xR) shielded
cables.
If you searched ni.com and could not find the answers you need, contact
your local office or NI corporate headquarters. Phone numbers for our
worldwide offices are listed at the front of this manual. You also can visit
the Worldwide Offices section of ni.com/niglobal to access the branch
office Web sites, which provide up-to-date contact information, support
phone numbers, email addresses, and current events.
Numbers/Symbols
° Degrees.
Ω Ohms.
/ Per.
% Percent.
± Plus or minus.
A
A Amperes.
A/D Analog-to-digital.
AC Alternating current.
AI Analog input.
AO Analog output.
B
bipolar A signal range that includes both positive and negative values (for example,
–5 to +5 V).
C
C Celsius.
CH Channel—Pin or wire lead to which you apply or from which you read the
analog or digital signal. Analog signals can be single-ended or differential.
For digital signals, you group channels to form ports. Ports usually consist
of either four or eight digital channels.
cm Centimeter.
common-mode Any voltage present at the instrumentation amplifier inputs with respect to
voltage amplifier ground.
CompactPCI Refers to the core specification defined by the PCI Industrial Computer
Manufacturer’s Group (PICMG).
D
D/A Digital-to-analog.
DAQ Data acquisition—A system that uses the computer to collect, receive,
and generate electrical signals.
DC Direct current.
DO Digital output.
E
EEPROM Electrically erasable programmable read-only memory—ROM that can be
erased with an electrical signal and reprogrammed.
F
FPGA Field-Programmable Gate Array.
FPGA VI A configuration that is downloaded to the FPGA and that determines the
functionality of the hardware.
G
glitch An unwanted signal excursion of short duration that is usually unavoidable.
H
h Hour.
HIL Hardware-in-the-loop.
Hz Hertz.
I
I/O Input/output—The transfer of data to/from a computer system involving
communications channels, operator interface devices, and/or data
acquisition and control interfaces.
L
LabVIEW Laboratory Virtual Instrument Engineering Workbench. LabVIEW is a
graphical programming language that uses icons instead of lines of text to
create programs.
M
m Meter.
max Maximum.
min Minimum.
N
noise An undesirable electrical signal—Noise comes from external sources such
as the AC power line, motors, generators, transformers, fluorescent lights,
CRT displays, computers, electrical storms, welders, radio transmitters,
and internal sources such as semiconductors, resistors, and capacitors.
Noise corrupts signals you are trying to send or receive.
O
OUT Output pin—A counter output pin where the counter can generate various
TTL pulse waveforms.
P
PCI Peripheral Component Interconnect—A high-performance expansion bus
architecture originally developed by Intel to replace ISA and EISA. It is
achieving widespread acceptance as a standard for PCs and work-stations.
PCI offers a theoretical maximum transfer rate of 132 MB/s.
pu Pull-up.
PXI PCI eXtensions for Instrumentation—An open specification that builds off
the CompactPCI specification by adding instrumentation-specific features.
R
RAM Random-access memory—The generic term for the read/write memory that
is used in computers. RAM allows bits and bytes to be written to it as well
as read from. Various types of RAM are DRAM, EDO RAM, SRAM, and
VRAM.
RTSI Real-time system integration bus—The timing and triggering bus that
connects multiple devices directly. This allows for hardware
synchronization across devices.
S
s Seconds.
S Samples.
S/s Samples per second—Used to express the rate at which a DAQ board
samples an analog signal.
slew rate The voltage rate of change as a function of time. The maximum slew rate
of an amplifier is often a key specification to its performance. Slew rate
limitations are first seen as distortion at higher signal frequencies.
T
THD Total harmonic distortion—The ratio of the total rms signal due to
harmonic distortion to the overall rms signal, in decibel or a percentage.
two’s complement Given a number x expressed in base 2 with n digits to the left of the radix
point, the (base 2) number 2n – x.
V
V Volts.
W
waveform Multiple voltage readings taken at a specific sampling rate.