Contents Acknowledgements. Abstract 1 Introduction 1.1 Aim of the assignment : 12 Digital Lock Finite State Machine 13 Mealy and Moore Machines Design 2.1 Assumptions 2.2 Mealy state machine 2.3 Moore state machine 2.4 State Minimisation 2.5 State tables, k-maps and state equations Implementation of digital lock on Multisim using flip-flops Implementation of digital lock using registered FPLA, WinCUPL implementation and WinSTM results, 5.1 Mealy machine implementation 5.2 Moore machine implementation 5.3 Hardware Implementation on GALIGV8, FPGA implementation Conclusion References ii 12 14 4 16 18 19 23 23List of Figures 10 12 13 14 Block diagram of digital lock Comparison between Mealy and Moore machines Mealy state machine Moore state machine K-maps for binary assignment. K-maps for gray code assignment Circuit diagram for implementation on Multisim Simulation results from Multisim Circuit for FPLA implementation Winsim results for Digital Lock Mealy machine Winsim results for Digital Lock Moore machine VHDL Design file VHDL Design file (continued) VHDL Top Level Design file List of Tables Minimisation of (a) Mealy Machine (b) Moore machine State table with binary assignment State table with gray code assignment (@) Truth table and K-maps for Alarm and Lock outputs (b) K-map for Alarm output (c) K-mmap for Lock output (@) Transition table for Mealy machine using binary assignment (b) Fuse map for FPLA imple- mentation Test results for implementation on GALIGV8 Test results of FPGA board ul 13 15 7 20 21 22 12 18 19Abstract This report presents the design and implementation of a digital lock consisting of the buttons A and B. It is unlocked with the combination A-A-B-A-B-A and equipped with an alarm system that goes for any out-of- sequence use of the A-button. The state diagram and state tables ate developed. ‘Through k-maps, the gray- coded digital lock is found to be the most hardware-efficient machine and it is implemented using combinational logic and memory elements on Multisim software. ‘Also, the design file for WinCUPL is developed for the implementation with Generic Array Logic GALI6V8 and experimentally tested, The VHDL file is then generated on Xilinx and implemented and tested using an FPGA.1 Introduction 1.1 Aim of the assignment The aim of this assignment is to design and implement a digital lock with two debounced push buttons, A and B, having the following specifications: ‘The push buttons cannot be activated simultaneously. ‘* The combination to open the lock is A-A-B-A-B-A, Three B pulses in a row reset the control to its initial state, ‘+ For any out of sequence use of the A-button, an alarm goes off Once unlocked, pressing either A or B closes the lock ‘The design files are developed on WinCUPL and Xilinx softwares for both the Mealy and Moore machines. The systems are then implemented on the GAL and FPGA devices. 1.2 Digital Lock Finite State Machine Below is the block diagram of the digital lock FSM. > Alarm (unlock Figure 1: Block diagram of digital lock ‘The digital lock detects a specific sequence/combination of Input 1 and Input 2 and outputs a 1 when it matches a pre-stored code at the Unlock output. In case of too many wrong combinations, the designer may choose to sound an alarm by outputting a I at the Alarm output.1.3 Mealy and Moore Machines Mealy Machine > Output Zis a function of both the present state Q/i) and the input x. {Sequential System ~ MPS Combinational | —}O¥tPHs ! if Logic ! ! Memory | ' ' (state) 1 Moore Machine > Output Z is a fonction of the present state Q(t) only. It changes synchronously with state changes {” Sequential System | Sequential Systen Put Combinational if Logie | ' Memory (state) Figure 2: Comparison between Mealy and Moore machines2 Design 2.1 Assumptions ‘* The machine restarts the sequence as soon as the start of the sequence is detected even if previous keystrokes do not match the code; overlapping is allowed. This means that the user can enter any se- quence except AAA and the alarm will not go off until the correct code is entered. ‘* The bit A or B used to reset the lock is not remembered by the system and thus discarded from the next sequence, ‘© Once the alarm goes off, it stays on irrespective of any additional keystroke. ‘© There is no limit as to how many times can the lock be opened in a given amount of time. 2.2 Mealy state machine Description x zpwhere put and ickand L= 1 for OPEN Lock and 0 otherwise orm and = 1 for Alaris ON and Otherwise Sp:intia/reset state for Input Aand X= 1 for input 8 SeAAB! Sri"AABA Sa: "AABAB? Sa ARBAB’ Figure 3: Mealy state machine2.3 Moore state machine Figure 4: Moore state machine Description SIZ & (K} where = Lock, L=1 for OPEN Lock and 0 otherwise Z=Alarm, Z=1 for Alarmis ON andO otherwise X=0 for Input Aand X= 1 for Input 8 So: initial/reset state sis Sus"! 52:10 Se:'ARR, 'AARA, STAR Se:'B8 Sr 'AABAY Se: "ARBAB" So:"AABABA’2.4 State Minimisation ‘Table 1: Minimisation of (a) Mealy Machine (b) Moore machine Present state Neat sate ‘Output Present state ‘Next sate ‘Ourpat Tapat a | tepatB | TapatA | Inputs Tapat A | Inputs 0 S Si Ss 0 ‘o = Si S om S: Se S 00 00 Si Si Ss 00 Ss 5 Ss 00 00 Ss 5 Ss 0 5 Se s 1 co 5 Se s oF Se Se Se 1 on Se Se Se or Se Si Se 00 00 Se Si Se 00 Se Si Se 0 0 Ss. S. S. 00 5: St 00 0 Si 5 S oo s 10 oo s 10 Se Si Si o 00 Ss Si Se 00 @ Cy From the above tables, it can observed that the Mealy and Moore machines cannot be further minimised.2.5. State tables, k-maps and state equations Binary assignment Table 2: State table with binary assignment Hlth xx x[x oc 10 xx xx x x x h x [Xx xx] x px x [Xx Ke o we x [x [x x [x [x x [x [x w ° xx x [x x x x 1 ° roar x 1x 0 ° 0 Xxx [xt x | a: xX x1x x 1x, xx xe x x x x x Pe x B x pe Px px px x px [xp x px x px [xp x px Oe x Xx] x [xx [xP x xx x [x xxx xx x x xx x Tx x x [xxx Pe xe [ee Pe oe ee ee ee x ee Pe Tx Te xxx Px x xe x Tx x x oe x Xx} x [xx [xp x [x [x -abdbabdb abab ab ab ab ababans or 0 0 0 0 o Or oF Tuput Xx Present sate [3 | oe [@ | Qo | & a & & & % ¥ % &Figure 5: K-maps for binary assignment {|x| wnt vions wenwat viens © RNB SEESAY aS Pac ea Lob ses) ES Ds = Q3.Q0-X + Q2.Qi-Qo.X Dr = Q3.Q0.X + BX +G.Qi.Qo+ QQ Dy = Q2.Q0.X + Q2.Qi.Qo + QQoX Dy = Q2.Qo.X + Q2.Qi.Qo.X + Qs.Qi.QoX + Q2.Q.X Ts = Q2.Q1.Q0.X + Qs.X + Q3.Qo Ta = Q3.Qo.X + Qa-X + Qi-Qo+ Q2Qr Ty = G2. Q.Qo-X + W2-Q1.-X + B.D. Qo + Q2-Q1.05 + G.Qo-X To = Qs. + VQ + Ti. Qo.X + WAX + QW + Q2.QoX Js = Q2.Q1.Qo.X Ky=X+Qo Jz = Q5.Qo-X + Q.X + Qi.Qo Ka=Q = Q Ki =QoX +@Q2X + Q2.Q@o Iy=BX+Q.X Ko = Q2-Qr.-X + GX + Qr.X + QsGray Code assignment Table 3: State table with gray code assignment Te Ti x] x xx x] x xx x [x xx 7 x x x [x x [Xx x [x x [x [x Tx KT 0 w x Ki x 0 0 xx, x px tx [x Px Tx x x px tx [x Px Tx x a 0 ict xe xx x [x o o 1 © x[x[x]xPx]x x px [x [xPx [x B 0 x x & xe xx xx xx x x a 0 o 0 we Oe eee ae ee xx [x [xt x [x xx x Px tx [xx [x x x Px Xx xe ex [exe ee xx [x [xt x [x xx x Px tx [xx [x x x Px ee Pe 9 ee Pe xe Pc Pe Xxx [xp xxx xx xxx Px x [xx Px tx pdb abdb ahah abide ab ababans Or x x x x x x x x x x Neat state @ = Input x ca Qu Present state Q @ S &Figure 6: K-maps for gray code assignment oon ot elie o ad on wo! vle@ oolxg xx} wr xix xfo | wl Oe ol SEES ROD -kOos) sb: abt Syren : "as ‘ i Te RR epee KK x ale ee [x x ee | Ge cclece' ad wtehoftex vale @ + ole Ol coal ae Stole seal fee trabe x be Ds = G02. Qi. Qo.X + Qs. Qo-X Dr = Qi.Qo + Q.X + Q2.Qi + Qs-Qo + Q2.Qo.X Di= A Q+ BAX +BU +B Do = Q2.X + Q3.Qo + Qa.QiQo + Q2.Q1.Qo + Q-Qo-X + Q.Q2.Q.Qo.X Ts = Q2.Qi.Qo.X + Qs.Q0 T = Q2-Qi-Qo + Q2.Qi-X + Q5-Q2- GX + Q2-G-Qo T= @B@-X +00 + Q1.Q0+G.2GGX To = Qo + BOX +B + G.Qo.X + Q2.Q1.Q0.X Ss = 2. Qi Qo.X K3=Qo4+X Fp = QQ + QrX Kr =O. X +T-Qo T= 2X +Q2.Qo + F.Q2.Qo.X Ki = Qo Jo = Qs + Qi + Oa.X Ko=Qs+ GX + 2.QX+ ax3. Implementation of digital lock on Multisim using flip-flops From the k-maps, we can deduce that the implementation of the gray-coded digital lock is more hardware efficient with the use of JK flip flops. Table 4: (@) Truth table and K-maps for Alarm and Lock outputs (b) K-map for Alarm output (c) K-map for Lock output Present state | Tuput Nest state LOCK | ALARM DE DE DE DE [QQ | @ @lelerlel . Z RBZ 0 0 0 0 sfotofofol o fofofoli{o o RBC 0 0 0 0 ofofofo| 1 }|ofojij1] o 0 Aci 1 0 0 s[ofofol1]/ o }|ofojijo]o 0 Reta) 0 0 0 ofofol1] 1 |o}foj1]1]o 0 BBC ex ee sfofof[i{1] o |ofojo|1] o 0 aC x x x © ofofr{1{ 1 [o}{1]o]{1]o 0 ABC x x x x E23 I A PT 1 aBZ 0 0 0 0 ofofrto, 1 fol{1j1]1]o © sfofi{1folo }fofiji1}ol]o 1 (0) ofrfrtot 1 fo}t1{1}o]o 1 sfol1[ifil[o fol+{[ololo ° (03) enone sr eenzes| vom seer) en1ea| como 0 DE DE DE DE sfolifol1{[o }|ofoj;o|1]o 0 0 0 0 0 CS a TT © RBc 0 0 0 0 sfolifolol o fofolijo]o o Rec 0 0 0 0 of1fofo, 1 [1}{1}ofo]o 0 RBZ 00 0 0 s{itifofolo tifijyoti] 4 0 ABE 0000 | [ata Pofot 1 folafo[i1y o 0 aBc 0 0 0 0 s{1t1fot1[o }ofoj;olol} o 0 ABC 0 0 0 0 tf1fotit 1 ~[ofototolo 0 apt 1 0 0 0 2 > BT x rate fet 1 fx txt xt xo x @ 7p aa Po fo x Px x Tx [0 x fiel=te a8 |eo2/enien|exejexelexelaxuleno x 71 poeta foto [x tx [x Tx [0 x fe) 20e/18| cos) ere exa)exa|=xe/axa (mao x tfpoti [ito [x |x txtx{o x rotary 1 x Tx Tx tx [0 x Teo ox Px Tx Tx to x rpofef+] 1 [x }x{[x]x{o x 71 fotofo[ oe [x |x][x xo x rfofefol 1 [x [x][x]x]o x ‘The state equations for the Alarm and Lock outputs are: Alarm = Qo.Q1.Qo + Q3.Q2.0X Lock = Qs.Q2.QiQo.X ‘The B-key is used for clock and the space-bar key is used for either button A or button B, 10~. «0 LEFPU TANF REBE GH.[ ALARM Te] soo0ms — oo0oy Dano rat | 9.0005 0.000 v 0.000 v ee Timebase_ Channel A Channel B Trigger scale: | 10 ms/Div scale: [5 VDiv scale: [5 ViDiv rdge: [FIR [a Xpos. (Div): [0 ] ¥pos.toie): [0 ‘] ¥p0s.con9: [0 J bevel: [o Tv] yit]|add| |B/a|[aye| [aco [oe ac | 0 |[be]|- Single [Normal] [Auto [None Figure 8: Simulation results from Multisim u4 Implementation of digital lock using registered FPLA ‘Table 5: (a) Transition table for Mealy machine using binary assignment (b) Fuse map for FPLA implementa tion. The size of the FPLA is 5 x 15 x 2 12a a2 al ao x AM ast az-airaos LZ Figure 9: Circuit for FPLA implementation 135 WinCUPL implementation and WinSIM results Based on the requirements of the system, the GAL16V8 is chosen for the WinCUPL implementation of the digital lock. Below are the Mealy and Moore machine implementation description. 5.1 Mealy machine implementation The following codes were written and tested on the WinCUPL. Name mealy_4 ; PartNo 00 ; Date 3/27/2018 ; Revision 01 ; Designer Engincer Company daby ; Assembly None ; Location ; Device glév8 ; ([Josonociorienis INPUT PINS siti ietereeaereeniee/ PIN 1 = clk j /* clock #/ Aj /® button A */ Bi; /* button B +/ Jemonccnenecnenis OUTPUT PINS /* locked */ J+ alarm */ TUS H Eno none, [93..0] ; /« £lip flop «/ FIELD input = (4,31; BA=inpat: ’b/10; BR=input: ’b/01; FIELD s_mea: 03..0); SEQUENCE s_mealy F BA NEXT 4 OUT 2; 4P BB NEXT 5 ; PRESENT 4 F BA NEXT 4 OUT 2; IF BB NEXT 4 OUT Z; PRESEN) -ANEXT 7 j BB NEXT 6 ; BA NEXT 1; IF BB NEXT 0; PRESENT 7 P BA NEX’ BE NEXT 3; PRESENT 8 A NEXT 9 OUT L; BB NEXT 6 ; PRE BA NEXT P BB NEX’ Figure 10: Winsim results for Digital Lock Mealy machine 155.2, Moore machine implementation Name dsd_moore ; PartNo 00 ; Date 3/27/2078 ; Revision 01 ; Designer Engineer ; Company daby ; Assembly None j Location ; Device gléva ; /peponeononconendc: INPUT BINS ssocnocucnnnonnennnn] PIN 1 = clk j /* clock +#/ PIN2=Aj /* button A +/ PING =B; /* button B «/ (Dopopecnonedoone: OUTPUT PINS Honnnuninniniiinies/ PINI2Z=L; /* locked */ PINIS = 2; = alarm */ PIN [14..17] = [93..0] 7 /* flip flop +/ FIELD input = [A,B]; BA=input: ‘b’ 10; BB=input: ‘b’ 01; FIELD MOORE = [03..01; SEQUENCE MOORE ‘ PRESENT 0 IF BA NEXT 1; IP BB NEXT 2; PRESENT 1 IF BA NEXT 3; IF BB NEXT 2; PRESENT 2 IP BA NEXT 1; IF BB NEXT 6; PRESENT 3 IF BA NEXT 4; IF BB NEXT 5; 16BSENT 7 BA NEXT BE NE: PRESENT & IF BA NEXT 9; IF BB NEXT 6; Figure I: Winsim results for Digital Lock Moore machine 75.3. Hardware Implementation on GAL16V8. ‘Table 6: Test results for implementation on GALIGV8 A o 1 j1 jo ja Jo [4 B L Zz a3 az aa a0 Bolo bh Be clo ofe 1 0 0 0 1 0 1 oe eo sfo ofe hee efo ofe hoon The above table is for both Mealy and Moore implementation. The initial clock pulse for the Moore machine is not shown, 186 FPGA implementation ‘The Digital Lock designed is implanted on a FPGA using Active-HDL with Xilinx ISE for Synthesis and Implementation and Diligent Adept to run the code on the Spartan 6 FPGA platform. The codes below are implemented and tested The states Q are declared in binary with 4 bits. A reset switch is implemented to return to state “0000” when needed. The states changes are synchronous with the rising edge of the clock pulse. ‘The inputs and outputs are mapped to switches, buttons and LEDs as shown in the top level design. ‘The code is tested and is found to be working as described in Table 6 below. Table 7: Test results of FPGA board. SEPPP SEEEE alePler === alr ler afer [21-5 alee ler === =P [21-5 alr ler alr ler -[e/>[2/- === -[[2[- 19Figure 12: VHDL Design file ‘Active HDL Student Eston ‘Vlackmesly.vhe Library TEBE; ‘use T8B8.S7D_LOGTC_1164.a11; entity locknealy is ort uke ¢ Sa emp toate) Sit in emp 4003 bin smpctoaze Sibem': cut sD Loore; Feset : in stp Togrer Tock : out SmB_Locre: de fond locknealy? architecture locknealy of locknealy is ‘signal Q, Qnext : SED LOGIE VECTOR(3 downto 0); begin sync_proc: process (elk, x bevin Te (reset ° e) 11) then 000" elsif (rising edge (elk) then (Q <= next end $e fend proces: ayne_proct conb_proc: process ta, by O) beait Tock <= *0"s alarm <= *0"2 ease 0 ie, ‘when "0000" => ‘alarm <= '0'7 lock = ‘0 fellas '1') and cb = "0")) chen onext <= "0001" elsif ((2 = 10") and (b= '1°)) then gnext <= "0010"; eleif (a> t1" and b= 'L') ar (a= "On and b= '0')) then on when "0001 ‘alarm <= "0"; lock 4 SoMa = '1") and (b= "0")) chen Qnext <= "0021 elsif (a= to*] and {b= '1*)) then Qpext <="001 elsif Ue at) ar (a= "Or and b= '0')) then on ext <= "0001 end Sf: lock <= *0 feta 126} ang cb = °0")) then onext <= “o200" 1 ‘Active-HOL Student Elton 20Figure 13: VHDL Design file (continued) ‘Active-HOL Student Eston eleif ({a = 10") and (b= '1")) then gnext < 0101"; Sasie (2 2 cieand'p's Tn) ar fas fon and b= 0") then on ext <= "oon" ond Sf when "0100 ‘alarm lock <= '0 Sela '1') and tb = "0")) chen Qnext <= "0100"; elsif (a= to" and {b= '1')] then Qoext <= "0100 elsif (a> t2" and b= TL) ar fas 1On and b= '0'S) then On ext < "o100"y end Sf when "0102 ‘alam <= '0'7 Lock <= 10's Ge'la'= 11°} and de = "0")) chen gnext <= "0121"; eleif (ia = to" and {b= '1')] then Ghent <= "0110 elsif (a 2 ti and be TL) or fa ‘then on ext < votoins end ith ‘alarm <= '0'y lock <= '0'y Ee't(a'= '1°} and b= "0")) then qnext <= "0003"; eleif' (ia = to") and (b= '1")] then Qpent <= Sleif Ua = sland be "1 oF fa ‘and b = '0")) then on ext 11" and b= at) Or (a= cor and b= '0"}) then ga ext <= "1001" ona Se nen others ‘onext 0007 end case: fend process conb_proc: end Tocknea! mh ‘Actve-HDL Student Elton anFigure 14: VHDL Top Level Design file ‘Active HDL Student Eton ‘Vlockmesly_top vhe Library TEER; use TEES, STD. LOGIG_1164,a11; entity lockrealy top is in_S1D_ LOGIC _VECTOR(4 downto 3); an'stp Toote VECTOR (2 downto 0) Tea’: Cu? S8_20GTE VECTOR(? downto’ 0) * fend locknealy top: architecture leckmealy top of locknealy top is component locknealy portt ‘eset : in sm zocr alk: in sm x0are: 2? in sep ware, Slarn : out 88 LOGrer Tock : out 8Y0_TOGrC) ‘end component for allt Tecknealy use entity work-locknealy (lockmealy) + begin Labeli : locknealy port map reset => pen (3), > sid eik => Bena), be oi), alarm => 1ed(o), Tock => ted) ” fend locknealy top: ‘Actve-HDL Student Elton 227 Conclusion The objectives of this assignment were to design a digital lock having particular specifications, identify the most hardware efficient machine to be implemented using combinational logic and memory elements and also, to implement the system using FPLA, GAL and FPGA. The state diagram and state tables for both Mealy and Moore machines were developed and, it was inferred from the k-maps that the implementation of the gray-coded digital lock with the use of JK flip flops is the most hardwate-efficient one, Implementation using registered FPLA is also demonstrated in this report. Furthermore, GALI6V8 was used to experimentally test the design files of both the Mealy and Moore machines developed on WinCUPL software. The VHDL file was generated on Xilinx and implemented using the FPGA. ‘The systems are found to be operating as per the required specifications. 8 References [1] Dr. ¥. Ramgolam, Lecture Notes, 2017-2018 [2] “VHDL Reference Guide - Contents”, Ics.uci.edu, 2018, [Online]. Available: http://www.ics.uci.edu/ jmoorkan/vhdlref/. [Accessed: 20- Mar- 2018], 23