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Digital Electronics
IMPORTANT FORMULAS TO REMEMBER

Digital Electronics (Formula Notes)

Number System and Codes:

A number system with base ‘r’, contents ‘r’ different digits and they are from 0 to r –1.

Decimal to other codes conversions: To convert decimal number into other system with base ‘r’,
divide integer part by r and multiply fractional part with r.

Other codes to Decimal Conversions:

( x2x1x0  x1y2 ) → ( A )10

A = x2r2 + x1r + x0 + y1r–1 + y2r–2

Hexadecimal to Binary: Convert each Hexadecimal digit into 4 bits binary.

(0101 1010 1111)2

Binary to Hexadecimal: Grouping of 4 bits into one hex digit.

(110101.11)2 → 00110101.1100 → (35.C)16

Octal Binary and Binary to Octal: Same procedure as discussed above but here group of 3 bits is
made.

Codes:

Binary coded decimal (BCD):

• In BCD code each decimal digit is represented with 4 bit binary format.

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 
Eg : (943)10 1001 0100 0011 
 
 9 4 9 BCD

• It is also known as 8421 code

Invalid BCD codes

Total number possible → 24  16

Valid BCD codes → 10

Invalid BCD codes 16 − 10  6

There 1010, 1011, 1100, 1110 and 1111

Excess-3 codes: (BCD + 0011)

• It can be derived from BCD by adding ‘3’ to each coded number.

• It is unweighted and self-complementing code.

Gray Code: It is also called minimum change codes or unit distance code or reflected code.

Binary code to Gray code:

Gray code to Binary code:

Alpha Numeric code: EBCDIC (Extended BCD interchange code)

It is 8-bit code. It can represent 128 possible characters.

• Parity method is most widely used schemes for error detection.

• Hamming code is most useful error correcting code.

• BCD code is used in calculators, counters.

Complements: Its base is r then we can have two complements.

(i) (r – 1)’s complement

(ii) r’s complement

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To determine(r – 1)’s complement: First write maximum possible number in the given system and
subtract the given number.

To determine r’s complements: (r – 1)’s complement + 1

First write (r – 1)’s complement and then add 1 to LSB

Example:

Find 7’s and 8’s complement of 2456

7777
7’s Complement −2456
5321

5321
8’s Complement +1
5322

Find 2’s complement of 101.110

1’s complements 010.001

For 2’s complement add 1 to the LSB

010.001
2’s complement +1
010.010

Data Representation:

Unsigned Magnitude: Range with n bit

→ 0 to 2n−1 +5  101

−5  Not possible

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Signed Magnitude: Range with n bit

−6  1 110 1 0000110
sign bit sign bit
with 4 bits with 8 bits

1’s complements: Range with n bit

( )
→ − 2n−1 − 1 to + 2n−1 − 1( )
+6  0110 −6  1 001
sign bit 1' s complement 6

2’s complements: With n bit range –2n-1 to (2n-1 –1)

+6  0110 −6  1 001
sign bit 1' s complement 6

In any representation + ve numbers are represented similar to +ve number in sign magnitude.

Boolean Laws:

Commutative
xy =yx xy =yx

Associative x  ( y  z) = ( x  y )  z x  ( y  z) = ( x  y  z)

Distribute x  ( y  z) = ( x  y )  ( x  z) x  ( y  z) = ( x  y )  ( x  z)

Idempotence xx =x xx =x

Absorption x  (x  y) = x x  (x  y) = x

Combining (x  y)  (x  y) = x (x  y)  (x  y) = x
DE Morgan’s (x  y) = x  y (x  y) = x  y

Dual of a function:

The dual of logic function, f, is the function fD derived from f by substituting a  for each , a  for
each  a 1 for each 0, and a 0 for each 1.

f (a,b) = (a  b)  (b  c) fD (a,b) = (a  b)  (b  c)

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Flip Flops:

RS Latch

SR Q Q Comment

00 QQ Hold

01 01 Reset
10 10 Set
11 00 Illegal
Where Q is the next state and Q is the current state.

JK Flip Flop

JK Q Q Comment

00 QQ Hold

01 01 Reset
10 10 Set
11 QQ Toggle

T – Flip Flop:

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T Q Q Comment

0 QQ Hold

1 QQ Reset

D – Flip Flop:

Excitation tables:

SR JK D T
00 0X 00 0X 00 0 00 0
01 10 01 1X 01 1 01 1
10 01 10 X1 10 0 10 1
11 X0 X0 X0 11 1 11 0

• Q(n + 1) = S + RQ = D = JQ + KQ = TQ + TQ

• For ring counter total no. of states = n

• For twisted ring counter = “2n” (Johnson counter/switch tail ring counter).

• In Master slave master is level triggered and slave is edge triggered.

COMBINATIONAL CIRCUITS

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Multiplexer:

• 2n inputs; 1 output and ‘n’ select lines.

• It can be used to implemented Boolean function by selecting select lines as Boolean variables.

• For implementing ‘n’ variables Boolean function 2n × 1 MUX is enough.

• For implementing “n+1” variables Boolean function 2n × 1 MUX + NOT gate is required.

• For implementing “n+2” variables Boolean function 2n × 1 MUX + Combinational circuit is required.

• If you want to design 2m × 1 MUX using 2n × 1 MUX. You need 2, 2n × 1 MUXs

Decoder:

• n input and 2n output.

• used to implement the Boolean function. It will generate required min terms @ output and those
terms should be “OR” ed to get the results.

• Suppose it consists of more min terms then connect the max terms to NOR gate then it will give
the same output with less no. of gates.

• If you want to design m × 2m Decoder n × 2n Decoder. Then no. of n × 2n Decoder required =

• In parallel (“n” bit) total time delay=2n tpd.

• For carry look ahead adder delay = 2 tpd.

PROM, PLA & PAL:

AND OR
Fixed Programmable PROM
Programmable Fixed PAL
Programmable Programmable PLA

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Asynchronous Sequential circuits:

Asynchronous Sequential circuits do not use a clock and can change their output state as fast as
the signal path's propagation delay from the input allows. This means they can be faster than
Synchronous Sequential circuits. However, they are considerably more likely to suffer from race
conditions (inputs arriving at different times causing different output states) and intermediate
output states (as the outputs change from one state to the next final state) than Synchronous
Sequential circuits:

Synchronous Sequential circuits: Synchronous Sequential circuits use a clock signal to alleviate
the two problems mentioned above. The outputs can only change state with the clock and are designed
such that all propagation delays are satisfied before the outputs are allowed to change. This however
makes them potentially slower (because the whole circuit must run at the speed of the slowest path
in it) and consumes significantly more power due to the extra circuitry required by distributing the
clock to all flip-flops, and the continual switching.

S.No. Asynchronous Counter S.No. Synchronous Counter

1. Clock input is applied to LSB FF. The output 1. Clock input is common to all FF.
of first FF is connected as clock to next FF.

2. All Flip-Flop are toggle FF. 2. Any FF can be used.

3. Speed depends on no. of FF used for n bit. 3. Speed is independent of no. of FF

4. No extra logic Gates are required. 4. Logic Gates required based on

5. Cost is less. 5. Cost is more.

IOH I
• Fan out of a logic gate = or OL
IIH IIL

• Noise margin: VOH – VIH or VOL – VIL

• Power Dissipation,

1 + _ I 
PD = VCC ICC = Vcc  
 2 

I → Ic when output low.

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• TTL , ECL & CMOS are used for MSI or SSI

• Logic swing: VOH - VOL

• RTL , DTL , TTL → saturated logic

ECL → Un saturated logic

• Advantages of Active pullup; increased speed of operation , less power consumption.

• For TTL floating input considered as logic “1” & for ECL it is logic “0”.

• “MOS” mainly used for LSI & VLSI. Fan out is too high.

• ECL is fastest gate & consumes more power.

• CMOS is slowest gate & less power consumption.

• NMOS is faster than CMOS.

• Gates with open collector output can be used for wired AND operation (TTL).

• Gates with open emitter output can be used for wired OR operation (ECL).

• ROM is nothing but combination of encoder & decoder. This is non volatile memory.

• SRAM: stores binary information in terms of voltage uses FF.

• DRAM: info stored in terms of charge on capacitor. Used Transistors & Capacitors.

• SRAM consumes more power & faster than DRAM.

• CCD, RAM are volatile memories.

• 1024 × 8 memory can be obtained by using 1024 × 2 memories.

• No. of memory ICs of capacity 1k × 4 required to construct memory of capacity 8k × 8 are “16”

DAC

 1
• FSV = V R 1 − 
 2

Step size V R / 2n 1
• Resolution = = = n−1  100%
FSV  1 
VR 1 − n  2
 2 

1 1
• Accuracy =  LSB =  n+1
2 2

• Analog output = K. digital output

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ADC

• LSB = Voltage range/2n

FSV
• Resolution =
2n − 1

VR
• Quantization error = %
2n

• Flash type ADC: 2n−1 → comparators

2n → resistors

2n  n → Encoder

Fastest ADC:

• Successive approximation ADC: n clock pulses.

• Counter type ADC: 2n – 1 clock pulses

• Dual slope integrating type: 2n+1 clock pulses.

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