Dacmcp 4901

MCP4901/4911/4921
8/10/12-Bit Voltage Output Digital-to-Analog Converter

with SPI Interface
Features Description
• MCP4901: 8-Bit Voltage Output DAC The MCP4901/4911/4921 devices are single channel
• MCP4911: 10-Bit Voltage Output DAC 8-bit, 10-bit and 12-bit buffered voltage output
• MCP4921: 12-Bit Voltage Output DAC Digital-to-Analog Converters (DACs), respectively. The
devices operate from a single 2.7V to 5.5V supply with
• Rail-to-Rail Output
an SPI compatible Serial Peripheral Interface. The user
• SPI Interface with 20 MHz Clock Support can configure the full-scale range of the device to be
• Simultaneous Latching of the DAC Output VREF or 2*VREF by setting the gain selection option bit
with LDAC Pin (gain of 1 of 2).
• Fast Settling Time of 4.5 µs The user can shut down the device by setting the Con-
• Selectable Unity or 2x Gain Output figuration Register bit. In Shutdown mode, most of the
• External Voltage Reference Input internal circuits are turned off for power savings, and
• External Multiplier Mode the output amplifier is configured to present a known
high resistance output load (500 ktypical.
• 2.7V to 5.5V Single-Supply Operation
• Extended Temperature Range: -40°C to +125°C The devices include double-buffered registers,
allowing synchronous updates of the DAC output using
the LDAC pin. These devices also incorporate a
Applications
Power-on Reset (POR) circuit to ensure reliable power-
• Set Point or Offset Trimming up.
• Precision Selectable Voltage Reference The devices utilize a resistive string architecture, with
• Motor Control Feedback Loop its inherent advantages of low Differential Non-Linear-
• Digitally-Controlled Multiplier/Divider ity (DNL) error and fast settling time. These devices are
specified over the extended temperature range
• Calibration of Optical Communication Devices
(+125°C).
Related Products The devices provide high accuracy and low noise
performance for consumer and industrial applications
Voltage where calibration or compensation of signals (such as
DAC No. of temperature, pressure and humidity) are required.
P/N Reference
Resolution Channels
(VREF) The MCP4901/4911/4921 devices are available in the
MCP4801 8 1 PDIP, SOIC, MSOP and DFN packages.
MCP4811 10 1
Internal Package Types
MCP4821 12 1
(2.048V)
MCP4802 8 2
8-Pin PDIP, SOIC, MSOP DFN-8 (2x3)*
MCP4812 10 2
MCP4822 12 2 VDD 1 8 VOUT VDD 1 8 VOUT
MCP49x1
MCP4901 8 1 CS 2 7 VSS CS 2 EP 7 VSS

MCP4911 10 1 SCK 3 6 VREF SCK 3 9 6 VREF
External
MCP4921 12 1 SDI 4 5 LDAC SDI 4 5 LDAC
MCP4902 8 2
MCP4912 10 2 MCP4901: 8-bit single DAC
MCP4911: 10-bit single DAC
MCP4922 12 2 MCP4921: 12-bit single DAC
Note: The products listed here have similar AC/DC
* Includes Exposed Thermal Pad (EP); see Table 3-1.
performances.
 2010 Microchip Technology Inc. DS22248A-page 1

MCP4901/4911/4921
Block Diagram
LDAC CS SDI SCK
Interface Logic
Power-on VDD
Reset
Input
Register VSS
DAC
Register
VREF String
DAC
Buffer
Gain
Output
Logic
Op Amp
Output
Logic
VOUT
DS22248A-page 2  2010 Microchip Technology Inc.

MCP4901/4911/4921
1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
CHARACTERISTICS a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
Absolute Maximum Ratings † operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
VDD ............................................................................................................. 6.5V may affect device reliability.
All inputs and outputs w.r.t ................VSS –0.3V to VDD+0.3V
Current at Input Pins ....................................................±2 mA
Current at Supply Pins ...............................................±50 mA
Current at Output Pins ...............................................±25 mA
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-55°C to +125°C
ESD protection on all pins  4 kV (HBM), 400V (MM)
Maximum Junction Temperature (TJ) . .........................+150°C
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain
(G) = 2x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85°C. Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Power Requirements
Operating Voltage VDD 2.7 — 5.5
Supply Current IDD — 175 350 µA VDD = 5V
— 125 250 µA VDD = 3V
VREF input is unbuffered, all digital
inputs are grounded, all analog
outputs (VOUT) are unloaded.
Code = 0x000h
Software Shutdown Current ISHDN_SW — 3.3 6 µA Power-on Reset circuit remains on
Power-On-Reset Threshold VPOR — 2.0 — V
DC Accuracy
MCP4901
Resolution n 8 — — Bits
INL Error INL -1 ±0.125 1 LSb
DNL DNL -0.5 ±0.1 +0.5 LSb Note 1
MCP4911
INL Error INL -3.5 ±0.5 3.5 LSb
DNL DNL -0.5 ±0.1 +0.5 LSb Note 1
MCP4921
INL Error INL -12 ±2 12 LSb
DNL DNL -0.75 ±0.2 +0.75 LSb Note 1
Note 1: Guaranteed monotonic by design over all codes.
2: This parameter is ensured by design, and not 100% tested.

MCP4901/4911/4921
ELECTRICAL CHARACTERISTICS (CONTINUED)
(G) = 2x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85°C. Typical values are at +25°C.
Offset Error VOS — ±0.02 1 % of Code = 0x000h
FSR
Offset Error Temperature VOS/°C — 0.16 — ppm/°C -45°C to 25°C
Coefficient — -0.44 — ppm/°C +25°C to 85°C
Gain Error gE — -0.10 1 % of Code = 0xFFFh, not including
FSR offset error
Gain Error Temperature G/°C — -3 — ppm/°C
Coefficient
Input Amplifier (VREF Input)
Input Range – Buffered VREF 0.040 — VDD – V Note 2
Mode 0.040 Code = 2048
Input Range – Unbuffered VREF 0 — VDD V VREF = 0.2 Vp-p, f = 100 Hz and
Mode 1 kHz
Input Impedance RVREF — 165 — k Unbuffered Mode
Input Capacitance – CVREF — 7 — pF
Unbuffered Mode
Multiplier Mode fVREF — 450 — kHz VREF = 2.5V ±0.2Vp-p,
-3 dB Bandwidth Unbuffered, G = 1
fVREF — 400 — kHz VREF = 2.5V ±0.2 Vp-p,
Unbuffered, G = 2
Multiplier Mode – THDVREF — -73 — dB VREF = 2.5V ±0.2Vp-p,
Total Harmonic Distortion Frequency = 1 kHz
Output Amplifier
Output Swing VOUT — 0.01 to — V Accuracy is better than 1 LSb for
VDD – VOUT = 10 mV to (VDD – 40 mV)
0.04
Phase Margin m — 66 — Degrees
Slew Rate SR — 0.55 — V/µs
Short Circuit Current ISC — 15 24 mA
Settling Time tsettling — 4.5 — µs Within 1/2 LSB of final value from
1/4 to 3/4 full-scale range
Dynamic Performance (Note 2)
DAC-to-DAC Crosstalk — 10 — nV-s
Major Code Transition — 45 — nV-s 1 LSB change around major carry
Glitch (0111...1111 to 1000...0000)
Digital Feedthrough — 10 — nV-s
Analog Crosstalk — 10 — nV-s

MCP4901/4911/4921
ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE

(G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Power Requirements
Input Voltage VDD 2.7 — 5.5
Input Current IDD — 200 — µA VREF input is unbuffered, all digi-
tal inputs are grounded, all analog
outputs (VOUT) are unloaded.
Code = 0x000h
Software Shutdown Current ISHDN_SW — 5 — µA
Power-on Reset Threshold VPOR — 1.85 — V
DC Accuracy
MCP4901
INL Error INL ±0.25 LSb
DNL DNL ±0.2 LSb Note 1
MCP4911
INL Error INL ±1 LSb
MCP4921
INL Error INL ±4 LSb
Offset Error VOS — ±0.02 — % of FSR Code = 0x000h
Offset Error Temperature VOS/°C — -5 — ppm/°C +25°C to +125°C
Coefficient
Gain Error gE — -0.10 — % of FSR Code = 0xFFFh, not including
offset error
Gain Error Temperature G/°C — -3 — ppm/°C
Coefficient
Input Amplifier (VREF Input)
Input Range – Buffered VREF — 0.040 to — V Note 1
Mode VDD- Code = 2048,
0.040 VREF = 0.2 Vp-p, f = 100 Hz and
1 kHz
Input Range – Unbuffered VREF 0 — VDD V
Mode
Input Impedance RVREF — 174 — k Unbuffered Mode
Input Capacitance – CVREF — 7 — pF
Unbuffered Mode
Multiplying Mode fVREF — 450 — kHz VREF = 2.5V ±0.1 Vp-p,
-3 dB Bandwidth Unbuffered, G = 1x
fVREF — 400 — kHz VREF = 2.5V ±0.1 Vp-p,
Unbuffered, G = 2x

MCP4901/4911/4921
ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE (CONTINUED)
(G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Multiplying Mode - Total THDVREF — — — dB VREF = 2.5V ±0.1Vp-p,
Harmonic Distortion Frequency = 1 kHz
Output Amplifier
Output Swing VOUT — 0.01 to — V Accuracy is better than 1 LSb for
VDD – VOUT = 10 mV to (VDD – 40 mV)
0.04
Phase Margin m — 66 — Degrees
Slew Rate SR — 0.55 — V/µs
Short Circuit Current ISC — 17 — mA
Settling Time tsettling — 4.5 — µs Within 1/2 LSB of final value from
1/4 to 3/4 full-scale range
Dynamic Performance (Note 2)
Major Code Transition — 45 — nV-s 1 LSB change around major carry
Glitch (0111...1111 to 1000...0000)
Digital Feedthrough — 10 — nV-s

MCP4901/4911/4921
AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)
Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125°C.
Typical values are at +25°C.
Schmitt Trigger High Level VIH 0.7 VDD — — V
Input Voltage (All digital input
pins)
Schmitt Trigger Low Level Input VIL — — 0.2 VDD V
Voltage (All digital input pins)
Hysteresis of Schmitt Trigger VHYS — 0.05 VDD —
Inputs
Input Leakage Current ILEAKAGE -1 — 1 A LDAC = CS = SDI =
SCK = VREF = VDD or VSS
Digital Pin Capacitance CIN, — 10 — pF VDD = 5.0V, TA = +25°C,
(All inputs/outputs) COUT fCLK = 1 MHz (Note 1)
Clock Frequency FCLK — — 20 MHz TA = +25°C (Note 1)
Clock High Time tHI 15 — — ns Note 1
Clock Low Time tLO 15 — — ns Note 1
CS Fall to First Rising CLK tCSSR 40 — — ns Applies only when CS falls with
Edge CLK high (Note 1)
Data Input Setup Time tSU 15 — — ns Note 1
Data Input Hold Time tHD 10 — — ns Note 1
SCK Rise to CS Rise Hold tCHS 15 — — ns Note 1
Time
CS High Time tCSH 15 — — ns Note 1
LDAC Pulse Width tLD 100 — — ns Note 1
LDAC Setup Time tLS 40 — — ns Note 1
SCK Idle Time before CS Fall tIDLE 40 — — ns Note 1
Note 1: This parameter is ensured by design and not 100% tested.
tCSH
CS
tIDLE
tCSSR tHI tLO tCHS
Mode 1,1
SCK Mode 0,0
tSU tHD
SI
MSB in LSB in
LDAC
tLS tLD
FIGURE 1-1: SPI Input Timing Data.

MCP4901/4911/4921
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Temperature Ranges
Specified Temperature Range TA -40 — +125 °C
Operating Temperature Range TA -40 — +125 °C Note 1
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-DFN (2 x 3) JA — 68 — °C/W
Thermal Resistance, 8L-PDIP JA — 90 — °C/W
Thermal Resistance, 8L-SOIC JA — 150 — °C/W
Thermal Resistance, 8L-MSOP JA — 211 — °C/W
Note 1: The MCP4901/4911/4921 devices operate over this extended temperature range, but with reduced
performance. Operation in this range must not cause TJ to exceed the maximum junction temperature of
150°C.

MCP4901/4911/4921
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
0.3 0.0766
0.0764
0.2
Absolute DNL (LSB)

0.0762
0.1
DNL (LSB)
0.076
0 0.0758
0.0756
-0.1
0.0754
-0.2 0.0752
-0.3 0.075
0 1024 2048 3072 4096 -40 -20 0 20 40 60 80 100 120
Code (Decimal) Ambient Temperature (ºC)
FIGURE 2-1: DNL vs. Code (MCP4921). FIGURE 2-4: Absolute DNL vs.
Temperature (MCP4921).
0.2 0.35
0.3
Absolute DNL (LSB)
0.1 0.25
DNL (LSB)
0.2
0
0.15
0.1
-0.1
0.05
-0.2 0
0 1024 2048 3072 4096 1 2 3 4 5
Code (Decimal) 125C 85C 25C Voltage Reference (V)
FIGURE 2-2: DNL vs. Code and FIGURE 2-5: Absolute DNL vs. Voltage
Temperature (MCP4921). Reference (MCP4921).
0.4 5
Ambient Temperature
0.3 4
125C 85 25
3
0.2
2
DNL (LSB)
INL (LSB)
0.1 1
0 0
-0.1 -1
-0.2 -2
-3
-0.3
-4
-0.4 -5
0 1024 2048 3072 4096 0 1024 2048 3072 4096
Code (Decimal) 1 2 3 4 5.5 Code (Decimal)
FIGURE 2-3: DNL vs. Code and VREF, FIGURE 2-6: INL vs. Code and
Gain=1 (MCP4921). Temperature (MCP4921).

MCP4901/4911/4921
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
2.5 2
2
Absolute INL (LSB)
INL (LSB)
1.5
-2
1
-4
0.5
0 -6
-40 -20 0 20 40 60 80 100 120 0 1024 2048 3072 4096
Ambient Temperature (ºC) Code (Decimal)
FIGURE 2-7: Absolute INL vs. FIGURE 2-10: INL vs. Code (MCP4921).
Temperature (MCP4921).
Note: Single device graph (Figure 2-10) for
illustration of 64 code effect.
3
0.2
2.5 Temp = - 40oC to +125oC
Absolute INL (LSB)
2 0.1
DNL (LSB)
1.5
0
1
0.5 -0.1
0
1 2 3 4 5 -0.2
0 128 256 384 512 640 768 896 1024
Voltage Reference (V) Code
FIGURE 2-8: Absolute INL vs. VREF FIGURE 2-11: DNL vs. Code and
(MCP4921). Temperature (MCP4911).
3
VREF 1.5
2 1 2 3 4 5.5
1 0.5 o
85 C
INL (LSB)
0
INL (LSB)
-0.5
-1
-1.5
-2
o
25 C
-3 -2.5 o
- 40 C
o
125 C
-4
0 1024 2048 3072 4096 -3.5
Code (Decimal) 0 128 256 384 512 640 768 896 1024
Code
FIGURE 2-9: INL vs. Code and VREF FIGURE 2-12: INL vs. Code and
(MCP4921). Temperature (MCP4911).

MCP4901/4911/4921
0.06 18
Temp = -40oC to +125oC
16
0.04
14
Occurrence
0.02 12
DNL (LSB)
10
0 8
6
-0.02 4
2
-0.04
0
143
145
147
149
151
153
155
157
159
161
163
165
167
-0.06
0 32 64 96 128 160 192 224 256 IDD (μA)
Code
FIGURE 2-13: DNL vs. Code and FIGURE 2-16: IDD Histogram (VDD =
Temperature (MCP4901). 2.7V).
0.5 9
8
o o
-40 C to +85 C 7
0.25
Occurrence
6
5
INL (LSB)
0 4
3
2
-0.25 o
125 C 1
0
-0.5 151 156 161 166 171 176 181 186 191 196 201
0 32 64 96 128 160 192 224 256 IDD (μA)
Code
FIGURE 2-14: INL vs. Code and FIGURE 2-17: IDD Histogram (VDD =
Temperature (MCP4901). 5.0V).
210 5.5V
5.0V
190 4.0V
3.0V
2.7V
170
IDD (µA)
VDD
150
130
110
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (°C)
FIGURE 2-15: IDD vs. Temperature and

VDD.

MCP4901/4911/4921
6 4 VDD
5.5V
5.5V
5 3.5
5.0V
VIN Hi Threshold (V)

5.0V
4 3
ISHDN_SW (μA)
4.0V
3 2.5 4.0V
3.0V
2.7V
2 2
VDD 3.0V
1 1.5 2.7V
0 1
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC) Ambient Temperature (ºC)
FIGURE 2-18: Shutdown Current vs. FIGURE 2-21: VIN High Threshold vs.
Temperature and VDD. Temperature and VDD.
0.12 1.6 VDD
VIN Low Threshold (V)

0.1 1.5
5.5V
1.4
Offset Error (%)
0.08 5.0V
VDD 1.3
0.06
1.2
0.04 4.0V
5.5V 1.1
0.02
1
3.0V
0 5.0V 0.9 2.7V
4.0V
-0.02 3.0V 0.8
2.7V
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
FIGURE 2-19: Offset Error vs.Temperature FIGURE 2-22: VIN Low Threshold vs.
and VDD. Temperature and VDD.
-0.08 VDD
5.5V
-0.1
Gain Error (%)
5.0V
-0.12
4.0V
-0.14 3.0V
2.7V
-0.16
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
FIGURE 2-20: Gain Error vs. Temperature

and VDD.

MCP4901/4911/4921
2.5 0.0045 VDD

VDD
2.25
VOUT_LOW Limit (Y-AVSS)(V)

5.5V 0.004
VIN_SPI Hysteresis (V)
2 5.5V
5.0V
1.75 0.0035
1.5
4.0V 0.003
1.25
5.0V
1
3.0V 0.0025
0.75 2.7V 4.0V
3.0V
0.5 0.002 2.7V
0.25
0 0.0015
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
FIGURE 2-23: Input Hysteresis vs. FIGURE 2-26: VOUT Low Limit vs.
18 VDD
175 5.5V -
2.7V 17
VREF_UNBUFFERED Impedance
5.5V
VDD 5.0V
IOUT_HI_SHORTED (mA)
16 4.0V
170 3.0V
15 2.7V
(kOhm)
165 14
13
160 12
11
155 10
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
FIGURE 2-24: VREF Input Impedance vs. FIGURE 2-27: IOUT High Short vs.
0.045 6.0
5.5V
0.04 5.0V
VOUT_HI Limit (VDD-Y)(V)
5.0
0.035
4.0V VREF=4.0
0.03 4.0
VOUT (V)
Output Shorted to VDD

0.025 3.0V
2.7V 3.0
0.02
0.015 VDD 2.0
0.01
1.0 Output Shorted to VSS
0.005
0 0.0
-40 -20 0 20 40 60 80 100 120 0 2 4 6 8 10 12 14 16
Ambient Temperature (ºC) IOUT (mA)
FIGURE 2-25: VOUT High Limit vs. FIGURE 2-28: IOUT vs. VOUT. Gain = 1.
Temperature and VDD.

MCP4901/4911/4921
VOUT
VOUT
SCK
LDAC LDAC
Time (1 µs/div) Time (1 µs/div)
FIGURE 2-29: VOUT Rise Time FIGURE 2-32: VOUT Rise Time
VOUT
VOUT
SCK
SCK
LDAC LDAC
Time (1 µs/div) Time (1 µs/div)

FIGURE 2-30: VOUT Fall Time. FIGURE 2-33: VOUT Rise Time Exit
Shutdown.
Ripple Rejection (dB)
VOUT
SCK
LDAC
Time (1 µs/div) Frequency (Hz)

FIGURE 2-31: VOUT Rise Time FIGURE 2-34: PSRR vs. Frequency.

MCP4901/4911/4921
0 D= 160
D= 416
0 D= 160
D= 672
D= 416
D= 672 D= 928
-2 -45 D= 1184
D= 928
qVREF – qVOUT
Attenuation (dB)
D= 1184 D= 1440
D= 1440
-4 D= 1696
D= 1696
D= 1952 -90 D= 1952
-6 D= 2208 D= 2208
D= 2464 D= 2464
D= 2720 D= 2720
-8 D= 2976 -135 D= 2976
D= 3232
D= 3488
D= 3232
-10
D= 3744 D= 3488
D= 3744
-12 -180
100 1,000 100 1,000
Frequency (kHz) Frequency (kHz)
FIGURE 2-35: Multiplier Mode Bandwidth. FIGURE 2-37: Phase Shift.
Figure 2-35 calculation:

Attenuation (dB) = 20 log (VOUT/VREF) – 20 log (G(D/4096))
600
580
560
Bandwidth (kHz)
540
520
500 G=1
480
460 G=2
440
420
400
16
41
67
92
11
14
16
19
22
24
27
29
32
34
37
0
6
2
8
84
40
96
52
08
64
20
76
32
88
44
Worst Case Codes (decimal)
FIGURE 2-36: -3 db Bandwidth vs. Worst

Codes.

MCP4901/4911/4921
NOTES:

MCP4901/4911/4921
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE

PDIP, MSOP, SOIC DFN Symbol Description
1 1 VDD Supply Voltage Input (2.7V to 5.5V)
2 2 CS Chip Select Input
3 3 SCK Serial Clock Input
4 4 SDI Serial Data Input
5 5 LDAC DAC Output Synchronization Input. This pin is used to transfer
the input register (DAC settings) to the output register (VOUT)
6 6 VREF Voltage Reference Input
7 7 VSS Ground reference point for all circuitry on the device
8 8 VOUT DAC Analog Output
— 9 EP Exposed Thermal Pad. This pad must be connected to VSS in
application
3.1 Supply Voltage Pins (VDD, VSS) 3.5 Latch DAC Input (LDAC)
VDD is the positive supply voltage input pin. The input The LDAC (latch DAC synchronization input) pin is
supply voltage is relative to VSS and can range from used to transfer the input latch register to the DAC reg-
2.7V to 5.5V. The power supply at the VDD pin should ister (output latches, VOUT). When this pin is low, VOUT
be as clean as possible for good DAC performance. It is updated with input register content. This pin can be
is recommended to use an appropriate bypass capaci- tied to low (VSS) if the VOUT update is desired at the
tor of about 0.1 µF (ceramic) to ground. An additional rising edge of the CS pin. This pin can be driven by an
10 µF capacitor (tantalum) in parallel is also recom- external control device such as an MCU I/O pin.
mended to further attenuate high-frequency noise
present in application boards. 3.6 Analog Output (VOUT)
VSS is the analog ground pin and the current return path
VOUT is the DAC analog output pin. The DAC output
of the device. The user must connect the VSS pin to a
has an output amplifier. The full-scale range of the DAC
ground plane through a low-impedance connection. If
output is from VSS to G*VREF, where G is the gain
an analog ground path is available in the application
selection option (1x or 2x). The DAC analog output
Printed Circuit Board (PCB), it is highly recommended
cannot go higher than the supply voltage (VDD).
that the VSS pin be tied to the analog ground path or
isolated within an analog ground plane of the circuit
board. 3.7 Voltage Reference Input (VREF)
VREF is the voltage reference input for the device. The
3.2 Chip Select (CS) reference on this pin is utilized to set the reference
voltage on the string DAC. The input voltage can range
CS is the chip select input, which requires an active-low
from VSS to VDD. This pin can be tied to VDD.
signal to enable serial clock and data functions.
3.8 Exposed Thermal Pad (EP)

3.3 Serial Clock Input (SCK)
There is an internal electrical connection between the
SCK is the SPI compatible serial clock input.
Exposed Thermal Pad (EP) and the VSS pin. They must
be connected to the same potential on the PCB.
3.4 Serial Data Input (SDI)
SDI is the SPI compatible serial data input.

MCP4901/4911/4921
NOTES:

MCP4901/4911/4921
4.0 GENERAL OVERVIEW TABLE 4-1: LSb OF EACH DEVICE
The MCP4901, MCP4911 and MCP4921 are single Gain
Device LSb Size
channel voltage output 8-bit, 10-bit and 12-bit DAC Selection
devices, respectively. These devices include a VREF MCP4901 1x VREF/256
input buffer, a rail-to-rail output amplifier, shutdown and (n = 8) 2x (2*VREF)/256
reset management circuitry. The devices use an SPI
serial communication interface and operate with a MCP4911 1x VREF/1024
single-supply voltage from 2.7V to 5.5V. (n = 10) 2x (2*VREF)/1024
The DAC input coding of these devices is straight MCP4921 1x VREF/4096
binary. Equation 4-1 shows the DAC analog output (n = 12) 2x (2*VREF)/4096
voltage calculation. where VREF is the external voltage reference.
EQUATION 4-1: ANALOG OUTPUT 4.1 DC Accuracy

VOLTAGE (VOUT)
 VREF  Dn  4.1.1 INL ACCURACY
VOUT = ------------------------------
- G
2
n Integral Non-Linearity (INL) error is the maximum
Where: deviation between an actual code transition point and
its corresponding ideal transition point, after offset and
VREF = EXternal voltage reference gain errors have been removed. The two endpoints
Dn = DAC input code (from 0x000 and 0xFFF) method is used for the calcu-
G = Gain Selection lation. Figure 4-1 shows the details.
= 2 for <GA> bit = 0 A positive INL error represents transition(s) later than
= 1 for <GA> bit = 1 ideal. A negative INL error represents transition(s) ear-
n = DAC Resolution lier than ideal.
= 8 for MCP4901
= 10 for MCP4911
= 12 for MCP4912
INL < 0
111
Actual
The ideal output range of each device is: 110 Transfer
Function
• MCP4901 (n = 8)
101
(a) 0V to 255/256*VREF when gain setting = 1x.
(b) 0V to 255/256*2*VREF when gain setting = 2x. Digital 100
Input
• MCP4911 (n = 10) Code 011 Ideal Transfer
(a) 0V to 1023/1024*VREF when gain setting = 1x. Function
010
(b) 0V to 1023/1024*2*VREF when gain setting = 2x.
• MCP4921 (n = 12) 001
(a) 0V to 4095/4096*VREF when gain setting = 1x.
000
(b) 0V to 4095/4096*2*VREF when gain setting = 2x. INL < 0
Note: See the output swing voltage specification DAC Output

in Section 1.0 “Electrical Characteris-
tics”. FIGURE 4-1: Example for INL Error.
1 LSb is the ideal voltage difference between two
successive codes. Table 4-1 illustrates the LSb 4.1.2 DNL ACCURACY
calculation of each device.
A Differential Non-Linearity (DNL) error is the measure
of variations in code widths from the ideal code width.
A DNL error of zero indicates that every code is exactly
1 LSB wide.

MCP4901/4911/4921
4.2.2 VOLTAGE REFERENCE AMPLIFIER
The input buffer amplifier for the MCP4901/4911/4921
devices provides low offset voltage and low noise. A
111
Configuration bit for each DAC allows the VREF input to
110 bypass the VREF input buffer amplifier, achieving
Actual
Buffered or Unbuffered mode. Buffered mode provides
Transfer
101 Function a very high input impedance, with only minor limitations
on the input range and frequency response. Unbuf-
Digital 100 Ideal Transfer fered mode provides a wide input range (0V to VDD),
Input
Function with a typical input impedance of 165 k with 7 pF.
Code 011
Unbuffered mode (<BUF> = 0) is the default
010 configuration.
Wide Code, > 1 LSb
001 4.2.3 POWER-ON RESET CIRCUIT
000 The internal Power-on Reset (POR) circuit monitors the
Narrow Code, < 1 LSb power supply voltage (VDD) during device operation.
The circuit also ensures that the device powers up with
DAC Output high output impedance (<SHDN> = 0, typically
500 k. The devices will continue to have a high-
FIGURE 4-2: Example for DNL Accuracy. impedance output until a valid write command is
received, and the LDAC pin meets the input low thresh-
4.1.3 OFFSET ERROR old.
An offset error is the deviation from zero voltage output If the power supply voltage is less than the POR
when the digital input code is zero. threshold (VPOR = 2.0V, typical), the device will be held
in its Reset state. It will remain in that state until
4.1.4 GAIN ERROR VDD > VPOR and a subsequent write command is
A gain error is the deviation from the ideal output, received.
VREF– 1 LSB, excluding the effects of offset error. Figure 4-3 shows a typical power supply transient
pulse and the duration required to cause a reset to
4.2 Circuit Descriptions occur, as well as the relationship between the duration
and trip voltage. A 0.1 µF decoupling capacitor,
4.2.1 OUTPUT AMPLIFIER mounted as close as possible to the VDD pin, can
provide additional transient immunity.
The DAC’s output is buffered with a low-power,
precision CMOS amplifier. This amplifier provides low
offset voltage and low noise. The output stage enables
5V
the device to operate with output voltages close to the
Supply Voltages
VPOR
power supply rails. Refer to Section 1.0 “Electrical VDD - VPOR
Characteristics” for the analog output voltage range
and load conditions. Transient Duration
In addition to resistive load driving capability, the

Time
amplifier will also drive high capacitive loads without
oscillation. The amplifier’s strong output allows VOUT to 10
TA =
be used as a programmable voltage reference in a
Transient Duration (µs)
8
system.
6
Selecting a gain of 2 reduces the bandwidth of the
amplifier in Multiplying mode. Refer to Section 1.0 4
Transients above the
“Electrical Characteristics” for the Multiplying mode 2
bandwidth for given load conditions. Transients below the
0
1 2 3 4 5
4.2.1.1 Programmable Gain Block VDD – VPOR (V)
The rail-to-rail output amplifier has two configurable FIGURE 4-3: Typical Transient Response.
gain options: a gain of 1x (<GA> = 1) or a gain of 2x
(<GA> = 0). The default value is a gain of 2x
(<GA> = 0).

MCP4901/4911/4921
4.2.4 SHUTDOWN MODE
VOUT
The user can shut down the device by using a software OP
command. During Shutdown mode, most of the internal Amp
circuits, including the output amplifier, are turned off for
power savings. The serial interface remains active,
Power-Down
thus allowing a write command to bring the device out
Control Circuit
of Shutdown mode. There will be no analog output at
the VOUT pin, and the VOUT pin is internally switched to
a known resistive load (500 k typical. Figure 4-4 Resistive 500 k
shows the analog output stage during Shutdown mode. Load
Resistive String DAC
The device will remain in Shutdown mode until it
receives a write command with <SHDN> bit = 1 and the
bit is latched into the device. When the device is
FIGURE 4-4: Output Stage for Shutdown
changed from Shutdown to Active mode, the output
settling time takes less than 10 µs, but more than the Mode.
standard active mode settling time (4.5 µs).

MCP4901/4911/4921
NOTES:

MCP4901/4911/4921
5.0 SERIAL INTERFACE 5.2 Write Command
The write command is initiated by driving the CS pin
5.1 Overview low, followed by clocking the four Configuration bits and
The MCP4901/4911/4921 devices are designed to the 12 data bits into the SDI pin on the rising edge of
interface directly with the Serial Peripheral Interface SCK. The CS pin is then raised, causing the data to be
(SPI) port, which is available on many microcontrollers latched into the DAC’s input register.
and supports Mode 0,0 and Mode 1,1. Commands and The MCP4901/4911/4921 utilizes a double-buffered
data are sent to the device via the SDI pin, with data latch structure to allow the analog output to be
being clocked-in on the rising edge of SCK. The synchronized with the LDAC pin, if desired.
communications are unidirectional, thus the data By bringing the LDAC pin down to a low state, the con-
cannot be read out of the MCP4901/4911/4921. The tent stored in the DAC’s input register is transferred into
CS pin must be held low for the duration of a write the DAC’s output register (VOUT), and VOUT is updated.
command. The write command consists of 16 bits and
is used to configure the DAC’s control and data latches. All writes to the MCP4901/4911/4921 devices are
Register 5-1 through Register 5-3 detail the input regis- 16-bit words. Any clocks past the 16th clock will be
ter that is used to configure and load the DAC register ignored. The Most Significant 4 bits are Configuration
for each device. Figure 5-1 through Figure 5-3 show bits. The remaining 12 bits are data bits. No data can
the write command for each device. be transferred into the device with CS high. This
transfer will only occur if 16 clocks have been
Refer to Figure 1-1 and the SPI Timing Specifications transferred into the device. If the rising edge of CS
Table for detailed input and output timing specifications occurs prior to that, shifting of data into the input
for both Mode 0,0 and Mode 1,1 operation. register will be aborted.

MCP4901/4911/4921
REGISTER 5-1: WRITE COMMAND REGISTER FOR MCP4921 (12-BIT DAC)

W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x
0 BUF GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
bit 15 bit 0

0 BUF GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x x
bit 15 bit 0

0 BUF GA SHDN D7 D6 D5 D4 D3 D2 D1 D0 x x x x
bit 15 bit 0
Where:
bit 15 0 = Write to DAC register

1 = Ignore this command
bit 14 BUF: VREF Input Buffer Control bit
1 = Buffered
0 = Unbuffered
bit 13 GA: Output Gain Selection bit
1 = 1x (VOUT = VREF * D/4096)
0 = 2x (VOUT = 2 * VREF * D/4096)
bit 12 SHDN: Output Shutdown Control bit
1 = Active mode operation. VOUT is available. 
0 = Shutdown the device. Analog output is not available. VOUT pin is connected to 500 ktypical)
bit 11-0 D11:D0: DAC Input Data bits. Bit x is ignored.
Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

MCP4901/4911/4921
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1)
SCK (Mode 0,0)
config bits 12 data bits
SDI 0 BUF GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LDAC
VOUT
FIGURE 5-1: Write Command for MCP4921 (12-bit DAC).
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1)
SCK (Mode 0,0)
SDI 0 BUF GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
LDAC
VOUT
FIGURE 5-2: Write Command for MCP4911 (10-bit DAC). Note: X are don’t care bits.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1)
SCK (Mode 0,0)
SDI 0 BUF GA SHDN D7 D6 D5 D4 D3 D2 D1 D0 X X X X
LDAC
VOUT
FIGURE 5-3: Write Command for MCP4901(8-bit DAC). Note: X are don’t care bits.

MCP4901/4911/4921
NOTES:

MCP4901/4911/4921
6.0 TYPICAL APPLICATIONS
The MCP4901/4911/4921 family devices are general VDD VDD
purpose DACs intended to be used in applications
C1 = 10 µF
where precision with low-power and moderate C2 C2
C2 = 0.1 µF C1 C1
bandwidth is required.
Applications generally suited for the devices are: VDD VREF
• Set Point or Offset Trimming CS1
VOUT
• Sensor Calibration
MCP49X1
SDI
• Digitally-Controlled Multiplier/Divider C1
• Portable Instrumentation (Battery Powered)
PIC® Microcontroller
• Motor Control Feedback Loop
6.1 Digital Interface VREF

SDI AVSS SDO
MCP49X1
The MCP4901/4911/4921 devices utilize a 3-wire
synchronous serial protocol to transfer the DAC’s setup SCK
and output values from the digital source. The serial VOUT
protocol can be interfaced to SPI or Microwire periph-
LDAC
erals that are common on many microcontrollers,
including Microchip’s PIC® MCUs and dsPIC® DSCs.
CS0
In addition to the three serial connections (CS, SCK
and SDI), the LDAC pin synchronizes the analog output AVSS VSS
(VOUT) with the pin event. By bringing the LDAC pin
down “low”, the DAC input code and settings in the
FIGURE 6-1: Typical Connection
input register are latched into the output register, and
the analog output is updated. Figure 6-1 shows an
Diagram.
example of the pin connections. Note that the LDAC pin
can be tied low (VSS) to reduce the required 6.3 Layout Considerations
connections from 4 to 3 I/O pins. In this case, the DAC
Inductively-coupled AC transients and digital switching
output can be immediately updated when a valid
noises can degrade the input and output signal
16-clock transmission has been received and CS pin
integrity, potentially reducing the device’s performance.
has been raised.
Careful board layout will minimize these effects and
increase the Signal-to-Noise Ratio (SNR). Bench test-
6.2 Power Supply Considerations ing has shown that a multi-layer board utilizing a
The typical application will require a bypass capacitor low-inductance ground plane, isolated inputs, and
in order to filter high-frequency noise. The noise can be isolated outputs with proper decoupling, is critical for
induced onto the power supply's traces from various best performance. Particularly harsh environments
events such as digital switching or as a result of may require shielding of critical signals.
changes on the DAC's output. The bypass capacitor Breadboards and wire-wrapped boards are not
helps to minimize the effect of these noise sources. recommended if low noise is desired.
Figure 6-1 illustrates an appropriate bypass strategy. In
this example, two bypass capacitors are used in
parallel: (a) 0.1 µF (ceramic) and (b) 10 µF (tantalum).
These capacitors should be placed as close to the
device power pin (VDD) as possible (within 4 mm).
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.

MCP4901/4911/4921
6.4 Single-Supply Operation 6.4.1.1 Decreasing Output Step Size
The MCP4901/4911/4921 devices are rail-to-rail volt- If the application is calibrating the bias voltage of a
age output DAC devices designed to operate with a diode or transistor, a bias voltage range of 0.8V may be
VDD range of 2.7V to 5.5V. Its output amplifier is robust desired with about 200 µV resolution per step. Two
enough to drive small signal loads directly. Therefore, it common methods to achieve a 0.8V range is to either
does not require an external output buffer for most reduce VREF to 0.82V or use a voltage divider on the
applications. DAC’s output.
Using a VREF is an option if the VREF is available with
6.4.1 DC SET POINT OR CALIBRATION the desired output voltage range. However,
A common application for DAC devices is occasionally, when using a low-voltage VREF, the noise
digitally-controlled set points and/or calibration of floor causes an SNR error that is intolerable. Using a
variable parameters, such as sensor offset or slope. voltage divider method is another option and provides
For example, the MCP4921 and MCP4922 provide some advantages when VREF needs to be very low or
4096 output steps. If the external voltage reference when the desired output voltage is not available. In this
(VREF) is 4.096V, the LSb size is 1 mV. If a smaller case, a larger value VREF is used while two resistors
output step size is desired, a lower external voltage scale the output range down to the precise desired
reference is needed. level.
Example 6-1 illustrates this concept. Note that the
bypass capacitor on the output of the voltage divider
plays a critical function in attenuating the output noise
of the DAC and the induced noise from the
environment.
(a) Single Output DAC:

MCP4901 VDD
MCP4911
MCP4921
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922 VCC+
RSENSE
VDD
VREF VO
Comparator
R1 VTRIP
VOUT
DAC
0.1 uF VCC–
R2
SPI
3-wire
Dn
V OUT = V REF  G  ------
N
G = Gain selection (1x or 2x)
2 Dn = Digital value of DAC (0-255) for MCP4901/MCP4902
= Digital value of DAC (0-1023) for MCP4911/MCP4912
 R2  = Digital value of DAC (0-4095) for MCP4921/MCP4922
Vtrip = V OUT  --------------------
 R1 + R2 N = DAC Bit Resolution
EXAMPLE 6-1: EXAMPLE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION.

MCP4901/4911/4921
6.4.1.2 Building a “Window” DAC If the threshold is not near VREF or VSS, then creating
a “window” around the threshold has several
When calibrating a set point or threshold of a sensor,
advantages. One simple method to create this
typically only a small portion of the DAC output range is
“window” is to use a voltage divider network with a
utilized. If the LSb size is adequate enough to meet the
pull-up and pull-down resistor. Example 6-2 and
application’s accuracy needs, the unused range is
Example 6-4 illustrate this concept.
sacrificed without consequences. If greater accuracy is
needed, then the output range will need to be reduced
to increase the resolution around the desired threshold.

MCP4901
MCP4911
MCP4921
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922 VCC+
VCC+ Rsense
VREF VDD
R3 Comparator
R1 Vtrip
VOUT
DAC
VCC-
R2 0.1 µF
SPI
3
VCC-
Dn
V OUT = VREF  G  ------
N
2
G = Gain selection (1x or 2x)

Dn = Digital value of DAC (0-255) for MCP4901/MCP4902
N = DAC Bit Resolution
R 2 R3 R1
R 23 = ------------------
R2 + R 3 VOUT VO
Thevenin
Equivalent  V CC+ R2  +  VCC- R3 
V 23 = ----------------------------------------------------
- R23
R 2 + R3
V OUT R23 + V 23 R1
V trip = -------------------------------------------
- V23
R 2 + R23
EXAMPLE 6-2: SINGLE-SUPPLY “WINDOW” DAC.

MCP4901/4911/4921
6.5 Bipolar Operation Example 6-3 illustrates a simple bipolar voltage source
configuration. R1 and R2 allow the gain to be selected,
Bipolar operation is achievable using the MCP4901/ while R3 and R4 shift the DAC's output to a selected
4911/4921 family devices by using an external offset. Note that R4 can be tied to VREF instead of VSS
operational amplifier (op amp). This configuration is if a higher offset is desired. Note that a pull-up to VREF
desirable due to the wide variety and availability of op could be used, instead of R4, if a higher offset is
amps. This allows a general purpose DAC, with its cost desired.
and availability advantages, to meet almost any
desired output voltage range, power and noise
performance.
(a) Single Output DAC: VREF

MCP4901 VREF VDD
MCP4911 R1 VCC+
MCP4921 VO
VOUT R3
(b) Dual Output DAC: VIN+
MCP4902 DAC
MCP4912 VCC–
MCP4922 R4 0.1 µF
SPI
3
Dn
VOUT = V REF  G  ------
N
2 G = Gain selection (1x or 2x)
V OUT R4 Dn = Digital value of DAC (0 – 255) for MCP4901/MCP4902
VIN+ = -------------------
-
R3 + R 4 = Digital value of DAC (0 – 1023) for MCP4911/MCP4912
= Digital value of DAC (0 – 4095) for MCP4921/MCP4922
R R2
VO = V IN+  1 + -----2- – VDD  ------ N = DAC Bit Resolution
R1 R1
EXAMPLE 6-3: DIGITALLY-CONTROLLED BIPOLAR VOLTAGE SOURCE.

6.5.1 DESIGN EXAMPLE: DESIGN A BIPOLAR 4. Next, solve for R3 and R4 by setting the DAC to
DAC USING EXAMPLE 6-3 WITH 12-BIT 4096, knowing that the output needs to be
MCP4912 OR MCP4922 +2.05V.
An output step magnitude of 1 mV with an output range
of ±2.05V is desired for a particular application. R4 2.05V + 0.5V REF 2
----------------------- = ----------------------------------------- = ---
The following steps show the details:  R3 + R 4  1.5VREF 3
1. Calculate the range: +2.05V – (-2.05V) = 4.1V.
2. Calculate the resolution needed: If R4 = 20 k, then R3 = 10 k
4.1V/1 mV = 4100
Since 212 = 4096, 12-bit resolution is desired.
3. The amplifier gain (R2/R1), multiplied by VREF,
must be equal to the desired minimum output to
achieve bipolar operation. Since any gain can
be realized by choosing resistor values
(R1 + R2), the VREF source needs to be deter-
mined first. If a VREF of 4.1V is used, solve for
the gain by setting the DAC to 0, knowing that
the output needs to be -2.05V. The equation can
be simplified to:
– R2 – 2.05 – 2.05 R2 1
--------- = ------------- = ------------- ------ = ---
R1 V REF 4.1 R1 2
If R1 = 20 k and R2 = 10 k, the gain will be 0.5

MCP4901/4911/4921
6.6 Selectable Gain and Offset Bipolar This circuit is typically used in Multiplier mode and is
Voltage Output Using DAC ideal for linearizing a sensor whose slope and offset
varies. Refer to Section 6.9 “Using Multiplier Mode”
Devices
for more information on Multiplier mode.
In some applications, precision digital control of the The equation to design a bipolar “window” DAC would
output range is desirable. Example 6-4 illustrates how be utilized if R3, R4 and R5 are populated.
to use the DAC devices to achieve this in a bipolar or
single-supply application.
R2
VREFA VDD
VCC+
R1
VOUTA
DACA
VCC+
VREFB VDD DACA (Gain Adjust) VO
R5
VOUTB R3
DACB
SPI DACB (Offset Adjust)

R4
0.1uF VCC–
3
VCC–
DA
VOUTA =  V REFA G A  ------
N
-
2
DB GX = Gain selection (1x or 2x)
V OUTB =  VREFB G B  ------
-
N N = DAC Bit Resolution
2
DA, DB = Digital value of DAC (0-255) for MCP4901/MCP4902
VOUTB R 4 + VCC- R3 = Digital value of DAC (0-1023) for MCP4911/MCP4912
V IN+ = -----------------------------------------------
-
R3 + R4 = Digital value of DAC (0-4095) for MCP4912/MCP4922
R R2
V O = V IN+  1 + -----2- – V OUTA  ------
 R   R 1
1
Offset Adjust Gain Adjust
Bipolar “Window” DAC using R4 and R5

Thevenin V CC+ R4 + V CC- R 5 R4 R5
Equivalent V45 = -------------------------------------------
- R 45 = ------------------
R4 + R5 R4 + R5
VOUTB R 45 + V45 R 3 R R2
V IN+ = ----------------------------------------------
- V O = VIN+  1 + -----2- – V OUTA  ------
R3 + R 45 R1 R1
Offset Adjust Gain Adjust
EXAMPLE 6-4: BIPOLAR VOLTAGE SOURCE WITH SELECTABLE GAIN AND OFFSET.

MCP4901/4911/4921
6.7 Designing a Double-Precision 1. Calculate the resolution needed:
DAC 4.1V/1 µV = 4.1x 106. Since 222 = 4.2 x 106,
22-bit resolution is desired. Since DNL = ±0.75
Example 6-5 illustrates how to design a single-supply LSB, this design can be done with the MCP4921
voltage output capable of up to 24-bit resolution by or MCP4922.
using 12-bit DACs. This design is simply a voltage 2. Since the DACB‘s VOUTB has a resolution of
divider with a buffered output. 1 mV, its output only needs to be “pulled” 1/1000
As an example, if a similar application to the one to meet the 1 µV target. Dividing VOUTA by 1000
developed in Section 6.5.1 “Design Example: would allow the application to compensate for
Design a bipolar dac using example 6-3 with 12-bit DACB’s DNL error.
MCP4912 or MCP4922” required a resolution of 1 µV 3. If R2 is 100, then R1 needs to be 100 k.
instead of 1 mV and a range of 0V to 4.1V, then 12-bit 4. The resulting transfer function is not perfectly
resolution would not be adequate. linear, as shown in the equation of Example 6-5.
VREF VDD
VCC+
VOUTA
DACA VO
DACA (Fine Adjust) R1
VDD
R1 >> R2
VOUTB R2 VCC–
DACB 0.1 µF
DACB (Course Adjust)
SPI
3
DA
V OUTA = VREFA GA -------
12 G = Gain selection (1x or 2x)
2 D = Digital value of DAC (0-4096)
VOUTA R 2 + VOUTB R 1
V O = -----------------------------------------------------
R 1 + R2
DB
V OUTB = VREFB GB -------
12
2
EXAMPLE 6-5: SIMPLE, DOUBLE PRECISION DAC WITH MCP4921 OR MCP4922.

MCP4901/4911/4921
6.8 Building Programmable Current When working with very small sensor voltages, plan on
Source eliminating the amplifier’s offset error by storing the
DAC's setting under known sensor conditions.
Example 6-6 shows an example for building a
programmable current source using a voltage follower.
The current sensor (sensor resistor) is used to convert
the DAC voltage output into a digitally-selectable
current source.
Adding the resistor network from Example 6-2 would
be advantageous in this application. The smaller Rsense
is, the less power is dissipated across it. However, this
also reduces the resolution that the current can be
controlled with. The voltage divider, or “window”, DAC
configuration would allow the range to be reduced, thus
increasing the resolution around the range of interest.
VDD or VREF
VREF VDD
(a) Single Output DAC: Load
VCC+
MCP4901
MCP4911 VOUT IL
MCP4921 DAC
(b) Dual Output DAC: Ib
MCP4902 SPI
VCC–
MCP4912 3-wire
MCP4922
RSENSE
I
Ib = ----L

VOUT  G = Gain select (1x or 2x)

IL = ---------------  ------------
R sense  + 1 Dn = Digital value of DAC (0-255) for MCP4901/MCP4902
where Common-Emitter Current Gain = Digital value of DAC (0-4095) for MCP4921/MCP4922
Dn N = DAC Bit Resolution
VOUT = V REF  G  ------
N
2
EXAMPLE 6-6: DIGITALLY-CONTROLLED CURRENT SOURCE.

MCP4901/4911/4921
6.9 Using Multiplier Mode If the gain selection bit is configured for 1x mode
(<GA> = 1), the resulting input signal will be attenuated
The MCP4901/4911/4921 and MCP4902/MCP4912/ by D/2n. With the 12-bit DAC (MCP4921 or MCP4922),
MCP4922 family devices use external reference, and if the gain is configured for 2x mode (<GA> = 0), codes
these devices are ideally suited for use as a multiplier/ less than 2048 attenuate the signal, while codes
divider in a signal chain. Common applications are: (a) greater than 2048 gain the signal.
precision programmable gain/attenuator amplifiers and
(b) motor control feedback loops. The wide input range A DAC provides significantly more gain/attenuation
(0V – VDD) is in Unbuffered mode, and near rail-to-rail resolution when compared to typical programmable
range in Buffered mode. Its bandwidth (> 400 kHz), gain amplifiers. Adding an op amp to buffer the output,
selectable 1x/2x gain and low power consumption give as illustrated in Examples 6-2 through 6-6, extends the
maximum flexibility to meet the application’s needs. output range and power to meet the precise needs of
the application.
To configure the device for multiplier applications,
connect the input signal to VREF and serially configure
the DAC’s input buffer, gain and output value. The
DAC’s output can utilize any of the examples from 6-1
to 6-6, depending on the application requirements.
Example 6-7 is an illustration of how the DAC can
operate in a motor control feedback loop.
VRPM_SET
VRPM

ZFB
MCP4901
VDD
MCP4911 VCC+
MCP4921 +
VOUT
(b) Dual Output DAC: VREF DAC
MCP4902
MCP4912 –
MCP4922
SPI VCC–
3
Rsense
Dn
V OUT = V REF  G  ------
N
2
EXAMPLE 6-7: MULTIPLIER MODE USING VREF INPUT.

MCP4901/4911/4921
7.0 DEVELOPMENT SUPPORT
7.1 Evaluation & Demonstration

Boards
The Mixed Signal PICtail™ Board supports the
MCP4901/4911/4921 family of devices. Please refer to
www.microchip.com for further information on this
product’s capabilities and availability.

MCP4901/4911/4921
NOTES:

MCP4901/4911/4921
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
8-Lead DFN (2x3) Example:
XXX AHS
YWW 010
NN 25
8-Lead MSOP Example:
XXXXXX 4901E
YWWNNN 010256
8-Lead PDIP (300 mil) Example:
XXXXXXXX MCP4901
XXXXXNNN E/P e3 256
YYWW 1010
8-Lead SOIC (150 mil) Example:
XXXXXXXX MCP4901E
XXXXYYWW SN e3 1010
NNN 256
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available characters
for customer-specific information.

MCP4901/4911/4921

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EXPOSED PAD
NOTE 1
NOTE 1
1 2 2 1
D2
TOP VIEW BOTTOM VIEW
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MCP4901/4911/4921

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MCP4901/4911/4921

/:#
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MCP4901/4911/4921
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

MCP4901/4911/4921

:#
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1 2 3
h α
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A1 L
L1 β
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MCP4901/4911/4921

:#
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MCP4901/4911/4921

?< < #
$&' ? *
+ 2% & %! %
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133)))&
&3
*
NOTE 1
E1
1 2 3
D
E
A A2
A1 L
c
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b1 eB
b
4% 60:,
& 5&% 6 67 8
6!&( $ 6 9
% /0

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" "* * . + .
/ % % . < <
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" "* ;"% , . 9
7 5 % +9 +>.

% % 5 . + .
5 "* 9 .
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7 )
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) 0 9/

MCP4901/4911/4921
APPENDIX A: REVISION HISTORY
Revision A (April 2010)

• Original Release of this Document.

MCP4901/4911/4921
NOTES:

MCP4901/4911/4921
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX
Examples:
Device Temperature Package a) MCP4901-E/P: Extended temperature,
Range PDIP package.
b) MCP4901-E/SN: Extended temperature,
SOIC package.
Device MCP4901: 8-Bit Voltage Output DAC
MCP4901T: 8-Bit Voltage Output DAC c) MCP4901T-E/SN: Extended temperature,
(Tape and Reel) SOIC package
MCP4911: 10-Bit Voltage Output DAC Tape and Reel.
MCP4911T: 10-Bit Voltage Output DAC d) MCP4901-E/MS: Extended temperature,
(Tape and Reel) MSOP package.
MCP4921: 12-Bit Voltage Output DAC e) MCP4901T-E/MS: Extended temperature,
MCP4921T: 12-Bit Voltage Output DAC MSOP package
(Tape and Reel) Tape and Reel.
f) MCP4901-E/MC: Extended temperature,
DFN package.
Temperature Range E = -40C to +125C (Extended)
g) MCP4901T-E/MC:Extended temperature,
DFN package
Package MC = 8-Lead Plastic Dual Flat, No Lead Package - Tape and Reel.
2x3x0.9 mm Body (DFN)
MS = 8-Lead Plastic Micro Small Outline (MSOP)
SN = 8-Lead Plastic Small Outline - Narrow, 150 mil h) MCP4911-E/P: Extended temperature,
(SOIC)
P = 8-Lead Plastic Dual In-Line (PDIP) PDIP package.
i) MCP4911-E/SN: Extended temperature,
SOIC package.
j) MCP4911T-E/SN: Extended temperature,
SOIC package
Tape and Reel.
k) MCP4911-E/MS: Extended temperature,
MSOP package.
l) MCP4911T-E/MS: Extended temperature,
MSOP package
Tape and Reel.
m) MCP4911-E/MC: Extended temperature,
DFN package.
n) MCP4911T-E/MC: Extended temperature,
DFN package
Tape and Reel.
o) MCP4921-E/P: Extended temperature,

PDIP package.
p) MCP4921-E/SL: Extended temperature,
SOIC package.
q) MCP4921T-E/SL: Extended temperature,
SOIC package
Tape and Reel.
r) MCP4921-E/MS: Extended temperature,
MSOP package.
s) MCP4921T-E/MS: Extended temperature,
MSOP package
Tape and Reel.
t) MCP4921-E/MC: Extended temperature,
DFN package.
u) MCP4921T-E/MC:Extended temperature,
DFN package
Tape and Reel.

MCP4901/4911/4921
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PIC32 logo, rfPIC and UNI/O are registered trademarks of
MICROCHIP MAKES NO REPRESENTATIONS OR
Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control
QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip
FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN:
Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

WORLDWIDE SALES AND SERVICE
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Web Address:
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01/05/10

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E/SN MCP4911-E/MC MCP4911-E/MS MCP4911-E/P MCP4911-E/SN MCP4911T-E/MC MCP4911T-E/MS
MCP4911T-E/SN MCP4921-E/MC MCP4921-E/MCVAO MCP4921T-E/MCVAO MCP4921T-E/SNVAO

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MCP4901/4911/4921

8/10/12-Bit Voltage Output Digital-to-Analog Converter

MCP4901 8 1 CS 2 7 VSS CS 2 EP 7 VSS

 2010 Microchip Technology Inc. DS22248A-page 1

DS22248A-page 2  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. DS22248A-page 3

DS22248A-page 4  2010 Microchip Technology Inc.

ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE

 2010 Microchip Technology Inc. DS22248A-page 5

DS22248A-page 6  2010 Microchip Technology Inc.

FIGURE 1-1: SPI Input Timing Data.

 2010 Microchip Technology Inc. DS22248A-page 7

DS22248A-page 8  2010 Microchip Technology Inc.

Absolute DNL (LSB)

Code (Decimal) Ambient Temperature (ºC)

 2010 Microchip Technology Inc. DS22248A-page 9

Ambient Temperature (ºC) Code (Decimal)

DS22248A-page 10  2010 Microchip Technology Inc.

FIGURE 2-15: IDD vs. Temperature and

 2010 Microchip Technology Inc. DS22248A-page 11

VIN Hi Threshold (V)

0.12 1.6 VDD

VIN Low Threshold (V)

FIGURE 2-20: Gain Error vs. Temperature

DS22248A-page 12  2010 Microchip Technology Inc.

2.5 0.0045 VDD

VOUT_LOW Limit (Y-AVSS)(V)

Output Shorted to VDD

 2010 Microchip Technology Inc. DS22248A-page 13

Time (1 µs/div) Time (1 µs/div)

Time (1 µs/div) Frequency (Hz)

DS22248A-page 14  2010 Microchip Technology Inc.

FIGURE 2-35: Multiplier Mode Bandwidth. FIGURE 2-37: Phase Shift.

Figure 2-35 calculation:

Worst Case Codes (decimal)

FIGURE 2-36: -3 db Bandwidth vs. Worst

 2010 Microchip Technology Inc. DS22248A-page 15

DS22248A-page 16  2010 Microchip Technology Inc.

TABLE 3-1: PIN FUNCTION TABLE

3.8 Exposed Thermal Pad (EP)

 2010 Microchip Technology Inc. DS22248A-page 17

DS22248A-page 18  2010 Microchip Technology Inc.

EQUATION 4-1: ANALOG OUTPUT 4.1 DC Accuracy

Note: See the output swing voltage specification DAC Output

 2010 Microchip Technology Inc. DS22248A-page 19

In addition to resistive load driving capability, the

DS22248A-page 20  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. DS22248A-page 21

DS22248A-page 22  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. DS22248A-page 23

REGISTER 5-1: WRITE COMMAND REGISTER FOR MCP4921 (12-BIT DAC)

REGISTER 5-2: WRITE COMMAND REGISTER FOR MCP4911 (10-BIT DAC)

REGISTER 5-3: WRITE COMMAND REGISTER FOR MCP4901 (8-BIT DAC)

bit 15 0 = Write to DAC register

DS22248A-page 24  2010 Microchip Technology Inc.

config bits 12 data bits

SDI 0 BUF GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

FIGURE 5-1: Write Command for MCP4921 (12-bit DAC).

config bits 12 data bits

5 ";"% ( >