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Cache Optimizations

The document discusses approaches for handling read and write operations in caches. It states that most processors prioritize reads over writes by checking the write buffer on a read miss to see if there is a conflict before allowing the read to continue. If the buffer is empty or there is no conflict, the read proceeds without waiting. This reduces the penalty for read misses.

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Shobha Kumar
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55 views4 pages

Cache Optimizations

The document discusses approaches for handling read and write operations in caches. It states that most processors prioritize reads over writes by checking the write buffer on a read miss to see if there is a conflict before allowing the read to continue. If the buffer is empty or there is no conflict, the read proceeds without waiting. This reduces the penalty for read misses.

Uploaded by

Shobha Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Giving Priority to Read Misses over Writes to Reduce Miss

Penalty
• Serves reads before writes have been completed.
• With write-through cache most important is a write buffer of the
proper size.
• Write buffers, however, do complicate memory access because they
might hold the updated value of a location need on read miss.

• R3-> Write buffer


• R1<- M[1024]-same cache index; read miss
• R2<- M[512], if write not completed, old value.
• Hence, R3 ≠ R2

• The simplest way for this dilemma is for the read miss to wait
until the write buffer is empty.

• The alternative is to check the contents of the write buffer on a


read miss, and if there are no conflicts, and the memory system is
available, let the read miss continue.

• Virtually all the desktop and server processors use the later
approach, giving reads priority over writes.
Reducing hit time

 Avoid address translation during indexing


o The CPU uses virtual addresses that must be mapped to a
physical address.
 
o The cache may either use virtual or physical addresses.
 A cache that indexes by virtual addresses is called
a  virtual cache, as opposed to a  physical cache.
 
o A virtual cache reduces hit time since a translation from a
virtual address to a physical address is not necessary on hits.
 
o Also, address translation can be done in parallel with
cache access, so penalties for misses are reduced as well.
 
o So why doesn't anyone use them ?
 
o Virtual cache difficulties include:
 Protection.
o Page-level protection is checked as part of the virtual to

physical address translation, and it must be enforced no


matter what. One solution is to copy the protection
information from the TLB on a miss, add a field to hold it,
and check it on every access to the virtually addressed
cache.
 Process switches require cache purging
o In virtual caches, different processes share the same
virtual addresses even though they map to different physical
addresses.
 
o When a process is swapped out, the cache must be purged
of all entries to make sure that the new process gets the
correct data.
 One solution:  PID tags
 Increase the width of the cache address tags to
include a process ID (instead of purging the cache.)
 
 The current process PID is specified by a register.
 
 If the PID does not match, it is  not a hit even if the
address matches.
 Aliasing

o Two different virtual addresses may have the same


physical address.
 
o In such a case, it is possible to end up with two copies of
the same block !
 
o Anti-aliasing hardware
o A hardware solution called  anti-aliasing guarantees

every cache block a unique physical address.

 Every virtual address maps to the same location


in the cache.
 
o Page coloring
o This software
technique forces aliases to share some address bits.
 Therefore, the virtual address and physical address
match over these bits.
 
o A  direct-mapped cache that is 2 k bytes (where
k is the number of matching bits) or smaller
can  never have duplicate physical addresses
for blocks.

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