www.Vidyarthiplus.

com

SELVAM COLLEGE OF TECHNOLOGY,NAMAKKAL

DEPARTMENT OF ECE
SUBJECT CODE: EC1203
DIGITAL ELECTRONICS
(FOR THIRD SEMESTER ECE)
TWO MARK QUESTIONS
QUESTIONS-ANSWERS

Unit – 1
Minimization techniques & logic gates
1. Define binary logic?
Binary logic consists of binary variables and logi cal operations. The variables are
designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two
distinct values: 1 and 0. There are three basic logic operations: AND, OR, and NOT.

2. What are the basic digital logic gates?

The three basic logic gates are
• AND gate
• OR gate
• NOT gate

3. What is a Logic gate?

Logic gates are the basic elements that make up a digital system. The electronic gate
is a circuit that is able to operate on a number of binary inputs in order to perform a
particular logical function.

4.. Which gates are called as the universal gates? What are its advantages?
The NAND and NOR gates are called as the universal gates. These gates are used to
perform any type of logic application.

5.. Mention the important characteristics of digital IC’s?

• Fan out
• Power dissipation
• Propagation Delay
• Noise Margin
• Fan In
• Operating temperature
• Power supply requirements
•
6.. Define Fan-out?
Fan out specifies the number of standard loads that the output of the gate can drive
with out impairment of its normal operation.

7.. Define power dissipation?

Power dissipation is measure of powe
power consumed by the gate when fully driven by all
its inputs.

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

8. What is propagation delay?

Propagation delay is the average transition delay time for the signal to propagate from
input to output when the signals change in value. It is expressed in ns.

9. What are the types of TTL logic?

1. Open collector output
2. Totem-Pole Output
3. Tri-state output.

10. Mention the characteristics of MOS transistor?

1. The n- channel MOS conducts when its gate- to- source voltage is positive.
2. The p- channel MOS conducts when its gate- to- source voltage is negative
3. Either type of device is turned of if its gate- to- source voltage is zero.

11. Why totem pole outputs cannot be connected together.

Totem pole outputs cannot be connected together because such a connection
might produce excessive current and may result in damage to the devices.

12.. State advantages and disadvantages of TTL

Adv:
• Easily compatible with other ICs
• Low output impedance
Disadv:
• Wired output capability is possible only with tristate and open collector types
• Special circuits in Circuit layout and sys tem design are required.

Unit – II
Combinational circuits
1. Define combinational logic
When logic gates are connected together to produce a specified output for certain
specified combinations of input variables, with no storage involved, the resulting circuit is
called combinational logic.

2. Explain the design procedure for combinational circuits

• The problem definition
• Determine the number of available input variables & required O/P variables.
• Assigning letter symbols to I/O variables
• Obtain simplified Boolean expression for each O/P.
• Obtain the logic diagram.
•
3. Define Half adder and full adder
The logic circuit that performs the addition of two bits is a half adder. The circuit that
performs the addition of three bits is a full adder.
.

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

4. Define Decoder?
A decoder is a multiple - input multiple output logic circuit that converts coded inputs
into coded outputs where the input and output codes are different.

5. What is binary decoder?

A decoder is a combinational circuit that converts binary information from n input lines
to a maximum of 2n out puts lines.

4. Define Encoder?
An encoder has 2ninput lines and n output lines. In encoder the output lines generate the
binary code corresponding to the input value.

5. What is priority Encoder?

A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest priority
will take precedence.

6. Define multiplexer?
Multiplexer is a digital switch. If allows digitalinformation from several sources to be
routed onto a single output line.

7. What do you mean by comparator

A comparator is a special combinational circuit designed primarily to compare the
relative magnitude of two binary numbers.

Unit 3
Memory Devices
1. List basic types of programmable logic devices.
• . Read only memory
• . Programmable logic Array
• . Programmable Array Logic
•
2. Explain ROM
A read only memory(ROM) is a device that includes both the decoder and the OR
gates within a single IC package. It consists of n input lines and m output lines. Each bit
combination of the input variables is called an address. Each bit combination that comes out
of the output lines is called a word. The number ofdistinct addresses possible with n input
variables is 2n.

3. Define address and word:

In a ROM, each bit combination of the input variable is called on address. Each bit
combination that comes out of the output lines is called a word.

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

4. State the types of ROM

• . Masked ROM.
• . Programmable Read only Memory
• . Erasable Programmable Read only memory.
• . Electrically Erasable Programmable Read only Memory.
•
5. What is programmable logic array? How it differs from ROM?
In some cases the number of don’t care conditions is excessive, it is more economical
to use a second type of LSI component called a PLA.A PLA is similar to a ROM in concept;
however it does not provide full decoding of the variables and does not generates all the
minterms as in the ROM.

6. Explain PROM.
PROM (Programmable Read Only Memory) It allows user to store data or program.
PROMs use the fuses with material like nichrome and polycrystalline. The user can blow these
fuses by passing around 20 to 50 mA of current for the period 5 to 20µs.The blowing of fuses is
called programming of ROM. The PROMs are one time programmable. Once programmed, the
information is stored permanent.

7. Explain EPROM.
EPROM(Erasable Programmable Read Only Memory) EPROM use MOS circuitry. They
store 1’s and 0’s as a packet of charge in a buried layer of the IC chip. We can erase the stored
data in the EPROMs by exposing the chip to ultraviolet light via its quartz window for 15 to 20
minutes. It is not possible to erase selective information. The chip can be reprogrammed.

8. Explain EEPROM.
EEPROM(Electrically Erasable Programmable Read Only Memory) EEPROM also use
MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated
floating gate in the device. EEPROM allows selective erasing at the register level rather
thanerasing all the information since the information can be changed by using electrical signals.

9. What is RAM?
Random Access Memory. Read and write operations can be carried out.

10. What is programmable logic array? How it differs from ROM?

In some cases the number of don’t care conditions is excessive, it is more economical to
use a second type of LSI component called a PLA.A PLA is similar to a ROM in concept;
however it does not provide full decoding of the variables and does not generates all the
minterms as in the ROM.

11.What is mask - programmable?

With a mask programmable PLA, the user must submita PLA program table to the
manufacturer.

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

12. What is field programmable logic array?

The second type of PLA is called a field programmable logic array. The user by means of
certain recommended procedures can programthe EPLA.

13. List the major differences between PLA and PAL

PLA:
Both AND and OR arrays are programmable and Complex .Costlier than PAL
PAL
AND arrays are programmable OR arrays are fixed .Cheaper and Simpler

14. Define PLD.

Programmable Logic Devices consist of a large array of AND gates and OR gates that
can be programmed to achieve specific logic functions.

15. Give the classification of PLDs.

PLDs are classified as PROM(Programmable Read OnlyMemory), Programmable Logic
Array(PLA), Programmable Array Logic (PAL), and Generic Array Logic(GAL)

16. Define PROM.

PROM is Programmable Read Only Memory. It consistsof a set of fixed AND gates
connected to a decoder and a programmable OR array.

17. Define PLA

PLA is Programmable Logic Array(PLA). The PLA is a PLD that consists of a
programmable AND array and a programmable OR array.

18. Define PAL

PAL is Programmable Array Logic. PAL consists of a programmable AND array and a
fixed OR array with output logic.

19. Why was PAL developed ?

It is a PLD that was developed to overcome certain disadvantages of PLA, such as
longer delays due to additional fusible links that result from using two programmable arrays and
more circuit complexity.

20. Why the input variables to a PAL are buffered?

The input variables to a PAL are buffered to prevent loading by the large number of AND
gate inputs to which available or its complement can be connected.

21. What does PAL 10L8 specify ?

PAL - Programmable Logic Array
10 - Ten inputs
L - Active LOW Ouput
8 - Eight Outputs

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

22.Give the comparison between PROM and PLA.

PROM PLA
1. And array is fixed and OR Both AND and OR arrays are array is
programmable. Programmable.
2. Cheaper and simple to use. Costliest and complex than PROMS.

Unit 4
Sequential circuits
1.. What are the classification of sequential circuits?
The sequential circuits are classified on the basis of timing of their signals into two
types. They are,
• Synchronous sequential circuit.
• Asynchronous sequential circuit.
•
2. Define Flip flop.
The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0
until directed by an input signal to change its state.

3.What are the different types of flip-flop?

There are various types of flip flops. Some of them are mentioned below they are,
• RS flip-flop
• SR flip-flop
• D flip-flop
• JK flip-flop
• T flip-flop
4.What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0,
the output is reset.

5. What is the operation of JK flip-flop?

•When K input is low and J input is high the Q output of flip-flop is set.
•When K input is high and J input is low the Q output of flip-flop is reset.
•When both the inputs K and J are low the output does not change
•When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output
toggle on the next positive clock edge.

6. What is the operation of T flip-flop?

T flip-flop is also known as Toggle flip-flop.
•When T=0 there is no change in the output.
•When T=1 the output switch to the complement state (ie) the output toggles.

7. Define race around condition.

In JK flip-flop output is fed back to the input. Therefore change in the output results
change in the input. Due to this in the positive half of the clock pulse if both J and K are high
then output toggles continuously. This condition iscalled ‘race around condition’.

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

8. What is edge-triggered flip-flop?

The problem of race around condition can solved byedge triggering flip flop. The term
edge triggering means that the flip-flop changes state either at the positive edge or negative edge
of the clock pulse and it is sensitive to its inputs only at this transition of the clock.

9. What is a master-slave flip-flop?

A master-slave flip-flop consists of two flip-flops where one circuit serves as a master
and the other as a slave.

10.Define rise time.

The time required to change the voltage level from 10% to 90% is known as rise time(tr).

11.Define fall time.

The time required to change the voltage level from90% to 10% is known as fall time(tf).

12.Define skew and clock skew.

The phase shift between the rectangular clock wave forms is referred to as skew and the
time delay between the two clock pulses is called clock skew.

13.Define setup time.

The setup time is the minimum time required to maintain a constant voltage levels at the
excitation inputs of the flip-flop device prior to the triggering edge of the clock pulse in order
for the levels to be reliably clocked into th e flip flop. It is denoted as tsetup.

14. Define hold time.

The hold time is the minimum time for which the voltage levels at the excitation inputs
must remain constant after the triggering edge of the clock pulse in order for the levels to be
reliably clocked into the flip flop. It is denoted as thold .

15. Define propagation delay.

A propagation delay is the time required to change the output after the application of the
input.

16.Define registers.
A register is a group of flip-flops flip-flop can store one bit information. So an n-bit
register has a group of n flip-flops and is capable of storing any binary information/number
containing n-bits.

17.Define shift registers.

The binary information in a register can be moved from stage to stage within the register
or into or out of the register upon application of clock pulses. This type of bit movement or
shifting is essential for certain arithmetic and logic operations used in microprocessors. This
gives rise to group of registers called shift registers.

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

18.What are the different types of shift type?

There are five types. They are,
• Serial In Serial Out Shift Register
• Serial In Parallel Out Shift Register
• Parallel In Serial Out Shift Register
• Parallel In Parallel Out Shift Register
• Bidirectional Shift Register

19. Define sequential circuit?

In sequential circuits the output variables dependent not only on the present input
variables but they also depend up on the past history of these input variables.

20. What do you mean by present state?

The information stored in the memory elements at any given time define.s the present
state of the sequential circuit.

21. What do you mean by next state?

The present state and the external inputs determine the outputs and the next state of
the sequential circuit.

22. State the types of sequential circuits?

1. Synchronous sequential circuits
2. Asynchronous sequential circuits

23. Define synchronous sequential circuit

In synchronous sequential circuits, signals can affect the memory elements only at
discrete instant of time.

Unit 5
Asynchronous & synchronous sequential circuits

1. Define Asynchronous sequential circuit?

In asynchronous sequential circuits change in input signals can affect memory element at any
instant of time.

2.What is race around condition?

In the JK latch, the output is feedback to the input, and therefore changes in the output
results change in the input. Due to this in the positive half of the clock pulse if J and K are both
high then output toggles continuously. This condition is known as race around condition.

3.The t pd for each flip-flop is 50 ns. Determine the maximum operating frequency for
MOD - 32 ripple counter
f max (ripple) = 5 x 50 ns = 4 MHZ

4. What are secondary variables?

Present state variables in asynchronous sequential circuits

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

5.What are excitation variables?

Next state variables in asynchronous sequential circuits

6. What is fundamental mode sequential circuit?

• -input variables changes if the circuit is stable
• -inputs are levels, not pulses
• -only one input can change at a given time

7. What are pulse mode circuit?

• -inputs are pulses
• -width of pulses are long for circuit to respond to the input
• -pulse width must not be so long that it is still present after the new state is reached

8. What are the significance of state assignment?

In synchronous circuits-state assignments are madewith the objective of circuit reduction
Asynchronous circuits-its objective is to avoid critical races

9. When do race condition occur?

Two or more binary state variables change their value in response to the change in i/p
variable

10.What is non critical race?

• -final stable state does not depend on the order in which the state variable changes
• -race condition is not harmful

11.What is critical race?

• -final stable state depends on the order in which the state variable changes
• -race condition is harmful

12. When does a cycle occur?

Asynchronous circuit makes a transition through aseries of unstable state

13.What are the different techniques used in state assignment?

• -shared row state assignment
• -one hot state assignment
•
14.What are the steps for the design of asynchronous sequential circuit?
• -construction of primitive flow table
• -reduction of flow table
• -state assignment is made
• -realization of primitive flow table

15.What is hazard?
Unwanted switching transients is Called hazards

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

16.What is static 1 hazard?

Output goes momentarily 0 when it should remain at 1

17.What is static 0 hazard?

Output goes momentarily 1 when it should remain a t 0

18. What is dynamic hazard?

Output changes 3 or more times when it changes from 1 to 0 or 0 to 1

19.What is the cause for essential hazards?

Unequal delays along 2 or more path from same input

20.What is flow table and primitive flow chart ?

State table of an synchronous sequential network . primitive flow chart is one stable state
per row
.
21.Define merger graph.
The merger graph is defined as follows. It contains the same number of vertices as the
state table contains states. A line drawn between the two state vertices indicates each compatible
state pair. It two states are incompatible no connecting line is drawn.

22.Define closed covering

A Set of compatibles is said to be closed if, for every compatible contained in the set, all its
implied compatibles are also contained in the set. A closed set of compatibles, which contains all
the states of M, is called a closed covering.

23.Define state table.

For the design of sequential counters we have to relate present states and next states. The
table, which represents the relationship between present states and next states, is called state
table.

24. Define total state

The combination of level signals that appear at the inputs and the outputs of the delays define
what is called the total state of the circuit.

25.What are the steps for the design of asynchronous sequential circuit?
1. Construction of a primitive flow table from theproblem statement.
2. Primitive flow table is reduced by eliminating redundant states using the state
reduction
3. State assignment is made
4. The primitive flow table is realized using appropriate logic elements.

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

26. Define primitive flow table :

It is defined as a flow table which has exactly one stable state for each row in the table.
The design process begins with the construction of primitive flow table.

27.What are the types of asynchronous circuits ?

1. Fundamental mode circuits
2. Pulse mode circuits
28.Give the comparison between state Assignment Synchronous circuit and state
assignment
asynchronous circuit.
In synchronous circuit, the state assignments are made with the objective of circuit
reduction. In asynchronous circuits, the objective of state assignment is to avoid critical races.

29.What are races?

When 2 or more binary state variables change their value in response to a change in an
input variable, race condition occurs in an asynchronous sequential circuit. In case of unequal
delays, a race condition may cause the state variables to change in an unpredictable manner.

30.Define non critical race.

If the final stable state that the circuit reachesdoes not depend on the order in which the
state variable changes, the race condition is not harmful and it is called a non critical race.

31.Define critical race?

If the final stable state depends on the order in which the state variable changes, the race
condition is harmful and it is called a critical race.

32.What is a cycle?
A cycle occurs when an asynchronous circuit makes a transition through a series of
unstable states. If a cycle does not contain a stable state, the circuit will go from one unstable to
stable to another, until the inputs are changed.

33.Write a short note on fundamental mode asynchronous circuit.

Fundamental mode circuit assumes that. The input variables change only when the circuit
is stable. Only one input variable can change at a given time and inputs are levels and not pulses.

34. Write a short note on pulse mode circuit.

Pulse mode circuit assumes that the input variables are pulses instead of level. The width
of the pulses is long enough for the circuit to respond to the input and the pulse width must not
be so long that it is still present after the new state is reached.

35.Define secondary variables

The delay elements provide a short term memory forthe sequential circuit. The present
state and next state variables in asynchronous sequential circuits are called secondary variables.

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

36. Define flow table in asynchronous sequential circuit.

In asynchronous sequential circuit state table is known as flow table because of the
behaviour of the asynchronous sequential circuit. The stage changes occur in independent of a
clock, based on the logic propagation delay, and cause the states to .flow. from one to another.

.
37.What is fundamental mode.
A transition from one stable state to another occurs only in response to a change in the
input state. After a change in one input has occurred, no other change in any input occurs until
the circuit enters a stable state. Such a mode of operation is referred to as a fundamental mode.

38. Write short note on shared row state assignment.

Races can be avoided by making a proper binary assignment to the state variables. Here,
the state variables are assigned with binary numbers in such a way that only one state variable
can change at any one state variable can change at any one time when a state transition occurs.
To accomplish this, it is necessary that states between which transitions occur be given adjacent
assignments. Two binary aresaid to be adjacent if they differ in only one variable.

39. Write short note on one hot state assignment.

The one hot state assignment is another method for finding a race free state assignment.
In this method, only one variable is active or hot for each row in the original flow table, ie, it
requires one state variable for each row of the flow table. Additional row are introduced to
provide single variable changes between internal state transitions.

PREPARED BY APPROVED BY
Ms.D.Praba Mr.M.Mathivanan
(Lect/ECE) (HOD/ECE)

www.Vidyarthiplus.com