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Assignment - 2 LST

This document contains an assignment submitted by a student for the course "Logic & Switching Theory". The assignment contains 10 sets of logic circuit design and analysis questions. For each question, it lists the description, marks allotted, cognitive level, and which course and program outcomes the question maps to. The student has provided their details at the top including name, date of submission, class, semester, academic year, and set numbers for the questions.

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Nagarjun Reddy
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0% found this document useful (0 votes)
82 views6 pages

Assignment - 2 LST

This document contains an assignment submitted by a student for the course "Logic & Switching Theory". The assignment contains 10 sets of logic circuit design and analysis questions. For each question, it lists the description, marks allotted, cognitive level, and which course and program outcomes the question maps to. The student has provided their details at the top including name, date of submission, class, semester, academic year, and set numbers for the questions.

Uploaded by

Nagarjun Reddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VASAVI COLLEGE OF ENGINEERING (AUTONOMOUS)

IBRAHIMBAGH, HYDERABAD-31
Department of Computer Science and Engineering
Name of the Course: Logic & Switching Theory
Assignment -2

Name of the Faculty: S.Swetha Date of submission: 28/10/2020


Class: BE- 2/4 – CSE-C Time: 7:00PM
Sem: 3rd sem
Academic Year: 2020-2021
Set-1(1602-19-733-122 to 127)
Q. No. Description of the question Marks BTL Mapped
(1/2/3/4/5/6) CO PO
1. Fine the Boolean Expression from the following Prime
Implicant Chart and draw the logic circuit for the
expression
2 3 2 1,2,3

2. Convert the following circuit to NAND- AND gate circuit


by following the procedure: 1 3 2
1,2,3

3. Find a circuit of AND and OR gates to realize


f (a, b, c, d) = Σ m(1, 5, 6, 10, 13, 14)
2 3 2 1,2,3

Set-2 (1602-19-733-128 to 133)


Q. No. Description of the question Marks BTL Mapped
(1/2/3/4/5/6) CO PO
1. Convert the following circuit to NOR-NOR gate by
following the steps:

2 3 1 1,2,3
2. Simplify the following Boolean function F, together with 2 3 1 1,2,3
don’t care conditions d, and then express the simplified
function in sum- of- minterms form using Quine
McCluskey Tabular Method:
F(A,B,C,D)= Σ(4,5,6,7,12,13,14)) + d (1,9,11,15)

3. Implement the following function using two-level NOR


1 3 1 1,2,3
gate circuit F(x,y,z) = [(x+y)(x’+z)]’

Set-3 (1602-19-733-134 to 139)


Q.No. Description of the question Marks BTL Mapped
(1/2/3/4/5/6) CO PO
1. The prime implicants of f (a, b, c, d ) = Σm(4, 5, 6, 7,
12, 13, 14, 15) are to be found using the Quine- 1 3 2 1,2,3
McCluskey method. Column III is given; find Column
IV and check off the appropriate terms in Column III.

Check your answer using Karnaugh map

2. Simplify the following Boolean function F, express the


simplified function in product- of- maxterms form using 2 3 2 1,2,3
Quine McCluskey Tabular Method:

F(A,B,C,D)= π (1,3,5,7,12,13,14,15)

3. Implement f(a, b, c, d) = Σ m(3, 4, 5, 6, 7, 11, 15) as a


two-level gate circuit, using a minimum number of
gates.
(a) Use AND-OR gates 2 3 2 1,2,3
(b) Convert it into NAND gates.
Set- 4 (1602-19-733-140 to 145)
Q.No. Description of the question Marks BTL Mapped
(1/2/3/4/5/6) CO PO
1. Find a minimum two-level, multiple-output AND-OR
gate circuit to realize these functions (eight gates 2 3 2 1,2,3
minimum).
f3 (a, b, c, d) =Σ m(4, 11, 13, 14, 15) +d(5, 9, 12)
f2 (a, b, c, d) = Σ m(0, 4, 8, 9) + d(1, 10, 12)
f1 (a, b, c, d) = Σ m(10, 11, 12, 15) + d(4, 8, 14)
2. Simplify the following Boolean function F and then express
the simplified function in sum- of- minterms form using 2 3 2 1,2,3
Quine McCluskey Tabular Method
F (x,y,z) =Σ m(0, 1, 2, 5, 6, 7)
3. Convert the following multilevel circuit into NOR gate
multilevel circuit 1 3 2 1,2,3

Set- 5 (1602-19-733-146 to 151)

Q.No. Description of the question Marks BTL Mapped


(1/2/3/4/5/6) CO PO
1. Implement the following Boolean function F, using the two-
level forms of logic : 2 3 2 1,2,3
(a) NAND-NAND (b) OR-NAND
F(A,B,C,D)= Σ(0,4,8,9,10,11,12,14)
2. Find the Boolean expressions using multiple Output
realization and draw the multiple output combinational 2 3 2 1,2,3
circuit for the obtained f1,f2,f3 expression:
3. Find all the prime implicants for the following Boolean
function and determine which are essential using Tabular 1 3 2 1,2,3
Method:
F(w,x,y,z)= Σ(0,2,4,5,6,7,8,10,13,15)

Set- 6 (1602-19-733-152 to 157)


Q.No. Description of the question Marks BTL Mapped
(1/2/3/4/5/6) CO PO
1. Convert the following circuit to NOR gate circuit by
following the procedure: 1 3 2 1,2,3

2. Using the truth table check the inequality with respect to


XOR and XNOR for the following Boolean Functions:
2 3 2 1,2,3
a) (A ⊙ B ⊙ C)’ = A ⊙ B ⊕ C
b) A ⊕ B ⊕ C ⊕ D = (A ⊕ B ⊙ C ⊕ D)’

3. Apply Quine-McCluskey method and find all 2 3 2 1,2,3


minimum sum-of-products expressions for
f(A, B, C, D, E)=Σ m(0, 1, 2, 3, 4, 8, 9, 10, 11, 19, 21,
22, 23, 27, 28, 29, 30)
Set- 7 (1602-19-733-158 to 163)
Q.No. Description of the question Marks BTL Mapped
(1/2/3/4/5/6) CO PO
1. Using the truth table check the inequality with respect to 2 3 2 1,2,3
XOR and XNOR for the following Boolean Functions:
a) (A ⊕ B ⊕ C)’ = A ⊕ B ⊙ C
b) A ⊙ B ⊕ C = A ⊕ B ⊙ C

2. Covert the following multi-level circuit into NAND gate


circuit 1 3 2 1,2,3
3. Simplify the following Boolean function F, together with
don’t care conditions d, and then express the simplified 2 3 2 1,2,3
function in sum- of- minterms form using Quine
McCluskey Tabular Method:
F(A,B,C,D)= Σ(0,6,8,13,14) + Σd (2,4,10)

Set- 8 (1602-19-733-164 to 169)


Q.No. Description of the question Marks BTL Mapped
(1/2/3/4/5/6) CO PO
1. Simplify the following Boolean function F, together with
don’t care conditions d, and then express the simplified 2 3 2 1,2,3
function in sum- of- minterms form using Quine McCluskey
Tabular Method:
F(A,B,C,D)= Σ(1,3,8,10,15) + Σd (0,2,9)

2. Draw the multi-level NAND gate circuits for the following


Boolean Expression: 2 3 2 1,2,3
(AB’ + CD’)E + BC’ (A + B)
3. Convert the following circuit to NOR-OR gate circuit by
following the procedure: 1 3 2 1,2,3

Set- 9 (1602-19-733-170 to 175)


Q.No. Description of the question Marks BTL Mapped
(1/2/3/4/5/6) CO PO
1. Convert the following Multiple Output Boolean function
circuit to NAND gate circuit
2 3 2 1,2,3
2. Using the truth table check the inequality with respect to
XOR and XNOR for the following Boolean Functions: 2 3 2 1,2,3
A ⊕ B ⊕ C ⊕ D = (A ⊕ B ⊙ C ⊕ D)’
3. Find expressions which correspond to a two-level,
minimum multiple output AND-OR realization of F1, 1 3 2 1,2,3
F2, and F3 and convert into NAND network

Set- 10 (1602-19-733-176 to 182)


Q.No. Description of the question Marks BTL Mapped
(1/2/3/4/5/6) CO PO
1. Simplify the following functions, and implement them with 1 3 2 1,2,3
two- level NOR gate circuits:
F=wx’+y’z’+w’yz’
2. Using the truth table check the inequality with respect to
XOR and XNOR for the following Boolean Functions:
2 3 2 1,2,3
A ⊕ B ⊕ C ⊕ D = (A ⊙ B ⊙ C ⊙ D)’

3. Convert the following multi-level AND-OR circuit to


NAND gate circuit by following the procedure 2 3 2 1,2,3

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