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    Faculty of Engineering: Electrical and Electronic Engineering Department

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    Endalk
    The document is the final exam for an Introduction to Logic Design/Digital Logic Design I course. It contains 5 questions testing various logic design concepts. Students are asked to simplify logic functions using NAND/NOR gates, implement a full adder circuit using a decoder and multiplexers, analyze a sequential circuit to derive its state table and diagram, design a sequential circuit from a given state diagram, and design a down counter circuit using T-flip flops. The exam is 120 minutes long and covers topics relevant to introductory digital logic design.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Faculty of Engineering: Electrical and Electronic Engineering Department

    Uploaded by

    Endalk
    92 views10 pages
    The document is the final exam for an Introduction to Logic Design/Digital Logic Design I course. It contains 5 questions testing various logic design concepts. Students are asked to simplify logic functions using NAND/NOR gates, implement a full adder circuit using a decoder and multiplexers, analyze a sequential circuit to derive its state table and diagram, design a sequential circuit from a given state diagram, and design a down counter circuit using T-flip flops. The exam is 120 minutes long and covers topics relevant to introductory digital logic design.

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    F11-12-EENG115-FN-S

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    The document is the final exam for an Introduction to Logic Design/Digital Logic Design I course. It contains 5 questions testing various logic design concepts. Students are asked to simplify logic functions using NAND/NOR gates, implement a full adder circuit using a decoder and multiplexers, analyze a sequential circuit to derive its state table and diagram, design a sequential circuit from a given state diagram, and design a down counter circuit using T-flip flops. The exam is 120 minutes long and covers topics relevant to introductory digital logic design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    92 views10 pages

    Faculty of Engineering: Electrical and Electronic Engineering Department

    Uploaded by

    Endalk
    The document is the final exam for an Introduction to Logic Design/Digital Logic Design I course. It contains 5 questions testing various logic design concepts. Students are asked to simplify logic functions using NAND/NOR gates, implement a full adder circuit using a decoder and multiplexers, analyze a sequential circuit to derive its state table and diagram, design a sequential circuit from a given state diagram, and design a down counter circuit using T-flip flops. The exam is 120 minutes long and covers topics relevant to introductory digital logic design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 10

    Faculty of Engineering

    ELECTRICAL AND ELECTRONIC ENGINEERING DEPARTMENT


    EENG115/INFE115 Introduction to Logic Design
    EENG211/INFE211 Digital Logic Design I

    Fall 2011-12

    Instructors:
    M. K. Uyguroğlu
    H. Demirel

    Final EXAMINATION

    Jan. 10, 2012

    Duration : 120 minutes

    Number of Problems: 5

    Good Luck

    STUDENT’S
    NUMBER
    NAME SOLUTIONS
    SURNAME
    GROUP NO

    Problem Achieved Maximum


    1 20
    2 20
    3 20
    4 20
    5 20
    TOTAL 100
    Introduction to Logic Design/ Digital Logic Design I - Final Examination

    Question 1 (20 points)


    a) Simplify the following function and implement it by using two-level NAND gates.
    (10 pts)

    F(A,B,C,D) = A’B’C +AC’ +ACD + ACD’ + A’B’D’

    B’C

    B’D’
    A

    F(A,B,C,D) = A + B’C + B’D’

    M. K. Uyguroğlu, H. Demirel Jan. 10, 2012


    Introduction to Logic Design/ Digital Logic Design I - Final Examination

    b) Simplify the following function and implement it by using two-level NOR gates. (10 pts)

    F(A,B,C,D) = ( A  B) ( AC   BC )   A' B' AB ( AC   BC )  ABC ' ABC

    A’

    B’

    F’(A,B,C,D)=A’ +B’
    F(A,B,C,D)=(A’ + B’)’

    M. K. Uyguroğlu, H. Demirel Jan. 10, 2012


    Introduction to Logic Design/ Digital Logic Design I - Final Examination

    Question 2 (20points):
    Implement a full adder circuit by using:
    a) 3 – to - 8 line Decoder (10 pts)
    b) 4 X 1 Multiplexers. (10 pts)

    x y z C S
    0 0 0 0 0
    0 0 1 0 1
    0 1 0 0 1
    0 1 1 1 0
    1 0 0 0 1
    1 0 1 1 0
    1 1 0 1 0
    1 1 1 1 1

    x y z C
    0 0 0 0
    0 0 1 0 I0=0
    0 1 0 0
    I1=z
    0 1 1 1
    1 0 0 0
    I2=z
    1 0 1 1
    1 1 0 1
    I3=1
    1 1 1 1

    M. K. Uyguroğlu, H. Demirel Jan. 10, 2012


    Introduction to Logic Design/ Digital Logic Design I - Final Examination

    x y z S
    0 0 0 0
    0 0 1 1 I0=z
    0 1 0 1
    I1=z’
    0 1 1 0
    1 0 0 1 I2=z’
    1 0 1 0
    1 1 0 0 I3=z
    1 1 1 1

    Question 3 (20 points):


    Analyze the following circuit to derive the state table and the state diagram of the
    sequential circuit shown below.
    x’B’
    x
    J A

    CLK
    x
    K

    Ax’
    J B

    CLK

    x K

    Clock

    JA= x’B’
    KA=x
    JB=Ax’
    KB=x

    M. K. Uyguroğlu, H. Demirel Jan. 10, 2012


    Introduction to Logic Design/ Digital Logic Design I - Final Examination

    Present State Input Next State Flip-flop inputs


    A B x A B JA KA JB KB
    0 0 0 0 0 0 0 0 0
    0 0 1 1 1 1 1 1 1
    0 1 0 1 1 1 0 0 0
    0 1 1 0 0 0 1 1 1
    1 0 0 1 0 0 0 0 0
    1 0 1 0 0 1 1 0 1
    1 1 0 1 1 1 0 0 0
    1 1 1 0 0 0 1 0 1

    Question 4 (20 points):

    Assume that the following state diagram is provided.

    0/0 1/0

    0/1
    a) Starting from state 00 determine state transitions and
    00 10
    output sequence that will be generated when an input
    sequence of 01011011011110 is applied. (5 pts)
    b) Design a sequential circuit using D flip fops. (15 pts)
    1/0 0/1 1/0
    0/1

    01 11
    1/0

    M. K. Uyguroğlu, H. Demirel Jan. 10, 2012


    Introduction to Logic Design/ Digital Logic Design I - Final Examination

    a)

    State 00 00 01 00 01 11 00 01 11 00 01 11 10 10 00
    Input 0 1 0 1 1 0 1 1 0 1 1 1 1 0
    Output 0 0 1 0 0 1 0 0 1 0 0 0 0 1

    b)
    Present State Input Next State Output Flip-flop Inputs
    A B x A B y DA DB
    0 0 0 0 0 0 0 0
    0 0 1 0 1 0 0 1
    0 1 0 0 0 1 0 0
    0 1 1 1 1 0 1 1
    1 0 0 0 0 1 0 0
    1 0 1 1 0 0 1 0
    1 1 0 0 0 1 0 0
    1 1 1 1 0 0 1 0

    DB = A’x
    DA = Ax + Bx = (A + B) x y = Bx’+Ax’= (A + B)x’

    M. K. Uyguroğlu, H. Demirel Jan. 10, 2012


    Introduction to Logic Design/ Digital Logic Design I - Final Examination

    M. K. Uyguroğlu, H. Demirel Jan. 10, 2012


    Introduction to Logic Design/ Digital Logic Design I - Final Examination

    Question 5 (20 points):

    Design a counter which counts down, with the repeated sequence: 2, 1, 0, when the input to the
    counter circuit is 1. The counter doesn’t count (stays at the same state) when the input is 0. The
    circuit is to be designed by treating the unused states as don’t care conditions. Analyze the circuit
    obtained from the design to determine the effect of the unused states. Use T flip flops in your
    design.

    Present State Input Next State Flip-flop Inputs


    A B x A B TA TB
    0 0 0 0 0 0 0
    0 0 1 1 0 1 0
    0 1 0 0 1 0 0
    0 1 1 0 0 0 1
    1 0 0 1 0 0 0
    1 0 1 0 1 1 1
    1 1 0 x x
    1 1 1 x x

    TA=B’x TB=Ax+Bx=(A+B)x

    Analysis for unused state:


    Present State Input Next State Flip-flop inputs
    A B x A B TA TB
    1 1 0 1 1 0 0
    1 1 1 1 0 0 1

    M. K. Uyguroğlu, H. Demirel Jan. 10, 2012


    Introduction to Logic Design/ Digital Logic Design I - Final Examination

    M. K. Uyguroğlu, H. Demirel Jan. 10, 2012

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