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M.Tech. Degree Examination Embedded Systems: (EPRES 233)

This document is the examination for the second semester M.Tech. Degree in Embedded Systems for the course Digital System Design. It contains 5 units, each with 2 questions worth 12 marks. The document instructs students to choose one question from each unit and answer all parts of the chosen question in one place. It provides examples of questions that may be asked, such as writing Verilog codes for multiplexers, decoders, counters, games, and other digital circuits. It also provides questions about concepts like finite state machines, VHDL vs. Verilog comparisons, and hardware bus models.

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Naresh Kumar
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88 views2 pages

M.Tech. Degree Examination Embedded Systems: (EPRES 233)

This document is the examination for the second semester M.Tech. Degree in Embedded Systems for the course Digital System Design. It contains 5 units, each with 2 questions worth 12 marks. The document instructs students to choose one question from each unit and answer all parts of the chosen question in one place. It provides examples of questions that may be asked, such as writing Verilog codes for multiplexers, decoders, counters, games, and other digital circuits. It also provides questions about concepts like finite state machines, VHDL vs. Verilog comparisons, and hardware bus models.

Uploaded by

Naresh Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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[April-14]

[EPRES 233]
M.Tech. Degree Examination
Embedded Systems
II SEMESTER
DIGITAL SYSTEM DESIGN
(Effective from the admitted batch 2012–13)
Time: 3 Hours Max.Marks: 60
----------------------------------------------------------------------------------------------------
Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
----------------------------------------------------------------------------------------------------
UNIT-I
1. a) Write a verilog HDL code for 2x1 MUX
b) What is the difference between the following lines of code?
• reg 1 ⇐ # 10 reg 2;
• reg 3 ⇐ # 10 reg 4;
c) What is the difference between = = = and == ? 12
OR
2. Write a verilogy HDL code for 4 × 16 decoder & write the test
bench for it, with a neat wave form 12
UNIT-II
3. a) Explain J-K flip-flop with verilog program 6
b) Write a note on Gate primitives 6
OR
4. a) Write the comparison between VHDL & Verilogy HDL 6
b) Write a VHDL code for up-down counter with test bench
wave forms 6
UNIT-III
5. Write a VHDL code for DICE game with a test bench & draw the
U U

waveform 12
OR
6. a) Explain the following
i) Operations and Assignments
ii) Functional Bifurcation 6
b) Write the differences between blocking and non blocking
assignments 6
UNIT-IV
7. a) How does the ASM chart differ from a Software flow chart 6
b) Draw & explain SM-chart for PEPSI WENDING MACHINE
U U U U U U

6
OR
8. a) What are the differences between melay & muore state machine 6
b) Explain the modeling of a MEALY SFM with suitable example 6
UNIT-V
9. a) Explain about UART Design 6
b) Write verilog code for UART 6
OR
10. a) Write notes on Altera CPLDs 6
b) Explain simplified 486 bus models 6

[15/II S/214]

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