Hardware Design Guidelines: Espressif Systems
Hardware Design Guidelines: Espressif Systems
Version 2.6
Espressif Systems
Copyright © 2019
www.espressif.com
About This Guide
This document provides product information of ESP8266EX series, including ESP8266EX
chip, ESP-LAUNCHER development board and ESP8266EX modules.
Release Notes
2016.01 V1.4 Update Section 1.5.2, Section 1.5.3 and Section 1.6.
Certification
Download certificates for Espressif products from https://www.espressif.com/en/
certificates.
Table of Contents
1. ESP8266EX ............................................................................................................................1
1.1. Overview ....................................................................................................................................1
1.4.5. RF ...............................................................................................................................10
2. ESP-LAUNCHER .................................................................................................................. 23
2.1. Overview ..................................................................................................................................23
1. ESP8266EX
1.1. Overview
Espressif’s ESP8266EX delivers a highly integrated Wi-Fi SoC solution to meet the
continuous demand for efficient power usage, compact design and reliable performance in
the industry.
With its complete and self-contained Wi-Fi networking capabilities, ESP8266EX can
perform either as a standalone application, or as a slave to a host MCU. When ESP8266EX
hosts an application, it promptly boots up from the external flash. The integrated high-
speed cache optimizes the system's performance and memory.
Also, ESP8266EX can be applied to any micro-controller design as a Wi-Fi adaptor through
SPI/SDIO or I2C/UART interfaces.
Besides the Wi-Fi functionalities, ESP8266EX also integrates an enhanced version of
Tensilica’s L106 Diamond series 32-bit processor and on-chip SRAM. It can be interfaced
with external sensors and other devices through the GPIOs, resulting in low development
cost at early stage and minimum footprint. Software Development Kit (SDK) provides
sample codes for various applications.
ESP8266EX integrates antenna switches, RF balun, power amplifier, low-noise receive
amplifier, filters and power management modules. The compact design minimizes the PCB
size and the external circuitry.
ESP8266EX enables sophisticated features, such as:
• Fast switching between sleep and wake-up modes for efficient energy use;
• Spur cancellation;
• Radio co-existence mechanisms for common cellular, Bluetooth, DDR, LVDS, LCD
interference mitigation.
Figure 1-1 shows the functional blocks of ESP8266EX.
RF balun
GPIO
Switch
Digital baseband
I2C
CPU
RF Analog I2S
transmit transmit
SDIO
Sequencers
PWM
ADC
Accelerator
PLL VCO 1/2 PLL
SPI
"
Figure 1-1. ESP8266EX Block Diagram
1.2. Specifications
Table 1-1. ESP8266EX Specifications
Standard FCC/CE/TELEC/SRRC
802.11 b: + 20 dBm
Security WPA/WPA2
Encryption WEP/TKIP/AES
"
RF antenna interface
2 LNA I/O Chip output impedance = 39 + j6 Ω. It is suggested that users
retain the π-type matching network which matches the antenna.
5 VDD_RTC P NC (1.1 V)
18 SDIO_DATA_2 I/O Connects to SD_D2 (Series R: 200 Ω); SPIHD; HSPIHD; GPIO 9
19 SDIO_DATA_3 I/O Connects to SD_D3 (Series R: 200 Ω); SPIWP; HSPIWP; GPIO 10
📖 Note:
GPIO2, GPIO0, and MTDO are configurable on PCB as the 3-bit strapping register that determines the
booting mode and the SDIO timing mode.
GND GND
3
U1
C1 C2
GND
GND XOUT
6.8pF 6.8pF
VDD33
XIN
GND
C6 C8
2
1uF 1uF(NC)
R1 GND
26MHz±10ppm
12K±1%
GND GND
VDD33 RST
L3 4.3nH
UTXDA R2 499R UTXD
GND URXD
C5 C3 C7
33
32
31
30
29
28
27
26
25
10uF 0.1uF TBD(NC)
GND
EXT_RSTB
VDDA
VDDD
RES12K
XTAL_IN
XTAL_OUT
U0TXD
U0RXD
VDD33
8
ANT1 1 24 GPIO5
VCC
1 WIFI_ANT C4 2.2nH 2 VDDA GPIO5 23 SDI/SD1 SCS/CMD 1 5 SDI/SD1
2 3 LNA SD_DATA_1 22 SDO/SD0 /CS DI
4 VDD3P3 SD_DATA_0 21 R3 200R SCK/CLK SCK/CLK 6 2 SDO/SD0
5 VDD3P3 SD_CLK 20 SCS/CMD CLK DO
L1 L2 VDD_RTC SD_CMD
6 19 SWP/SD3 SHD/SD2 7 3 SWP/SD3
GND
2.4pF 3.0pF 7 TOUT SD_DATA_3 18 SHD/SD2 /HOLD /WP
8 CHIP_EN SD_DATA_2 17
GND XPD_DCDC VDDPST FLASH U3
4
GND GND
VDDPST
GPIO2
GPIO0
GPIO4
MTMS
MTDO
TOUT
MTCK
CH_PU MTDI GND
GPIO16
ESP8266EX U2
9
10
11
12
13
14
15
16
VDD33
GPIO14
GPIO12
GPIO13
GPIO15
GPIO2
GPIO0
GPIO4
"
• Flash
• Crystal oscillator
• RF
• External resistor
• UART
CHIP_EN SD_DATA_2 17
XPD_DCDC VDDPST
VDDPST
GPIO2
GPIO0
GPIO4
MTMS
MTDO
MTCK
MTDI
ESP8266EX U2
9
10
11
12
13
14
15
16
VDD33
"
Figure 1-4. ESP8266EX Digital Power Supply Pins
GND
C6 C8
1uF 1uF(NC)
R1
12K±1%
GND GND
VDD33
L3 4.3nH
GND
C5 C3 C7
33
32
31
30
29
10uF 0.1uF TBD(NC) 28
GND
RES12K
EXT_RSTB
VDDA
VDDD
XTAL_IN
ANT1 1
1 WIFI_ANT C4 2.2nH 2 VDDA
2 3 LNA
4 VDD3P3
5 VDD3P3
L1 L2 VDD_RTC
"
📖 Note:
• ESP8266EX’s EMC is in conformity with FCC and CE requirements. There is no need to add ferrite
beads in the analog power-supply circuit.
• When using a single power supply, the recommended output current is 500 mA.
⚠ Notice:
If CHIP_EN is driven by a power management chip, then the power management chip controls the
ESP8266EX power state. When the power management chip turns on/off Wi-Fi through the high/low level on
GPIO, a pulse current may be generated. To avoid level instability on CHIP_EN, an RC delay (R=10 kΩ,
C=100 nF) circuit is required.
1.4.2.2. Reset
Pin32 EXT_RSTB serves as the reset pin of ESP8266EX. This pin contains an internal pull-
up resistor and is active low. To avoid resets caused by external interference, we
recommend that you keep the PCB trace of EXT_RSTB as short as possible, and add an
RC circuit at the EXT_RSTB pin.
Pin7 CHIP_EN serves as the enable pin of ESP8266EX. In this case, ESP8266EX powers
off when this pin is held low. Pin7 CHIP_EN also serves as the reset pin of ESP8266EX. In
this case, ESP8266EX reboots when the input level of this pin is below 0.6 V and lasts for
at least 200 μs.
We recommend that you use CHIP_EN, instead of EXT_RSTB, to reset the chip.
⚠ Notice:
1.4.3. Flash
The demo flash used on ESP8266EX is an SPI Flash with 2-MB ROM in an SOP8 (208 mil)
package. Pin21 SD_CLK is connected to the flash CLK pin together with a 0402 resistor in
serial connection, which reduces the drive current and eliminates external interruption. The
initial resistance of the resistor is 200 Ω.
VDD33
8
24 GPIO5
VCC
GPIO5 23 SDI/SD1 SCS/CMD 1 5 SDI/SD1
SD_DATA_1 22 SDO/SD0 /CS DI
SD_DATA_0 21 R3 200R SCK/CLK SCK/CLK 6 2 SDO/SD0
SD_CLK 20 SCS/CMD CLK DO
SD_CMD 19 SWP/SD3 SHD/SD2 7 3 SWP/SD3
GND
SD_DATA_3 18 SHD/SD2 /HOLD /WP
SD_DATA_2 17
VDDPST FLASH U3
4
GND
U2
"
Figure 1-6. ESP8266EX Flash
29
VDDD 28 GND
XTAL_IN 27
C1
XTAL_OUT 26
U0TXD 25 1 4
26MHz±10ppm
2 3
GND XOUT
UTXDA
GND
C2
GND
"
⚠ Notice:
Defects in the craftsmanship of the crystal oscillators (for example, high frequency deviation and unstable
working temperature) may lead to the malfunction of ESP8266EX, resulting in the decrease of overall
performance.
1.4.5. RF
ANT1 1
1 WIFI_ANT C4 2.2nH 2 VDDA
2 3 LNA
4 VDD3P3
5 VDD3P3
L1 L2 VDD_RTC
6
2.4pF 3.0pF 7 TOUT
8 CHIP_EN
GND XPD_DCDC
GND GND
"
32
R1
EXT_RSTB 31 GND
RES12K 30
VDDA 29
"
Figure 1-9. ESP8266EX External Resistor
1.4.7. UART
Users need to connect a 499 R resistor to the U0TXD line in order to suppress the 80 MHz
harmonics. See Figure 1-10a.
"
By default, UART0 will output some printed information when ESP8266EX is powered on.
For the applications that are sensitive to this feature, users can exchange the pins of UART
(UART SWAP) during system initialization, that is, exchange U0TXD, U0RXD with U0RTS
(GPIO15), U0CTS (GPIO13). After the exchange, GPIO15 and GPIO13 will be connected
respectively to MCU_RXD and MCU_TXD as swapped U0TXD and U0RXD for serial
communication. For reference design, please refer to Figure 1-10b.
"
Figure 1-10b. ESP8266EX UART SWAP
"
Figure 1-10c. UART Voltage-level Switch circuit
⚠ Notice:
When using GPIO13 and GPIO15 as serial communications, please pay attention to the direction of sending
and receiving information, and they need to be connected correctively to MCU UART pins.
2019.10
GND
4
GND U1 GND
GND
GND XOUT
C1 C2
VDD33 6.8pF
1
GND
C3 C4
1uF 1uF(NC)
R1 GND Optional VDD33
26MHz±10ppm
GND GND 12K±1% R5 499R TXD0 SD1/INT R2 10K
RXD0 SD0/MISO R3 10K
VDD33 GND CMD/MOSI R4 10K
L1 4.3nH SD3/CS R6 10K
33
32
31
30
29
28
27
26
25
C5 C6 C7 SD2 R7 10K
GND
EXT_RSTB
RES12K
VDDA
VDDD
XTAL_IN
XTAL_OUT
U0TXD
U0RXD
8
4 VDD3P3 SD_DATA_0 21 R12 100R CLK 10K 10K
C9 L2 VDD3P3 SD_CLK
5 20 R13 100R CMD/MOSI
VCC
1.6nH VDD_RTC SD_CMD MTDO 1 5 MTCK
2.4pF 6 19 SD3/CS /CS DI
TOUT SD_DATA_3
" /32
7 18 SD2
CHIP_EN SD_DATA_2 MTMS R14 50R 6 2 MTDI
GND VDD33 8 17 CLK DO
XPD_DCDC VDDPST
7 3
13
GND GND
GND
/HOLD /WP
VDDPST
R15
FLASH U3
GPIO2
GPIO0
GPIO4
MTMS
MTDO
MTCK
10K
4
MTDI
CHIP_PU
GPIO16
ESP8266EX U2
C10 GND
9
10
11
12
13
14
15
16
VDD33
0.1uF
MTMS
MTDO
GPIO2
GPIO0
GPIO4
GND
MTCK
MTDI
R16
J1
2
1
10K
1.5. Slave SDIO/SPI
Espressif
"
1. ESP8266EX
"
📖 Note:
• Please refer to the design of ESP-WROOM-S2 for further details.
• UART Download Mode: Jumper J1 short circuit.
• SDIO Boot Mode: Jumper J1 open circuit.
• If the external host CPU's SDIO or SPI interface has been pulled up, the optional pull-up resistor can
be omitted.
"
• The second layer is the GND layer, where no signal lines are laid to ensure a complete
GND plane.
• The third layer is the POWER layer where only power lines can be placed. It is
acceptable to place some signal lines under unavoidable circumstances.
• The forth layer is the BOTTOM layer. Only signal lines can be laid. Placing
components on this layer is not recommended.
Below are the suggestions for a two-layer PCB design.
• The first layer is the TOP layer for signal traces and components.
• The second layer is the BOTTOM layer, where power traces are routed. Placing any
components on this layer is not recommended. Do not route any power or signal
traces under or around the RF and crystal oscillator, and so that there is a complete
GND plane, which is connected to the Ground Pad at the bottom of the chip.
1 2 3
Base Board
5 4
"
📖 Note:
As is shown in Figure 1-13, the recommended position of ESP8266EX module on the base board should be:
• Position 3, 4: Highly recommended;
• Position 1, 2, 5: Not recommended.
If the positions recommended are not suitable, please make sure that the module is not
covered by any metal shell. The antenna area of the module and the area 15 mm outside
the antenna should be kept clean, (namely no copper, routing, components on it) as shown
in Figure 1-14:
Clearance
15 mm
15 mm
15 mm
Base Board
"
Figure 1-14. Keepout Zone for ESP8266EX Module's Antenna on the Base Board
The center ground pad at the bottom of the chip should be connected to ground plane
through at least 9 ground vias.
"
"
1.6.3.3. RF Design
The characteristic RF impedance is 50 Ω. The ground plane should be complete. The RF
trace should be as short as possible with dense ground via stitching around it for isolation.
The width of RF lines should be as short as possible and there should be dense vias
stitched around.
π-type matching circuitry should be reserved on the RF trace and placed close to the RF
Pin2. The components of the π-matching network should be placed in the same direction
(see Figure 1-17).
There should be no vias for the RF trace. The RF trace should be routed at a 135 ° angle,
or with circular arcs if trace bends are required.
There should be no RF routing around the high-frequency signal lines.
The RF antenna should be set away from high-frequency transmitting devices, such as
crystal oscillators, DDR, and certain high frequency clocks (SDIO_CLK, etc.). Besides, the
USB ports, USB-to-UART signal chips, UART signal lines (including traces, vias, test points,
headers, etc.) must be placed as far away from the antenna as possible. The UART signal
line is packaged and ground shielding is added.
For PCB onboard antenna design please refer to Type-B version by Espressif. If there are
power traces near the antenna, the power traces and antenna must be isolated with GND
copper.
"
When ESP8266EX works as a slave device in a system, users need to pay more attention
to signal integrity in the PCB design. It is important to keep ESP38266EX away from the
interferences caused by the complexity of the system and an increased number of high-
frequency signals. We use the mainboard of a PAD or TV Box as an example here to
provide guidelines for the PCB layout and design.
"
The digital signal between the CPU and the DDR is the major producer of high-frequency
noise and interferes with Wi-Fi radio from the air. Below are the key points when designing
the PCB layout:
• As shown in Figure 1-18, ESP8266EX should be placed near the edge of the PCB
and away from the CPU and DDR, the main high-frequency noise sources. The
distance between the chip and the noise sources decreases the interference and
reduces the coupled noise.
• It is suggested that a 100 Ω ~ 200 Ω series resistor is added to the six signal traces
when ESP8266EX communicates with the CPU via SDIO to decrease the drive
current and any interferences, and also to eliminate the sequencing problem caused
by the inconsistent length of the SDIO traces.
• On-board PCB antenna is not recommended, as it receives much interference and
coupling noise, both of which impact the RF performance. We suggest that you use
an external antenna which should be directed away from the PCB board via a cable,
in order to weaken the high frequency interference with Wi-Fi.
• The high-frequency signal traces between the CPU and associated memory should
be routed strictly ac- cording to the routing guidelines (please refer to the DDR trace
routing guidelines). CLK and data/addr lines should be laid underground.
• The GND of the Wi-Fi circuit and that of other high-power devices should be
separated and connected through wires if there are high-power components, such as
motors, in the design.
• The antenna should be kept away from high-frequency noise sources, such as LCD,
HDMI, Camera Sensor, USB, etc.
1. Q: The current ripple is not large, but the Tx performance of RF is rather poor.
Analysis:
Ripple has a strong impact on the performance of RF Tx. It should be noted that ripple
must be tested when ESP8266EX is in the normal working mode. The ripple increases
when the power gets high. Generally, the ripple should be <80 mV when sending 11n
MCS7 packets, and <120 mV when sending 11b packets.
Solution:
Add a 10-μF filter capacitor to the branch of source circuit (ESP8266EX AVDD pin). The 10-
μF capacitor should be adjacent to the VDDA pin.
2. Q: The power ripple is small, but the Tx performance is poor.
Analysis:
The RF Tx performance can be affected not only by power ripples, but also by the crystal
oscillator itself. Poor quality and big frequency offsets (more than ±40 ppm) of the crystal
oscillator decrease the RF Tx performance. The crystal oscillator clock may be corrupted
by other interfering signals, such as high-speed output or input signals. Besides, sensitive
components or radiation components, such as inductors and antennas, may also decrease
the RF performance.
Solution:
This problem is caused by improper layout and can be solved by re-layout. See Section 1.5
for details.
3. Q: When ESP8266EX sends data packages, the power value is much higher or
lower than the target power value, and the EVM is relatively poor.
Analysis:
The disparity between the tested value and the target value may be due to signal reflection
caused by the impedance mismatch on the transmission line connecting the RF pin and the
antenna.
Solution:
Match the antenna’s impedance with the reserved π-type circuit on the RF trace, so that
the resistance from the RF pin to the antenna approaches (39-j6)Ω.
4. Q: TX performance is not bad, but the Rx sensitivity is low.
Analysis:
Good Tx performance indicates proper RF impedance matching. External coupling to the
antenna can affect the Rx performance. For instance, the crystal oscillator signal harmonics
could couple to the antenna. If ESP8266EX serves as slave device, there will be other high-
frequency interference sources on the board, which may affect the Rx performance.
Solution:
Keep the antenna away from crystal oscillators. Do not route high-frequency signal traces
close to the RF trace.
UART0 (Pin 25) U0RXD+ (Pin 26) U0TXD Receive and transmit user’s data packages.
1.7.2. Sensor
ESP8266EX can be used for developing sensor products by using the I2C interface. The
I2C works in the master mode and can connect to multiple sensors. The slave devices are
identified through the addressing mode, as each slave device has a unique address.
The sensor products send real-time data to ESP8266EX via the I2C interface, and
ESP8266EX uploads the data to the server wirelessly. Users can acquire information from
the server through the mobile app when their mobile phones connect to the internet.
ESP8266EX can be used for developing such smart home products as smart light by using
the PWM and infrared interfaces. The three PWM interfaces control red, blue, and green
LEDs respectively. The minimal PWM duty ratio is 1/214. In addition, the infrared interface
allows specific control on LEDs, such as reset, power on/off, color switch, etc.
ESP8266EX can be used for developing smart plug products. The GPIOs control the power
switch through the high/low-level switch and connection/disconnection of relay. A smart
plug requires three modules: 220 V to 3.3 V power conversion module, ESP8266EX Wi-Fi
module and relay control module.
2. ESP-LAUNCHER
2.1. Overview
Espressif provides ESP8266EX development board—ESP-LAUNCHER for quick
configuration and further development. The size of the board is 46 mm x 78.5 mm (see
Figure 2-1).
Pin 14
Pin 9
GND
Pin 26
Pin 25
Pin 14
3V3
Pin 12
Pin 13
Pin 15
Pin 7
GND
IO 14
IO 2
IO 13
IO 15
IO 3
IO 0
IO 2
IO 1
Mode select
SDA
SCL
CTS0
RTS0
RX0
TX0
Chip_En
TX1 UART I2C
5
1 16 21 1
9 10
Pin 12 IO 13 Reset key 2
6 17
22
3
11 12
USB UART Micro USB
24
4
23
7
Pin 9 IO 14 CLK
18 25
Pin 10 IO 12 MISO 13
HSPI ADC_IN TOUT Pin 6
Pin 12 IO 13 MOSI
Pin 13 IO 15 CS 26
Deep sleep XPD-DCDC IO 16 Pin 8
4
19 wake up EXT_RSTB Pin 32
5 V power Micro USB
14
15
8
1 24 1
20
Transmittor
SD_CMD
SD_CLK
Detector
SD_D0
SD_D3
SD_D2
SD_D1
W
G
B
R
IO 10
IO 14
IO 12
IO 11
IO 15
IO 15
IO 8
IO 6
IO 7
IO 9
IO 4
IO 14
IO 5
Pin 20
Pin 23
Pin 22
Pin 18
Pin 19
Pin 21
GND
Pin 24
Pin 10
Pin 16
Pin 13
Pin 13
Pin 9
Pin 9
GND
5V
"
1 Chip positioning hole 8 5V power switch 15 Relay control 22 Undefined LED and buttons
3 Wi-Fi LED, Link LED 10 CH_EN switch 17 Test board 24 2.0 mm pin header
Micro USB There are two USB interfaces. Both can be used as a 5 V power supply or for serial
interface communication (2-1-4).
The USB interface provides 5 V power supply which can be converted to 3.3 V through a
Power supply DC-to-DC converter. An LED light indicates the power, and a header pin is used for testing
the power current.
Three slide switches are used for the 5 V power supply (2-1-8), GPIO0 voltage level switch
(2-1-9) and chip enable pin CH_EN (2-1-10), respectively. When the switches are toggled to
the outer side, the voltage level is high, while when the switches are toggled to the inner
side, the voltage level is low.
• For the 5 V power switch:
- Toggled to the inner side, the board is powered on;
Slide switch
- Toggled to the outer side, the board is powered off.
• For the GPIO0 Control:
- Toggle to the inner side, the UART download mode is enabled and users can
download firmware with ESP Flash Download Tool;
- Toggle to the outer side, the Flash boot mode is enabled and the UART debug tool
can be used for debugging.
SW1 is connected to MTCK (GPIO13) for application reset and clearing the Wi-Fi
Reset Key
configuration (2-1-2). SW2 is not defined (2-1-22).
• J82: It needs to be shorted by a jumper, so that the 3.3 V power supply can be
channeled into other circuits. It can also be used to test the power current (2-1-14).
• J3: CS of HSPI flash. HSPI flash is disabled when the two upper pins are shorted by a
jumper. HSPI flash is enabled when the two lower pins are shorted by a jumper (2-1-12).
Jumper
• J14 and J67: Short-circuit J14 to connect GPIO13 to U0CTS. Short-circuit J67 to
connect GPIO15 to U0RTS (2-1-6).
• J77: Short-circuit J77 to connect GPIO16 to EXT_RSTB for Deep-sleep wake up
(2-1-26).
Interfaces UART, HSPI, SDIO/SPI, I2C, ADC_IN, GPIO16, relay control, PWM and IR TX/RX
• 32-Mbit Flash1 (mounted on the test board): Flash1 is connected to the chip via the SPI
interface. Currently, Flash1 is used when the chip is working in the Wi-Fi standalone
mode. R9 and R85 can be used for the CS of Flash1. By default, Flash1 is enabled
(2-1-18).
Flash • 32-Mbit Flash2 (mounted on the baseboard): Flash2 is connected to the chip via the
HSPI interface. HSPI is used in SIP mode. For the ESP-LAUNCHER, when ESP8266EX
works as a slave device, it connects to the host MCU via the SPI interface that is defined
in SDIO specifications. HSPI is connected to Flash2. J3 can be used for the CS of
Flash2 (2-1-11).
There are multiple modules that can be connected to the ESP-LAUNCHER for testing and
development, through the 1.27mm double-row pin headers (2-1-23) and 2.00 mm double-
Test modules row pin headers (2-1-24).
Please note that module pins should be connected to their corresponding pins on the
board. Besides, only one module at a time can be used.
HSPI It can interface SPI flash (Flash2), display screen, MCU, etc (2-1-13).
SDIO/SPI It can interface flash, host MCU, display screen, etc (2-1-19).
Currently the PWM interface has four channels, and users can extend the channels as
PWM needed. The PWM interface can be used to control LED lights, buzzers, relays, motors, etc
(2-1-20).
The functionality of the infrared remote control interface can be implemented via software
IR programming. NEC coding, modulation and demodulation are used by this interface. The
frequency of the modulated carrier signal is 38 KHz (2-1-24).
The interface is used to test the power supply voltage of VDD3P3 (pin3 and pin4), as well
ADC
as the input voltage of TOUT (pin6). It can also be used in sensors (2-1-25).
It can interface sensors and display screens with 2.54 mm or 1.27 mm pin headers
I2C
(2-1-21).
By default, UART0 will output some printed information when the device is powered on. For
the applications that are sensitive to this feature, users can exchange the pins of UART
during system initialization, that is, exchange U0TXD, U0RXD with U0RTS, U0CTS.
R1/3/5/7 should not be mounted with other components, while R2/4/6/8 can be mounted
with other components. J14 and J67 should be shorted.
Relay control It is used to control, with an indicator light, the on-and-off switch of the relay in a smart plug
terminal application ( 2-1-15).
To use the SDIO/SPI interfaces on ESP-LAUNCHER, please follow the steps below:
1. Move the 0R at R85 to R9, and then disable the flash on the ESP_Test Board;
2. Short-circuit the two lower pins on J3 with a jumper to enable HSPI flash;
3. Remove C8 (next to the Reset key on the left of the PCB);
4. Remove R58 on the PCB and disconnect GPIO14 with the infrared transmitting tube;
5. Remove the pull-down resistor R29 of MTDO/IO15 (next to J11);
6. When downloading firmware, pull the IO15/CS at J11 to low level and toggle the
switch of GPIO0 inwards to enable UART Download mode;
7. When downloading is completed, release IO15/CS to enable SDIO Boot mode;
8. Connect SDIO/SPI at J5 to host for communication.
2.3. Schematics
2.3.1. Interfaces
6 1 VBUS
7 GND VBUS 2
8 GND D- 3
9 GND D+ 4
CON8 GND NC 5
J6 GND U5
EXT_5V
Micro USB 4 1
VCCIO TXD TXD
6 1 R49 0R 20 5
GND VBUS VCC RXD RXD
7 2 R51 0R DM 16 3 RTS
8 GND D- 3 R46 0R DP 15 USBDM RTS# 11
GND D+ USBDP CTS# CTS
9 4
CON8 GND NC 5 C9 C11 C10 8 2
J7 GND 19 NC DTR# 9
R47
RED LED
GND GNDGND OSCO D10
GND R54 23 TX_LED R55 2K
0R CUSB0 22 RX_LED
CUSB1 13
U0RTS R1 0R 17 CUSB2 14 D11 R56 2K
CTS 3V3OUT CUSB3 12
CUSB4
AGND
0.1uF
R4 NC
25
7
18
21
26
GND
U0TXD U0TXD R3 0R
RXD
R8 NC J14
CON2
R6 NC
1
2
U0CTS R5 0R RTS
GPIO13 U0CTS
J67
1.Normal:use R1 R3 R5 R7 CON2
2. Swap: use R2 R4 R6 R8
(for cancelling log print when power on )
1
2
GPIO15 U0RTS
3.Flow control: short J14 and J67
J69 GND
CON6
1
2 U0TXD
3 U0RXD
4 GPIO2 UART
5 U0CTS
6 U0RTS
!
Figure 2-2. ESP-LAUNCHER Interface
EXT_5V EXT_5V
1
2
3
2
1
R57 L3 2.2uH
2K 4 IN LX 3
GND
C12 1 5
J64 EN FB
GND
CON3 4.7uF GND R59 C13 C14
Toggle Switch U6 680K 6.8pF 22uF
2
GND D12
GND
RED LED R60
150K
5V Power LED
GND GND
"
J4 J2 VDD33
GND
TOUT
1 TOUT 1
GPIO14 GPIO14 CH_EN
2 2 CH_EN
GPIO12 GPIO12
3 GPIO13 3 RST
4 GPIO13 4 RST
GPIO15 GPIO15 GPIO16 GPIO16
5 SD_D2 5 GPIO5
6 SD_D2 6 GPIO5
SD_D3 SD_D3 GPIO4 GPIO4
7 SD_CMD 7 U0TXD
8 SD_CMD 8 U0TXD
SD_CLK SD_CLK U0RXD U0RXD
9 SD_D0 9
10 SD_D0 10
SD_D1 SD_D1 GPIO0 GPIO0
11 11 GPIO2
12 12 GPIO2
GND
CON12 CON12
GND
ESP_Test board
VDD33 VDD33 VDD33 VDD33
J8 J9 VDD33
1 GPIO14 1
1 2 GPIO12 1 2 GPIO13
2 3 GPIO15 2 3 GPIO2 C18 C21 C19 C20
3 4 GPIO0 3 4 GPIO4
4 5 GPIO16 4 5 CH_EN 10uF 0.1uF 10uF 0.1uF
5 6 TOUT 5 6 RST
6 7 GPIO5 6 7 U0RXD
7 8 7 8 U0TXD
8 GND 8
9 9 GND
9 9
GND
GND GND GND GND
CON9 CON9
ESP_WROOM-01/02 2 . 0
ESP8266EX Module 1 . 27
!
Figure 2-4. ESP-LAUNCHER Test Module Schematics
GND
GND GND
4
U1
GND XOUT
GND
C1 C2
VDD33
6.8pF 6.8pF
XIN
C19 GND
1
10uF
R4
12K±1%
GND GND
26MHz±10ppm
EXT_RSTB
U0TXD
VDD33 U0RXD
GND
VDD33 VDD33
C3 C4
33
32
31
30
29
28
27
26
25
10uF 0.1uF
EXT_RSTB
GND
RES12K
VDDA
XTAL_OUT
VDDD
XTAL_IN
U0TXD
U0RXD
R9
NC
GND GND
U3
8
1 VCC 5 SD_D1
SMA 1 24 GPIO5 /CS DIO
5 WIFI_ANT C6 5.6pF 2 VDDA GPIO5 23 R12 100R SD_D1 SD_CLK 6 2 SD_D0
4 3 LNA SD_DATA_1 22 R11 100R SD_D0 CLK DO
GND
3 4 VDD3P3 SD_DATA_0 21 R10 100R SD_CLK R85 SD_D2 0R R14 7 3 0R R15 SD_D3
2 L1 L2 5 VDD3P3 SD_CLK 20 R13 100R SD_CMD 0R /HOLD /WP
1 NC NC 6 VDD_RTC SD_CMD 19 R75 100R SD_D3 FLASH
TOUT SD_DATA_3
4
GND
GPIO2
GPIO0
GPIO4
MTMS
MTDO
MTCK
TOUT
MTDI
CH_EN
GPIO16
ESP8266EX U2
9
10
11
12
13
14
15
16
VDD33
GPIO2
GPIO0
GPIO4
MTMS
MTDO
MTCK
MTDI
"
GND
3. ESP8266EX Module
Espressif provides two types of modules, the SMD module (ESP-WROOM-02) and the DIP
module (ESP-WROOM-01). The modules have been improved to achieve the optimum RF
functionality. It is recommended that users use these modules for testing or further
development.
3.1. ESP-WROOM-S2
The module size is 16 ± 0.2 mm x 23 ± 0.2 mm x 3 ± 0.15 mm (see Figure 1-1). The flash
used on this module is a 2-MB SPI flash connected to HSPI, with a package size of SOP
8-150 mil. The gain of the on-board PCB antenna is 2 dBi.
The ESP-WROOM-S2 works as the SDIO/SPI slave with the SPI speed of up to 8 Mbps.
" "
Figure 3-1. ESP-WROOM-S2 Module
3.2. ESP-WROOM-02
The module size is (18 ± 0.2) mm x (20 ± 0.2) mm x (3 ± 0.15) mm. The type of flash used
on this module is an SPI flash with a package size of SOP 8-150 mil. The gain of the on-
board PCB antenna is 2 dBi.
3.3. ESP-WROOM-02D/ESP-WROOM-02U
The module size of ESP-WROOM-02D is (18 ± 0.2) mm x (20 ± 0.2) mm x (3 ± 0.15) mm.
The type of flash used on this module is an SPI flash with a package size of SOP 8-150 mil.
The gain of the on-board PCB antenna is 3 dBi.
"
Figure 3-3. ESP-WROOM-02D Module
The module size of ESP-WROOM-02U is (18 ± 0.1) x (14.3 ± 0.1) x (3.2 ± 0.1) mm. The
type of flash used on this module is an SPI flash with a package size of SOP 8-150 mil.
ESP-WROOM-02U integrates a U.FL connector and has no onboard antenna.
"
Figure 3-4. ESP-WROOM-02U Module