5 4 3 2 1

D D

C C

TMDSSK3358 Board
-See the Hardware Implementation Document for design details
-See the Hardware User Guide for board details
-See the PCB Build Specification for PCB Details

PCB1 PCB2

TMDSSK3358 Board Bare PCB TMDSSK3358 LCD Carrier Bare PCB

B B

A A

Texas Instruments, Inc.

ARM MPU Business Unit
12500 TI Blvd
Dallas, TX 75243
Preliminary
TMDSSK3358
Title Page
Size Document Number Modified By: Rev
C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 1 of 17
5 4 3 2 1
 5 4 3 2 1

D D

C250 18pF, 50V AM335X_OSC0_IN VDDSHV6

Y6 R216
GND_OSC0
24MHz DNI
AM335X
R191
R213 0 AM335X_OSC0_OUT 10K
C245 18pF, 50V

U26A
V10 B15 PMIC_RESETOUTn
XTALIN [OSC0_IN] [PORZ] PWRONRSTn A10 PMIC_RESETOUTn <5>
SYS_WARMRESETn
[NRESETIN_OUT] WARMRSTn SYS_WARMRESETn <6,12,14,17>
U11 B5 RTC_PORZ
C247 22pF V11 XTALOUT [OSC0_OUT] [RTC_PORZ]RTC_PWRONRSTn
R49
GND_OSC0 VSS_OSC B18 100K
[NNMI] NMIn AM335x_EXTINT <6,12,13>
GND_OSC1 32.768KHz MC-306 Y7 AM335X_OSC1_IN A6 A15 R186 22
RTC_XTALIN [OSC1_IN] [XDMA_EVENT_INTR0//TIMER4/CLKOUT1/SPI1_CS1/PR1_PRU1_PRU_R31_16/EMU2/GPIO0_19] XDMA_EVENT_INTR0 D14 R52 22
AM335X_XDMA_EVENT_INTR0 <14>
[XDMA_EVENT_INTR1//TCLKIN/CLKOUT2/TIMER7/PR1_PRU0_PRU_R31_16/EMU3/GPIO0_20] XDMA_EVENT_INTR1 AM335X_XDMA_EVENT_INTR1 <8>
C249 22pF 0 R217 AM335X_OSC1_OUT A4 DGND
A5 RTC_XTALOUT [OSC1_OUT] B10
DDR_A[14..0] GND_OSC1 VSS_RTC [NTRST] TRSTn JTAG_TRSTn <17>
C11
<7> DDR_A[14..0] TMS JTAG_TMS <17>
B11
DDR_A0
DDR_A1
F3
H1 DDR_A0 AM335x TDI
TCK
A12
A11
JTAG_TDI <17>
JTAG_TCK <17>
DDR_A2 E4 DDR_A1 TDO C14 JTAG_TDO <17>
DDR_A3 C3 DDR_A2 ZCZ Package EMU0///////GPIO3_7 B14 JTAG_EMU0 <17>
DDR_A3 EMU1///////GPIO3_8 JTAG_EMU1 <17>
C DDR_A4 C2 C
B1 DDR_A4 V12 PMIC_INT1_GPIO <2>
DDR_A5 LCD_CAP_TOUCH_WAKE <5>
DDR_A5 [GPMC_CLK/LCD_MEMORY_CLK/GPMC_WAIT1/MMC2_CLK/PR1_MII1_CRS/PR1_MDIO_MDCLK/MCASP0_FSR/GPIO2_1] GPMC_CLK
DDR_A6 D5 V6
DDR_A6 [GPMC_CSN0///////GPIO1_29] GPMC_CSn0 AM335X_MCASP0_AHCLKR <8>
DDR_A7 E2 U9 R220 22
D4 DDR_A7 [GPMC_CSN1/GPMC_CLK/MMC1_CLK/PR1_EDIO_DATA_IN6/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_12/PR1_PRU1_PRU_R31_12/GPIO1_30] GPMC_CSn1 V9 MMC1_CLK <8>
DDR_A8 [GPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31] GPMC_CSn2
DDR_A8 MMC1_CMD <8>
DDR_A9 C1 T13
DDR_A9 [GPMC_CSN3///MMC2_CMD/PR1_MII0_CRS/PR1_MDIO_DATA/EMU4/GPIO2_0] GPMC_CSn3 CAP_TOUCH_INT <14>
DDR_A10 F4 U6
DDR_A10 [GPMC_WEN//TIMER6/////GPIO2_4] GPMC_WEn RGMII1_INT <12>
DDR_A11 F2 T7
DDR_A11 [GPMC_OEN_REN//TIMER6/////GPIO2_3] GPMC_OEn_REn GPIO_KEY2 <15>
DDR_A12 E3 R7
H3 DDR_A12 [GPMC_ADVN_ALE//TIMER4/////GPIO2_2] GPMC_ADVn_ALE T6 GPIO_KEY3 <15>
DDR_A13
DDR_BA[2..0] DDR_A13 [GPMC_BE0N_CLE//TIMER5/////GPIO2_5] GPMC_BEn0_CLE GPIO_KEY4 <15>
DDR_A14 H4 U18 AM335X_LCD_DISEN <9>
<7> DDR_BA[2..0] D3 DDR_A14 [GPMC_BE1N/GMII2_COL/GPMC_CSN6/MMC2_DAT3/GPMC_DIR/PR1_MII1_RXLINK/MCASP0_ACLKR/GPIO1_28] GPMC_BEn1 T17
DDR_A15 [GPMC_WAIT0/GMII2_CRS/GPMC_CSN4/RMII2_CRS_DV/MMC1_SDCD/PR1_MII1_COL/UART4_RXD/GPIO0_30] GPMC_WAIT0 GPIO_KEY1 <15>
DDR_BA0 C4 U17 AM335X_COM_WL_IRQ <8>
E1 DDR_BA0 [GPMC_WPN/GMII2_RXERR/GPMC_CSN5/RMII2_RXERR/MMC2_SDCD/PR1_MII1_TXEN/UART4_TXD/GPIO0_31] GPMC_WPn
DDR_BA1
DDR_D[15..0] DDR_BA2 B3 DDR_BA1 U7 MMC1_D0
<7> DDR_D[15..0] DDR_BA2 [GPMC_AD0/MMC1_DAT0//////GPIO1_0] GPMC_AD0 MMC1_D0 <8>
V7 MMC1_D1
M3 [GPMC_AD1/MMC1_DAT1//////GPIO1_1] GPMC_AD1 R8 MMC1_D1 <8>
DDR_D0 MMC1_D2
DDR_D0 [GPMC_AD2/MMC1_DAT2//////GPIO1_2] GPMC_AD2 MMC1_D2 <8>
DDR_D1 M4 T8 MMC1_D3
DDR_D1 [GPMC_AD3/MMC1_DAT3//////GPIO1_3] GPMC_AD3 MMC1_D3 <8>
DDR_D2 N1 U8
DDR_D2 [GPMC_AD4/MMC1_DAT4//////GPIO1_4] GPMC_AD4 AM335X_GPIO_LED4 <6>
DDR_D3 N2 V8
DDR_D3 [GPMC_AD5/MMC1_DAT5//////GPIO1_5] GPMC_AD5 AM335X_GPIO_LED3 <6>
DDR_D4 N3 R9 AM335X_GPIO_LED2 <6>
N4 DDR_D4 [GPMC_AD6/MMC1_DAT6//////GPIO1_6] GPMC_AD6 T9
DDR_D5 AM335X_GPIO_LED1 <6>
DDR_D5 [GPMC_AD7/MMC1_DAT7//////GPIO1_7] GPMC_AD7
DDR_D6 P3 U10 AM335X_LCD_DATA23
P4 DDR_D6 [GPMC_AD8/LCD_DATA23/MMC1_DAT0/MMC2_DAT4/EHRPWM2A/PR1_MII_MT0_CLK//GPIO0_22] GPMC_AD8 T10
DDR_D7 AM335X_LCD_DATA22
J1 DDR_D7 [GPMC_AD9/LCD_DATA22/MMC1_DAT1/MMC2_DAT5/EHRPWM2B/PR1_MII0_COL//GPIO0_23] GPMC_AD9 T11
DDR_D8 AM335X_LCD_DATA21
DDR_D8 [GPMC_AD10/LCD_DATA21/MMC1_DAT2/MMC2_DAT6/EHRPWM2_TRIPZONE_INPUT/PR1_MII0_TXEN//GPIO0_26] GPMC_AD10
DDR_D9 K1 U12 AM335X_LCD_DATA20
K2 DDR_D9 [GPMC_AD11/LCD_DATA20/MMC1_DAT3/MMC2_DAT7/EHRPWM2_SYNCO/PR1_MII0_TXD3//GPIO0_27] GPMC_AD11 T12
DDR_D10 AM335X_LCD_DATA19
DDR_D10 [GPMC_AD12/LCD_DATA19/MMC1_DAT4/MMC2_DAT0/EQEP2A_IN/PR1_MII0_TXD2/PR1_PRU0_PRU_R30_14/GPIO1_12] GPMC_AD12
DDR_D11 K3 R12 AM335X_LCD_DATA18
K4 DDR_D11 [GPMC_AD13/LCD_DATA18/MMC1_DAT5/MMC2_DAT1/EQEP2B_IN/PR1_MII0_TXD1/PR1_PRU0_PRU_R30_15/GPIO1_13] GPMC_AD13 V13
DDR_D12 AM335X_LCD_DATA17
L3 DDR_D12 [GPMC_AD14/LCD_DATA17/MMC1_DAT6/MMC2_DAT2/EQEP2_INDEX/PR1_MII0_TXD0/PR1_PRU0_PRU_R31_14/GPIO1_14] GPMC_AD14 U13
DDR_D13 AM335X_LCD_DATA16
DDR_D13 [GPMC_AD15/LCD_DATA16/MMC1_DAT7/MMC2_DAT3/EQEP2_STROBE/PR1_ECAP0_ECAP_CAPIN_APWM_O/PR1_PRU0_PRU_R31_15/GPIO1_15] GPMC_AD15 AM335X_LCD_DATA[23..0]
DDR_D14 L4
M1 DDR_D14 R13 AM335X_LCD_DATA[23..0] <3,6,9>
DDR_D15 RGMII2_TXEN R56 22
DDR_D15 [GPMC_A0/GMII2_TXEN/RGMII2_TCTL/RMII2_TXEN/GPMC_A16/PR1_MII_MT1_CLK/EHRPWM1_TRIPZONE_INPUT/GPIO1_16] GPMC_A0 AM335X_RGMII2_TXEN <13>
V14 AM335X_RGMII2_RXDV
[GPMC_A1/GMII2_RXDV/RGMII2_RCTL/MMC2_DAT0/GPMC_A17/PR1_MII1_TXD3/EHRPWM0_SYNCO/GPIO1_17] GPMC_A1 AM335X_RGMII2_RXDV <13>
DDR_CLK D2 U14 RGMII2_TXD3 R192 22
<7> DDR_CLK D1 DDR_CK [GPMC_A2/GMII2_TXD3/RGMII2_TD3/MMC2_DAT1/GPMC_A18/PR1_MII1_TXD2/EHRPWM1A/GPIO1_18] GPMC_A2 T14 AM335X_RGMII2_TXD3 <13>
DDR_CLKn RGMII2_TXD2 R180 22
<7> DDR_CLKn DDR_CKn [DDR_NCK] [GPMC_A3/GMII2_TXD2/RGMII2_TD2/MMC2_DAT2/GPMC_A19/PR1_MII1_TXD1/EHRPWM1B/GPIO1_19] GPMC_A3 AM335X_RGMII2_TXD2 <13>
DDR_CKE G3 R14 RGMII2_TXD1 R51 22
<7> DDR_CKE H2 DDR_CKE [GPMC_A4/GMII2_TXD1/RGMII2_TD1/RMII2_TXD1/GPMC_A20/PR1_MII1_TXD0/EQEP1A_IN/GPIO1_20] GPMC_A4 V15 AM335X_RGMII2_TXD1 <13>
DDR_CSn RGMII2_TXD0 R174 22
<7> DDR_CSn DDR_CSn0 [DDR_CSN0] [GPMC_A5/GMII2_TXD0/RGMII2_TD0/RMII2_TXD0/GPMC_A21/PR1_MII1_RXD3/EQEP1B_IN/GPIO1_21] GPMC_A5 AM335X_RGMII2_TXD0 <13>
DDR_CASn F1 U15 RGMII2_TXCLK R168 22
B <7> DDR_CASn DDR_CASn [DDR_CASN] [GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/PR1_MII1_RXD2/EQEP1_INDEX/GPIO1_22] GPMC_A6 AM335X_RGMII2_TXCLK <13> B
DDR_RASn G4 T15 AM335X_RGMII2_RXCLK
<7> DDR_RASn B2 DDR_RASn [DDR_RASN] [GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/PR1_MII1_RXD1/EQEP1_STROBE/GPIO1_23] GPMC_A7 V16 AM335X_RGMII2_RXCLK <13>
DDR_WEn AM335X_RGMII2_RXD3
<7> DDR_WEn DDR_WEn [DDR_WEN] [GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/PR1_MII1_RXD0/MCASP0_ACLKX/GPIO1_24] GPMC_A8 AM335X_RGMII2_RXD3 <13>
U16 AM335X_RGMII2_RXD2
M2 [GPMC_A9/GMII2_RXD2/RGMII2_RD2/MMC2_DAT7/GPMC_A25/PR1_MII_MR1_CLK/MCASP0_FSX/GPIO1_25] GPMC_A9 T16 AM335X_RGMII2_RXD2 <13>
DDR_DQM0 AM335X_RGMII2_RXD1
<7> DDR_DQM0 DDR_DQM0 [GPMC_A10/GMII2_RXD1/RGMII2_RD1/RMII2_RXD1/GPMC_A26/PR1_MII1_RXDV/MCASP0_AXR0/GPIO1_26] GPMC_A10 AM335X_RGMII2_RXD1 <13>
DDR_DQS0 P1 V17 AM335X_RGMII2_RXD0
<7> DDR_DQS0 DDR_DQS0 [GPMC_A11/GMII2_RXD0/RGMII2_RD0/RMII2_RXD0/GPMC_A27/PR1_MII1_RXER/MCASP0_AXR1/GPIO1_27] GPMC_A11 AM335X_RGMII2_RXD0 <13>
DDR_DQSN0 P2
<7> DDR_DQSN0
DDR_DQM1 J2 DDR_DQSn0 [DDR_DQSN0]
<7> DDR_DQM1 DDR_DQS1 L1 DDR_DQM1 G17 R132 22
<7> DDR_DQS1 L2 DDR_DQS1 [MMC0_CLK/GPMC_A24/UART3_CTSN/UART2_RXD/DCAN1_TX/PR1_PRU0_PRU_R30_12/PR1_PRU0_PRU_R31_12/GPIO2_30] MMC0_CLK G18 AM335X_MMC0_CLK <10>
DDR_DQSN1
<7> DDR_DQSN1 DDR_DQSn1 [DDR_DQSN1] [MMC0_CMD/GPMC_A25/UART3_RTSN/UART2_TXD/DCAN1_RX/PR1_PRU0_PRU_R30_13/PR1_PRU0_PRU_R31_13/GPIO2_31] MMC0_CMD AM335X_MMC0_CMD <10>
G16
[MMC0_DAT0/GPMC_A23/UART5_RTSN/UART3_TXD/UART1_RIN/PR1_PRU0_PRU_R30_11/PR1_PRU0_PRU_R31_11/GPIO2_29] MMC0_DAT0 AM335X_MMC0_D0 <10>
DDR_ODT G1 G15
<7> DDR_ODT G2 DDR_ODT [MMC0_DAT1/GPMC_A22/UART5_CTSN/UART3_RXD/UART1_DTRN/PR1_PRU0_PRU_R30_10/PR1_PRU0_PRU_R31_10/GPIO2_28] MMC0_DAT1 F18 AM335X_MMC0_D1 <10>
DDR_RESETn
<7> DDR_RESETn DDR_RESETn [DDR_RESETN] [MMC0_DAT2/GPMC_A21/UART4_RTSN/TIMER6/UART1_DSRN/PR1_PRU0_PRU_R30_9/PR1_PRU0_PRU_R31_9/GPIO2_27] MMC0_DAT2 AM335X_MMC0_D2 <10>
J3 F17
DDR_VTP [MMC0_DAT3/GPMC_A20/UART4_CTSN/TIMER5/UART1_DCDN/PR1_PRU0_PRU_R30_8/PR1_PRU0_PRU_R31_8/GPIO2_26] MMC0_DAT3 AM335X_MMC0_D3 <10>

<7> DDR_VREF J4
DDR_VREF
AM335X_ZCZ
R226
49.9 C125
0.1uF

DGND DGND
RTC RESET CKT

VRTC VRTC
VRTC
8

R108 U19B VRTC

8

U19A 10K 5
1 3 RTC_PORZ
7 R107 1K PMIC_GPIO_RTC 6
A 2 C192 A
SN74AUP2G08 R125 0.01uF
4

SN74AUP2G08 100K Frost Byte 1

4

C191
0.01uF DGND
DGND DGND Texas Instruments, Inc.
DGND DGND ARM MPU Business Unit
12500 TI Blvd
Dallas, TX 75243
Preliminary
TMDSSK3358
AM335X Section 1 of 3

Size Document Number Modified By: Rev

C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 2 of 17
5 4 3 2 1
 5 4 3 2 1

D D

AM335X

U26B
R210 0 K18 RGMII1_TXCLK R134 22
DGND [GMII1_TXCLK/UART2_RXD/RGMII1_TCLK/MMC0_DAT7/MMC1_DAT0/UART1_DCDN/MCASP0_ACLKX/GPIO3_9] MII1_TXCLK AM335X_RGMII1_TXCLK <12>
C6 K17 RGMII1_TXD0 R135 22
C5 PMIC_POWER_EN [GMII1_TXD0/RMII1_TXD0/RGMII1_TD0/MCASP1_AXR2/MCASP1_ACLKR/EQEP0B_IN/MMC1_CLK/GPIO0_28] MII1_TXD0 K16 AM335X_RGMII1_TXD0 <12>
R211 DNI RGMII1_TXD1 R130 22
<12,13> AM335X_EXT_WAKEUP EXT_WAKEUP [GMII1_TXD1/RMII1_TXD1/RGMII1_TD1/MCASP1_FSR/MCASP1_AXR1/EQEP0A_IN/MMC1_CMD/GPIO0_21] MII1_TXD1 AM335X_RGMII1_TXD1 <12>
K15 RGMII1_TXD2 R136 22
VDDA_ADC
AM335X_XLeft B6
AM335X [GMII1_TXD2/DCAN0_RX/RGMII1_TD2/UART4_TXD/MCASP1_AXR0/MMC2_DAT2/MCASP0_AHCLKX/GPIO0_17]
[GMII1_TXD3/DCAN0_TX/RGMII1_TD3/UART4_RXD/MCASP1_FSX/MMC2_DAT1/MCASP0_FSR/GPIO0_16]
MII1_TXD2
MII1_TXD3
J18
J16
RGMII1_TXD3
RGMII1_TXEN
R133
R129
22
22
AM335X_RGMII1_TXD2
AM335X_RGMII1_TXD3
<12>
<12>
<9> AM335X_XLeft AIN0 [GMII1_TXEN/RMII1_TXEN/RGMII1_TCTL/TIMER4/MCASP1_AXR0/EQEP0_INDEX/MMC2_CMD/GPIO3_3] MII1_TXEN AM335X_RGMII1_TXEN <12>
AM335X_XRight C7 H17 AM335X_AUDA_BCLK <14>
<9> AM335X_XRight B7 AIN1 [GMII1_CRS/RMII1_CRS_DV/SPI1_D0/I2C1_SDA/MCASP1_ACLKX/UART5_CTSN/UART2_RXD/GPIO3_1] MII1_CRS H16
AM335X_YUp
R73
<9> AM335X_YUp
AM335X_YDown A7 AIN2 ZCZ Package [GMII1_COL/RMII2_REFCLK/SPI1_SCLK/UART5_RXD/MCASP1_AXR2/MMC2_DAT3/MCASP0_AXR2/GPIO3_0] MII1_COL AM335X_AUDA_DIN <14>
<9> AM335X_YDown AIN3
0 C8 L18 AM335X_RGMII1_RXCLK
B8 AIN4 [GMII1_RXCLK/UART2_TXD/RGMII1_RCLK/MMC0_DAT6/MMC1_DAT1/UART1_DSRN/MCASP0_FSX/GPIO3_10] MII1_RXCLK M16 AM335X_RGMII1_RXCLK <12>
AM335X_RGMII1_RXD0
AIN5 [GMII1_RXD0/RMII1_RXD0/RGMII1_RD0/MCASP1_AHCLKX/MCASP1_AHCLKR/MCASP1_ACLKR/MCASP0_AXR3/GPIO2_21] MII1_RXD0 AM335X_RGMII1_RXD0 <12>
A8 L15 AM335X_RGMII1_RXD1
C9 AIN6 [GMII1_RXD1/RMII1_RXD1/RGMII1_RD1/MCASP1_AXR3/MCASP1_FSR/EQEP0_STROBE/MMC2_CLK/GPIO2_20] MII1_RXD1 L16 AM335X_RGMII1_RXD1 <12>
AM335X_RGMII1_RXD2
AIN7 [GMII1_RXD2/UART3_TXD/RGMII1_RD2/MMC0_DAT4/MMC1_DAT3/UART1_RIN/MCASP0_AXR1/GPIO2_19] MII1_RXD2 AM335X_RGMII1_RXD2 <12>
GNDA_TSC L17 AM335X_RGMII1_RXD3
[GMII1_RXD3/UART3_RXD/RGMII1_RD3/MMC0_DAT5/MMC1_DAT2/UART1_DTRN/MCASP0_AXR0/GPIO2_18] MII1_RXD3 AM335X_RGMII1_RXD3 <12>
VREFP_ADC B9 J15
VREFP [GMII1_RXERR/RMII1_RXERR/SPI1_D1/I2C1_SCL/MCASP1_FSX/UART5_RTSN/UART2_TXD/GPIO3_2] MII1_RXERR AM335X_AUDA_FSX <14>
C88 C89 A9 J17 AM335X_RGMII1_RXDV
VREFN [GMII1_RXDV/LCD_MEMORY_CLK/RGMII1_RCTL/UART5_TXD/MCASP1_ACLKX/MMC2_DAT0/MCASP0_ACLKR/GPIO3_4] MII1_RXDV AM335X_RGMII1_RXDV <12>
0.001uF 0.1uF
AM335X_SPI0_SCLK 22 R171 A17 H18
SPI0_SCLK [SPI0_SCLK/UART2_RXD/I2C2_SDA/EHRPWM0A/PR1_UART0_CTS_N/PR1_EDIO_SOF/EMU2/GPIO0_2] [RMII1_REFCLK/XDMA_EVENT_INTR2/SPI1_CS0/UART5_TXD/MCASP1_AXR3/MMC0_POW/MCASP1_AHCLKX/GPIO0_29] MII1_REFCLK AM335X_AUDA_DOUT <14>
AM335X_SPI0_D0 B17 M18
SPI0_D0 [SPI0_D0/UART2_TXD/I2C2_SCL/EHRPWM0B/PR1_UART0_RTS_N/PR1_EDIO_LATCH_IN/EMU3/GPIO0_3] [MDIO_CLK/TIMER5/UART5_TXD/UART3_RTSN/MMC0_SDWP/MMC1_CLK/MMC2_CLK/GPIO0_1] MDIO_CLK AM335X_RGMII1_MDIO_CLK <12,13>
AM335X_SPI0_D1 B16 M17
AM335X_SPI0_CS0 A16 SPI0_D1 [SPI0_D1/MMC1_SDWP/I2C1_SDA/EHRPWM0_TRIPZONE_INPUT/PR1_UART0_RXD/PR1_EDIO_DATA_IN0/PR1_EDIO_DATA_OUT0/GPIO0_4] [MDIO_DATA/TIMER6/UART5_RXD/UART3_CTSN/MMC0_SDCD/MMC1_CMD/MMC2_CMD/GPIO0_0] MDIO_DATA AM335X_RGMII1_MDIO_DATA <12,13>
C15 SPI0_CS0 [SPI0_CS0/MMC2_SDWP/I2C1_SCL/EHRPWM0_SYNCI/PR1_UART0_TXD/PR1_EDIO_DATA_IN1/PR1_EDIO_DATA_OUT1/GPIO0_5] AM335X_LCD_DATA[23..0]
C C
<10> AM335X_SPI0_CS1 SPI0_CS1 [SPI0_CS1/UART3_RXD/ECAP1_IN_PWM1_OUT/MMC0_POW/XDMA_EVENT_INTR2/MMC0_SDCD/EMU4/GPIO0_6] R1 AM335X_LCD_DATA[23..0] <2,6,9>
AM335X_LCD_DATA0
[LCD_DATA0/GPMC_A0/PR1_MII_MT0_CLK/EHRPWM2A//PR1_PRU1_PRU_R30_0/PR1_PRU1_PRU_R31_0/GPIO2_6] LCD_DATA0
GNDA_TSC E16 R2 AM335X_LCD_DATA1
<17> AM335X_UART0_TXD
E15 UART0_TXD[UART0_TXD/SPI1_CS1/DCAN0_RX/I2C2_SCL/ECAP1_IN_PWM1_OUT/PR1_PRU1_PRU_R30_15/PR1_PRU1_PRU_R31_15/GPIO1_11] [LCD_DATA1/GPMC_A1/PR1_MII0_TXEN/EHRPWM2B//PR1_PRU1_PRU_R30_1/PR1_PRU1_PRU_R31_1/GPIO2_7] LCD_DATA1 R3 AM335X_LCD_DATA2
<17> AM335X_UART0_RXD E18 UART0_RXD[UART0_RXD/SPI1_CS0/DCAN0_TX/I2C2_SDA/ECAP2_IN_PWM2_OUT/PR1_PRU1_PRU_R30_14/PR1_PRU1_PRU_R31_14/GPIO1_10] [LCD_DATA2/GPMC_A2/PR1_MII0_TXD3/EHRPWM2_TRIPZONE_INPUT//PR1_PRU1_PRU_R30_2/PR1_PRU1_PRU_R31_2/GPIO2_8] LCD_DATA2 R4 AM335X_LCD_DATA3
<17> AM335X_UART0_CTSn UART0_CTSn [UART0_CTSN/UART4_RXD/DCAN1_TX/I2C1_SDA/SPI1_D0/TIMER7/PR1_EDC_SYNC0_OUT/GPIO1_8] [LCD_DATA3/GPMC_A3/PR1_MII0_TXD2/EHRPWM2_SYNCI_O//PR1_PRU1_PRU_R30_3/PR1_PRU1_PRU_R31_3/GPIO2_9] LCD_DATA3
E17 T1 AM335X_LCD_DATA4
<5,17> AM335X_UART0_RTSn UART0_RTSn [UART0_RTSN/UART4_TXD/DCAN1_RX/I2C1_SCL/SPI1_D1/SPI1_CS0/PR1_EDC_SYNC1_OUT/GPIO1_9] [LCD_DATA4/GPMC_A4/PR1_MII0_TXD1/EQEP2A_IN//PR1_PRU1_PRU_R30_4/PR1_PRU1_PRU_R31_4/GPIO2_10] LCD_DATA4 T2 AM335X_LCD_DATA5
[LCD_DATA5/GPMC_A5/PR1_MII0_TXD0/EQEP2B_IN//PR1_PRU1_PRU_R30_5/PR1_PRU1_PRU_R31_5/GPIO2_11] LCD_DATA5
[LCD_DATA6/GPMC_A6/PR1_EDIO_DATA_IN6/EQEP2_INDEX/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_6/PR1_PRU1_PRU_R31_6/GPIO2_12] T3 AM335X_LCD_DATA6
LCD_DATA6 T4 AM335X_LCD_DATA7
[LCD_DATA7/GPMC_A7/PR1_EDIO_DATA_IN7/EQEP2_STROBE/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_7/PR1_PRU1_PRU_R31_7/GPIO2_13] LCD_DATA7 U1 AM335X_LCD_DATA8
[LCD_DATA8/GPMC_A12/EHRPWM1_TRIPZONE_INPUT/MCASP0_ACLKX/UART5_TXD/PR1_MII0_RXD3/UART2_CTSN/GPIO2_14] LCD_DATA8
D15 U2 AM335X_LCD_DATA9
<8> AM335X_UART1_TXD UART1_TXD [UART1_TXD/MMC2_SDWP/DCAN1_RX/I2C1_SCL//PR1_UART0_TXD/PR1_PRU0_PRU_R31_16/GPIO0_15] [LCD_DATA9/GPMC_A13/EHRPWM1_SYNCO/MCASP0_FSX/UART5_RXD/PR1_MII0_RXD2/UART2_RTSN/GPIO2_15] LCD_DATA9
D16 U3 AM335X_LCD_DATA10
<8> AM335X_UART1_RXD UART1_RXD [UART1_RXD/MMC1_SDWP/DCAN1_TX/I2C1_SDA//PR1_UART0_RXD/PR1_PRU1_PRU_R31_16/GPIO0_14] [LCD_DATA10/GPMC_A14/EHRPWM1A/MCASP0_AXR0//PR1_MII0_RXD1/UART3_CTSN/GPIO2_16] LCD_DATA10
D18 [LCD_DATA11/GPMC_A15/EHRPWM1B/MCASP0_AHCLKR/MCASP0_AXR2/PR1_MII0_RXD0/UART3_RTSN/GPIO2_17] U4 AM335X_LCD_DATA11
<8> AM335X_UART1_CTSn UART1_CTSn [UART1_CTSN/TIMER6/DCAN0_TX/I2C2_SDA/SPI1_CS0/PR1_UART0_CTS_N/PR1_EDC_LATCH0_IN/GPIO0_12] LCD_DATA11
D17 V2 AM335X_LCD_DATA12
<8> AM335X_UART1_RTSn UART1_RTSn [UART1_RTSN/TIMER5/DCAN0_RX/I2C2_SCL/SPI1_CS1/PR1_UART0_RTS_N/PR1_EDC_LATCH1_IN/GPIO0_13] [LCD_DATA12/GPMC_A16/EQEP1A_IN/MCASP0_ACLKR/MCASP0_AXR2/PR1_MII0_RXLINK/UART4_CTSN/GPIO0_8] CD_DATA12 V3 AM335X_LCD_DATA13
[LCD_DATA13/GPMC_A17/EQEP1B_IN/MCASP0_FSR/MCASP0_AXR3/PR1_MII0_RXER/UART4_RTSN/GPIO0_9] LCD_DATA13
AM335X_I2C0_SCL C16 V4 AM335X_LCD_DATA14
I2C0_SCL [I2C0_SCL/TIMER7/UART2_RTSN/ECAP1_IN_PWM1_OUT////GPIO3_6] [LCD_DATA14/GPMC_A18/EQEP1_INDEX/MCASP0_AXR1/UART5_RXD/PR1_MII_MR0_CLK/UART5_CTSN/GPIO0_10] LCD_DATA14
AM335X_I2C0_SDA C17 T5 AM335X_LCD_DATA15
I2C0_SDA [I2C0_SDA/TIMER4/UART2_CTSN/ECAP2_IN_PWM2_OUT////GPIO3_5] [LCD_DATA15/GPMC_A19/EQEP1_STROBE/MCASP0_AHCLKX/MCASP0_AXR3/PR1_MII0_RXDV/UART5_RTSN/GPIO0_11] LCD_DATA15
N17 V5
<16> USB0_DP N18 USB0_DP [LCD_PCLK/GPMC_A10/PR1_MII0_CRS/PR1_EDIO_DATA_IN4/PR1_EDIO_DATA_OUT4/PR1_PRU1_PRU_R30_10/PR1_PRU1_PRU_R31_10/GPIO2_24] LCD_PCLK U5 AM335X_LCD_PCLK <9>
<16> USB0_DM USB0_DM [LCD_VSYNC/GPMC_A8//PR1_EDIO_DATA_IN2/PR1_EDIO_DATA_OUT2/PR1_PRU1_PRU_R30_8/PR1_PRU1_PRU_R31_8/GPIO2_22] LCD_VSYNC AM335X_LCD_VSYNC <9>
TP3 AM335X_USB0_CE M15 R5
P16 USB0_CE [LCD_HSYNC/GPMC_A9//PR1_EDIO_DATA_IN3/PR1_EDIO_DATA_OUT3/PR1_PRU1_PRU_R30_9/PR1_PRU1_PRU_R31_9/GPIO2_23] LCD_HSYNC R6 AM335X_LCD_HSYNC <9>
TP4 USB0_ID
USB0_ID [LCD_AC_BIAS_EN/GPMC_A11/PR1_MII1_CRS/PR1_EDIO_DATA_IN5/PR1_EDIO_DATA_OUT5/PR1_PRU1_PRU_R30_11/PR1_PRU1_PRU_R31_11/GPIO2_25] LCD_AC_BIAS_EN AM335X_LCD_AC_BIAS_EN <9>
F16
<13> RGMII2_INT USB0_DRVVBUS [USB0_DRVVBUS///////GPIO0_18]
AM335X_USB0_VBUS P15
<16> USB0_VBUS USB0_VBUS A14
[MCASP0_AHCLKX/EQEP0_STROBE/MCASP0_AXR3/MCASP1_AXR1/EMU4/PR1_PRU0_PRU_R30_7/PR1_PRU0_PRU_R31_7/GPIO3_21] MCASP0_AHCLKX AM335X_MCASP0_AHCLKX <8>
R17 A13
<11> USB1_DP R18 USB1_DP [MCASP0_ACLKX/EHRPWM0A//SPI1_SCLK/MMC0_SDCD/PR1_PRU0_PRU_R30_0/PR1_PRU0_PRU_R31_0/GPIO3_14] MCASP0_ACLKX B13 AM335X_MCASP0_ACLKX <8>
<11> USB1_DM USB1_DM [MCASP0_FSX/EHRPWM0B//SPI1_D0/MMC1_SDCD/PR1_PRU0_PRU_R30_1/PR1_PRU0_PRU_R31_1/GPIO3_15] MCASP0_FSX AM335X_MCASP0_FSX <8>
AM335X_USB1_CE P18 D12
USB1_CE [MCASP0_AXR0/EHRPWM0_TRIPZONE_INPUT//SPI1_D1/MMC2_SDCD/PR1_PRU0_PRU_R30_2/PR1_PRU0_PRU_R31_2/GPIO3_16] MCASP0_AXR0 AM335X_MCASP0_AXR0 <8>
TP6 USB1_ID P17 C12
F15 USB1_ID [MCASP0_AHCLKR/EHRPWM0_SYNCI_O/MCASP0_AXR2/SPI1_CS0/ECAP2_IN_PWM2_OUT/PR1_PRU0_PRU_R30_3/PR1_PRU0_PRU_R31_3/GPIO3_17] MCASP0_AHCLKR B12 LCD_BACKLIGHTEN <9>
AM335X_USB1_DRVVBUS
<11> AM335X_USB1_DRVVBUS USB1_DRVVBUS [USB1_DRVVBUS///////GPIO3_13] [MCASP0_ACLKR/EQEP0A_IN/MCASP0_AXR2/MCASP1_ACLKX/MMC0_SDWP/PR1_PRU0_PRU_R30_4/PR1_PRU0_PRU_R31_4/GPIO3_18] MCASP0_ACLKR AM335X_USB1_OC <11>
VUSB_VBUS1 AM335X_USB1_VBUS T18 C13
USB1_VBUS [MCASP0_FSR/EQEP0B_IN/MCASP0_AXR3/MCASP1_FSX/EMU2/PR1_PRU0_PRU_R30_5/PR1_PRU0_PRU_R31_5/GPIO3_19] MCASP0_FSR D13 ACC_INT1 <15>
R126 1.2K, 1/4W
[MCASP0_AXR1/EQEP0_INDEX//MCASP1_AXR0/EMU3/PR1_PRU0_PRU_R30_6/PR1_PRU0_PRU_R31_6/GPIO3_20] MCASP0_AXR1 AM335X_MCASP0_AXR1 <8>
R243 0
<15> DDR_VTT_EN
C18
<15> ACC_INT2 ECAP0_IN_PWM0_OUT [ECAP0_IN_PWM0_OUT/UART3_TXD/SPI1_CS1/PR1_ECAP0_ECAP_CAPIN_APWM_O/SPI1_SCLK/MMC0_SDWP/XDMA_EVENT_INTR2/GPIO0_7]
AM335X_ZCZ R219
B B
4.7K

VDDSHV6

C214 D6 C18
0.1uF DNI 0.1uF

DGND
DGND
ZIGBEE HEADER
I2C _HEADER

VDDSHV6 VDDSHV6 V3_3D V3_3D

J8
J11 4
1 3
2 2 AM335X_I2C0_SCL <3,5,6,15>
AM335X_SPI0_CS0
AM335X_I2C0_SDA <3,5,6,15>
AM335X_I2C0_SDA R233 0 DGND AM335X_SPI0_D1 3 1
I2C_SDA_AUDIO <14> 4
AM335X_I2C0_SCL R232 0 R142 R141 R179 R177 R131
I2C_SCL_AUDIO <14>
4.7K 4.7K 4.7K 4.7K 4.7K AM335X_SPI0_SCLK 5 DNI
<3,5,6,15> AM335X_SPI0_SCLK
AM335X_SPI0_D0 6 DGND
<3,5,6,15> AM335X_SPI0_D0
DNI

AM335X_I2C0_SCL AM335X_SPI0_CS0
AM335X_I2C0_SDA AM335X_SPI0_D1
AM335X_UART0_RTSn

A A

USB1_ID Frost Byte 1

R143
0 Texas Instruments, Inc.
ARM MPU Business Unit
12500 TI Blvd
DGND Dallas, TX 75243

TMDSSK3358
AM335X Section 2 of 3
Size Document Number Modified By: Rev
C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 3 of 17
5 4 3 2 1
 5 4 3 2 1

AM335X POWER
VDDSHV1
D D
U26C
F6 P7 150OHM800mA FB9
VDD_CORE VDD_CORE VDDSHV1 VDIG1
F7 P8
G6 VDD_CORE VDDSHV1 VDDSHV2
G7 VDD_CORE
G10 VDD_CORE P10 150OHM800mA FB5
VDD_CORE VDDSHV2 VMMC
H11 P11
J12 VDD_CORE VDDSHV2 VDDSHV3
K6 VDD_CORE
K8 VDD_CORE P12 150OHM800mA FB3
VDD_CORE VDDSHV3 VMMC
K12 P13
L6 VDD_CORE VDDSHV3
L7 VDD_CORE VDDSHV4
L8 VDD_CORE
L9 VDD_CORE H14 150OHM800mA FB4
VDD_CORE VDDSHV4 VMMC
M11 J14
M13 VDD_CORE VDDSHV4
N8 VDD_CORE VDDSHV5
N9
N12
VDD_CORE
VDD_CORE AM335X K14 150OHM800mA FB2
R212 VDD_CORE VDDSHV5 VMMC
N13 L14
0.1ohm1% Sense VDD_CORE VDDSHV5
VDD_MPU_AM335X F10
ZCZ Package
VDD_MPU VDD_MPU
F11
F12 VDD_MPU E10
F13 VDD_MPU VDDSHV6 E11
G13 VDD_MPU VDDSHV6 E12 VDDSHV6
H13 VDD_MPU VDDSHV6 E13
J13 VDD_MPU VDDSHV6 F14 150OHM800mA FB6
VDD_MPU VDDSHV6 VAUX2
DNI R223 VDDMPU_MON A2 G14
<5> PWR_SMPS1_FB VDD_MPU_MON VDDSHV6 N5
CAP_VDD_SRAM_CORE D9 VDDSHV6 P5
H15 CAP_VDD_SRAM_CORE VDDSHV6 P6
VDIG2 VDDS_PLL_MPU VDDSHV6

VDIG2 D10
CAP_VDD_SRAM_MPU D11 VDDS_SRAM_MPU_BB
CAP_VBB_MPU C10 CAP_VDD_SRAM_MPU E6
E9 CAP_VBB_MPU VDDS E14
C VDIG2 C
VDDS_SRAM_CORE_BG VDDS F9
VDDS VDAC
K13
N15 VDDS N6
VMMC VDDA3P3V_USB0 VDDS
N16 P9
C83 C254 C256 VDDA1P8V_USB0 VDDS P14
1uF 1uF 1uF M14 VDDS
VAUX1 DGND VSSA_USB VDDA_ADC
R15
R16 VDDA3P3V_USB1 D8 150OHM800mA 1 2 FB7
VDDA1P8V_USB1 VDDA_ADC VPLL
FB8
DGND DGND DGND N14 E8 GNDA_ADC 150OHM800mA 1 2
DGND VSSA_USB VSSA_ADC
VDIG2 M5
E7 VPP R10
VDDS_PLL_DDR VDDS_PLL_CORE_LCD VDIG2
GNDA_ADC DGND
E5
F5 VDDS_DDR D7 VDDS_RTC 0 R72
VDDS_DDR VDDS_RTC VRTC
G5 D6 VDD_RTC
H5 VDDS_DDR CAP_VDD_RTC B4
VDDS_DDR [ENZ_KALDO_1P8V] RTC_KALDO_ENn
J5
K5 VDDS_DDR
L5 VDDS_DDR R11 GNDA_TSC GNDA_ADC
VDDS_DDR VDDS_OSC VDIG2
A3 TP10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RESERVED
[TESTOUT]
C84 C59 C98 C52 C78 C56 C55 C53 AM335X_ZCZ
A1
A18
F8
G8
G9
G11
G12
H6
H7
H8
H9
H10
H12
J6
J7
J8
J9
J10
J11
K7
K9
K10
K11
L10
L11
L12
L13
M6
M7
M8
M9
M10
M12
N7
N10
N11
V1
V18
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF

R218 C122 C95 C239 C72 C99

DGND DGND DGND DGND DGND DGND 10K, 1% 1uF 0.01uF 0.01uF 0.01uF 0.01uF

DGND
R238
B B
0.24ohm1% Sense
VDDS_DDR VDDS_DDR3_AM335X DGND DGND GND_OSC0 DGND DGND GNDA_ADC

DE-CAPS

VDD_CORE VDD_CORE VDD_MPU_AM335X

VDDS_DDR3_AM335X

C51 C94 C101 C49 C91 C103 C100 C102 C92 C123 C82 C85 C107 C86 C104 C267 C261 C112 C113 C109 C110 C111 C114 C121 C120 C118 C108 C119 C128 C271 C129 C131 C130 C268 C269 C260
0.01uF 0.01uF 0.01uF 10uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 10uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 10uF 10uF 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V

DGND
DGND DGND
DGND

VDDSHV1 VDDSHV2 VDDSHV3 VDDSHV4 VDDSHV5 VDDSHV6 VDAC

A A

Frost Byte 1
C117 C105 C106 C203 C90 C96 C28 C50 C60 C30 C80 C57 C29 C79 C45 C27 C258 C116 C127 C93 C255 C126 C44 C87 C62 C61 C236
10uF 0.01uF 0.01uF 10uF 0.01uF 0.01uF 10uF 0.01uF 0.01uF 10uF 0.01uF 0.01uF 10uF 0.01uF 0.01uF 10uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 10uF 0.01uF 0.01uF 0.01uF 0.01uF Texas Instruments, Inc.
ARM MPU Business Unit
12500 TI Blvd
DGND DGND DGND DGND DGND DGND Dallas, TX 75243
DGND
TMDSSK3358
SubArctic Power
Size Document Number Modified By: Rev
C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 4 of 17
5 4 3 2 1
 5 4 3 2 1

Main Power Input

VBAT
TP11

J9
U30 D8 F1
1 1 2 VPWRIN_JCK VPWRIN_PREFUSE 1 2

4 3 B520C-13-F Fuse 4A

2
DLW5BTN501SQ2L C262 C124 C138 C132 C137
GND_IN 100uF 0.1uF 0.1uF 10uF 1uF
Power Jack RAPC712X D7
D D
DGND SMCJ7.0CA

DGND
DGND

Power Management IC
VRTC_PMIC
U25
VBAT 28 31
29 VCC7 SW3 30
C76 VRTC VFB3
4.7uF C238 20 VAUX33
DGND OSC32KIN
2.2uF 36
VCC1 VBAT
C C
21 35 PWR_SMPS1 L11 2.2uH
OSC32KOUT SW1 VDD_MPU
VRTC R59 10K, 1% PMIC_GPIO DGND DGND 38 32 R201 0 C74 R240
CLK32KOUT VFB1 34 C244 10uF 150
R139 0 PMIC_I2C_SCL 9 GND1 10uF
<3,6,15> AM335X_I2C0_SCL SCL_SCK
R140 0 PMIC_I2C_SDA 8
<3,6,15> AM335X_I2C0_SDA SDA_SDI PWR_SMPS1_FB <4>
DGND DGND DGND
VAUX33 PMIC_GPIO 39 41
GPIO_CKSYNC VCC2 VBAT
D5
R137 DNI PMICSR_I2C_SCL 11 42 PWR_SMPS2 L10 2.2uH Green LED
SCLSR_EN1 SW2 VDD_CORE
R28 R138 DNI PMICSR_I2C_SDA 10 44 C97
10K SDASR_EN2 VFB2 43 C67 10uF
R128 DNI PMIC_INT1 45 GND2 10uF DGND
<2> PMIC_INT1_GPIO INT1
PMIC_SLEEP 37
TP9 EXP_PB_POWERON 33 SLEEP DGND DGND DGND
19 PWRON 13
VRTC_PMIC BOOT1 VCCIO VBAT
26
R27 10K PMIC_PWRHOLD 1 BOOT0 14 PWR_SWIO L8 2.2uH
VAUX33 PWRHOLD SWIO VDDS_DDR
PMIC_RESETOUTn 40 16 C43
<2> PMIC_RESETOUTn nRESPWRON VFBIO 15 C235 10uF
GNDIO 10uF
18
DGND C225 VREF DGND DGND DGND
0.01uF 25 12 PWR_VDDIO R144 0
TESTV VDDIO VAUX33
17
REFGND

VBAT DGND 23
22 VCC5 6
VDAC VDAC VCC6 VBAT
24 7
VPLL VPLL VDIG1 VDIG1
C42 5 VDIG2
4.7uF VDIG2 C77
C227 C232 C211 C210 4.7uF
DGND 2.2uF 2.2uF 27 2.2uF 2.2uF
VBAT VBACKUP DGND
DGND TP5 DGND DGND
DGND
VBAT 47 3 VBAT
B VCC4 VCC3 4 B
GNDP VAUX33 VAUX33
46 2
VAUX1 VAUX1 VMMC VMMC
C46 VAUX2 48 C63
4.7uF VAUX2 C213 C212 4.7uF
C221 TPS65910A3 2.2uF 2.2uF
PPAD

DGND 2.2uF DGND

C31 DGND DGND
2.2uF
DGND

DGND DGND

PWR ON SWITCH
RTC LDO

VBAT

VBAT R112
U21 VRTC 10K
A 1 5 R121 0 A
IN OUT
3 EXP_PB_POWERON Frost Byte 1
EN
3
4

C217
1uF
4
NR GND
2 C197
1uF
Texas Instruments, Inc.
TPS71718 SW5 ARM MPU Business Unit
B3SL 12500 TI Blvd
DGND DGND DGND Dallas, TX 75243
1
2

TMDSSK3358
Platform_Power
VRTC R23 DNI VRTC_PMIC DGND
Size Document Number Modified By: Rev
C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 5 of 17
5 4 3 2 1
 5 4 3 2 1

User Reset/Interrupt Switches

ID Memory
VDDSHV6

VDDSHV6 VDDSHV6 R117

0

U8
6 8
<3,5,15> AM335X_I2C0_SCL SCL VCC
5 SYS_WARMRESETn R29 DNI
D <3,5,15> AM335X_I2C0_SDA SDA SYS_WARMRESETn <2,12,14,17> D
C115 R74

3
4

3
4
4 0.01uF DNI
1 VSS
2 A0 SW7
3 A1 7 B3SL C279 SW6
A2 WP DNI B3SL
CAT24C256W

1
2

1
2
R167 0
DGND DGND AM335x_EXTINT <2,12,13>
DGND
DGND
R166 C32
1K 1uF

DGND DGND

User LEDs
Mechanical

VBAT

MH1 MH3 MH2 MH4

C C

1
R113 R111

1
150 150 R114 R116
150 150

D3 D4
Green LED Green LED D2 D1 DGND
Green LED Green LED
D Screws
M2 M3 M4 M5
Q3
G D
S D D
Q2 Screw2-56_1/4in Screw2-56_1/4in Screw2-56_1/4in Screw2-56_1/4in
BSS138 G Q5 Q4
S G G
S S StandOffs
BSS138
DGND BSS138 BSS138 M6 M7 M8 M9

DGND
DGND DGND Standoff2-56_3/16x3/8in Standoff2-56_3/16x3/8in Standoff2-56_3/16x3/8in Standoff2-56_3/16x3/8in

StandOffs
M10 M11 M12 M13
<2> AM335X_GPIO_LED1 <2> AM335X_GPIO_LED3 <2> AM335X_GPIO_LED4
<2> AM335X_GPIO_LED2
Standoff2-56_3/16x5/8in Standoff2-56_3/16x5/8in Standoff2-56_3/16x5/8in Standoff2-56_3/16x5/8in
R100
100K R98
100K R105 R104
B B
100K 100K
DGND
GND Probe points
DGND DGND
DGND
TP13 TP2

Boot Configuration
DGND
AM335X_LCD_DATA[15.0] 0100XXXXXXXX110111b MMC0, SPI0, UART0, USB0

VDDSHV6 VDDSHV6
R164

R163

R162

R161

R160

R159

R158

R157

R156

R155

R154

R153

R152

R151

R150

R149
AM335X_LCD_DATA[23..0]
<2,3,9> AM335X_LCD_DATA[23..0]
100K

100K

100K

100K

100K

100K
DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI
AM335X_LCD_DATA0
AM335X_LCD_DATA1
AM335X_LCD_DATA2 AM335X_LCD_DATA3 AM335X_LCD_DATA4 AM335X_LCD_DATA11 AM335X_LCD_DATA12
AM335X_LCD_DATA3
AM335X_LCD_DATA4 AM335X_LCD_DATA2 AM335X_LCD_DATA5 CLKOUT1 enabled AM335X_LCD_DATA10 AM335X_LCD_DATA13
AM335X_LCD_DATA5
A AM335X_LCD_DATA6 AM335X_LCD_DATA1 AM335X_LCD_DATA6 AM335X_LCD_DATA9 AM335X_LCD_DATA14 A
AM335X_LCD_DATA7
AM335X_LCD_DATA8 AM335X_LCD_DATA0 AM335X_LCD_DATA7 AM335X_LCD_DATA8 AM335X_LCD_DATA15
AM335X_LCD_DATA9
AM335X_LCD_DATA10
R31

R32

R33

R34

R35

R36

R37

R38

R39

R40

R41

R42

R43

R44

R45

R46

AM335X_LCD_DATA11
AM335X_LCD_DATA12
Texas Instruments, Inc.
AM335X_LCD_DATA13 ARM MPU Business Unit
AM335X_LCD_DATA14 12500 TI Blvd
AM335X_LCD_DATA15 Dallas, TX 75243
10K

10K

10K

10K

10K

10K

10K

10K

10K

10K
DNI

DNI

DNI

DNI

DNI

DNI

TMDSSK3358
SysBoot_LEDs_Mech

Size Document Number Modified By: Rev

DGND DGND C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 6 of 17
5 4 3 2 1
 5 4 3 2 1

D D

R237 DDR3 SDRAM

10K, 1%
VDDS_DDR
DDR_A[14..0]
DDR_A[14..0] <2>
Terminations
U32
R242 DDR_RESETn T2
<2> DDR_RESETn RESET#
10K, 1%
DDR_CLK J7 N3 DDR_A0
DGND <2> DDR_CLK CK A0
DDR_CLKn K7 P7 DDR_A1
<2> DDR_CLKn CKn A1
DDR_CKE K9 P3 DDR_A2
<2> DDR_CKE L2 CKE A2 N2
DDR_CSN0 DDR_A3 DDR_CLK R89 33
<2> DDR_CSn CSn A3
DDR_RASN J3 P8 DDR_A4 C167 VDDS_DDR
<2> DDR_RASn K3 RASn A4 P2
DDR_CASN DDR_A5 DDR_CLKn R88 33 0.1uF
<2> DDR_CASn CASn A5
DDR_WEn L3 R8 DDR_A6
DDR_D[15..0] <2> DDR_WEn WEn A6 R2 DDR_A7
<2> DDR_D[15..0] E3 A7 T8
DDR_D3 DDR_A8 VTT_DDR
DDR_D6 F7 DQ0 A8 R3 DDR_A9
DDR_D5 F2 DQ1 A9 L7 DDR_A10
DDR_D7 F8 DQ2 A10 R7 DDR_A11 DDR_CASN 1 16 RP6
DDR_D2 H3 DQ3 A11 N7 DDR_A12 DDR_RASN 2 15 33x8
DDR_D0 H8 DQ4 A12 T3 DDR_A13 DDR_A10 3 14
DDR_D4 G2 DQ5 A13 T7 DDR_A14 DDR_BA[2..0] DDR_A12 4 13
H7 DQ6 A14 M2 DDR_BA[2..0] <2> 5 12
DDR_D1 DDR_BA0 DDR_A1
DDR_D11 D7 DQ7 BA0 N8 DDR_BA1 DDR_BA1 6 11
DDR_D8 C3 DQ8 BA1 M3 DDR_BA2 DDR_A4 7 10
DDR_D14 C8 DQ9 BA2 DDR_A6 8 9 RP5
DDR_D12 C2 DQ10 K1 DDR_ODT DDR_ODT 1 16 33x8
A7 DQ11 ODT DDR_ODT <2> 2 15
DDR_D15 DDR_CSN0
DDR_D10 A2 DQ12 DDR_A5 3 14
DDR_D13 B8 DQ13 B2 DDR_A3 4 13
DQ14 VDD1 VDDS_DDR
DDR_D9 A3 G7 DDR_BA0 5 12
DQ15 VDD2 R9 DDR_WEn 6 11
DDR_DQS1 C7 VDD3 K2 DDR_A0 7 10
<2> DDR_DQS1 UDQS VDD4
DDR_DQSN1 B7 K8 DDR_BA2 8 9
<2> DDR_DQSN1 UDQSn VDD5 N1 1 16 RP7
DDR_DQS0 F3 VDD6 N9 DDR_A8 2 15 33x8
<2> DDR_DQS0 LDQS VDD7
C DDR_DQSN0 G3 R1 DDR_A14 3 14 C
<2> DDR_DQSN0 LDQSn VDD8 D9 4 13
DDR_A11
DDR_DQM1 D3 VDD9 DDR_A2 5 12
<2> DDR_DQM1 UDM
DDR_DQM0 E7 A9 DDR_A9 6 11
<2> DDR_DQM0 LDM VSS1 B3 7 10
DDR_A13
VSS2 E1 DDR_A7 8 9
VDDS_DDR VSS3
A1 G8
A8 VDDQ1 VSS4 J2
C1 VDDQ2 VSS5 J8
C9 VDDQ3 VSS6 M1
D2 VDDQ4 VSS7 M9 DDR_RESETn R241
E9 VDDQ5 VSS8 P1 DNI
F1 VDDQ7 VSS9 P9
H2 VDDQ8 VSS10 T1
H9 VDDQ9 VSS11 T9
VDDQ10 VSS12
J1 B1
J9 NC1 VSSQ1 B9 DGND
L1 NC2 VSSQ2 D1
L9 NC3 VSSQ3 D8 VTT Regulator VAUX33
M7 NC4 VSSQ4 E2
NC5 VSSQ5 E8
VSSQ6 F9 U14 R96
DDR_VREF M8 VSSQ7 G1 R93 10K, 1% REFIN_DDR 1 10 10K, 1%
<2,7> DDR_VREF VREF_CA VSSQ8 VDDS_DDR REFIN VIN VAUX33
G9
VSSQ9 2 9 TP23
VDDS_DDR VLDOIN PGOOD
H1 L8 R94 240, 1%
VREF_DQ ZQ R95 C171 0.75V 3 8
VTT_DDR VO GND DGND
10K, 1% 0.001uF
7

PWRPD
MT41J128M16JT-125 4 EN DDR_VTT_EN <15>
DGND PGND
C145 5 6 TP25 R245 10K, 1%
0.1uF DGND VOSNS REFOUT
DGND TPS51200

11
C187 DDR_VREF <2,7> DGND
0.1uF

B B
DGND
DGND DGND

VTT REG. DECAPS

DDR3 DECAPS
VTT_DDR VDDS_DDR VAUX33

VDDS_DDR

C277 C158 C175 C173 C174 C172 C165 C142 C148 C169 C147 C168 C143 C144 C182 C141 C186 C140 C273 C176
10uF 10uF 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 0.1uF, 6.3V 10uF 10uF 10uF 10uF 10uF 4.7uF

DGND DGND DGND

DGND

A A

Texas Instruments, Inc.

ARM MPU Business Unit
12500 TI Blvd
Dallas, TX 75243

TMDSSK3358
DDR3_Memory
Size Document Number Modified By: Rev
C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 7 of 17
5 4 3 2 1
 5 4 3 2 1

D VOLTAGE TRANSLATORS D
WLAN MODULE
V1_8D
COMWL_RST
AM335X_MCASP0_AHCLKR <3>

R58

R57
R182
R185
R183

R184
V1_8D V3_3D
V1_8D VCOM_BAT 3.3V
L7 2.2uH L12 2.2uH U12
16 1
VCCB VCCA

10K
10K
10K
10K

10K
DNI
COMWL_IRQ 13 4
1B1 1A1 AM335X_COM_WL_IRQ <2>
MMC1_CMD COMAUD_OUT 12 5
1B2 1A2 AM335X_MCASP0_AXR1 <3>
MMC1_CLK
MMC1_D0 C230 C136 COMAUD_FSYNC 11 6
2B1 2A1 AM335X_MCASP0_FSX <3>
MMC1_D1 0.01uF 0.01uF COM_BTRST 10 7
2B2 2A2 AM335X_MCASP0_AHCLKX <3>
MMC1_D2
MMC1_D3 15 2 V1_8D V3_3D
DGND DGND 14 1OE 1DIR 3
2OE 2DIR

12
A1

3
2
9 8
TP17 COM_WL_UART_DBG 5 26 COMAUD_CLK GND GND C170 C180

VIO
VBAT
VBAT
COMWL_RST 6 UART_DBG AUD_CLK 25 COMAUD_FSYNC SN74AVC4T245 0.01uF 0.01uF
TP15 COM_WL_RS232_RX 7 WLAN_EN AUD_FSYNC 23 COMAUD_IN DGND DGND
TP19 COM_WL_RS232_TX 8 RS232_RX AUD_IN 24 COMAUD_OUT
COMWL_IRQ 9 RS232_TX AUD_OUT DGND DGND
WLAN_IRQ 27 COMBTUARTRTS
VBAT_WLAN VBAT_WLAN UART_RTS

BLUETOOTH
MMC1_CMD 15 28 COMBTUARTCTS
<2> MMC1_CMD SDIO_CMD/SPI_D UART_CTS
MMC1_CLK 16 29 COMBTUARTTX
<2> MMC1_CLK 17 SDIO_CLK/SPI_C UART_TX 30
Y2 MMC1_D0 COMBTUARTRX
<2> MMC1_D0 SDIO_D0/SPI_DOUT UART_RX

WLAN
1 12 MMC1_D1 18
VIO VDD <2> MMC1_D1 SDIO_D1
2 11 MMC1_D2 14 10 COM_BTRST
3 NC1 NC8 10 <2> MMC1_D2 19 SDIO_D2 BT_EN 32
MMC1_D3 COM_BTUARTDEBUG TP12
NC2 NC7 <2> MMC1_D3 SDIO_D3/SPI_CS BT_TX_DBG
C C70 4 9 11 C
0.01uF 5 NC3 NC6 8 BT_FUNC1 34
6 NC4 NC5 7 COM_SLOW_CLK_XO 0 R187 21 BT_FUNC5 33
GND OUT SLEEP_CLK BT_FUNC6
32.768Khz,5+/-23ppm COM_SLOW_CLK DNI R188
DGND 40 V1_8D
2.4G_ANT V3_3D
1 57 U29
4 GND GND 58 16 1
13 GND GND 59 VCCB VCCA
20 GND LBEE5ZSTNC-523 GND 60 COMAUD_CLK 13 4
22 GND GND 61 12 1B1 1A1 5 AM335X_MCASP0_ACLKX <3>
COMAUD_IN
Antenna Matching 31 GND GND 62 1B2 1A2 AM335X_MCASP0_AXR0 <3>
GND GND 11 6
2B1 2A1 DGND
3

ANT1 DGND J10 COM_SLOW_CLK 10 7

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2B2 2A2 AM335X_XDMA_EVENT_INTR1 <2>
L15
G

2 1 1 2 0 L14 4 1 0 R239 15 2
NC FEED 1.3nH OUT IN 14 1OE 1DIR 3 V1_8D V3_3D
35
36
37
38
39
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
2OE 2DIR
1

LDA312G7313F-237 L13 MM8130-2600 9 8

5

5.1nH GND GND

SN74AVC4T245 C264 C259
DGND DGND 0.01uF 0.01uF
DGND
2

DGND
DGND DGND

DGND

V1_8D V3_3D

B B
U11
WLAN POWER 16 1
VCCB VCCA
COMBTUARTRX 13 4
VCOM_BAT VBAT_WLAN_OUT VBAT_WLAN 1B1 1A1 AM335X_UART1_TXD <3>
200mA max COMBTUARTCTS 12 5
1B2 1A2 AM335X_UART1_RTSn <3>
COMBTUARTTX 11 6
2B1 2A1 AM335X_UART1_RXD <3>
L6 2.2uH 3.3V@500mA max COMBTUARTRTS 10 7
2B2 2A2 AM335X_UART1_CTSn <3>
VBAT VCOM_BAT
C69 VBAT 15 2
1OE 1DIR
1

C215 0.01uF U27 14 3

0.01uF 2 4 2OE 2DIR V1_8D V3_3D
VIN

VOUT

IN OUT 9 8
U22 C252 1 GND GND
VMMC EN
DGND 1uF 5 SN74AVC4T245
VSS

DGND FB R224 C257 DGND DGND C149 C151

6 3 51K 15pF 0.01uF 0.01uF
XC6218P182HR-G DGND GND GND
3

TPS79501 VCOM_BATFB
DGND DGND
C135
DGND 2.2uF
DGND R222
30.1K

DGND

A A

Frost Byte 1

Texas Instruments, Inc.

ARM MPU Business Unit
12500 TI Blvd
Dallas, TX 75243

TMDSSK3358
WLAN_Module
Size Document Number Modified By: Rev
C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 8 of 17
5 4 3 2 1
 5 4 3 2 1

LCD

CAPACITIVE TOUCH OPTION

V3_3D J2
DGND 1
2
<3,5,6,15> AM335X_I2C0_SCL 3
<3,5,6,15> AM335X_I2C0_SDA 4
R80 0
<14> CAP_TOUCH_INT 5
<5> LCD_CAP_TOUCH_WAKE R84 0
D 6 D

R225 DNI 7
V3_3D 8
0522070685

A2
LCD TFT 480X272
RGB Display
with Cap TouchScreen
V3_3D
NHD-4.3-480272MF-ATXI#-CTP

C231
AM335X_LCD_DATA[23..0] 0.01uF
<2,3,6> AM335X_LCD_DATA[23..0]
J1
LED- 1
DGND LED+ 2
3 BackLight Driver
4
AM335X_LCD_DATA15 1 16 RP3 CBB7 CBR0 5
AM335X_LCD_DATA14 2 15 33x8 CBB6 CBR1 6
AM335X_LCD_DATA13 3 14 CBB5 CBR2 7
AM335X_LCD_DATA12 4 13 CBB4 CBR3 8
AM335X_LCD_DATA11 5 12 CBB3 CBR4 9
AM335X_LCD_DATA17 6 11 CBB2 CBR5 10 VBAT
AM335X_LCD_DATA20 7 10 CBB1 CBR6 11 BKLT_L L9 4.7uH BKLT_SW
AM335X_LCD_DATA23 8 9 CBB0 CBR7 12
AM335X_LCD_DATA10 1 16 CBG7 CBG0 13
AM335X_LCD_DATA9 2 15 RP2 CBG6 CBG1 14
AM335X_LCD_DATA8 3 14 33x8 CBG5 CBG2 15
C AM335X_LCD_DATA7 4 13 CBG4 CBG3 16 C
AM335X_LCD_DATA6 5 12 CBG3 CBG4 17 C33

PAD
AM335X_LCD_DATA5 6 11 CBG2 CBG5 18 4.7uF DGND

54132-4097
AM335X_LCD_DATA19 7 10 CBG1 CBG6 19 U7
AM335X_LCD_DATA22 8 9 CBG0 CBG7 20 1 10

TPAD
AM335X_LCD_DATA4 1 16 CBR7 CBB0 21 L SW LED Backlight pwr 32mA @ 20V
AM335X_LCD_DATA3 2 15 RP1 CBR6 CBB1 22 DGND 2
AM335X_LCD_DATA2 3 14 33x8 CBR5 CBB2 23 VIN 9 LED+
AM335X_LCD_DATA1 4 13 CBR4 CBB3 24 R48 6 OUT
VMMC EN
AM335X_LCD_DATA0 5 12 CBR3 CBB4 25 Q1 10, 1%
AM335X_LCD_DATA16 6 11 CBR2 CBB5 26 D SS 3
AM335X_LCD_DATA18 7 10 CBR1 CBB6 27 SS 5 LED-
AM335X_LCD_DATA21 8 9 CBR0 CBB7 28 FB

PGND
1 16 29 G 7 C75

GND
2 15 30 <2> LCD_BACKLIGHTEN S FSW
RP4 CCLK R50 C64 4.7uF
3 14 33x8 DISEN 31 44.2K, 1% DNI
AM335X_LCD_AC_BIAS_EN 4 13 CDEN CHSYNC 32 BSS138 TPS61081DRC R63
<3> AM335X_LCD_AC_BIAS_EN

8
AM335X_LCD_VSYNC 5 12 CVSYNC CVSYNC 33 10, 1%
<3> AM335X_LCD_VSYNC
AM335X_LCD_HSYNC 6 11 CHSYNC CDEN 34
<3> AM335X_LCD_HSYNC 7 10 35
AM335X_LCD_DISEN DISEN
<2> AM335X_LCD_DISEN
AM335X_LCD_PCLK 8 9 CCLK 36 DGND
<3> AM335X_LCD_PCLK 37
AM335X_XRight
<3> AM335X_XRight
AM335X_YDown 38
<3> AM335X_YDown
AM335X_XLeft 39
<3> AM335X_XLeft 40
AM335X_YUp DGND
<3> AM335X_YUp
Touch Screen Interface 54132-4097 DGND
41

42

DGND

DGND

B B

1.8V LDO 3.3V LDO

VBAT
V1_8D VBAT
U13 V3_3D 1500mA MAX
2 4 U3
IN OUT 2 4
1 IN OUT
VMMC EN 5 VMMC 1
FB EN 5
6 3 C162 C152 FB
GND GND 0.01uF 2.2uF 6 3 C19 C26 C20
VBAT TPS79518 VBAT GND GND 0.01uF 4.7uF 0.01uF
TPS78633

DGND
C154 DGND
1uF DGND C25
2.2uF, 10V DGND

DGND
DGND

A A

Texas Instruments, Inc.

ARM MPU Business Unit
12500 TI Blvd
Dallas, TX 75243
Preliminary
TMDSSK3358
LCD_Power
Size Document Number Modified By: Rev
C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 9 of 17
5 4 3 2 1
 5 4 3 2 1

D D

SD/MMC Connector

VDDSHV4

R4 R3 R1 R2 R5
10K 10K 10K 10K 10K

C C

VDDSHV6

R11
470K

J4
1 9 DGND
<2> AM335X_MMC0_D2 2 DAT2 GND 10
<2> AM335X_MMC0_D3 CD/DAT3 CD
3 11 VDDSHV4
<2> AM335X_MMC0_CMD AM335X_SPI0_CS1 <3>

microSD
4 CMD GND3 12
VDDSHV4 VDD GND4
5 13
<2> AM335X_MMC0_CLK CLOCK GND5
6 14
7 VSS GND6 15
<2> AM335X_MMC0_D0 DAT0 GND7

3
5
2
8 16
<2> AM335X_MMC0_D1 DAT1 GND8 C1 C3

IO1
IO2
NC
SCHA5B0200 0.1uF 4.7uF
U2
DGND TPD2E001

GND
VCC
CHASSIS_SD
FB12 DGND
1 2

4
150OHM800mA

DGND CHASSIS_SD
VDDSHV6

DGND
B B
U1
AM335X_MMC0_D0 8 9
AM335X_MMC0_D1 7 IO6 NC2 4
AM335X_MMC0_D2 6 IO5 NC1
AM335X_MMC0_D3 3 IO4 5
IO3 GND DGND
AM335X_MMC0_CMD 2
AM335X_MMC0_CLK 1 IO2 10
IO1 VCC VDDSHV4
TPD6E001

A A

Texas Instruments, Inc.

ARM MPU Business Unit
12500 TI Blvd
Dallas, TX 75243

TMDSSK3358
SDMMC Interface

Size Document Number Modified By: Rev

C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 10 of 17
5 4 3 2 1
 5 4 3 2 1

D D
USB1 Port

VUSB_VBUS1

C193
4.7uF

DGND
J5
S1
L2 4 S1
1 4 USB1_CONN_DP 3 GND
<3> USB1_DP DP
USB1_CONN_DM 2
2 3 1 DM
<3> USB1_DM VBUS S2
V5_0D ACM2012 S2
USB A
U18
2 6 VUSB_VBUS1 DGND CHASSIS_USB1
3 IN OUT 7
IN OUT 8
USB1_VBUS_EN 4 OUT U17
<3> AM335X_USB1_DRVVBUS EN 5 1 6
OC AM335X_USB1_OC <3> D+ VBUS
1 C190 FB1 150OHM800mA
GND 2 0.01uF
TPS2051BD R102 D- 5
C C
R127 10K 3 NC
10K ID 4
DGND GND DGND CHASSIS_USB1
VDDSHV6 TPD4S012

DGND DGND

USB1 Power

B B

L4 4.7uH

U20
VBAT VMMC VBAT B1 D1 V5_0D
B2 L1 L2 D2
L1 L2
A1 E1
A2 VIN VOUT E2
VIN VOUT
B3
C24 C23 R120 A3 VINA1 E3 USB5V_FB C207 C21 C22
DNI 4.7uF 100K VINA FB 2.2uF, 10V 22uF 22uF
V5_0D_EN A4 C1 R19
EN PGND C2 1.62M
C4 PGND
D4 PS C3
DGND VSEL GND D3 DGND
B4 GND E4
SYNC GND
C198 TPS63010 R18
0.1uF 180K
DGND

DGND DGND

DGND

A A

Texas Instruments, Inc.

ARM MPU Business Unit
12500 TI Blvd
Dallas, TX 75243

TMDSSK3358
USB1
Size Document Number Modified By: Rev
C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 11 of 17
5 4 3 2 1
 5 4 3 2 1

3.3V POWER INPUT +1.1V

VDDL_PHY

V3_3D VETH_AVDD_3_3 VADDL_PHY FB17 600mAFB10ohm 4.7uH L5 VETH_LX

C40

C54

C66

C48
FB16 600mAFB10ohm

VETH_AVDD_3_3
C224 C205 C216

VETH_VDDIO
0.1uF 0.1uF 10uF

VDDH_PHY
0.1uF

0.1uF

0.1uF

0.1uF

V3_3D
C222 C219
0.1uF 10uF
D D

DGND
DGND

DGND

U23

13

19

44

47

16

10

29
8

3
ETHER_D0P
36 11 ETHER_D0P ETHER_D0N

AVDDL

AVDDL

AVDDL

AVDDL

DVDDL

VDD33

AVDD33

VDDH_REG

VDDIO_REG

LX
<3> AM335X_RGMII1_TXD0 TXD0 TRXP0
37 12 ETHER_D0N
<3> AM335X_RGMII1_TXD1 38 TXD1 TRXN0 ETHER_D1P J6
<3> AM335X_RGMII1_TXD2 TXD2
39 14 ETHER_D1P ETHER_D1N 10
<3> AM335X_RGMII1_TXD3 TXD3 TRXP1 15 9
ETHER_D1N
R204 22 ETH1_RXD0 31 TRXN1 ETHER_D2P 8
<3> AM335X_RGMII1_RXD0 RXD0
R203 22 ETH1_RXD1 30 17 ETHER_D2P ETHER_D2N 7
<3> AM335X_RGMII1_RXD1 28 RXD1 TRXP2 18 6
R69 22 ETH1_RXD2 ETHER_D2N
<3> AM335X_RGMII1_RXD2 RXD2 TRXN2
R71 22 ETH1_RXD3 27 5
<3> AM335X_RGMII1_RXD3 RXD3 20 4
ETHER_D3P ETHER_D3N
34 TRXP3 21 ETHER_D3N ETHER_D3P 3
<3> AM335X_RGMII1_TXEN TX_EN TRXN3 2
R206 22 ETH1_RXDV 32 1
<3> AM335X_RGMII1_RXDV RX_DV 46
R208 22 ETH1_RXCLK 33 SIP 45 D1
<3> AM335X_RGMII1_RXCLK RX_CLK SIN D2
35 43 VDDL_PHY PHY_LED_ACTn R6 220
<3> AM335X_RGMII1_TXCLK GTX_CLK SOP 42 D3
SON PHY_LED_1000n R7 220 D4
R190 22 CLK_25M 25 41 R170 DNI
<13> CLK_25M_R CLK_25M SD RJ-45 Gigabit

M1
M2

SHLD1
SHLD2
TP7 R176 22 PHY_PPS/GPIO 22 1
C201 27pF PPS MDC 48 AM335X_RGMII1_MDIO_CLK <3,13>
ETH_RESETn 2 MDIO AM335X_RGMII1_MDIO_DATA <3,13>
RST
2

7 23 PHY_LED_ACTn
Y4 6 XTLI LED_ACT
DGND XTLO
25MHz 24 PHY_LED_1000n DGND
ETH1_RBIAS 9 LED_LINK1000 CHASSIS_ETH1
C C
1

RBIAS 26 PHY_LED_10/100n
C202 27pF 0 R122 ETH1_INTn 5 LED_LINK10_100
<2> RGMII1_INT INT
DNI R173 WOL_INT_1 40 C240 C229 C226

EP
<3,13> AM335X_EXT_WAKEUP WOL_INT DNI DNI DNI
DNI R124 AR8031_AL1A

49
<2,6,13> AM335x_EXTINT
R146
2.37K C9 0.1uF

DGND
DGND C10 0.1uF

DGND

DGND CHASSIS_ETH1

B B

Decaps Power SEL

Pull ups PHY Address Bootstrapping Reset

VETH_VDDIO VDDH_PHY
VETH_VDDIO

VDDH_PHY
VDDSHV1

V3_3D
VRTC

MODE SELECTION
R55 0 PHYADDRESS = 00000 Mode "0000" = 1000 BASE-T, RGMII
C38 C39
0.1uF 1uF VDDSHV6
C73 C41 ANA_MOD (IPU) PHY_LED_ACTn R53 10K MODE2[0] ETH1_RXDV R207 10K
0.1uF 1uF

5
DGND DGND PHYADDRESS LSB ETH1_RXD0 R205 10K MODE2[1] ETH1_RXD2 R68 10K U6 VDDSHV6
R25 R30
DNI 1.5K PHYADDRESS ETH1_RXD1 R202 10K MODE2[2] ETH1_RXCLK R209 10K 2 4 ETH_RESETn
<2,6,14,17> SYS_WARMRESETn ETH_RESETn <13>
DGND DGND
AM335X_RGMII1_MDIO_CLK MODE2[3] ETH1_RXD3 R70 10K C206
SN74LVC1G07 0.01uF

1
3
AM335X_RGMII1_MDIO_DATA SEL_GPIO_INT PHY_LED_1000n R60 10K

WOL_INT_1 R178 10K DGND

DGND DGND
ETH1_INTn R123 10K DGND

ETH_RESETn R26 100K

A A

Texas Instruments, Inc.

ARM MPU Business Unit
12500 TI Blvd
Dallas, TX 75243

TMDSSK3358
RGMII1
Size Document Number Modified By: Rev
C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 12 of 17
5 4 3 2 1
 5 4 3 2 1

+1.1V
VDDL_PHY2

VADDL_PHY2 FB14 600mAFB10ohm 4.7uH L3 VETH2_LX

C65

C47

C36

C58
V3_3D VETH2_AVDD_3_3
D D
C223 C199 C200

0.1uF

0.1uF

0.1uF

0.1uF
FB15 600mAFB10ohm 0.1uF 0.1uF 10uF

VETH2_AVDD_3_3
C218 C204 DGND
0.1uF 10uF DGND

VETH2_VDDIO
V3_3D

VDDH_PHY2
DGND

U24

13

19

44

47

16

10

29
8

3
36 11 ETHER2_D0P ETHER2_D0P

AVDDL

AVDDL

AVDDL

AVDDL

DVDDL

VDD33

AVDD33

VDDH_REG

VDDIO_REG

LX
<2> AM335X_RGMII2_TXD0 TXD0 TRXP0
<2> AM335X_RGMII2_TXD1 37 12 ETHER2_D0N ETHER2_D0N
38 TXD1 TRXN0
<2> AM335X_RGMII2_TXD2 TXD2
39 14 ETHER2_D1P ETHER2_D1P J7
<2> AM335X_RGMII2_TXD3 TXD3 TRXP1 15 ETHER2_D1N ETHER2_D1N 10
R195 22 ETH2_RXD0 31 TRXN1 9
<2> AM335X_RGMII2_RXD0 RXD0
<2> AM335X_RGMII2_RXD1 R194 22 ETH2_RXD1 30 17 ETHER2_D2P ETHER2_D2P 8
R65 22 ETH2_RXD2 28 RXD1 TRXP2 18 ETHER2_D2N ETHER2_D2N 7
<2> AM335X_RGMII2_RXD2 RXD2 TRXN2
R67 22 ETH2_RXD3 27 6
<2> AM335X_RGMII2_RXD3 RXD3 20 ETHER2_D3P 5
34 TRXP3 21 ETHER2_D3N ETHER2_D3N 4
<2> AM335X_RGMII2_TXEN TX_EN TRXN3 ETHER2_D3P 3
R197 22 ETH2_RXDV 32 2
<2> AM335X_RGMII2_RXDV RX_DV 46 1
R200 22 ETH2_RXCLK 33 SIP 45
<2> AM335X_RGMII2_RXCLK RX_CLK SIN D1
35 43 VDDL_PHY2 D2
<2> AM335X_RGMII2_TXCLK GTX_CLK SOP 42 PHY2_LED_ACTn R8 220
SON D3
C 25 41 R169 DNI PHY2_LED_1000n R9 220 D4 C
R24 22 CLK_25M SD
<12> CLK_25M_R
TP8 R181 22 PHY_PPS2/GPIO 22 1 ETH_MDIO_CLK R147 22 RJ-45 Gigabit
AM335X_RGMII1_MDIO_CLK <3,12>

M1
M2

SHLD1
SHLD2
PPS MDC 48 ETH_MDIO_DATA R148 22
2 MDIO AM335X_RGMII1_MDIO_DATA <3,12>
ETH_RESETn
<12> ETH_RESETn RST
C208 DNI XTALIN_2 7 23 PHY2_LED_ACTn
XTALOUT_2 6 XTLI LED_ACT
XTLO
2

24 PHY2_LED_1000n
Y1 ETH2_RBIAS 9 LED_LINK1000 DGND CHASSIS_ETH2
DGND RBIAS
DNI 26 PHY2_LED_10/100n
R20 0 ETH2_INTn 5 LED_LINK10_100
<3> RGMII2_INT
1

INT
C209 DNI R189 DNI WOL_INT2 40

EP
<3,12> AM335X_EXT_WAKEUP WOL_INT
AR8031_AL1A 49 C237 C81 C68 C8 0.1uF
R21 DNI DNI DNI DNI
<2,6,12> AM335x_EXTINT R145
2.37K C17 0.1uF

DGND
DGND

DGND CHASSIS_ETH2
DGND

B B

Decaps Power SEL Pull ups

PHY Address
BootStrapping
VDDH_PHY2

PHYADDRESS = 00001
VDDSHV3

VETH2_VDDIO VDDH_PHY2
V3_3D
VRTC

VETH2_AVDD_3_3 MODE SELECTION

Mode "0000" = 1000 BASE-T, RGMII

C34 C35 R54 0

0.1uF 1uF PHYADDRESS0 (IPD) ETH2_RXD0 R196 10K MODE2[0] ETH2_RXDV R198 10K

PHYADDRESS2 PHY2_LED_ACTn R62 10K MODE2[1] ETH2_RXD2 R64 10K

DGND DGND C71 C37
0.1uF 1uF PHYADDRESS1 (IPD) ETH2_RXD1 R193 10K MODE2[2] ETH2_RXCLK R199 10K

MODE2[3] ETH2_RXD3 R66 10K

DGND DGND ETH2_INTn R22 10K

WOL_INT2 R175 10K SEL_GPIO_INT PHY2_LED_1000n R61 10K

ETH_RESETn R47 DNI DGND

DGND

A A

Texas Instruments, Inc.

ARM MPU Business Unit
12500 TI Blvd
Dallas, TX 75243

TMDSSK3358
RGMII2
Size Document Number Modified By: Rev
C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 13 of 17
5 4 3 2 1
 5 4 3 2 1

D D

Audio Codec

U31
R87 0 AUD_RESETn 33 31
<2,6,12,17> SYS_WARMRESETn RESETn RIGHT_ROP
I2C_SCL_AUDIO 1 32
<14> I2C_SCL_AUDIO 2 SCL RIGHT_ROM
I2C_SDA_AUDIO
<14> I2C_SDA_AUDIO SDA 29
AUD_MCLK 37 LEFT_LOP
<2> AM335X_XDMA_EVENT_INTR0 MCLK
AUD_FSX 39 30
<3> AM335X_AUDA_FSX WCLK LEFT_LOM
AUD_BCLK 38
<3> AM335X_AUDA_BCLK 40 BCLK
AUD_DIN
<3> AM335X_AUDA_DIN DIN
AUD_DOUT 41 23 HD_SPKRP
<3> AM335X_AUDA_DOUT DOUT HPROUT 18 HS_SPKRP
48 HPLOUT
TP14 35 MFP3 22 HD_SPKRM TP21
V3_3AUD GPIO1 HPRCOM
TP16 34 19 HS_SPKRM TP24
GPIO2 HPLCOM
45 14
V3_3D MFP0 MIC3R
C177 C278 46 12
10uF 0.1uF 47 MFP1 MICDET
MFP2 13
MICBIAS 11
25 MIC3L 7
AVDD_DAC LINE2LP 8
AGND_AUD LINE2LM
16 3
V3_3AUD DRVDD LINE1LP
C V3_3AUD 17 4 C
24 DRVDD LINE1LM
DRVDD 5
44 LINE1RP 6
V3_3D IOVDD LINE1RM
V1_8D 36 27
DVDD MONO_LOP 28
43 MONO_LOM
42 SELECT 9
C178 C179 C139 DVSS LINE2RP 10
10uF 10uF 10uF C270 LINE2RM
10uF 15
C281 C280 C272 C276 26 AVSS_ADC
0.1uF 0.1uF 0.1uF 0.1uF AVSS_DAC

TPAD
20
21 DRVSS
DRVSS C163 C160 C157 C161 C155 C153 C150 C146 C159 C156 C164 C166
TLV320AIC3106 0.01uF 0.01uF 0.01uF 0.01uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF

TPAD
AGND_AUD

DGND

AGND_AUD AGND_AUD AGND_AUD

B B

J13
1 FB10
HS_SPKRP C181 47uF 3 V3_3D V3_3AUD

150OHM800mA
10 FB11
HD_SPKRP C185 47uF 2
AGND_AUD DGND
150OHM800mA

3.5mm SJ3524

AGND_AUD

A A

Texas Instruments, Inc.

ARM MPU Business Unit
12500 TI Blvd
Dallas, TX 75243

TMDSSK3358
Audio
Size Document Number Modified By: Rev
C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 14 of 17
5 4 3 2 1
 5 4 3 2 1

D D

Keypad Switches
VDDSHV3

KEYPAD_PWRA R115 0 VDDSHV1

2
1

2
1

2
1

2
1
SW3 SW1 SW2 SW4
B3SL B3SL B3SL B3SL

4
3

4
3

4
3

4
3
KEYPAD_SCN0
GPIO_KEY1 <2>

KEYPAD_SCN1
GPIO_KEY2 <2>

KEYPAD_SCN2
GPIO_KEY3 <2>

KEYPAD_SCN3
GPIO_KEY4 <2>

C R215 R165 R172 R231 C

2.2K 2.2K 2.2K 2.2K

C243 C220 C228 C263

1uF 1uF 1uF 1uF

DGND DGND DGND DGND

Accelerometer
B B

V3_3D

U10 V3_3D V3_3D

4 1
<3,5,6> AM335X_I2C0_SCL SCL/SPC VDD_IO
6
<3,5,6> AM335X_I2C0_SDA SDA/SDI/SDO 14
7 VDD C274 C275
R86 10K 8 SDO/SA0 2 0.01uF 0.01uF
V3_3D CS NC0 3
11 NC1 15
<3> ACC_INT1 INT1 RSV1
9 DGND DGND
<3> ACC_INT2 INT2
R244 DNI 5
GND 12
GND 13
R85 10 GND 16
0 RSV0 GND
LIS331DLH

DGND DGND
DGND

A A

Texas Instruments, Inc.

ARM MPU Business Unit
12500 TI Blvd
Dallas, TX 75243

TMDSSK3358
Keypad_Gyro

Size Document Number Modified By: Rev

C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 15 of 17
5 4 3 2 1
 5 4 3 2 1

USB HUB

D D

USB CONNECTOR

USB_DC
J3
S4
L1 1 S4 S3 USB_DC
HUB_USBDP_UP 1 4 USBDP_UP USBDM_UP 2 VBUS S3
USBDP_UP 3 DM
DP CHASSIS_USB0
HUB_USBDM_UP 2 3 USBDM_UP 4 C2
5 ID S2 4.7uF
ACM2012 GND S2 S1
S1
USB_DC USB_MicroAB DGND
U15 DGND
1 6
D+ VBUS
2 FB13
D- 5 C188
USB_DC 3 NC 0.01uF
ID 4 150OHM800mA
GND
TPD4S012 DGND CHASSIS_USB0
DGND
R103 U16
100K Upstream
22 HUB_USBDP_UP
VBUS_DET 18 USBDP_UP 21 HUB_USBDM_UP
VBUS_DET USBDM_UP V5_0D

R101
100K Downstream 1USBDP_DN1 1
FT_DP <17>
R15
28 4.7K
USBDM_DN1 FT_DM <17>
C 8 U5B C
OCS1 7
PRTPWR1 FT_VBUS <17>
DGND
3 4
3 USB0_VBUS <3>
DownstreamUSBDP_DN2
2 USB0_DP <3>
12 2 V3_3D SN74LVC2G07
OCS2 USBDM_DN2 USB0_DM <3>
V3_3D 11 USB0_VBUS_PWR
PRTPWR2
R118 R13
NON_REM[0:1]/nc NC 5 DNI DNI

R106 13 NON_REM1
100K NON_REM1 19 NON_REM2 TP1
SUSP_IND/NON_REM0

RESETn 17 26 HUB_BIAS R99 12.1K, 1% DGND R119 R12

RESET RBIAS 10K, 1% 100K
Common V3_3D
6
C189 TEST 14
0.1uF VDD33 10
DGND VDDCRREF/VDD33
DGND DGND
DGND C16 C12 C15
C6 18pF, 10V, 2% XTALIN 24 0.1uF 4.7uF 0.1uF
XTALIN/CLKIN
4
VDD33
3

20 DGND DGND DGND

Y3 4 2 VDD33 27
R10 24MHz VDDPLLREF/VDD33
DNI
1

C13 C11 C5 C14

0.1uF 0.1uF 0.1uF 1uF
C4 18pF, 10V, 2% XTALOUT 23
XTALOUT
9 CRFILT
B
HS_IND 16 CRFILT B
HS_IND DGND

DGND R14
100K R109 0 rsvd3 15 25 PLLFILT
VSS PLLFILT
29
VSS(FLAG)
C7 C195
USB2412_QFN28 1uF 1uF
DGND DGND

DGND DGND

A A

Texas Instruments, Inc.

ARM MPU Business Unit
12500 TI Blvd
Dallas, TX 75243

TMDSSK3358
USB_HUB
Size Document Number Modified By: Rev
C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 16 of 17
5 4 3 2 1
 5 4 3 2 1

D USB - UART (Optional) D

VDD_1V8FT

V3_3D

C134 C241 C251 C253

4.7uF 0.1uF 0.1uF 0.1uF VDD_FTVPLL
VDD_FTVPHY V3_3D

12
37
64

20
31
42
56
4
9
U28
DGND

VPLL

VCORE.1
VCORE.2
VCORE.3

VCCIO.1
VCCIO.2
VCCIO.3
VCCIO.4
VPHY
16 F_ADBUS0 R75 0 V3_3D
ADBUS0 JTAG_TCK <2> V3_3D
17 F_ADBUS1 R227 0 R16
ADBUS1 JTAG_TDI <2>
FB18 150OHM800mA VDD_FTREGIN 50 18 F_ADBUS2 R228 0 DNI
V3_3D VREGIN ADBUS2 JTAG_TDO <2>
19 F_ADBUS3 R79 0 C196 0.1uF
ADBUS3 JTAG_TMS <2>
49 21 F_ADBUS4 R229 0 C194 0.1uF
VREGOUT ADBUS4 22 JTAG_TRSTn <2>
ADBUS5 23 F_ADBUS6 R230 0
ADBUS6 JTAG_EMU0 <2>
7 24 U4 DGND
<16> FT_DM DM ADBUS7

5
8 DGND U5A
<16> FT_DP DP 26 F_ADBUS5 R78 0 FT_SRESET 1
ACBUS0 27 4 FT_SRESETn 1 6 FT_SRESETB R17 0
ACBUS1 SYS_WARMRESETn <2,6,12,14>
DGND R214 12.1K, 1% FT_REF 6 28 V3_3D FT_VBUS 2
REF ACBUS2 29
ACBUS3 30 F_ADBUS7 R77 0 SN74LVC1G00DCK SN74LVC2G07
JTAG_EMU1 <2>

2
R221 2.2K FT_RESETn 14 ACBUS4 32 4.75K, 1%
V3_3D RESET# ACBUS5 33
C234 27pF XTIN ACBUS6 34
DGND ACBUS7 DGND DGND DGND
2 38
XTIN BDBUS0 AM335X_UART0_RXD <3>
C 39 AM335X_UART0_TXD <3> DGND C
Y5 3 BDBUS1 40
XTOUT BDBUS2 AM335X_UART0_CTSn <3>
12MHz,+/-50ppm 41 AM335X_UART0_RTSn <3,5>
BDBUS3 43
C233 27pF XTOUT BDBUS4 44
DGND BDBUS5 45
BDBUS6 46
10K, 1% R76 F_EECS 63 BDBUS7 V3_3D
EECS 48
10K, 1% R82 F_EESK 62 BCBUS0 52
V3_3D EESK BCBUS1 53
10K, 1% R83 F_EEDOUT R81 2.2K F_EEDATA 61 BCBUS2 54
EEDATA BCBUS3 55 R110
BCBUS4 57 10K, 1%
13 BCBUS5 58
TEST BCBUS6 59
BCBUS7 FT_VBUS <16>
60
PWREN# 36
GND.1
GND.2
GND.3
GND.4
GND.5
GND.6
GND.7
GND.8
SUSPEND#
AGND

DGND

FT2232HL
10

1
5
11
15
25
35
47
51

DGND

B FILTERS B
V3_3D

FB20 150OHM800mA VDD_FTVPLL

JTAG
FB19 150OHM800mA VDD_FTVPHY

J12
C242 C248 JTAG_TMS 1 2 JTAG_TRSTn R235 DNI
0.1uF 0.1uF V3_3D JTAG_TDI 3 TMS TRSTn 4 TDIS R236 DNI
TDI TDIS DGND
C184 DNI 5 6
DGND TVDD NC
JTAG_TDO 7 8
JTAG_TCK R92 DNI RTCK 9 TDO GND 10
TCKRTN GND DGND
DGND R91 DNI TCK 11 12
R90 DNI JTAG_EMU0 13 TCK GND 14 JTAG_EMU1 R234 DNI
V3_3D EMU0 EMU1 V3_3D
R97 DNI EMU_RSTn 15 16
V3_3D EEPROM <6,12,14,17> SYS_WARMRESETn
EMU2 17 SRST GND 18 EMU3 TP18
U9 TP20 EMU4 19 EMU2 EMU3 20
6 5 F_EECS TP22 EMU4 GND
VCC CS 4 F_EESK C183 DNI
SK 3 F_EEDATA DNI
2 DIN 1 F_EEDOUT DGND
GND DOUT
93LC56B DGND

DGND

FT2232 DECAPS

V3_3D

A A

Frost Byte 1

C265
0.1uF
C133
0.1uF
C266
0.1uF
C246
0.1uF
Texas Instruments, Inc.
ARM MPU Business Unit
12500 TI Blvd
Dallas, TX 75243

TMDSSK3358
DGND USB_UART
Size Document Number Modified By: Rev
C TMDSSK3358_1.2A.dsn Radha 1.2A
Date: Friday, August 10, 2012 Sheet: 17 of 17
5 4 3 2 1