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Transistor-Transistor Logic (TTL) Gates: Objectives

This document describes an experiment on Transistor-Transistor Logic (TTL) gates. The objectives are to become familiar with TTL circuits, study the internal connections of AND, OR, NAND and NOR gates, determine the voltage transfer characteristics (VTC) of these gates, and compare TTL to Diode-Transistor Logic (DTL). The document explains the basic TTL inverter circuit and how NAND, AND, NOR and OR gates are constructed using TTL inverters. It provides truth tables and voltage characteristics for each gate. The procedure involves building circuits in Orcad for the NAND, AND, NOR and OR gates and obtaining their VTCs.

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118 views6 pages

Transistor-Transistor Logic (TTL) Gates: Objectives

This document describes an experiment on Transistor-Transistor Logic (TTL) gates. The objectives are to become familiar with TTL circuits, study the internal connections of AND, OR, NAND and NOR gates, determine the voltage transfer characteristics (VTC) of these gates, and compare TTL to Diode-Transistor Logic (DTL). The document explains the basic TTL inverter circuit and how NAND, AND, NOR and OR gates are constructed using TTL inverters. It provides truth tables and voltage characteristics for each gate. The procedure involves building circuits in Orcad for the NAND, AND, NOR and OR gates and obtaining their VTCs.

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Hassan alla
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Islamic University of Gaza Digital Electronics Lab (EELE 3121)

Faculty of Engineering Eng. Mohammed S. Jouda


Electrical Engineering department Eng. Amani S. abu reyala

Experiment 6 Transistor-Transistor Logic (TTL) Gates

Objectives

 Be familiar with the Transistor –Transistor Logic TTL circuits.


 Studying the internal connection of AND, OR, NAND and NOR.
 To determine the VTC of these gates.
 To find the advantages of this family over DTL family.

Introduction

Looking at the DTL input circuit; we note that the two diodes are opposite to
each other in direction. That is, there P_ anode are connected together and to the pull
up resistor, while on cathode is the signal input and the other is connected to the
transistor's base. This gives rise to a bit of speculation; could we perhaps replace these
two diodes with a single NPN–transistor.
If it works, we can also make use of the fact that the amount space required by a
transistor in an IC is essential the same as the space required by a diode. Thus, we can
make the IC smaller by eliminating the space required by one of the two diodes

Theoretical Background

 The Basic TTL Inverter


Figure1 shows the proposed change to convert a DTL inverter to a Transistor-
Transistor logic TTL equivalent. We have merely used one transistor to replace two
diodes.

Figure 1. The TTL inverter


If the input is less than VIL = VBE, 2(FA) – VCE, 1(sat) then the BJT (Q2) is cutoff.
As a result the output voltage is
VOH = VCC.
If the input is greater than or equal to VIL, the corresponding BJT conduct and if the
input reaches VIH = VBE, 2(sat) – VCE, 1(sat) the output drops to
VOL = VCE (sat).

 The NAND Gate

Figure 2 shows a two input TTL NAND gate. A multiple emitter BJT is used to
provide the inputs to the gate. A separate BJT could be used for each input with
coupled collectors. An advantage of the multiple emitters BJT is that it requires much
less chip area than using individual resistors.

Figure 2. Two-input NAND Gate

If the input is less than VIL = VBE, 2(FA) – VCE, 1(sat) then the BJT (Q2) is cutoff.
As a result the output voltage is
VOH = VCC.
If all inputs are greater than or equal to VIL, the BJT (Q2) conduct and if they reach
VIH = VBE, 2(sat) – VCE, 1(sat) the output drops to
VOL = VCE (sat).

 The AND Gate

The TTL AND gate combines the TTL NAND Gate with TTL Inverter.
Figure 3 shows a two-input AND Gate.

Figure 3. Two-input AND Gate


if any input is less than VIL = VBE,2(FA) – VCE,1(sat), the transistor Q(2) is cutoff
and Q is saturated, the output is
VOL = VCE (sat).

If all inputs reach VIL = VBE,2(FA) – VCE,1(sat), the output is

VOH = VCC.

 The NOR Gate

Figure 4 shows the schematic diagram of a TTL NOR Gate. As you recall
from earlier experiments, it is substantially the same as the RTL and DTL NOR Gates
we have already explored. The only difference is that this time we are using the TTL
input circuit.

Figure 4. Two-input NOR Gate

If all inputs are less than VIL = VBE, 2(FA) – VCE, 1(sat) then both BJT's (Q2, Q4)
is cutoff. As a result the output voltage is

VOH = VCC.

If any input is greater than or equal to VIL, the corresponding BJT conduct and if it
reaches VIH = VBE, 2(sat) – VCE, 1(sat) the output drops to

VOL = VCE (sat).


 The OR Gate

The TTL OR gate combines the TTL NOR Gate with TTL Inverter. Figure 5
shows a two-input OR Gate.

Figure 5. Two-input OR Gate

If all inputs are less than VIL = VBE, 2(FA) – VCE, 1(sat) then both BJT's (Q2, Q4)
is cutoff, and Q6 is saturated. As a result the output voltage is
VOL = VCE (sat).
Procedure:

Part 1:

1. Construct the circuit shown in Figure 2, V = 5V, RC= 1K, RB =10K


2. Find the truth table filling the following

VA VB VOUT
0 0
0 5
5 0
5 5

3. Filling the following table by making VA = VB = VIN and Draw the VTC of
this gate :

Vin 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 3 4 5
Vout

4. Determine VOH,VOL,VIH,VIL
5. Draw the VTC of this gate by using the Orcad.

Part 2:

Draw the VTC of the circuit shown in Figure 3 by using the Orcad and show
the results.

V = 5V, RC= 1K, RB =10K


Part 3:
1. Construct the circuit shown in Figure 4, V = 5V, RC= 1K, RB =10K
2. Find the truth table filling the following

VA VB VOUT
0 0
0 5
5 0
5 5

3. Filling the following table by making VA = VB = VIN and Draw the VTC of
this gate :

Vin 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 3 4 5
Vout

4. Determine VOH,VOL,VIH,VIL
5. Draw the VTC of this gate by using the Orcad.

Part 4:

Draw the VTC of the circuit shown in Figure 5 by using the Orcad and show
the results.

V = 5V, RC= 1K, RB =10K

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