L6388

HIGH-VOLTAGE HIGH AND LOW SIDE DRIVER

1 FEATURES Figure 1. Package

■ HIGH VOLTAGE RAIL UP TO 600 V
■ dV/dt IMMUNITY ± 50 V/nsec IN FULL
TEMPERATURE RANGE
■ DRIVER CURRENT CAPABILITY:400 mA
( s ) SO8 DIP8

SOURCE,650 mA SINK
c t
Table 1. Order Codes
■ SWITCHING TIMES 70/40 nsec RISE/FALL
WITH 1nF LOAD
d u Part Number Package

■ 3.3V, 5V, 15V CMOS/TTL INPUTS

r o s) L6388 DIP8

COMPARATORS WITH HYSTERESYS AND P c t( L6388D SO8

PULL DOWN

e t e u L6388D013TR SO8 in Tape & Reel

■ INTERNAL BOOTSTRAP DIODE

o l rod It has a Driver structure that enables to drive inde-
■

■
OUTPUTS IN PHASE WITH INPUTS
DEAD TIME AND INTERLOCKING FUNCTION
b s P pendent referenced N Channel Power MOS or IG-
BT. The Upper (Floating) Section is enabled to

- O ete work with voltage Rail up to 600V.

2 DESCRIPTION
s ) o l The Logic Inputs are CMOS/TTL compatible for

t (
The L6388 is an high-voltage device, manufac-

b s
tured with the BCD"OFF-LINE" technology.
c
ease of interfacing with controlling devices.

Figure 2. Block Diagram

d u -O
r o s)
P
e uc t (
e t
l od BOOTSTRAP DRIVER

o
s Pr
8 Vboot

b
O ete
VCC 3 UV
DETECTION
UV
DETECTION R
HVG
DRIVER
H.V.
Cboot

o l LOGIC
R
7
HVG

b s HIN
2
SHOOT
LEVEL
SHIFTER
S
OUT

O LIN
1
THROUGH
PREVENTION
VCC
6

5 LVG
TO LOAD

LVG
DRIVER 4 GND

Rev. 2
May 2005 1/11
L6388

Table 2. Absolute Maximum Rating

Symbol Parameter Value Unit
Vout Output Voltage -3 to Vboot - 18 V

Vcc Supply Voltage - 0.3 to +18 V

Vboot Floating Supply Voltage - 1 to 618 V
Vhvg High Side Gate Output Voltage - 1 to Vboot V
Vlvg Low Side Gate Output Voltage -0.3 to Vcc +0.3 V
Vi Logic Input Voltage -0.3 to Vcc +0.3 V
dVout/dt Allowed Output Slew Rate 50 V/ns
Ptot Total Power Dissipation (Tj = 85°C)
( s ) 750 mW
Tj Junction Temperature
c t 150 °C
Tstg Storage Temperature
d u -50 to 150 °C

r o s)
Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900V (Human Body Model)

Figure 3. Pin Connection (Top view) P c t(

e t e u
o
LINl rod 1 8 Vboot

b s P
HIN 2 7 HVG

- O ete VCC 3 6 OUT

s ) o l
GND 4 5 LVG

c t ( b s D97IN517A

d u -O
o s)
Table 3. Pin Description

r
N.
1 P
Name

e uc
LIN t ( Type
I Low Side Driver Logic Input
Function

2
e t
l od HIN I High Side Driver Logic Input
3
o
s Pr
Vcc I Low Voltage Power Supply

b4

O ete
5
GND
LVG (*) O
Ground
Low Side Driver Output

o l
6 OUT O High Side Driver Floating Reference

bs
7 HVG (*) O High Side Driver Output
8 Vboot Bootstrap Supply Voltage
O
(*) The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA). This allows to omit the "bleeder" resistor connected between the gate
and the source of the external MOSFET normally used to hold the pin low.

Table 4. Thermal Data

Symbol Parameter SO8 Minidip Unit

Rth j-amb Thermal Resistance Junction to Ambient 150 100 °C/W

2/11
 L6388

Table 5. Recommended Operating Conditions

Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
Vout 6 Output Voltage Note 1 580 V

VBS (*) 8 Floating Supply Voltage Note 1 17 V

fsw Switching Frequency HVG,LVG load CL = 1nF 400 kHz

Vcc 3 Supply Voltage 17 V

Tj Junction Temperature -45 125 °C

Note 1: If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V
(*): VBS = Vboot - Vout

( s )
Table 6. Electrical Characteristics
(Vcc = 15V; Tj = 25°C)
c t
Symbol Pin Parameter
d u Test Condition Min. Typ. Max. Unit
AC OPERATION
r o s)
ton 1 vs 5 High/Low Side Driver Turn-On P c t(
Vout = 0V 225 300 ns
2 vs 7 Propagation Delay

e t e u
toff
Propagation Delay
o l rod
High/Low Side Driver Turn-Off Vout = 0V 160 220 ns

tr 7,5 Rise Time

b s P CL = 1000pF 70 100 ns
tf 7,5 Fall Time
- O ete CL = 1000pF 40 80 ns
DT 7,5 Dead Time

s ) o l 220 320 420 ns

DC OPERATION

c t ( b s
Vccth1 3
d u -O
Low Supply Voltage Section
Vcc UV Turn On Threshold 9.1 9.6 10.1 V
Vccth2
r o s)
Vcc UV Turn Off Threshold 7.9 8.3 8.8 V
Vcchys P
e uc t (
Vcc UV Hysteresis 0.9 V
Iqccu
e t
l od Undervoltage Quiescent Supply Vcc ≤ 9V 250 330 µA

Iqcc o
s Pr
Current
Quiescent Current Vcc = 15V 350 450 µA
b
O ete
Rdson Bootstrap Driver on Resistance (**) Vcc 125 Ω

l
Bootstrapped Supply Voltage Section

o
bs
VBSth1 8 VBS UV Turn On Threshold 8.5 9.5 10.5 V
VBSth2 VBS UV Turn Off Threshold 7.2 8.2 9.2 V

O VBShys
IQBS
VBS UV Hysteresis
VBS Quiescent Current HVG ON
0.9
250
V
µA
ILK High Voltage Leakage Current Vhvg = Vout = Vboot = 600V 10 µA
High/Low Side Driver
Iso 5,7 Source Short Circuit Current VIN = Vih (tp < 10µs) 300 400 mA
Isi Sink Short Circuit Current VIN = Vil (tp < 10µs) 500 650 mA

3/11
L6388

Table 6. Electrical Characteristics (continued)

(Vcc = 15V; Tj = 25°C)
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
Logic Inputs
Vil 1, 2 Low Level Logic Input Voltage 1.1 V
Vih High Level Logic Input Voltage 1.8 V
Iih High Level Logic Input Current VIN = 15V 20 70 µA
Iil Low Level Logic Input Current VIN = 0V -1 µA

s ) ( V CC – V CBOOT1 ) – ( V CC – V CBOOT2 )
(**) RDSON is tested in the following way: R DSON = --------------------------------------------------------------------------------------------------------------

(
I 1 ( V CC, V CCBOOT1 ) – I 2 ( V CC, V CCBOOT2 )

c t
where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2.

Figure 4. Dead Time Waveforms Definitions

d u
r o s)
P c t(
LIN

e t e u
o l rod

Interlocking function
H IN

b s P DT DT

- O ete
LVG

s ) o l
( s
DT

c t b
d u -O HVG

r o s)
P t (
Figure 5. Propagation Delay Waveform Definitions
e uc
e t
l od
o
s Pr
b
O ete
LIN
50% 50% 50%

o l > DT > DT

bs
HIN 50% 50%

O LVG
ton

10%
toff
90%

ton
90%
HVG 10%
toff

4/11
 L6388

3 INPUT LOGIC
Input logic is provided with an interlocking circuitry which avoids the two outputs (LVG, HVG) to be active at the
same time when both the logic input pins (LIN, HIN) are at a high logic level. In addition, to prevent cross con-
duction of the external MOSFETs, after each output is turned-off the other output cannot be turned-on before a
certain amount of time (DT) (see Figure 4).

Figure 6. Typical Rise and Fall Times vs. Load Figure 7. Quiescent Current vs. Supply
Capacitance Voltage
time D99IN1054
Iq D99IN1055
(nsec) (µA)
250 104

200

( s )
150
Tr

c t103

Tf
d u
100

r o s) 102
50
P c t(
e t e u
l rod
0 10
0 1 2 3 4 5 C (nF)
o
s P
For both high and low side buffers @25˚C Tamb 0 2 4 6 8 10 12 14 16 VS(V)

3.1 BOOTSTRAP DRIVER b

O ete
) - l
A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a

t ( s s o
high voltage fast recovery diode (fig. 8a). In the L6388 a patented integrated structure replaces the external di-
ode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series
a diode, as shown in fig. 8b
c
u -O b
d
An internal charge pump (fig. 8b) provides the DMOS driving voltage .

o s)
P r
The diode connected in series to the DMOS has been added to avoid undesirable turn on of it.

(
e uc t
3.2 CBOOT selection and charging
t
e
l od
To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor

o
CEXT is related to the MOS total gate charge :

b s Pr Q gate
C EXT = ---------------

O ete V gate

o l
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss .
It has to be:

O bs CBOOT>>>CEXT

e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV.
If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses.
e.g.: HVG steady state consumption is lower than 200µA, so if HVG TON is 5ms, CBOOT has to supply 1µC to
CEXT. This charge on a 1µF capacitor means a voltage drop of 1V.
The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually
has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile
the LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are fulfilled and it

5/11
L6388

has to be long enough to charge the capacitor.

The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ohm). At low fre-
quency this drop can be neglected. Anyway increasing the frequency it must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Q gate
V drop = I ch arg e R dson → V drop = -------------------- R dson
T ch arg e
where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS,
and Tcharge is the charging time of the bootstrap capacitor.
For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about
1V, if the Tcharge is 5µs. In fact:
30nC
s )
V drop = --------------- ⋅ 125Ω ∼ 0.8V
(
5µs

c t
d u
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the
circuit topology doesn't allow a sufficient charging time, an external diode can be used.

Figure 8. Bootstrap Driver.

r o s)
P c t(
DBOOT
e t e u
o l rod
VS

b s P VBOOT

- O ete H.V.

s ) o l HVG

(
CBOOT

c t b s VOUT

d u -O TO LOAD

r o s) LVG

P
e uc at (
e t
l od
o
s Pr
b
O ete VS
VBOOT

o l H.V.

bs
HVG
CBOOT

O VOUT
TO LOAD

LVG

6/11
 L6388

Figure 9. VBOOT UV Turn On Threshold vs. Figure 12. VCC UV Turn Off Threshold vs.
Temperature Temperature

13 11

12 @ Vcc = 15V
10
11
Typ.
10

Vccth2(V)
9
VBSth1(V)

9 Typ.
8
8
7
7
6

( s )
5
-45 -25 0 25 50 75 100 125
c t 6
-45 -25 0 25 50 75 100 125
Tj (˚C)
d u Tj (˚C)

r o s)
Figure 10. VBOOT UV Turn Off Threshold vs.
P c t( Figure 13. Output Source Current vs.
Temperature
Temperature

e t e u
14
o l rod 1000
@ Vcc = 15V
13

b s P@ Vcc = 15V 800

O ete
12
current (mA)

11

) - l
600
VBSth2(V)

Typ.
10

t ( s s o 400
9
8 c
u -O b 200
7
Typ.
d
o s)
6
P r (
0
-45 -25 0 25 50 75 100 125

t
-45

e uc t -25 0 25 50 75 100 125 Tj (˚C)

o e
l od
Figure 11. VCC UV Turn On Threshold vs. Figure 14. Output Sink Current vs.

b s Pr
Temperature Temperature

O ete 13 1000

o l 12
800
@ Vcc = 15V

bs 11
current (mA)
Vccth1(V)

600

O 10
Typ. 400
Typ.

9
200
8

7 0
-45 -25 0 25 50 75 100 125 -45 -25 0 25 50 75 100 125
Tj (˚C)
Tj (˚C)

7/11
L6388

Figure 15. DIP8 Mechanical Data & Package Dimensions

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 3.32 0.131

a1 0.51 0.020

B 1.15 1.65 0.045 0.065

b 0.356 0.55 0.014 0.022

b1 0.204 0.304 0.008 0.012

( s )
D 10.92 0.430

c t
E 7.95 9.75 0.313 0.384

d u
e 2.54 0.100

r o s)
e3 7.62 0.300
P c t(
e4 7.62
t
0.300

e e u
F 6.6
o l rod 0.260

I 5.08
b s P 0.200

L 3.18 3.81

- O eteDIP-8
0.125 0.150

Z 1.52

s ) o l 0.060

c t ( b s
d u -O
r o s)
P
e uc t (
e t
l od
o
s Pr
b
O ete
o l
Obs

8/11
 L6388

Figure 16. SO8 Mechanical Data & Package Dimensions

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D (1) 4.80 5.00 0.189 0.197

( s )
E 3.80 4.00 0.15
c t
0.157

e 1.27 0.050

d u
H 5.80 6.20 0.228
r o s) 0.244

h 0.25 0.50 0.010

P c t( 0.020

L 0.40 1.27
t
0.016

e e u 0.050

k
l rod
0˚ (min.), 8˚ (max.)

o
ddd 0.10

b s P 0.004

O
- le
sions or gate burrs.
e
Note: (1) Dimensions D does not include mold flash, protru-

t SO-8
Mold flash, potrusions or gate burrs shall not exceed

( s )
0.15mm (.006inch) in total (both side).

s o
c t b
d u -O
r o s)
P
e uc t (
e t
l od
o
s Pr
b
O ete
o l
Obs

0016023 C

9/11
L6388

Table 7. Revision History

Date Revision Description of Changes

January 2005 1 First Issue

May 2005 2 Changed from Preliminary Data to Final

( s )
c t
d u
r o s)
P c t(
e t e u
o l rod
b s P
- O ete
s ) o l
c t ( b s
d u -O
r o s)
P
e uc t (
e t
l od
o
s Pr
b
O ete
o l
Obs

10/11
 L6388

( s )
c t
d u
r o s)
P c t(
e t e u
o l rod
b s P
- O ete
s ) o l
c t ( b s
d u -O
r o s)
P
e uc t (
e t
l od
o
s Pr
b
O ete
o l
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

bs
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

O
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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All other names are the property of their respective owners

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11/11