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Assignment Module - 1HDL

This document provides instructions for Assignment #1 of the course "Verilog HDL" being taught in the Electronics and Communication Engineering department at CMR Institute of Technology, Bangalore during the semester from August 1, 2018 to November 24, 2018. The assignment covers an overview of digital design using Verilog HDL, including hierarchical modeling concepts. Students are asked to discuss topics like the evolution of CAD tools and HDLs, digital design flows, top-down and bottom-up methodologies, modules and instances in Verilog. They are also asked to write code for test benches and basic components like a 4-bit ripple carry counter and adder.

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vijayarani.katkam
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66 views

Assignment Module - 1HDL

This document provides instructions for Assignment #1 of the course "Verilog HDL" being taught in the Electronics and Communication Engineering department at CMR Institute of Technology, Bangalore during the semester from August 1, 2018 to November 24, 2018. The assignment covers an overview of digital design using Verilog HDL, including hierarchical modeling concepts. Students are asked to discuss topics like the evolution of CAD tools and HDLs, digital design flows, top-down and bottom-up methodologies, modules and instances in Verilog. They are also asked to write code for test benches and basic components like a 4-bit ripple carry counter and adder.

Uploaded by

vijayarani.katkam
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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CMR Institute of Technology, Bangalore

Department(s): Electronics and Communication Engineering


Semester: 05 Section(s): C&D Lectures/week: 04
Subject: Verilog HDL Code: 15EC53
Course Instructor: Sunil Kumar K H
Course duration: 01 Aug 2018 – 24 Nov 2018
Assignment # 01 – Overview of Digital Design with Verilog HDL, Hierarchical Modeling Concepts
Date of issue: 7 Aug., 2018 | Submission Due: 16 Aug., 2018
Course Site: https://sites.google.com/a/cmrit.ac.in/sunilkumarkh/

Instructions:

 ANSWER NEATLY AND LEGIBLY on A4 sheets only and not in sheets torn from a book.
 Sketch diagrams wherever relevant. Explain your notations explicitly and clearly.
 An incomplete assignment is not acceptable for submission.
 ON the top of the first page, write your Name, Class, Section, Roll No., Due Date and Date of
Submission.

Module 1:
Overview of Digital Design with Verilog HDL: Evolution of CAD, emergence of HDLs, typical
HDL-flow, why Verilog HDL? Trends in HDLs.
Hierarchical Modelling Concepts: Top-down and bottom-up design methodology, differences
between modules and module instances, parts of a simulation, design block, stimulus block.

1 Discuss in brief about the evolution of CAD tools and HDLs used in digital system design
2 Explain a typical design flow for designing VLSI IC circuit using the block diagram.
3 Discuss the trends in HDLs?
4 Why Verilog HDL has evolved as popular HDL in digital circuit design?
5 Explain the advantages of using HDLs over traditional schematic based design.
6 Describe the digital system design using hierarchical design methodologies.
7 Explain top down design methodology and bottom up design methodology.
8 With a block diagram of 4-bit ripple carry counter explain the design hierarchy.
9 Apply the top-down design methodology to demonstrate the design of ripple carry counter.
10 Apply the bottom-up design methodology to demonstrate the design of 4-bit ripple carry
adder.
11 Write Verilog HDL program to describe the 4-bit ripple carry counter.
12 Define Module and an Instance. Describe 4 different description styles of Verilog HDL
13 Differentiate simulation and synthesis. What is stimulus?
14 Write a test bench to test the 4-bit ripple carry counter.
15 Write a test bench to test the 4-bit ripple carry adder.
16 An interconnect switch (IS) contains the following components, a shared memory (MEM),
a system controller (SC) and a data crossbar (Xbar).
a. Define the modules MEM, SC, and Xbar, using the module/endmodule keywords. You
do not need to define the internals. Assume that the modules have no terminal lists.
b. Define the module IS, using the module/endmodule keywords. Instantiate the modules
MEM, SC, Xbar and call the instances mem1, sc1, and xbar1, respectively. You do not
need to define the internals. Assume that the module IS has no terminals.
c. Define a stimulus block (Top), using the module/endmodule keywords. Instantiate the
design block IS and call the instance is1. This is the final step in building the simulation
environment.
17 A 4-bit ripple carry adder (Ripple-Add) contains four l-bit full adders (FA).
a. Define the module FA. Do not define the internals or the terminal list.
b. Define the module Ripple-Add. Do not define the internals or the terminal list. Instantiate
four full adders of the type FA in the module Ripple-Add and call them fa0, fal, fa2, and
fa3.

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