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Experiment No. 6: Aim: To Design and Simulate 6T Ram Using Symicade Tool. Tools Used: Symicade

The document describes an experiment to design and simulate a 6T RAM cell using the SymicaDE tool. It provides the theory of how a 6T RAM cell works to store a bit using six transistors and feedback inverters. The document includes the circuit diagram that was designed in SymicaDE and observations about the read and write operations that were simulated including transistor widths and lengths, supply voltage, input signals, and results showing the RAM was successfully designed and its operations analyzed.

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109 views3 pages

Experiment No. 6: Aim: To Design and Simulate 6T Ram Using Symicade Tool. Tools Used: Symicade

The document describes an experiment to design and simulate a 6T RAM cell using the SymicaDE tool. It provides the theory of how a 6T RAM cell works to store a bit using six transistors and feedback inverters. The document includes the circuit diagram that was designed in SymicaDE and observations about the read and write operations that were simulated including transistor widths and lengths, supply voltage, input signals, and results showing the RAM was successfully designed and its operations analyzed.

Uploaded by

Vmosa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Date: 30/09/2020

EXPERIMENT NO. 6

AIM: To design and simulate 6T RAM using SymicaDE tool.

TOOLS USED: SymicaDE


THEORY: The memory cell shown here forms the basis for most static random-access
memories in CMOS technology. It uses six transistors to store and access one bit. The four
transistors in the center form two cross-coupled inverters. In actual devices, these transistors
are made as small as possible to save chip-area, and are very weak. Due to the feedback
structure, a low input value on the first inverter will generate a high value on the second
inverter, which amplifies (and stores) the low value on the second inverter. Similarly, a high
input value on the first inverter will generate a low input value on the second inverter, which
feeds back the low input value onto the first inverter. Therefore, the two inverters will store
their current logical value, whatever value that is.
The two lines between the inverters are connected to two separate bitlines via two n-channel
pass-transistors (left and right of the cell). The gates of those transistors are driven by a
wordline. In a larger SRAM, the wordline is used to address and enable all bits of one memory
word (e.g. all 32 bits at address 0xcafe from a 64Kx32 SRAM chip). As long as the wordline is
kept low, the SRAM cell is disconnected from the bitlines. The inverters keep feeding
themselves, and the SRAM stores its current value.
When the wordline is high, both n-channel transistors are conducting and connect the
inverter inputs and outputs to the two vertical bitlines. That is, the two inverters drive the
current data value stored inside the memory cell onto the bitline (left) and the inverted data
value on the inverted-bitline (right). This data can then be amplified and generates the output
value of the SRAM cell during a read operation.
To write new data into the memory, the wordline is activated, and the strong bitline input-
drivers (on top of the schematics) are activated. Depending on the current value stored inside
the SRAM cell there might be a short-circuit condition, and the value inside the SRAM cell is
literally overwritten. This only works because the transistors inside the SRAM cell are very
weak.

Figure 6.1: 6T RAM Circuit


CIRCUIT DIAGRAM:

Figure 6.2: 6T RAM circuit has been successfully designed using SymicaDE tool.

OBSERVATIONS:

Parameters Values
CMOS PTM 130nm
Technology
NMOS: W/L 720nm/180nm
PMOS: W/L 360nm/180nm
VDD 1.8V
Input signal V1=0V, V2=1.8V, Time
(Pulse) Period=100ns, Pulse Width=50ns
B
Input signal (For Read)V1=0V, V2=1.8V Time
(Pulse) Period=10n Pulse Width=5n
B_b (For Write)V1=1.8V, V2=0, Time
Period=10ns, Pulse Width=5ns

Input Signal V1=0V, V2=1.8V, Time Period=12ns,


WL Pulse Width=6ns

Table 6.1: Specifications of 6T RAM


Figure 6.3: Read operation of SRAM

Figure 6.4: Write operation of SRAM

RESULT:
• SRAM circuit has been successfully designed using SymicaDE tool.
• Transient analysis performed for read and write operations.

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