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Design of Digital Circuits (252-0028-00L), Spring 2019 Optional HW 1: DRAM Refresh

This document discusses DRAM refresh in a supercomputer memory system with the following key points: - The memory system has a total capacity of 1 Exabyte and each DRAM row is 8 Kilobytes, meaning it has 2^64 rows. - With a refresh period of 64ms, there will be 2^16 refreshes per period. - To calculate refresh power, the document provides links to DRAM datasheets specifying refresh current. Using provided values and assumptions, the refresh energy per cycle and per day can be calculated. - Additional questions discuss how DRAM refresh affects different applications' performance and energy usage under various memory access and refresh policies.

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51 views3 pages

Design of Digital Circuits (252-0028-00L), Spring 2019 Optional HW 1: DRAM Refresh

This document discusses DRAM refresh in a supercomputer memory system with the following key points: - The memory system has a total capacity of 1 Exabyte and each DRAM row is 8 Kilobytes, meaning it has 2^64 rows. - With a refresh period of 64ms, there will be 2^16 refreshes per period. - To calculate refresh power, the document provides links to DRAM datasheets specifying refresh current. Using provided values and assumptions, the refresh energy per cycle and per day can be calculated. - Additional questions discuss how DRAM refresh affects different applications' performance and energy usage under various memory access and refresh policies.

Uploaded by

nxp He
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Design of Digital Circuits (252-0028-00L), Spring 2019

Optional HW 1: DRAM Refresh

Instructor: Prof. Onur Mutlu


TAs: Mohammed Alser, Can Firtina, Hasan Hassan, Juan Gomez-Luna, Lois Orosa, Giray Yaglikci
Released: Monday, Feb 25, 2019

1 DRAM Refresh
A new supercomputer has a DRAM-based memory system with the following configuration:
• The total capacity is 1 ExaByte (EB).

• The DRAM row size is 8 KiloByte (KB).


• The minimum retention time among all DRAM rows in the system is 64 ms. In order to ensure that
no data is lost, every DRAM row is refreshed once every 64 ms. (Note: For each calculation in this
question, you may leave your answer in simplified form in terms of powers of 2 and powers of 10.)

(a) How many DRAM rows does the memory system have?

(b) How many DRAM refreshes happen in 64ms?

(c) What is the power consumption of DRAM refresh? (Hint: you will need to figure out how much current
the DRAM device draws during refresh operations. You can find useful information in the technical
note by Micron https://safari.ethz.ch/digitaltechnik/spring2019/lib/exe/fetch.php?media=
tn4704.pdf. Use the current (IDD) numbers specified in the datasheet posted on the website https:
//safari.ethz.ch/digitaltechnik/spring2019/lib/exe/fetch.php?media=1gb_ddr3_sdram.pdf.
Clearly state all the assumptions and show how you derive the power numbers. You are welcome to use
other data sheets as well. Make sure you specify how you obtain the power numbers and show your
calculations and thought process.)

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(d) What is the total energy consumption of DRAM refresh during a refresh cycle? And during a day?

This question is an extended version of the question on Slide 78 in Lecture 2:


https://safari.ethz.ch/digitaltechnik/spring2019/lib/exe/fetch.php?media=kgf-digitaldesign-
2019-lecture2-mysteries-beforelecture.pdf.
Video: https://youtu.be/199g9NsYTC8.

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2 Main Memory Potpourri
A machine has a 4 GB DRAM main memory system. Each row is refreshed every 64 ms.
(a) The machine’s designer runs two applications A and B (each run alone) on the machine. Although
applications A and B have a similar number of memory requests, application A spends a surprisingly
larger fraction of cycles stalling for memory than application B does? What might be the reasons for
this?

(b) Application A also consumes a much larger amount of memory energy than application B does. What
might be the reasons for this?

(c) When applications A and B are run together on the machine, application A’s performance degrades
significantly, while application B’s performance does not degrade as much. Why might this happen?

(d) The designer decides to use a smarter policy to refresh the memory. A row is refreshed only if it has not
been accessed in the past 64 ms. Do you think this is a good idea? Why or why not?

(e) When this new refresh policy is applied, the refresh energy consumption drops significantly during a run
of application B. In contrast, during a run of application A, the refresh energy consumption reduces only
slightly. Is this possible? Why or why not?

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