ECE 274 Report Template: Lab 1 Report Example

Lance Saldanha
Department of Electrical and Computer Engineering
University of Arizona
[email protected]

inverter will output 0, and vice versa. The truth table for an
Abstract inverter is provided in Figure 6.
Lab 1 provides an introduction to the Verilog hardware
description language (HDL), simulation and synthesis of digital Figure 5: Inverter (NOT gate).
circuits using Xilinx Integrated Software Environment (ISE), and
implementation of a digital circuit using a field-programmable
gate array (FPGA). The lab familiarizes students with the design,
simulation, and synthesis of basic logic gates, including a 2-input
AND gate, a 2-input OR gate, and an inverter (NOT gate), onto
Figure 6: Truth table for inverter (NOT gate).
the Xilinx Spartan-3E Starter Board.
INPUT OUTPUT
1. INTRODUCTION
A basic two-input AND gate, as shown in Figure 1, has two A F
inputs, A and B, and a single output, F. An AND gate will output 0 1
1 only if both A and B are 1. The truth table for a two-input AND 1 0
gate is provided in Figure 2.

Figure 1: Two-input AND gate. 2. IMPLEMENTATION

The Verilog code for a 2-input AND gate is shown in Figure 7.
The description begins with a timescale directive that defines the
time units used during simulation. The declaration of a Verilog
module consists of defining the module name (and2gate) followed
Figure 2: Truth table for two-input AND gate. by a list of all inputs and outputs within parenthesis. All inputs
and outputs of the module are explicitly defined within the
INPUT OUTPUT module using input and output statements. Note that outputs
A B F should be defined as a reg type in order to assign a value within
0 0 0 always procedure. The functionality of the module is defined
within an always procedure that is sensitive to the AND gate’s A
0 1 0 and B inputs. The always procedure consists of a single
1 0 0 assignment statement that assigns “A & B” to the output F.
1 1 1
Figure 7: Verilog code for two-input AND gate.
A basic two-input OR gate, as shown in Figure 3, has two `timescale 1ns / 1ps
inputs, A and B, and a single output, F. An OR gate will output 1
if at least one of its inputs, A or B, are 1. The truth table for a two- module and2gate(A, B, F);
input A, B;
input OR gate is provided in Figure 4. output F;
reg F;
Figure 3: Two-input OR gate.
always @ (A, B)
begin
F <= A & B;
end
endmodule
Figure 4: Truth table for two-input OR gate.
INPUT OUTPUT In order to test a design for correct functionality, a testbench
A B F can be used to provide input stimuli to the design and monitor the
outputs. The testbench used to test the and2gate module is
0 0 0 provided in Figure 8. The testbench is defined as a module named
0 1 1 and2gate_tb that has no inputs or outputs and instantiates a single
1 0 1 instance of the and2gate design. As the testbench will assign
values to the instance’s inputs and read the outputs, reg nets are
1 1 1 used to connect to the instance’s inputs and wires are used to the
As shown in Figure 5, an inverter, also referred to as a NOT connect to the instance’s outputs. The testbench for the module
gate has a single input A and a single output F. An inverter will consists of a single initial procedure that exhaustively tests all
output the opposite of its Boolean input, e.g., if the input is 1 the
possible input combinations of the and2gate design, printing the same way that a software binary provides the configuration for
results of each test case using the $display function. executing a software application on a microprocessor. The
To simulate and test the and2gate design, both the and2gate Configure Device (iMPACT) command will launch the Xilinx
and and2gate_tb modules are checked for correct syntax and iMPACT tools that will communicate with the Xilinx Spartan-3E
simulated using the Xilinx ISE Simulator. FPGA Starter Board using the provided USB cable to program the
FPGA.
Figure 8: Verilog testbench for two-input AND gate design.
3. EXPERIMENTAL RESULTS
`timescale 1ns / 1ps
The Verilog descriptions to the two-input AND gate, two-input
module and2gate_tb(); OR gate, and inverter were verified through simulation using the
reg A_t, B_t; Xilinx ISE Simulator and through exhaustive testing after
wire F_t; downloading each design to the Xilinx Spartan-3E FPGA Starter
Board. As was to be expected, the 2-input AND gate produced the
and2gate and2gate_1(A_t, B_t, F_t); correct outputs for the various possible input combinations. As
shown in Figure 10, the AND gate only outputs 1 when both
initial
inputs, A and B are 1.
begin
// case 0
A_t<=0; B_t<=0; Figure 10: Simulation waveform verifying correct behavior of
#1 $display("F_t = %b", F_t); two-input AND gate design.

// case 1
A_t<=0; B_t<=1;
#1 $display("F_t = %b", F_t);

// case 2
A_t<=1; B_t<=0;
#1 $display("F_t = %b", F_t);

// case 3
A_t<=1; B_t<=1; Figure 11 presents the simulation waveform for the two-input OR
#1 $display("F_t = %b", F_t); gate design and illustrates the correct operation of an OR gate.
end The OR gate design correctly outputs 1 whenever at least one of
endmodule
the inputs, A or B is a 1.
Implementing the design onto the Xilinx Spartan-3E FPGA
Starter Board requires the design to be synthesized for the target Figure 11: Simulation waveform verifying correct behavior
FPGA. This process includes selecting the appropriate Spartan-3E of two-input OR design.
FPGA devices within the project’s properties. The basic
procedure involved in implementing a design on an FPGA
includes specifying user constraints, synthesizing the design,
implementing the design, and downloading the resulting bitstream
to the FPGA. A User Constraints File (UCF) is needed to assign
the and2gate’s inputs and outputs to the appropriate pins of the
FPGA. The simplify this process, the Xilinx Spartan-3E FPGA
Starter Board includes the FPGA pins numbers printed on the
board next to the various components, such as LEDs, buttons, Figure 12 illustrates the simulation waveform for the inverter
connectors, switches, etc. For the 2-input AND gate, the inputs design and correctly demonstrates that an input of 1 will result in
were connected to switches on the board, and the single output an output of 0, and vice versa.
was connected to an LED. The resulting UCF file is presented in
Figure 9. Figure 12: Simulation waveform verifying correct behavior of
inverter design.
Figure 9: UCF file.
NET "A" LOC = "N17";
NET "B" LOC = "H18";
NET "F" LOC = "F12";

After specifying the user constraints, the design can be

synthesized and implemented, by executing the Synthesize – XST
and Implement Design commands within Xilinx ISE tool. The
final bitstream needed to program the FPGA can then be
generated by executing the Generate Programming File Finally, the AND gate and OR gate designs were implemented
command. on the Xilinx Spartan-3E FPGA Starter Board and exhaustively
The resulting bitstream file provides the configuration needed tested by iterating through all possible input combinations while
to program the FPGA to implement the target design, much in the observing the output LED to ensure correctness.
4. CONCLUSIONS Xilinx ISE and physical implementation on the Xilinx Spartan-3E
The two-input AND gate, two-input OR gate, and inverter designs FPGA Starter Board. The basic methodology for deigning and
were successfully implemented using the Verilog hardware implementing digital circuits using FPGAs provides a solid
description language and verifying through simulation using foundation for learning Verilog based digital design.