Digital

 Circuits  and  Systems  

Unit  3  
Combina7onal  Integrated  Circuits  
 1
COMBINATIONAL ICs  
 
• REPRESENTATION OF BINARY VARIABLES AT THE PHYSICAL LEVEL
 
• BASIC SWITCH. STRUCTURE OF GATES AND THEIR OPERATION
 
• REALIZATION OF GATES USING cmos CIRCUITS
 
• CHARACTERISTICS OF CIRCUITS: LOAD FACTORS AND FANOUT FACTORS, PRO
AGATION DELAYS, TRANSITION TIMES, AND EFFECT OF LOAD
 
• THREE-STATE GATES (DRIVERS) AND BUSES
 
• NOISE AND NOISE MARGINS
 
• EVOLUTION OF ICs. VLSI CIRCUIT-LEVEL DESIGN STYLES
 
• PACKAGING LEVELS: CHIPS, BOARDS AND CABINETS.
 
 2
REPRESENTATION OF BINARY VARIABLES  
 

• REPRESENTATION OF 0 AND 1 BY ELECTRICAL SIGNALS

 
• VOLTAGES
 • CURRENTS
 • ELECTRICAL CHARGES
 
• REALIZATION OF CIRCUITS THAT OPERATE ON THESE SIGNALS TO
IMPLEMENT DESIRED SWITCHING FUNCTIONS
 

TYPICAL VALUES FOR A 3.3V cmos TECHNOLOGY

  VHmax 3.3V VLmax 0.8V
 VHmin 2.0V VLmin 0.0V
 
     
 3
VOLTAGE REGIONS  
 

voltage
 
VHmax
   
V
H region
V    
Hmin
   
Forbidden region
VLmax  
    V
V   L region
Lmin  
   

Figure 3.1: VOLTAGE REGIONS.

 
 4
POSITIVE AND NEGATIVE LOGIC  
 

x
  f z
y    
 

Input Output Positive Negative

POSITIVE LOGIC
voltagesvoltage   logic logic
VH ←→ 1
  x y z x  y z x y z
V
  L ←→ 0
  V   L VL VL  0 0 0 1 1 1
 VL VH VL  0 1 0 1 0 1
NEGATIVE LOGIC  1 0 0
V   H VL VL 0 1 1
VH ←→ 0
VH VH VH 1   1 1 0 0 0
V
  L ←→ 1
  f =and f =or
 
 
 5
STRUCTURE AND OPERATION OF GATES  
 

SWITCH AND mos TRANSISTORS

 

N-TYPE:
 
open (off) if VCA < VT n
closed (on) if VCA > VT n
V
  T n - THE THRESHOLD VOLTAGE FOR N-TYPE SWITCH
 

P-TYPE:
 
open (off) if VBC > Vdd - |VT p|
closed (on) if VBC < Vdd - |VT p|  
VT p - THE THRESHOLD VOLTAGE FOR P-TYPE SWITCH
 
 6
 
V VBC
CA n-type switch p-type switch
       
 
Resistance between A and B Resistance between A and B
very low: switch CLOSED (on)  
V   VTp very low: switch CLOSED (on)
Tn
  Resistance between A and B     Resistance between A and B
very high: switch OPEN (off) very high: switch OPEN (off)
   

B V + B
BC
C nS   -
+     pS
    C
V  
CA - (a)  
    A   A
 
 
NMOS transistor logical PMOS transistor logical
  symbol   symbol
   
B B
  B   B
drain source
C   C C   C
  gate source   gate drain
       
  A A
A A
   
  (b)
 
Figure 3.3: a) N-TYPE AND P-TYPE CONTROLLED SWITCHES. b) nmos AND pmos TRANSISTORS.
 
    THE  INVERTERS  
 DIGITAL  GATES    
Fundamental  Parameters  

•  Func7onality  
•  Reliability,  Robustness  
•  Area  
•  Performance  
–  Speed  (delay)  
–  Power  Consump7on  
–  Energy  
 Noise  in  Digital  Integrated  Circuits

VDD
v(t)
i(t)

(a) Inductive coupling (b) Capacitive coupling (c) Power and ground
noise
 DC  Opera7on:    
Voltage  Transfer  Characteris7c

V(y)
V(x) V(y)

V f
OH
V(y)=V(x)

V Switching Threshold
M

VOL

VOL V V(x)
OH

Nominal Voltage Levels

Mapping  between  analog  and  digital  signals

V V(y)
"1" OH
Slope = -1
V V
IH OH

Undefined
Region
Slope = -1
V
IL VOL
"0"
V
OL V V V(x)
IL IH
 Defini7on  of  Noise  Margins

"1"
V
OH
NMH
V
Noise Margin High IH
Undefined
Region
Noise Margin Low
NML V
IL
V
OL
"0"

Gate Output Gate Input

Fan-­‐in  and  Fan-­‐out

(a) Fan-out N

M
(b) Fan-in M
N
 The  Ideal  Gate

Vout

Ri = ∞

Ro = 0
g= −∞

Vin
 VTC  of  Real  Inverter

5.0

4.0 NML

3.0
Vout (V)

2.0
VM
NMH
1.0

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)
 Delay  Defini7ons
Vin

50%

t
t t
pHL pLH
Vout
90%

50%

10% t
tf tr
Power  Dissipa7on
CMOS  INVERTER  
 The  CMOS  Inverter:    
A  First  Glance
VDD

Vin Vout

CL
Switch  Model  of  CMOS  Transistor
|V GS|

Ron

|VGS| > |VT|

|VGS| < |VT|
CMOS  Inverter:  Steady  State  Response  

VDD VDD

Ron
VOH = VDD

Vout VOL= 0
Vout

Ron VM = f(Ronn,Ronp)

Vin = V DD Vin = 0
CMOS  Inverter:  Transient  Response

VDD

tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout ln(0.5)
CL
Ron
1 VDD

0.5
0.36

Vin = V DD
t
RonCL
 CMOS  Proper7es  
•  Full  rail-­‐to-­‐rail  swing  
•  Symmetrical  VTC  
•  Propaga7on  delay  func7on  of  load  capacitance  and  
resistance  of  transistors  
•  No  sta7c  power  dissipa7on  
•  Direct  path  current  during  switching  
 The  Miller  Effect

Cgd1 Vout Δ
ΔV Vout V

ΔV
Vin 2Cgd1

M1
M1 ΔV
Vin

“A capacitor experiencing identical but opposite voltage swings

at both its terminals can be replaced by a capacitor to ground,
whose value is two times the original value.”
Where  Does  Power  Go  in  CMOS?

• Dynamic Power Consumption

Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Leakage
Leaking diodes and transistors
Dynamic  Power  Dissipa7on  
Vdd  
Vin   Vout  
    CL

Energy/transition = C     * V       2

     * V        * f  
L dd

Power = Energy/transition * f  = C L dd
2

Not a function of transistor sizes!  

Need to reduce C    
, V   ,  and f    to reduce power.  
L dd
Static Logic Gates
 Complex Logic CMOS functions
•  One extremely powerful aspect of CMOS is the ability to create single gate
circuits that can implement functions consisting of several basic logic
operations.

•  This makes digital CMOS design quite different from classical logic design
techniques.

•  A static logic gate is one that has a well defined output once the inputs are
stabilized and the switching transients have decayed away.

•  Static CMOS logic gates are relatively easy to design and use.
 Complex Logic functions
•  Complex logic gates provide functions that consist of several primitive
NOT, AND, or OR operations.

•  This is an example of a canonical AOI (and-or-invert) equation1 which

falls into the category of a complex logic operation.
•  Complex logic gates are constructed using the CMOS inverter as a basis.
•  nFET and pFET are placed to act as pass transistors.
•  The input voltage controls the conduction modes of both transistors.
•  When input = 0V, the pFET conducts the power supply voltage to the
output. When input is Vdd, the nFET is ON, and transmits the ground (0v)
to the output.
 Construction of Complex Logic Gates
•  In order to construct a complex logic gate, let us replace the single
inverter nFET by an array of nFETs that are connected to operate
as a large switch.
•  Similarly, we will substitute an array of pFETs for the single pFET
used in the inverter, and view the pFET array as a “giant” switch.
•  In order to insure proper electrical operation, however, we must
exercise care so that operation of the nFET array complements the
operation of the pFET array.
•  This means that if one array is a closed switch, the other must be
open.
 Construction of Complex Logic Gates
•  The general structure of a complex logic gate can be created
by the following steps.
Ø  Provide a complementary pair (an nFET and a pFET with a common
gate) for each input;
Ø  Replace the single nFET with an array of nFETs that connects the
output to ground;
Ø  Replace the single pFET with an array of pFETs that connects the
output to Vdd
Ø  Design the nFET and pFET switching network so that only one
network acts as a closed switch for any given input combination.
•  For multiple inputs, the nFET and pFET
arrays are viewed as large “composite”
switches, with each array containing m
MOSFETs.

•  For a given input combination, only one

composite switch can be closed. If the
pFET switching array is closed, then the
output voltage is Vdd.

•  Conversely, if the nFET array is closed,

then the output is a logic 0
•  for proper operation, the arrays must be designed so that the
two cases where either (i) both switching arrays are closed, or,
(ii) both switching arrays are open, cannot occur, since both
situations give an undefined output.
 CMOS NAND Gate
•  The NAND2 operation is described by

•  To construct a CMOS circuit that provides this

function we will use two complementary pairs, one
for each of the inputs A and B, and create the nFET
and pFET arrays according to the needed outputs.
Circuit of CMOS NAND2 Gate
 Logical operation
•  Denoting the inputs by simply A
and B results in the circuit
shown in Figure. The output is
viewed as the OR operation
between the pFET switches
and the nFET switches such
that.

•  By Demorgan’s law
 CMOS NOR Gate
•  The NOR2 operation is described by
Circuit of CMOS NOR2 Gate
 Logical operation
•  Denoting the inputs by simply A
and B results in the circuit
shown in Figure. The output is
viewed as the OR operation
between the pFET switches
and the nFET switches such
that.

•  By Demorgan’s law
 Comparison of NAND and NOR gate
•  Both NAND and NOR gates are easy to implement in CMOS
logic.

•  However, for equal numbers of inputs and device sizes,

NAND gates have better transient response than NOR gates,
making them more popular in high-performance design.

•  We can understand this with help of delay times:

–  The series-connected transistors are the limiting factor.
–  In a NAND gate, the discharge delay time is determined by a chain of
n-channel MOSFETs.
–  A NOR gate, on the other hand, has a charging time which is due to
charging through a chain of p-channel transistors.
 Complex  Logic  Gates  

Complex  logic  func7ons  can  be  implemented  by  designing  the  nFET  and  
pFET  switching  arrays  such  that  only  one  composite  switch  is  closed  for  a  
given  set  of  inputs.  
 
If  the  nFET  switch  is  closed  while  the  pFET  switch  is  open,  then  the  
output  is  a  logic  0.  Conversely,  a  closed  pFET  switch  and  an  open  nFET  
switch  results  in  a  logic  1  output.    
•  The arrays must be designed to avoid two situations:
–  (1) both switches are open at the same time, since this gives an
undetermined value;
–  (2) both are closed at the same time, since the voltage will not be a
well-defined logic voltage.

•  we have labelled the nFET switching block by f¯, the pFET

block by f, and the output is also given as f.
•  This notation is defined to mean that if the output f is a logical
1, the nFET block is OPEN and the pFET block is CLOSED.
•  Conversely, if the nFET block is CLOSED while the pFET
block is OPEN, the output is at a value of f=0 , With regards to
the individual blocks themselves, the outcome is TRUE (a
logic 1)
 Examples of Complex Logic Gates
•  Consider the function
•  Either A.B=1 OR C=1 will connect the output to ground by turning on an
nFET conduction path.
•  C=0 AND (A=0 OR B=0), then the pFETs provide a conduction path
between the power supply and the output, giving a logic 1 output voltage
Basic Logic Cascades
Exclusive OR and equivalence (XNOR)
Gates
XOR CMOS implementation
XNOR CMOS Implementation
Multiple XOR function
Binary Adder
Full adder Circuit using AOI structure
CMOS Circuit using AOI structuring
SR Latch
Set Operation
Simplified SR Latch Circuit
D Latch
CMOS D Latch circuit
 CMOS SRAM cell
•  A random-access memory (RAM) cell is a circuit that has three main
operations.
–  Write - A data bit is stored in the circuit
–  Hold - The value of the data bit is maintained in the cell
–  Read - The value of the data bit is transferred to an external circuit
Write Operation in SRAM Cell
Voltage characteristics of SRAM cell
Read operation in SRAM cell
Pseudo NMOS Logic Gates

A resistive load NMOS inverter

Pseudo NMOS logic Gates
 Complex Pseudo NMOS gates

NOR3  Gate  in  pseudo  nMOS     Pseudo  nMOS  NAND2  gate  

Simplified XNOR gate

Thus  for  equal  input  voltages  

both  nFET  would  be  cut  off  and  
thus  o/p  =  high  
 
When  either  voltage  is  high  and  
other  is  low,  then  one  of  the  
nFET  is  ac7ve  and  thus  provide  
a  path  to  ground  and  output  is  
0  
Transmission  Gate  Logic  Circuit  
Designs  
 Basic  Structure  
•  Transmission gate is an ideal switch formed by using a pair of MOSFETs
wired in parallel.
•  It consists of an nFET Mn in parallel with a pFET Mp such that the gates
are controlled by the complementary voltages.
–  (VG) applied to the nFET, and
–  (VDD – VG) applied to the pFET.
 TG-­‐Based  Switch  Logic  Gates  
•  Basic  Mul7plexer  
•  A  2  input  path  selector    
 is    
4:1  Mul7plexer  
 OR  Gate  
•  The  input  variable  A  and  
its  complement  are  used  
to  control  both  the  pMOS  
pass  transistor  Mp  and  
the  transmission  gate.    

•  The  upper  branch  

transmits  when  A=1,  
while  the  lower  TG  circuit  
propagates  B  to  the  
output  when  A=0.  
XOR  and  Equivalence  
TG  based  XOR  and  XNOR  
 Transmission-­‐gate  Adders  

•  Since  transmission  gate  logic  allows  for  direct  implementa7on  

of  the  XOR  func7on,  various  full  adder  networks  can  be  
constructed  using  the  TG  circuits  discussed  above.  
 TG  Registers  
•  Transmission  gates  can  be  used  as  simple  switches  to  create  
circuits  that  have  at  least  two  dis7nct  opera7onal  modes:  
–  Load  -­‐  The  value  of  a  bit  D  is  used  as  an  input  to  the  circuit,  and,  
–  Hold  -­‐  The  input  line  is  disconnected  from  the  circuit,  and  the  value  is  
held.  
•  This  allows  us  to  create  memory  circuits  that  can  be  used  for  
latches,  registers,  and  other  state  elements.  Figure  below  
shows  the  basic  circuit  for  a  level-­‐sensi7ve  D  latch.  
 Opera7on  of  D  Latch  
When  LD  =  1,  the  input  transmission  gate  
TG1  acts  as  a  closed  switch,  while  TG2  is  
open.  The  value  of  the  input  data  bit  D  
enters  the  circuit,  and  is  available  at  the  
outputs  Q  and  Since  the  outputs  change  
in  response  to  a  change  in  D,  the  latch  is  
said  to  be  transparent.  
 
At  LD  =  0,  TG1  is  open,  disconnec7ng  the  
input  line  from  the  circuit;  the  new  input  
bit  A  cannot  enter  the  circuit.  
Transmission  gate  TG2  is  closed,  and  
completes  the  feedback  loop  between  
the  inverters,  changing  it  into  a  bistable  
circuit  that  can  store  either  a  0  or  1  state.