IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO.

3, MARCH 2016 1179

Design-Time Reliability Enhancement Using

Hotspot Identification for RF Circuits
Doohwang Chang, Jennifer N. Kitchen, Bertan Bakkaloglu, Sayfe Kiaei, and Sule Ozev

Abstract— Failure due to aging mechanisms in CMOS devices is an the circuit without changing its performance if reliability is taken into
important concern of RF circuits. Lifetime of analog/RF circuits is defined consideration at design time.
as the point where at least one specification will fail due to aging effects.
In this brief, we present a methodology for analyzing the performance
degradation of RF circuits caused by aging mechanisms in MOSFET II. AGING M ECHANISMS : HCI, NBTI, AND EM
devices and inductors at design time (presilicon). We identify reliability HCI is one of the degradation mechanisms mainly considered for
hotspots and concentrate on these circuit components to enhance the n-type MOSFETs. The hot carriers can cause both interface state
lifetime with low area and no performance impact.
generation and charge traps, which increase the substrate leakage
Index Terms— Electromigration (EM), hot-carrier current and decrease drain current. After hot-carrier stress, transistor
injection (HCI), hotspot identification, lifetime enhancement, characteristics, such as threshold voltage and channel mobility, may
negative bias temperature instability (NBTI), RF reliability. shift and change the device characteristics. The threshold voltage
degradation under HCI stress can be expressed as [6], [7].
NBTI is caused by the interface traps and fixed charge under high
I. I NTRODUCTION temperature and negative gate voltage bias. It causes a degradation in
Technology scaling and integration enable high-frequency, low-cost the threshold voltage, resulting in a decrease in the drain current over
device manufacturing, but also introduce new challenges of aging stress time and leads to performance degradation. NBTI effects can
and long-term reliability. Reliability is defined as the ability of a be categorized into two models depending on the stress conditions:
circuit to conform to its specifications over a specified period of 1) static and 2) dynamic NBTI. In the dynamic NBTI, the device
time [1]. Most reliability studies have concentrated on digital circuits, undergoes ac operation alternating between degradation and recovery
which have been more susceptible to aging effects, since they have phase [6].
led analog circuits in terms of technology nodes. This is no longer During EM effects, the metal atoms move in the direction of
true, as both RF/analog and digital components are being integrated electron flow along the grain boundaries. Over time, enough material
with the leading edge manufacturing process. may move, resulting in a significant change in the metal
For future complex wireless systems, RF and analog circuits will resistance. While most EM research has focused on digital circuits
face the same challenges as digital circuits, namely, higher process and catastrophic failure modes [8], studies show that EM results in
variations, higher defect rates, and in-field degradation due to aging. a continuous increase of trace resistances as soon as current starts
Various researchers have focused on different aspects of degradation flowing through the metal [9], [10].
in RF circuits, including hot-carrier injection (HCI) [1], [2],
oxide breakdown (OBD) [2], negative bias temperature III. S IMULATION F RAMEWORK FOR AGING M ECHANISMS
instability (NBTI) [3], and electromigration (EM) [4]. An analysis To develop a design-for-reliability approach for RF circuits,
of the effects of HCI on the performance of the CMOS LC-tank we need a framework for simulating aging effects. While com-
oscillator is presented in [5]. We conclude that HCI causes increased mercial tools exist to simulate for digital circuits, they typically
phase noise due to the decrease in the oscillation amplitude. report an overall lifetime in terms of a catastrophic, mean-time-to
Xiao et al. [2] study both HCI and OBD effects on ring-oscillator- failure (MTTF). Therefore, we develop an aging simulation method
based voltage-controlled oscillators and RF amplifiers. These studies that is based on SPICE to: 1) analyze each circuit component and
show a continuous degradation of circuit performance parameters. each aging mechanism independently and 2) evaluate parametric
The existing research works indicate that RF circuit aging degradation in specifications and determine lifetime.
increasingly becomes a bottleneck in the overall lifetime of the To enable these simulations using the existing tools (e.g., SPICE),
devices. However, there is little emphasis on systematic design-time we modify each circuit component model with an equivalent that
approaches to address this challenge. In this brief, we propose a changes circuit parameters with respect to the amount of degradation.
systematic approach to design an RF circuit with expected lifetime The degradation amount with stress time for presilicon simulation is
as a specification parameter. We develop a framework for analyzing determined based on the well-established reliability models [6], [7]
parametric aging effects for RF circuits and determining the overall and the current state of the circuit performance. In our simulation
lifetime. We present an algorithm to determine reliability hotspots framework, we include the effects of HCI, NBTI, and EM.
in the circuit and design-time optimization methods to enhance the Similar to [11], our simulation framework uses improved circuit
lifetime by making the most likely to fail circuit components more components to model the degradation effects. However, [11] aims at
reliable. Based on the information that has been collected from analyzing the effect of degradation on the circuit when all circuit
simulations, we show that it is possible to enhance the lifetime of components are under stress. This approach does not provide the
Manuscript received October 23, 2014; revised February 17, 2015; accepted
necessary information for hotspots identification. Moreover, device-
April 8, 2015. Date of publication June 1, 2015; date of current version to-device mismatch for process or degradation parameters has not
February 23, 2016. This work was supported by the National Science been previously considered. Mismatch results in unequal degradation
Foundation under Contract NSF CCF 111652. in different transistors and has a profound effect on analog circuit
The authors are with the School of Electrical, Computer and performance. In our framework, we pay particular attention to the
Energy Engineering, Arizona State University, Tempe, AZ 85287 following issues.
USA (e-mail: [email protected]; [email protected];
[email protected]; [email protected]; [email protected]). 1) Circuit components are subject to both die-to-die and
Color versions of one or more of the figures in this paper are available within-die (mismatch) variations.
online at http://ieeexplore.ieee.org. 2) Degradation model parameters are also subject to mismatch
Digital Object Identifier 10.1109/TVLSI.2015.2428221 variations among circuit components.
1063-8210 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1180 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 3, MARCH 2016

Fig. 1. Flow of (a) reliability simulation approach and (b) proposed

design-time optimization method.

3) Each circuit component is subject to differing levels of stress

due to bias conditions and dynamic signal behavior.
4) Circuit bias conditions change over time; simulations based on
an initial bias point are unreliable.
Fig. 1(a) shows the flow of the reliability simulation Fig. 2. (a) HCI analysis. (b) EM analysis of cascode LNA. (c) HCI analysis
approach. Initial bias voltages and currents are determined via of n-type. (d) NBTI analysis of p-type LC oscillators.
simulations. For small-signal operation, degradation parameters
(e.g., threshold voltage) can be determined using dc bias.
For large-signal operation, dynamic signals also need to be collected, it is possible to decide the most vulnerable component to
considered. An initial time step (e.g., N months) is used aging effects. Component-centric lifetime enhancement can be done
to calculate degradations in circuit component parameters. using established techniques by adjusting the component parameters.
The circuit is simulated again to determine the change in Clearly, once one component is modified, circuit specifications shift,
dc operating point. If the shift in dc point is above a tolerable thus requiring modifications on other components. Hence, circuit
threshold (e.g., >α mV), the time step is reduced and the prediction modifications need to be done incrementally to avoid ping-pong
is repeated. Otherwise, the circuit is simulated for performance behavior of the optimization process. Moreover, a circuit component
evaluation (e.g., gain and phase noise). With this simulation is not modified to enhance the lifetime to beyond what is limited by
framework, we can simulate the aging effect for a single or multiple another circuit component.
components.
V. C ASE S TUDIES
IV. D ESIGN -T IME O PTIMIZATION M ETHODOLOGY
A. Low-Noise Amplifier With HCI and EM Analysis
After analyzing the reliability impact of aging mechanisms on
the circuits in several steps, we can concentrate on each circuit A cascode low-noise amplifier (LNA) is used as an example to
component and determine at what point it will cause a specification demonstrate the RF performance degradation due to HCI and EM
failure, assuming that it is the only contributor to degradation. This effects. Fig. 2(a) shows a narrow-band LNA where the transistors
proposed method enables us to determine the reliability hotspots and are enhanced to account for degradation effects [12]. The circuit is
concentrate design optimization efforts on these circuit components. designed with the following specifications:
If the projected lifetime is not satisfactory, the most dominant [S21 > 17 dB, S11 < −10 dB, S22 < −10 dB
lifetime-limiting component is modified so as to increase its and NF < 1.5 dB] @ 1.5 GHz.
reliability.
Fig. 1(b) shows an overview of the proposed methodology. The Reliability simulations of the LNA due to HCI effects are
first step in the process is to analyze the aging effects on circuit performed using the framework outlined in Section IV over three
performances using the analytical models of each aging effect. One years of stress time. Time-varying threshold voltage shift of HCI is
aging effect for one device is activated at a time to isolate the hotspot modeled as a dependent voltage source with input node voltages.
device and the cause of the degradation. The stress time is gradually These node voltages are connected to gate, drain, or source of the
increased with an adaptive time interval and the aging impact on device and updated after each time step to obtain more accurate
circuit specifications is analyzed. This information combined with the actual simulation responses. In this design example, there are three
circuit specifications yields a certain time point at which the specifi- voltage sources VTH0,1,2 at the gate of each nMOSFET to consider
cation will fail. The sensitivity of circuit specifications with respect the effects of threshold voltage shift. Degradation profiles of the
to each circuit component degraded by aging effects differs. Due to LNA specifications, such as S-parameters and noise figure (NF),
different sizes and operating points, this profile will be different for are shown in Fig. 3. Due to the degradation of threshold voltage, it
each circuit component. Therefore, each circuit component will cause reduces the drain–source current of transistor and hence its transcon-
a distinct failure time for each specification. ductance gm , thus resulting in degradation in specifications [12].
Note that at this point, we focus on one circuit component at a time From the simulations, we observe that the circuit is likely to fail
to determine the lifetime-limiting factors. The actual failure point input return loss (S11), gain (S21), and NF between 1 and 3 years
of the circuit will differ from this first-level sensitivity study, since of lifetime, which is generally not acceptable.
all circuit components simultaneously age, albeit at a differing rate. To analyze the reliability impact of EM on the LNA, it is important
We iteratively go through each circuit component and track the failure to concentrate on conductors (via and inductor), as shown in Fig. 2(b).
time of the each circuit specification. Once all the failure times are Both on-chip inductors, L d and L s , are implemented using metals.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 3, MARCH 2016 1181

Fig. 3. Performance degradation due to HCI effect in cascode LNA during

one and three years of operation at room temperature.

Fig. 5. Performance degradations of (a) n-type and (b) p-type LC oscillators

versus stress time.

the tail transistor, although the stress conditions for cross-coupled

transistors are greater than the tail transistor in the p-type
LC oscillator. Fig. 5(b) also represents the simulation results for the
p-type oscillator after NBTI effect.
Fig. 5 also shows the reliability simulation results of cross-coupled
transistors with ±5% mismatch in process parameters and aging para-
Fig. 4. EM simulation results. meters. While these transistors undergo similar stress patterns, in both
dc and ac domains, there is still some mismatch in their parameters.
The inductor Q is modeled using the resistors, R Ld and R Ls , in series This is due to the mismatch in process and degradation patterns.
with ideal inductors, L d and L s , respectively. The inductor EM model We observe that the degradation in cross-coupled transistors does
Remd and Rems are additional resistances in series with R Ld and R Ls . not cause a significant degradation in the overall performance. This
Since there is no dc current into the gate of the input transistor, there result may be at first counterintuitive. However, it can be explained
is no EM effect on L g . EM results in a slow linear change in the with the phase noise model [13]. The gm of the cross-coupled
resistance of the metal line [10]. LNA S-parameter degradation due transistors plays a role in determining the equivalent resistance, hence
to increasing line resistances within three years is shown in Fig. 4. the phase noise. However, it is primarily determined by the tail
We observe that the circuit is projected to fail the gain specification transistor, since the transistor size does not change. Hence, a change
within eight months (∼20 × 106 s) of its deployment. in the threshold voltage of cross-coupled transistors does not cause
significant degradation in the phase noise of the oscillator, unless it
alters the bias so significantly that the circuit diverts from the desired
B. CMOS LC Oscillator With HCI and NBTI Analysis
operating point.
Fig. 2(c) and (d) shows the two types of CMOS LC-tank oscillators
used in our experiments. Important performance parameters of the
LC oscillator are phase noise and output amplitude [13]. The n-type VI. H OTSPOT I DENTIFICATION
oscillator is designed to yield a phase noise better than −114 dB/Hz The degradation of threshold voltage and LNA performances due
at 1-MHz offset and an output amplitude higher than 2V pp at 5-GHz to the HCI effect during three years of stress time are shown in
center frequency. Fig. 6. This analysis indicates that the S11 will fail earliest due to
Fig. 5(a) shows the performance degradations in n-type the degradation in transistor M1 . Hence, for the first iteration, M1 is
LC oscillator over stress time. Note that the cross-coupled transistors determined as the reliability hotspot due to HCI.
degrade faster due to higher voltage stress. Therefore, we predict To identify the critical component of EM resistances on LNA
a lifetime of <60 × 106 s when output amplitude is higher lifetime, the functions relating the resistance of Rs (=R Ls + Rems )
than 2V pp . and Rd (=R Ld + Remd ) to stress time are shown in Fig. 7(a) by
The performance degradation for the p-type oscillator is similar scaling the slope for our design’s current density. EM results in
to the n-type. However, NBTI has unique characteristics due to a linear increase in resistances Remd and Rems with stress time.
stress recovery [6]. In a p-type oscillator circuit, the cross-coupled The variations in LNA performance parameters due to EM are
transistors are exposed to ac stress, while the tail transistor is under shown in Fig. 8. Based on these simulations, we conclude that the
dc stress. Due to the recovery phase of the NBTI, the parameter Remd resistance is the critical component for S21. For specifications
degradations on cross-coupled transistors are less compared with (S21 > 17 dB and S11 < −10 dB), the lifetime of this device is
1182 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 3, MARCH 2016

Fig. 6. Hotspot identifications of LNA due to HCI effects. Fig. 9. Lifetime enhancement of LNA due to HCI effects.

bias voltage of Vds = Vgs ≈ Vdd . From the degradation results,

shown in Fig. 5(a), although the degradation of threshold voltage in
cross-coupled transistor is higher than tail transistor, the degradation
performances, such as phase noise and output amplitude, for tail
transistor N0 only aged are more significant than those of cross-
coupled only aged during three years. It is concluded that the tail
transistor of n-type LC oscillator is a critical device due to HCI.
The same simulation process is implemented for the p-type
LC oscillator. The degradation model of NBTI effect is used to
demonstrate the threshold voltage shift under the stress condition.
Fig. 5(b) represents the reliability simulation results for a p-type
Fig. 7. (a) Rs and Rd variations due to EM effects over stress time. oscillator considering NBTI. As predicted earlier, the cross-coupled
(b) Lifetime enhancement of LNA due to EM effects. transistors will introduce less degradation effects on the perfor-
mance than the tail transistor because of the recovery phase in the
cross-coupled transistors. Therefore, the tail transistor P0 of the
p-type LC oscillator is the critical device causing degradations due
to NBTI.

VII. D ESIGN -T IME O PTIMIZATION

To reduce or eliminate the HCI and NBTI effects, the circuits are
redesigned with adjusted bias to relieve the stress on the hotspot.
After identifying the critical transistor(s) with HCI or NBTI effects,
it is possible to minimize the performance degradation by chang-
ing the size of this critical transistor(s). HCI effect has a strong
dependence on the channel length of the nMOS device. For the
cascode LNA and n-type LC oscillator with the HCI effect, as the
length of the nMOSFET device is reduced, the lateral channel electric
field increases, and the HCI effect becomes more significant [6].
Therefore, redesigned LNA and n-type LC oscillator have increased
critical transistor length from 65 to 130 nm, thus reducing the
lateral electric field through the channel, and reducing threshold
voltage degradation. The critical transistor’s bias conditions and the
RF performance of the original and redesigned circuits should be the
Fig. 8. Impacts of each EM resistor on circuit performances. same at initial stress time. To achieve comparable performance to the
original design, it is required to codesign the circuits by adjusting
estimated as 50 × 106 s (∼20 months). Thus, the reliability of this circuit parameters, such as transistor dimensions and passive com-
design is limited by the current path through L d . ponent values, in the redesigned circuits. The reliability simulation
For the n-type LC oscillator, shown in Fig. 2(c), the degradation results shown in Fig. 9 confirm that the redesigned LNA with 130-
model of each transistor is adjusted by HCI effect. First, the threshold nm critical transistor length has less performance degradations than
voltage shift model of tail transistor is adopted to analyze the the original LNA with 65-nm transistor length. Furthermore, lifetime
performance with gradually increased stress time. Because both tail has been increased significantly. For instance, the lifetime of original
transistor and cross-coupled transistor are biased with different dc cascode LNA which is estimated as 15 × 106 s due to a failure
bias conditions, different amounts of degradation in threshold voltage in S11 (S11 < −10 dB) has increased to 35 × 106 s after the
shift are determined and applied to the circuit. The overdrive voltage redesign technique is applied. The simulation results illustrating the
at the tail transistor is usually kept low to allow a higher output enhanced performance in the n-type and p-type oscillators are shown
swing. Thus, the transistor at the cross-coupled pair experience a dc in Fig. 10. For specifications (output amplitude > 2 V), the original
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 3, MARCH 2016 1183

degradation. By increasing the width of L d , lifetime can be increased.

The total resistance Rd at the drain side with a wider width of L d will
have less series resistance compared with the original design at a
certain stress time. Although a decrease in resistance is achieved
by the increase in total area, a decreased resistance of the inductor
can improve RF performance and extend the LNA lifetime. An area
penalty exists, but this technique is better than blindly resizing all
components. From Fig. 7(b), modifying the critical device within
layout increases the circuit lifetime by 100%, from 30 × 106 to
60 × 106 s. Table I shows circuit specifications such as power, area,
and lifetime when the redesign technique is used. Compared with the
results of redesign layout technique without hotspot identification,
which means all circuit components are resized blindly, it should
be noted that focusing the layout technique on the critical device
identified through hotspot analysis enhances lifetime without a large
area penalty.
VIII. C ONCLUSION
In this brief, we present a methodology to analyze the
Fig. 10. Lifetime enhancement of (a) n-type and (b) p-type LC oscillators. performance of RF circuits degraded by aging mechanisms,
such as HCI, NBTI, and EM. The method that we propose is focused
TABLE I on finding the device that is most critical to circuit performance
degradation. Once the critical device of RF circuits is determined,
C OMPARISON OF C IRCUIT S PECIFICATIONS FOR A GING E FFECTS
remedial action can be taken to mitigate the circuit performance
degradations. We demonstrate our technique on an LNA and
two LC oscillators as case studies. Experimental results show that
the degradation performance and the lifetime were enhanced by
increasing the critical transistor size or widening the inductor line.
The methodology should be applied to the particular design at hand
to fully gauge the impact of aging effects.
R EFERENCES
[1] G. Gielen et al., “Emerging yield and reliability challenges in
nanometer CMOS technologies,” in Proc. IEEE DATE, Mar. 2008,
pp. 1322–1327.
[2] E. Xiao, J. S. Yuan, and H. Yang, “CMOS RF and DC reliability subject
to hot carrier stress and oxide soft breakdown,” IEEE Trans. Device
Mater. Rel., vol. 4, no. 1, pp. 92–98, Mar. 2004.
[3] N. K. Jha, P. S. Reddy, D. K. Sharma, and V. Ramgopal Rao,
“NBTI degradation and its impact for analog circuit reliability,”
n-type oscillator’s lifetime is estimated as 50×106 s. However, it is IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2609–2615,
possible to achieve longer lifetime (>100 × 106 s) by adopting the Dec. 2005.
[4] Y.-L. R. Lu, Y.-H. Lee, W. J. McMahon, and T.-C. Fung, “Robust
longer channel length for the tail transistor. Therefore, the proposed
inductor design for RF circuits,” in Proc. IEEE CICC, Sep. 2006,
design technique mitigates the degraded performance and increases pp. 571–574.
both the LNA and the n-type LC oscillator’s lifetimes. [5] S. Naseh, M. J. Deen, and O. Marinov, “Effects of hot-carrier stress
While designing a p-type LC oscillator to reduce the NBTI on the performance of the LC-tank CMOS oscillators,” IEEE Trans.
effect, we consider the critical device’s bias condition which is a Electron Devices, vol. 50, no. 5, pp. 1334–1339, May 2003.
tail transistor in the p-type LC oscillator. Contrary to HCI, NBTI [6] W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda, S. Krishnan, and
is relatively independent of the channel length of device. Because Y. Cao, “Compact modeling and simulation of circuit reliability for
the higher vertical electric field across the gate oxide results in the 65-nm CMOS technology,” IEEE Trans. Device Mater. Rel., vol. 7, no. 4,
pp. 509–517, Dec. 2007.
NBTI effect of the pMOSFET, one can select a lower tail transistor [7] E. Maricau, P. De Wit, and G. Gielen, “An analytical model for hot
gate bias voltage to reduce the degradation in threshold voltage carrier degradation in nanoscale CMOS suitable for the simulation of
shift. By decreasing the gate bias voltage and increasing the tail degradation in analog IC applications,” Microelectron. Rel., vol. 48,
transistor’s device width, the RF performance remains the same as nos. 8–9, pp. 1576–1580, 2008.
the original circuit. The source–drain voltage and transconductance [8] R. L. de Orio, H. Ceric, and S. Selberherr, “Physically based models
of the pMOS tail transistor are chosen to have similar values to the of electromigration: From Black’s equation to modern TCAD models,”
original circuit so that the phase noise and output amplitude of the Microelectron. Rel., vol. 50, no. 6, pp. 775–789, 2010.
[9] J. R. Lloyd and R. H. Koch, “Study of electromigration-induced resis-
redesigned circuit are comparable with the original circuit.
tance and resistance decay in A1 thin film conductors,” in Proc. 25th
The performance degradation and lifetime limitation of RF circuits Annu. Rel. Phys. Symp., Apr. 1987, pp. 161–168.
due to EM are mainly due to current stress. To increase the lifetime of [10] B. K. Jones, Y. Z. Xu, T. C. Denton, and P. Zobbi, “Electrical mea-
degraded circuits, the current density through the critical component surements as early indicators of electromigration failure,” Microelectron.
should be decreased. Decreasing actual current would affect other Rel., vol. 35, no. 1, pp. 13–25, 1995.
circuit performance parameters. Therefore, a layout improvement [11] G. T. Sasse, M. Acar, F. G. Kuper, and J. Schmitz, “RF CMOS reliability
technique that increases the metal line width(s) to decrease current simulations,” Microelectron. Rel., vol. 48, nos. 8–9, pp. 1581–1585,
density is proposed for mitigation of the EM effect. As presented 2008.
[12] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise
in Section VI, the critical EM component in the cascode LNA is amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745–759,
the drain inductor L d . For inductors, increasing the line width has May 1997.
two effects. First, it decreases the initial baseline resistance, making [13] T. H. Lee and A. Hajimiri, “Oscillator phase noise: A tutorial,” IEEE J.
the initial point lower. Second, it decreases the rate of the resistance Solid-State Circuits, vol. 35, no. 3, pp. 326–336, Mar. 2000.