SIR C.R.R COLLEGE OF ENGINEERING.

, ELURU-7

Dept. of Electronics and Communication Engg.

Subject: VLSI DESIGN Class : III/IV B.Tech Date of Exam : 16/10/20

1. Design for testability is considered in production for chips because:

a) Manufactured chips are faulty and are required to be tested

b) The design of chips are required to be tested

c) Many chips are required to be tested within short interval of time which yields timely delivery for
the customers

d) All of the mentioned

Answer: c

Explanation: Design for testability is considered in production for chips because many chips are
required to be tested within short interval of time which yields timely delivery for the customers.

2. The functions performed during chip testing are:

a) Detect faults in fabrication b) Detect faults in design

c) Failures in functionality d) All of the mentioned

Answer: d

Explanation: The functions performed during chip testing are detecting faults in fabrication and
design failures in functionality.

3. ATPG stands for:

a) Attenuated Transverse wave Pattern Generation b) Automatic Test Pattern Generator

c) Aligned Test Parity Generator d) None of the mentioned

Answer: b

Explanation: ATPG is an Automatic Test Pattern Generator.

4. Delay fault is considered as:

a) Electrical fault b) Logical fault c) Physical defect d) None of the Mentioned

Answer: b

Explanation: Delay fault is considered a logical fault.

5. A metallic blob present between drain and the ground of the n-MOSFET inverter acts as:
a) Physical defect b) Logical fault as output is stuck on 0

c) Electrical fault as resistor short d) All of the mentioned

Answer: d

Explanation: A metallic blob present between drain and the ground of the n-MOSFET inverter acts as
Physical defect, Logical fault as output is stuck on 0, Electrical fault as resistor short.

6. High resistance short present between drain and ground of n-MOSFET inverter acts as:

a) Pull up delay error b) Logical fault as output is stuck at 1

c) Electrical fault as transistor stuck on d) All of the mentioned

Answer: a

Explanation: High resistance short present between drain and ground of n-MOSFET inverter acts as
Pull up delay error.

7. The defect present in the following MOSFET is:

a) Logical stuck at 1 b) Logical stuck at 0

c) Physical defect d) Electrical Transistor stuck open

Answer: d

Explanation: The dimensions of the gate is less than the distance between source and drain.

8. The fault simulation detects faults by:

a) Test generation b) Construction of fault Dictionaries

c) Design analysis under faults d) All of the mentioned

Answer: d

Explanation: None.

9. The ease with which the controller establishes specific signal value at each node by setting input
values is known as:

a) Testability b) Observability c) Controllability d) Manufacturability

Answer: c

Explanation: Controllability is defined as the ease with which the controller establishes specific signal
value at each node by setting input values.

10. The ease with which the controller determines signal value at any node by setting input values is
known as:
a) Testability b) Observability c) Controllability d) Manufacturability

Answer: b

Explanation: Observability is defined as the ease with which the controller determines signal value at
any node by setting input values.

11. The poor controllability circuits are:

a) Decoders b) Clock generators c) Circuits with feedback d) All of the mentioned

Answer: d

Explanation: None.

12. The circuits with poor observability are:

a) ROM b) PLA

c) Sequential circuits with long feedback loops d) All of the mentioned

Answer: c

Explanation: None.

13. Large number of input vectors are used to set a particular node (1) or (0), to propagate an error
at the node to output makes the circuit low on:

a) Testability b) Observability c) Controllability d) All of the mentioned

Answer: a

Explanation: The circuit is said to be low on Testability if large number of input vectors are used to
set a particular node (1) or (0), to propagate an error at the node to output.

14. Divide and Conquer approach to large and complex circuits for testing is found in:

a) Partition and Mux Technique b) Simplified automatic test pattern generation technique

c) Scan based technique d) All of the mentioned

Answer: a

Explanation: Divide and Conquer approach to large and complex circuits for testing is found in the
partition and Mux technique.

15. LSSD stands for:

a) Linear system synchronous detection b) Level sensitive system detection

c) Level sensitive scan design d) Level sensitive scan detection

Answer: c
Explanation: None.

16. Which are processing faults?

a) missing contact window b) parasitic transistor

c) oxide breakdown d) all of the mentioned

Answer: d

Explanation: Some of the real defects in chip such as processing faults are missing contact window,
parasitic transistor and oxide breakdown.

17. Surface impurities occurs due to ion migration.

a) true b) false

Answer: a

Explanation: Some of the material defects are bulk defects and surface impurities. Bulk defects are
cracks and crystal imperfection and surface impurities occurs due to ion migration.

18. Electromigration is a

a) processing fault b) material defects

c) time dependent failure d) packaging fault

Answer: c

Explanation: Different types of real defects in chips are processing fault, material defects, time
dependent failure and packaging fault. Time dependent failures are dielectric breakdown and
electromigration.

19. Which relation is correct?

a) failure – error – fault b) fault – error – failure

c) error – fault – failure d) error – failure – fault

Answer: b

Explanation: The relation fault – error – failure is correct. Error is caused by faults and failure which
is a deviation of the circuit is caused by error.

20. For a circuit with k lines __________ single stuck-at fault is possible.

a) k b) 2k c) k/2 d) k2

Answer: b

Explanation: For a circuit with k lines, 2k single stuck-at faults are possible and 3^k – 1 multiple
stuck-at faults are possible.
21 Single stuck-at fault is technology independent.

a) true b) false

Answer: a

Explanation: Single stuck-at fault is technology independent. It can be applied to TTL, CMOS etc. It is
also design style independent.

22. For a n signal lines circuit _____________ bridging faults are possible.

a) n b) 2n c) n2 d) n/2

Answer: c

Explanation: For circuit with n lines, n2 bridging faults are possible. Bridging fault occurs when two
lines are connected when they should not be connected. It leads to wired AND or wired OR.

23. IDDQ fault occurs when there is

a) increased voltage b) increased quiescent current

c) increased power supply d) increased discharge

Answer: b

Explanation: When input is low, both P and N transistors are conducting causing increase in
quiescent current which leads to IDDQ fault.

24. Which fault causes output floating?

a) stuck-open b) stuck-at c) stuck-on d) IDDQ

Answer: a

Explanation: Transistor with stuck-open fault causes output floating. Stuck-open faults requires two
vector tests.

25. Data retention time comes under __________ fault.

a) functional fault b) memory fault c) parametric fault d) structural fault

Answer: c

Explanation: One of the memory faults is a parametric fault. Some of the parametric faults are noise
margin, data retention time, power consumption, output levels, etc.

26. In PLA, missing cross point in OR-array leads to

a) OR fault b) growth fault c) missing fault d) disappearance fault

Answer: d
Explanation: In PLA, missing cross point in AND array leads to growth fault and missing cross point in
OR-array leads to disappearance fault.

27. In PLA, extra crosspoint in AND-array leads to

a) OR fault b) growth fault c) missing fault d) disappearance fault

Answer: d

Explanation: In PLA, extra crosspoint in AND-array leads to shrinkage or disappearance fault whereas
extra crosspoint in OR-array leads to appearance fault.

28. The number of paths ___________ with number of gates.

a) increases exponentially b) decreases exponentially

c) remains the same d) increases rapidly

Answer: a

Explanation: The number of paths increases exponentially with number of gates. Propagation delay
of the path exceeds the clock interval.

29. The quality of the test set is measured by

a) fault margin b) fault detection c) fault correction d) fault coverage

Answer: d

Explanation: The quality of a test set is measured by its fault coverage. It gives the fraction of fault
that are detected by the test set.

30. Circuit nodes cannot be probed for monitoring or excitation.

a) true b) false

Answer: a

Explanation: The entire surface of the chip other than the pads are sealed by an overglass layers and
thus circuit nodes cannot be probed for monitoring and excitation.

31. The circuit should be tested at

a) design level b) chip level c) transistor level d) switch level

Answer: b

Explanation: Chip design mistakes can be very costly both in terms of time and money. The circuit
should be tested at chip level itself. Design for testability is essential for good design.

32. ______ of the area is dedicated for testability.

a) 20% b) 10% c) 30% d) 25%

Explanation: Design for testability is an essential process for good design. Thus the designers
dedicate around 30% or more of chip area for testing.

33. Partitioning into subsystems are done at

a) design stage b) prototype stage c) testing stage d) fabrication stage

Answer: b

Explanation: At the prototype stage, partitioning into subsystems are done to solve all the
complexity problem. Each of these subsystems are self contained and independent.

34. In prototype testing, the circuits are

a) open circuited b) short circuited c) tested as a whole circuit d) programmed

Answer: a

Explanation: The connections are made open circuited so that one system can be divorced from
another as a last resort in prototype testing.

35. The number of test vectors for exhaustive testing is calculated by

a) 2(m+n) b) 2((m+n)/2) c) 2(m-n) d) 22(m+n)

Answer: a

Explanation: The total number of test vectors for exhaustive testing is given by 2(m+n). For example
if m is 20 and n is 24, the resultant number of test vectors for exhaustive testing is 244.

36. After partitioning, number of vectors is given by

a) 2(m+n) b) 2((m+n)/2) c) 2n+ 2m d) 22(m+n)

Answer: c

Explanation: If the system is partitioned for testing, exhaustive testing can be reduced to 2n + 2m a
much more reasonable proportion.

37. What are the dominant faults in diffusion layers?

a) short citcuit faults b) open circuit faults

c) short and open circuit faults d) power supply faults

Answer: a

Explanation: In MOS circuits, short circuit and open circuit in metal layer and short circuit in diffusion
layer are the dominant fault experienced.
38. Test pattern generation is assisted using

a) automatic test pattern generator b) exhaustive pattern generator

c) repeated pattern generator d) loop pattern generator

Answer: a

Explanation: Test pattern generation is assisted using automatic test pattern generators but they are
complicated to use properly and ATPG costs tend to rise rapidly with circuit size.

39. _____ of faults are easier to detect.

a) 50% b) 60% c) 70% d) 80%

Answer: d

Explanation: It is relatively easy to detect the first 80% of faults using various classical test strategies.

40. Hot carrier injection causes

a) threshold voltage shift b) transconductance degradation

c) threshold voltage shift & transconductance degradation d) none of the mentioned

Answer: c

Explanation: Hot carrier injection causes both threshold voltage shift and transconductance
degradation due to charge accumulation in the gate oxide.

41. Oxide breakdown occurs due to

a) electrostatic charge b) threshold voltage

c) voltage shift d) poor input/output pad circuitry

Answer: d

Explanation: Oxide breakdown occurs due to inadequate protection against electrostatic discharge
and also due to defect or poor design in input/output pad circuitry.

42. Which model is used for pc board testing?

a) stuck at b) stuck in c) stuck on d) stuck through

Answer: a

Explanation: The stuck at model is used in the testing of pc boards and is not sufficient to test actual
VLSI CMOS circuits.

43. Which type of PLD should be used to program basic logic functions?

1. SLD 2. CPLD 3. PAL 4. PLA

44. PLAs, CPLDs, and FPGAs are all which type of device?

1. SLD 2. EPROM 3. SRAM 4. PLD

Answer: PLD

45.The content of a simple programmable logic device (PLD) consists of:

1. thousands of basic logic gates and advanced sequential logic functions

2. advanced sequential logic functions

3. thousands of basic logic gates

4. fuse-link arrays

ANSWER : thousands of basic logic gates and advanced sequential logic functions

46.The complex programmable logic device (CPLD) contains several PLD blocks and:

1. a language compiler 2. field-programmable switches

3. AND/OR arrays 4. a global interconnection matrix

ANSWER : a global interconnection matrix

47. The input signal combination in exhaustive testing is given as

a) 2N b) 21/N c) 2(M+N) d) 1/2N

Answer: a

Explanation: For testing an N input circuit using exhaustive testing, the total number of input
combinations can be given as 2N.

48. Observability is the process of

a) checking all inputs b) checking all outputs

c) checking all possible inputs d) checking errors and performance

Answer: b

Explanation: Observability is the process of observing outputs for all the input combinations.

49. Exhaustive testing is suitable when N is

a) small b) large c) any value for N d) very large

Explanation: Exhaustive testing is the process where all possible input combinations are used. This is
suitable when N is relatively small.

50. Test vectors in sensitized path-based testing is generated

a) before enumerating faults b) after enumerating faults

c) after designing d) before designing

Answer: b

Explanation: In sensitized path-based testing, test vectors are generated after enumerating the
possible faults because many patterns may not occur during the application of the circuit.

51. To propagate the fault along the selected path to primary output, setting _____ is done.

a) AND to 1 b) OR to 1 c) NOR to 1 d) NAND to 0

Answer: a

Explanation: Inputs of another gate is determined so as to propagate the fault signal along the
selected path to primary output of the circuit. This is done by setting AND/NAND to 1 and OR/NOR
to 0.

52. In D-algorithm, a particular ______ fault is detected by examining the _____ conditions.

a) internal, output b) internal, input c) external, output d) external, input

Answer: a

Explanation: In a circuit comprising combinational logic, D-algorithm aims at detecting a particular

53. D-algorithm is based on

a) existence of one fault machine b) existence of one good machine

c) existence of one fault and one good machine d) existence of two fault machines alone

Answer: c

Explanation: D-algorithm is based on the hypothesis of the existence of two machines – one good
machine and one faulty machine.

54. The existence of fault in faulty machine causes discrepancy in behaviour of the circuit for all
values on inputs.

a) true b) false

Answer: b
Explanation: The existence of fault in faulty machine causes discrepancy in its behaviour and that of
the good machine for some particular values of inputs.

55. In D-algorithm, the discrepancy is driven to _____ and observed and thus detected.

a) all inputs b) particular inputs c) output d) end of the circuit

Answer: c

Explanation: In D-algorithm, a systematic means is provided to driven the discrepancy to output and
it is observed and detected.

56. D-algorithm is time intensive for large circuits.

a) true b) false

Answer: a

Explanation: D-algorithm is extremely time intensive and computing intensive for large circuits and
many modifications and improvements are done.

57. The basic figures of merit for MOS devices are

a) Minimum Feature size b) Low Power dissipation

c) Maximum operational frequency d) All of the mentioned

Answer: d

Explanation: All the mentioned are the basic figures of merit for MOS devices.

58. For the constant field model, the scaling factors β and α are related as:

a) β = α b) α = 2β c) β = 1 d) β = α = 0

Answer: a

Explanation: In Constant field model, β = α.

59. In Constant Voltage model, the scaling factors β and α are related as:

a) β = α b) α = 2β c) β = 1 d) β = α = 1

Answer: c

Explanation: In Constant Voltage model, β = 1.

60. The scaling factor for the supply voltage VDD is:

a) 1 b) 0 c) 1/α d) 1/β
Answer: d

Explanation: The supply voltage VDD has the scaling factor of 1/β.