Logic selection guide 2016

Standard Logic and Mini Logic

in leaded and leadless packages
2 NXP Logic selection guide 2016
Standard Logic and Mini Logic:
tuned for today’s systems

Logic may have been around since the days when

engineers still used slide rules, but logic is still an
essential part of embedded design.
It’s the go-to resource for I/O expansion and interfacing 4 
Enables quick reconfiguration, by adding gates
between analog and digital domains, but that’s just the outside the core logic or MCU, for selection of
beginning. In many ways, today’s designers need logic debugging and functional modes
more than ever. Why? Because today’s systems need 4 Provides the interface between peripherals, by
to be smaller, more power efficient, and more portable performing level translation, reset control, power
than ever before. That means managing tight layouts, sequencing, signal switching, signal isolation, and so on
and dealing with looped traces, which can generate 4 Uses low-power functions to add new features
cross-talk and create signal-integrity issues. It also means without overtaxing the battery
working with multi-layer boards, implementing real-time 4 
Enables the integration of touchscreens and
responses to real-world events, and supporting multi- touchpads with multiplexers, shifters, and latches
tasking operations. In many cases, the right logic device 4  Implements video switching between different
makes these things easier to manage, and helps optimize displays and video formats by doing format
operation. conversion, adapting interfaces to controllers, and
multiplexing/demultiplexing the connectors
Here are just some of the ways that Standard and Mini 4 E xtends GPIO and drives LEDs
Logic works in today’s embedded systems: 4 
Supports automotive applications by implementing
simple motor control, smart key detection, security
alarms, speed alerts, and more

NXP Logic selection guide 2016 3

 Table of contents

Standard Logic and Mini Logic: Product listing by function 65

tuned for today’s systems 3 Analog switches 66
Buffers/inverters/drivers 68
Where logic really stands out 6 Bus switches 75
Counters/frequency dividers 76
NXP is the #1 volume leader 7
Decoders/demultiplexers 78
Combination and configurable logic 8 Digital comparators 80
Digital multiplexers 80
Our approach to quality 11 Encoders 81
FIFO registers 82
Portfolio overview 12
Flip-flops 82
Special features 15 Full adders 86
Bus hold 16 Gates 87
Source termination 17 AND gates 87
Overvoltage-tolerant inputs 18 Combination gates 88
Overvoltage-tolerant outputs 19 EXCLUSIVE-OR gates 89
Power-off leakage (IOFF) circuitry 19 EXCLUSIVE-NOR gates 89
Schmitt-trigger inputs 20 NAND gates 90
Live insertion 21 NOR gates 92
Low-threshold inputs 22 OR gates 93
Open-drain outputs 23 Latches / registered drivers 94
Input-clamping diodes 23 Level shifters/translators 96
Low delay isolation 24 Multivibrators 98
Parity generators/checkers 99
High-voltage families 25 Phase-locked loops 99
HEF4000B logic 25 Schmitt triggers 100
HC(T) logic 28 Shift registers/LED drivers 102
AHC(T) logic 38 Transceivers 104
VHC(T) logic 42
XC7 logic 43 Q100 Standard Logic functions & packages 107
NPIC logic 44 Analog switches 107
CBT(D) logic 45 Buffers/inverters  108
Bus switches 110
Low-voltage families 46 Counters/frequency dividers 110
LV logic 46 Digital decoders/demultiplexers 111
LVC logic 48 Flip-flops 112
ALVC logic 54 Digital multiplexers 112
LVT logic  56 Gates 114
ALVT logic 58 Latches/registered drivers 116
AVC(M) logic 59 Multivibrators 117
AUP logic 60 Level shifters/translators 117
AXP logic 63 Shift registers 118
CBTLV(D) logic 64 Schmitt triggers 118

4 NXP Logic selection guide 2016

 Transceivers 120 SOT337-1 145
Standard logic packages 121 SOT338-1 145
SOT339-1 146
Q100 Mini Logic functions & packages 122 SOT519-1 146
Bus switches 122 SOT724-1 147
Analog switches 122 SOT1174 147
Buffers/inverters 123 SOT1161 148
Flip-flops 125 SOT137-1 148
Digtial multiplexers 125 SOT556-1 149
Digtial decoders/demultiplexers 125 SOT340-1 149
Gates 126 SOT355-1 150
Multivibrators 128 SOT815-1 150
Scmitt-triggers  128
Latches/registered drivers 128 Design tools 151
Mini Logic packages 129
Level shifters/translators 129 Competitive cross reference 154

Packages 130

Nomenclature 133

Package diagrams 134

SOT353 134
SOT363 134
SOT457 135
SOT505-2 135
SOT650-1 136
SOT753-1 136
SOT765-1 137
SOT833-1 137
SOT886 138
SOT891 138
SOT902-2 139
SOT996 139
SOT1049-3 140
SOT1081-1/2 140
SOT1089 141
SOT1202 141
SOT1203 142
SOT1226 142
SOT815-1 143
SOT402-1 143
SOT403-1 144
SOT360-1 144
 Where logic really stands out

Logic is great for making minor modifications and fine-tuning performance

in the later design stages, but that’s not all it can do. Today’s logic devices
let you add features and improve functionality, so you can meet your design
requirements right from the start, even before you need to think about last-
minute revisions.

ASIC-driven systems Computing

In systems that use application-specific integrated In tablets and laptops, logic can be used for battery
circuits (ASICs), logic gates can be used to provide charging and discharging blocks, and to provide
control or “glue” functions. Modern logic families standby mode, power-down, and start-up control
include features, such as overvoltage tolerance, sequences. In docking stations and systems that
that enable them to be used as glue logic between support multiple displays, logic provides the bus
ASICs that use different supply voltages. In some switches, resets, and audio blocks that reduce the
cases, this can extend the lifetime of legacy ASICs. impact of noisy signals, and can be used to buffer
Available in small-footprint packages, such as the clock and data signals.
PicoGate, MicroPak, and Diamond, today’s glue
logic is suitable for space-constrained applications. Mobile
In mobile devices such as smartphones, tablets, and
MCU-driven systems cameras, logic provides multiplexing, buffering,
In systems that use a microcontroller (MCU), logic and level-translation functions for the baseband, RF
products are used for low-cost I/O expansion. interfaces, memory, and other peripherals.
Shift registers are used for digital I/O expansion,
and analog switches are used to multiplex analog Audio
sensor inputs. The combination of the two enables Logic buffers are used in external speakers and
the selection of lower-pincount MCUs with fewer other high-end audio equipment to buffer the
analog-to-digital converters. When used this way, clock, sync, and data signals sent to the audio
standard logic enables true cost optimization of an interface and docking station.
application. Dual supply-voltage translators make it
possible to use MCU-based systems across multiple
supply-voltage domains.

6 NXP Logic selection guide 2016

NXP is the #1 volume leader

For the last 50 years, NXP’s logic business has supported the growing global
demand for logic. Today, as the No. 1 volume logic supplier, we offer a
remarkably broad portfolio of cutting-edge solutions and best-in-class packages.
Add this to our ability to support high-volume requirements, and our reputation
as a trusted supplier of exceptionally high quality, and NXP is the logical choice as
a partner for the long term.

Selection formats, so you can be confident that, whichever

We offer thousands of products, so it’s easier to package you select, it will be available for as long
find what you want, when you want it. You can as you need it.
be certain that our portfolio has just the right
combination of functions, packages, and operating Voltages
voltages. We also offer special features that make Today’s systems often include products that
your work easier, by simplifying design, increasing work at different operating voltages, and there’s
performance, adding flexibility, or all of the above. no single voltage that works for every system.
We offer a wide variety of operating voltages to
Innovation choose from, so you can simplify your selection
Logic continues to evolve, and that means our process and improve system performance. Look for
portfolio does, too. We consistently deliver new coverage in both the low and the high end of the
ideas, whether it’s higher integration, lower power, operating range, from 0.8 to 5 V and beyond.
smaller packaging, or just a better way to do
things. Combination logic, for example, provides Ruggedness
more than one function in a single package, so If you’re designing a system that needs to perform
you can do more with a single inventory item. in rugged environments, our many products that
Another example is configurable logic, which lets conform to the automotive standard AEC-Q100
you use a single package to configure up to nine can help you meet the necessary requirements.
different functions. The benefits are better system Our automotive logic devices have been verified
performance with a lower bill of materials, and a to perform at higher temperatures, and can be
smaller board. counted on to provide reliable operation in tough
situations.
Packaging
We are a recognized leader in packaging Commitment
technology, and offer the industry’s largest Having a partner you can count on makes it easier
portfolio of logic functions in leadless DQFN, to meet deadlines and complete designs. At NXP,
MicroPak, and Diamond packages. That includes we are fully committed to the logic market and
more than 50 leadless packages, all of which are continue to invest in new process technologies, new
qualified for use in automotive applications. And, packaging technologies, and new manufacturing
while we offer a wide range of the latest leadless facilities. These are the things that keep our
formats, we also understand that legacy packages, portfolio competitive, and ensure our longevity as
like SO and TSSOP, still have their place in some technology partner.
designs. We continue to support these older

NXP Logic selection guide 2016 7

 Combination and configurable logic

NXP’s combination and configurable logic devices make it possible to do more with less,
because they give you more ways to implement the “glue” logic functions commonly
found in today’s complex systems. These flexible and innovative single-package
solutions let you replace discrete logic solutions with a configurable or combination
logic device, so you can potentially reduce pin count, device count, system cost, and
assembly-related expenses. These devices can also simplify inventory control and
reduce qualification effort, since there are fewer discrete logic devices to deal with.

What is combination logic? makes pick-and-place operations more efficient, and

Combination logic places two or more dissimilar lowers the cost of assembly. Combining functions also
functions in a single package. The functions can either be reduces the footprint of the solution and, if the devices
internally cascaded or fully independent. are internally cascaded, simplifies the PCB layout.

Benefits of combination logic Learn more:

Combination logic reduces the number of components www.nxp.com/logic
in the bill of materials (BOM), and that improves logistics,

0832 COMBINATION 3208 COMBINATION

1 1
A A
3
OR 3
B B
4 4
6 Y 6 Y
C C

3 INPUT OR – AND 3 INPUT AND – OR

Combination logic = one package, two or more different functions

8 NXP Logic selection guide 2016

What is configurable logic? device requires only one tape-and-reel position in the
Configurable logic places up to nine functions in a pick-and-place machine, and this increased efficiency
single package. These functions include 2-input AND, lowers the assembly cost.
OR, NAND, NOR, XOR, or XNOR gates, plus inverters
and buffers, and a 2:1 mux. The logic function is Dual PCB configurable logic for more ways to save
selected by connecting input pins to either GND or space and lower cost
VCC. Schmitt-trigger inputs are standard. Low input- Dual PCB configurable logic from NXP combines two
threshold options are included in NXP’s portfolio, to configurable logic devices in a single package. It gives
interface between different supply-voltage domains. engineers a more flexible, more economical way to
implement control logic solutions. These advantages
Benefits of configurable logic can mean lower system cost, improved inventory
Using a configurable logic device to replace three management, and fewer qualification expenses during
components in an application (an inverter, a buffer, development. Simply put, dual PCB configurable logic is
and an AND gate, for example), means only one device the next step in logic design.
needs to be qualified, not three. Similarly, from a
logistics standpoint, the configurable device replaces Learn more:
three types on the BOM, and this reduces inventory www.nxp.com/logic
costs. In the manufacturing phase, the configurable

B
Y
C

A
Y B
C Y
C B
Y
C
A
Y
C

B
Y
C
B Y
B
Y
C

A
Y
C
A Y
A
Y
C

Configurable logic = one package, nine or more functions

NXP Logic selection guide 2016 9

10 NXP Logic selection guide 2016
Our approach to quality

At NXP, we recognize the vital importance of quality in electronic components, and

understand its critical effect on the viability and economics of finished equipment. This is
especially true for semiconductors, which often perform critical circuit functions in harsh
environments. Our commitment to quality means we continuously strive to improve our
products and processes to ensure they reach the highest possible quality standards.

Zero-defect program
We have an NXP-wide “zero-defect” quality program in Green products
place, and view it as a part of our everyday way of doing Concern for the environment has driven us to offer a
business. Our pursuit of improvement is ongoing, as we broad portfolio of Dark Green products that are free
strive to eliminate incidents in production, reduce the of lead and halogen, and we comply fully with the
rate of incoming complaints, and lower the defect-per- European Union’s Restriction on Hazardous Substances
billion (DPB) level to zero. (RoHS) Directive 2002/95/EC.

Six-Sigma program Automotive portfolio

As part of our overall corporate strategy, we involve the To support automotive applications and other
entire organization in process improvement. “Design applications that operate under extreme conditions,
for Six-Sigma” and “Design for eXcellence” (DfX) are we offer the –Q100 portfolio. These are all qualified to
embedded in our processes for creating products. NXP's internal automotive grade, which exceeds the
In production, we employ a structured approach to requirements required by the Automotive Electronics
identifying outliers (maverick lots) and defects, and Council AEC-Q100 standard.
remove them from the manufacturing process to
minimize any spill-over effect. Certifications and standards
We have achieved certification for all the international
Safe-Launch (DfX) standards relevant to our industry, including ISO/IEC
Our guiding philosophy for all product launches is to 9001, ISO/IEC 14001, and OHSAS 18001, as well as ISO/
achieve a best-in-class DPB level immediately, at the TS 16949 and VDA 6.3 (for automotive sites).
start of production.

Complaint handling
In cooperation with customers, we use continual process
improvement to achieve best-in-class performance in
handling complaints and solving problems.

NXP Logic selection guide 2016 11

 Portfolio overview

From old favorites to new innovations We help reduce complexity while adding flexibility, by
We offer one of the broadest selections of logic, from offering a long list of special features available across
mature BiCMOS families to the latest in advanced, low- a number of families. Also, to support industrial and
power CMOS technology. We constantly find ways to automotive applications, our logic is available in options
reduce power consumption and minimize footprint. Our that are characterized and specified from -40 to +125 °C.
advanced CMOS processes deliver robust performance,
and are the reason why we can provide so many low- The NXP logic portfolio includes:
power families that support low-voltage applications. Standard logic functions available in SO, TSSOP and
DQFN packages with 14 contacts or more.
We are always careful to match the needs of today’s Mini Logic functions in smaller footprint PicoGate and
applications and systems, and that’s why our portfolio MicroPak packages with 10 contacts or less.
focuses on reduced power consumption and smaller size.

Logic portfolio by family, in high- and low-voltage categories

High-voltage families
I N C R E A S I N G P E R F O R M A N C E

Family HEF4000B HC(T) AHC(T) VHC(T) XC7 NPIC CBT(D)

Supply voltage (V) 3 to 15 2 to 6 2 to 5.5 2 to 5.5 2 to 5.5 2.3 to 5.5 4.5 to 5.5
Propagation delay, typ (ns) 60 9 5 5 5 5 0.25
Output drive (mA) ±3 ±8 ±8 ±8 ±8 100 Not applicable
Standby current (µA) 600 80 40 40 40 200 3
Temperature range (°C) -40 to +85 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +85
AEC-Q100 option • • • • • • •
Process technology
CMOS • • • • • • •
Functions
Gates • • • • •
MSI • • • • • •
Buffers • •
Analog switches • • •
Bus interfaces/channels (bits) 8 8
LED drivers • •
Bus switches •
Level translators •
Features
Overvoltage-tolerant inputs up
• • • •
to 5 V
Schmitt-trigger inputs • • • • •
Low-threshold inputs • • • •
Open-drain outputs • • •
Input-clamping diodes • • •
TTL inputs • • • •
Low delay isolation •

12 NXP Logic selection guide 2016

Low-voltage families
I N C R E A S I N G P E R F O R M A N C E

Family LV LVC ALVC LVT ALVT AVC(M) AUP AXP CBTLV(D)

Supply voltage (V) 1 to 3.61

1.2 to 3.6 2
1.2 to 3.6 2.7 to 3.6 2.3 to 3.6 1.2 to 3.6 0.8 to 3.6 0.7 to 2.75 2.3 to 3.6

Propagation delay, typ (ns) 9 2 2 2 1.5 2 4 3 0.15

Not
Output drive (mA) ±8 ±24 ±24 -32/64 -32/64 ±8 ±4 ±8
applicable
Standby current (µA) 20 20 40 120 90 20 0.9 0.6 10

Temperature range (°C) -40 to +125 -40 to +125 -40 to +85 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125

AEC-Q100 option • • • • • •

Process technology

CMOS • • • • • • •

BiCMOS • •

Functions

Gates • • • • • •

MSI • •

Buffers • • • • • • • •
Configurable and
• • •
combination logic
Analog switches • •
Bus interfaces/channels
8/16/32 8/16/32 8/16/32 8/16 16/32
(bits)
Bus switches •

Level translators • • • • •

Features

Bus hold • • • • •
Source
• • • • •
termination
Live insertion3 • • • • • •
Overvoltage-tolerant inputs
• • •
to 5 V
Overvoltage-tolerant inputs
• • • • •
to 3 V4
Power-off leakage (IOFF)
• • • • • •
circuitry
Schmitt-trigger inputs • • • • • • •

Low-threshold inputs •

Open-drain outputs • • • •

Input-clamping diodes •

Low delay isolation •

Rail-to-rail switching •

1
Some functions up to 5.5 V
2
PicoGate functions (1G, 2G, and 3G) operate up to 5.5 V
3
Functions meet some or all the requirements for live insertion
4
AXP inputs tolerant to 2.75 V only

NXP Logic selection guide 2016 13

Logic portfolio by function

High-voltage families Low-voltage families

HEF4000B

CBTLV(D)
Functions

AVC(M)
AHC(T)

VHC(T)

CBT(D)
HC(T)

ALVC

ALVT
NPIC

AUP

AXP
XC7

LVC

LVT
LV
Analog switches • • • • •

Buffers/inverters/drivers • • • • • • • • • • • • •

Bus switches • •

Counters/frequency
• • • •
dividers

Decoders/demultiplexers • • • • • •

Digital comparators • •

Digital multiplexers • • • • •

Encoders •

FIFO registers •

Flip-flops • • • • • • • • • •

Full adders •

Gates • • • • • • • • • • •

AND gates • • • • • • • • • • •

Combination gates • • • •

Configurable
• • •
multi-function gates
EXCLUSIVE-NOR
• •
gates

EXCLUSIVE-OR gates • • • • • •

NAND gates • • • • • • • • •

NOR gates • • • • • • • • • • •

OR gates • • • • • • • • • • •

Latches/registered
• • • • • • • • • •
drivers

Level shifters/translators • • • • • •

Multivibrators • • • • •

Parity generators/
•
checkers

Phase-locked loops • •

Schmitt triggers • • • • • • • • • • •

Shift registers/LED
• • • • • • •
drivers

Transceivers • • • • • • • • •

14 NXP Logic selection guide 2016

Special features

NXP offers a variety of special features that improve

performance, simplify design, lower cost, reduce the design
footprint, and eliminate external components.

This section highlights the features available across a number of families:

Bus hold 16
Source termination 17
Overvoltage-tolerant inputs 18
Overvoltage-tolerant outputs 19
Power-off leakage (IOFF) circuitry 19
Schmitt-trigger inputs 20
Live insertion 21
Low-threshold inputs 22
Open-drain outputs 23
Input-clamping diodes 23
Low delay isolation 24

The portfolio matrixes on page 14 show the features available in each family.

NXP Logic selection guide 2016 15

 BUS HOLD
What it does
Defines inputs and ensures that oscillations and excessive VCC Control Data
signals signals
current consumption, due to floating inputs, are avoided.
Can eliminate external pull-up/pull-down resistors. OE1 VCC

Controller
A0 OE2

74LVCH541
A1 Y0
A2 Y1
A3 Y2
Why it’s important A4
A5
Y3
Y4

CMOS inputs are high impedance. If they’re not defined, A6

A7
Y5
Y6
GND Y7

they can cause false switching and increase power

consumption. The bus-hold feature defines the input by
latching in the last logic level applied to the input. This
Using resistors to set default logic state
eliminates the external components required to define
the inputs, and that saves space, reduces the BOM, and
Resistors that set the default logic state can be sized as
reduces placement cost.
follows:
RPD < V TH/IBHHO
VCC RPU < (VCC - V TH)/ IBHLO
Input
pin
The input switching threshold voltage (V TH) is
approximately equal to (VIH + VIL)/2

Where you’ll find it

Bus-hold cell
The bus-hold feature is standard on all LVT and ALVT
CMOS input buffer
bus-interface products, including 8-, 16-, and 32-bit
buffers, inverters, drivers, flip-flops, latches/registered
The bus-hold feature drivers, level shifters/translators, and transceivers. On
other families, the bus-hold feature is indicated by an
The state of the bus-hold cell is indeterminate at power- “H” in the product number (e.g. 74LVCH245).
up, so external resistors may be needed to set a default
state at power-up, as shown here: 3.3 V 2.5 V 1.8 V 1.2 V

LVC,
LVC,
ALVC, LVC,
ALVC,
Bus hold LVT, ALVC, AVC(M)
ALVT,
ALVT, AVC(M)
AVC(M)
AVC(M)

16 NXP Logic selection guide 2016

SOURCE TERMINATION
What it does
Improves impedance matching in distributed systems Where you’ll find it
and eliminates the need for external termination Source-termination options are available in the low-
resistors. voltage BiCMOS families (LVT and ALVT) and the low-
voltage CMOS families [LVC, ALVC, AVC(M)]. Many of
NXP’s 8-, 16-, and 32-bit products – including buffers,
inverters, drivers, flip-flops, latches/registered drivers,
Rs ZL and transceivers – have source-termination options. In
transceivers, source termination is included on all I/O
ports.
VIN VSIG
A “2” is used to identify device types that include source
Buffer driving a source-terminated distributed load termination (e.g. 74LVT2244 & 74LVC162244).

3.3 V 2.5 V 1.8 V 1.2 V

Source-termination resistor
LVC,
LVC,
Why it’s important Source- ALVC, LVC,
ALVC,
termination LVT, ALVC, AVC(M)
Source termination is commonly used to terminate ALVT,
resistors ALVT, AVC(M)
AVC(M)
distributed systems so as to avoid issues with signal AVC(M)
integrity. The output resistance of the driver is matched
to the characteristic impedance of the distributed system
using an external resistor. Integrated source termination
solves signal-integrity issues associated with distributed
systems without the need of external components, and
thus reduces BOM and cost.

NXP Logic selection guide 2016 17

 OVERVOLTAGE-TOLERANT INPUTS
Input voltage Supply voltage
What they do Family
max (V) (V)
Enable high-to-low voltage-level translation without LVC 5.5 1.65 to 3.6
external components.
LVC PicoGate devices 5.5 1.65 to 5.5
ALVC devices without bus
Why they’re important 3.6 1.65 to 3.6
hold
Devices with overvoltage-tolerant inputs do not have LVT 5.5 2.7 to 3.6
input clamp diodes on digital inputs, and can be used
ALVT 5.5 2.3 to 3.6
to interface to higher-voltage systems without using
external current-limiting resistors. This reduces BOM and
CMOS input with no diode to VCC
cost.
The overshoot clamp diode in a typical CMOS input is
removed and there is no DC current path to VCC through
Where you’ll find them
the inputs. In an input cell with overvoltage protection,
The following families, in alphabetical order, have digital
as VIN > VCC + Vt, no current flows to VCC in the input cell.
inputs that are overvoltage-tolerant and can be used to
This feature is available across all voltages. As mentioned
interface with subsystems operating at a higher supply
above, the AVC and AUP families have a maximum VIN
voltage: AHC, ALVC, ALVT, AUP, AVC, AXP, CBTLV(D),
of 3.6 V. The LVC and ALVC families offer the feature on
LVC, and LVT. PicoGate devices in the LVC family can
versions without bus hold.
be used to interface subsystems with a power supply
of 5.0 V to subsystems with a supply of as low as 1.8 V.
The table shows the supply range of each family and the
maximum input voltage that can be applied.
VCC VCC

Input voltage Supply voltage

Family
max (V) (V)
AXP 2.75 0.7 to 2.75

AUP 3.6 0.8 to 3.6 ESD Input ESD Input

protection buffer protection buffer

AVC 3.6 1.2 to 3.6 Typical simplified CMOS input Over-voltage-tolerant CMOS input

AHC 5.5 2.0 to 5.5

Overvoltage protection provided by CMOS input with no diode to VCC
CBTLV(D) 3.6 2.3 to 3.6

18 NXP Logic selection guide 2016

OVERVOLTAGE-TOLERANT OUTPUTS
3-state CMOS output
3-stated outputs prevent a current path from the VCC
output to the supply voltage when a voltage higher 1
D G S+BG
than the supply voltage is applied to the output. In
3-State Bus P N P
some applications, such as mixed-voltage multi-drop 0
backplane applications, there is a risk of data contention
and even damage due to clamping caused by 3-state
outputs that are not overvoltage-tolerant. The AUP, Simplified CMOS Input Parasitic diode to VCC

AVC(M), AXP, and LVC logic families all have overvoltage-

tolerant 3-state CMOS outputs that switch the back gate Overvoltage protection provided by 3-state CMOS output
of the PMOS output driver to VCC or the output voltage,
whichever is higher.
VCC
3-state BiCMOS output
The LVT and ALVT families have overvoltage-tolerant
3-state BiCMOS outputs. A Schottky diode between
Comparator
VCC and the back gate prevents current flow to VCC. The VOUT
BiCMOS outputs also include self-protection. The output OE
is set to 3-state when VOUT > VCC + 0.5 V. IN

CMOS portion of BICMOS output

Overvoltage protection provided by 3-state CMOS output

POWER-OFF LEAKAGE (IOFF) CIRCUITRY

5V 3.3 V 2.5 V 1.8 V 1.2 V 0.8 V
What it does
Prevents potentially damaging leakage paths through LVC, LVC,
Power- LVC,
ALVC, ALVC,
the device when it’s powered down. off
LVT, ALVT,
ALVC, AVC(M),
leakage LVC AVC(M), AUP, AXP
ALVT, AVC(M),
(IOFF) AUP, AXP
Why it’s important AVC(M), AUP,
circuitry AXP
AUP AXP
Enables power-management strategies to use partial
power-down of subsystems, saves energy in battery-
powered applications, and prevents damage to devices Bus
VCC2
in telecommunications-infrastructure applications.

VCC1 = 0 Device 1
Where you’ll find it Ioff
The following families, in alphabetical order, include VCC3
AUP1G08
power-off leakage (IOFF) circuitry: ALVC, ALVT, AVC(M), Ioff
AUP, AXP, LVC, and LVT. Device 2
Ioff
Disabling power using the IOFF feature

NXP Logic selection guide 2016 19

 SCHMITT-TRIGGER INPUTS
What it does Where you’ll find it
Uses input hysteresis to prevent false switching and Schmitt-trigger inputs are standard on any of NXP’s 14,
ensure well-defined outputs when driven by slowly 17, 132, 4093, 40106, and configurable logic devices.
transitioning signals.
5V 3.3 V 2.5 V 1.8 V 1.2 V 0.8 V
Why it’s important HC,
Enables asynchronous analog systems to interface with AHC, HC,
HEF4000B, VHC, AHC,
digital systems. LVC,
Schmitt- HC(T), XC7, VHC,
ALVC, AUP,
trigger AHC(T), LV, LVC, XC7, AXP
AUP, AXP
inputs VHC(T), ALVC, LVC,
AXP
XC7, LV, LVC LVT, ALVC,
ALVT, ALVT
AUP

Logic 1
High treshold level

Low threshold level

Output
voltage

Symbol for a
Logic 0 Schmitt-trigger
0.8 V 1.8 V input

Lower threshold Upper threshold

Input voltage

Operation of Schmitt-trigger input

20 NXP Logic selection guide 2016

LIVE INSERTION
What it does flow into the inputs and outputs of an unpowered
Enables the installation or removal of a board while the device ensures that, when the device is inserted, the
system is powered up. effective load seen on a powered data bus is minimal.
Upon detection of the inserted board, the output enable
input should be used to prevent data contention on the
Low backplane. Devices that include power-up 3-state allow
System part
powering more time for the inserted board to be detected and the
up/down state of the output enable pin to be set.
Bus

Live insertion with IOFF and 3-state outputs

Active This feature, listed in datasheets as IPU/IPD or IOZPU/IOZPD,
system
part supports the same power-down mode as IOFF, but adds
High
the ability to keep outputs 3-stated during power-up
and power-down. This prevents outputs from turning
Live insertion
on before reaching the VCC trip point, as shown in the
figure. 3-state power-up mode also prevents the bus
Why it’s important
from loading at power-up. The 3-state power-up feature
Live insertion, which is also known as hot swapping or is available on NXP’s low-voltage LVT and ALVT families
hot plugging, involves inserting or extracting a board (the outputs 3-state below VCC = 1.2 V), and on the 5 V
without switching off the power. That minimizes down ABT family (the outputs 3-state below VCC = 2 V).
time, and makes it easier to repair or upgrade a system.
The goal is to maintain data integrity on the system
bus while preventing damage to components on the OE follows VCC, ensuring device remains in 3-state
host system or on the inserted/extracted card. Various (Z) during power-up/down

degrees of bus isolation makes this possible. Vcc

3.3 V

Where you’ll find it

Every NXP logic family supports some level of bus 1.2 V

isolation, but live insertion is enabled by using one of

three features: IOFF on its own, IOFF with 3-state outputs,
or IOFF, 3-state outputs and the BIAS V pin. Output
Off (Z) On Off (Z)

Live insertion with IOFF

The IOFF feature, which is described later in this chapter, Power-up mode with 3-state outputs
supports partial power-down mode. Preventing current

5V 3.3 V 2.5 V 1.8 V 1.2 V 0.8 V

LVC, ALVC, LVC, ALVC,

LVC Mini LVC, AVC(M), AVC(M), AUP,
Live insertion with IOFF AVC(M), AUP, AVC(M), AUP, AXP
Logic AUP AXP
AXP AXP
Live insertion with IOFF and 3-state
LVT, ALVT
outputs

NXP Logic selection guide 2016 21

 LOW-THRESHOLD INPUTS
What it does The circuitry is shown below:
Support voltage-level translation.
The combination of N1 sizing and drop across D1
Why it’s important determines the input threshold. Also, the P2 PMOS
Being able to configure the system to translate voltages, reduces the crossbar current through the inverter. HCT
according to the recommended guidelines for the input and AHCT products include TTL inputs, they operate at
and output voltage levels of each component, makes the 5 V supply and can be used to interface to 3.3 V outputs.
system more predictable, improves overall performance, AUP1T devices operate in the 3.6 V range and can be
and saves energy. used to interface with 1.8 V outputs.

Low-threshold inputs 5V 3.3 V 2.5 V 1.8 V

CMOS devices with input switching thresholds lower HCT
than the typical values can be used for low-to-high Low-threshold AHCT
AUP AUP AUP
inputs VHCT
voltage-level translation. XC7SET

VCC

D2 D3 P2

P1 P3
input 100 Ω 170 Ω
to logic
circuit
polysilicon D1
resistor N3
diffused N1
diode
resistor

GND

Simplified CMOS input with lower-then-typical threshold values

22 NXP Logic selection guide 2016

OPEN-DRAIN OUTPUTS
Open-drain outputs Where you’ll find it
An open-drain output can be pulled up to a voltage level The AHCT and HCT families support legacy TTL levels.
that matches the requirements of the device it’s driving. They operate at 5 V and can be used to interface with
As shown in the figure, a pull-up resistor (RPU) is used 3.3 V inputs. AUP1T devices operate at 3.3 V and can be
between the output and the pull-up voltage (VPU). VPU used to interface with 1.8 V inputs. The LVT and ALVT
can be set higher or lower than VCC, making open-drain families operate at 3.3 V and can be used to interface
outputs suitable for both low-to-high and high-to-low with 2.5 V inputs. Many of NXP’s buffer, inverter, and
voltage-level translation. gate devices include open-drain outputs.

VPU 5V 3.3 V 2.5 V 1.8 V 1.2 V 0.8 V

HEF4000B,
Pull-up HC,
resistor Open- NPIC, LVC,
Level shifter AHC, AUP, AUP,
with open-drain (RPU) drain HC(T), AUP, AXP
LV, LVC, AXP AXP
output outputs AHC(T), AXP
AUP
LV, LVC
Input

GND

Open-drain output and pull-up resistor for level translation

INPUT-CLAMPING DIODES
5V 3.3 V 2.5 V 1.8 V 1.2 V
What they do
Provide overvoltage and ESD protection, and enable Input- HEF4000B,
high-to-low level translation. clamping HC(T), HC, LV HC, LV LV LV
diodes LV

Why they’re important

In families that have an input-clamping diode to VCC, the Clamping
diode is a critical part of the input ESD-protection circuit. diode

The clamping property of the diode can also be used

VCC2 = 5 V
with an external current-limiting resistor so the input
can be interfaced to higher voltages. On some NXP
logic devices, the inputs have input-clamping diodes VCC1 = 15 V

to VCC and GND. When using CMOS devices that have Device A

current-limiting resistors at the inputs, the input voltage

can exceed maximum specified values as long as the RCL GND
maximum current rating is observed.
15 V - (5.0 V + 0.7 V) ESD Input
RCL = buffer
Where you’ll find them IIK
protection

The HEF4000B, HC(T), NPIC, and LV families all utilize

IIK is found in the limiting values table of the datasheet
ESD-protection circuits that include input-clamping
diodes to VCC. Input-clamping diodes support high-to-low level translation

NXP Logic selection guide 2016 23

 LOW DELAY ISOLATION
What it does Where you’ll find it
Enables the isolation of outputs on the same bus line NXP’s CBT(D) and CBTLV(D) families of bus switches
without introducing significant delay. provide isolation with a propagation delay of just 250 ps.

Why it’s important 5V 3.3 V 2.5 V 1.8 V 1.2 V

The propagation delay of 3-state buffers used for output Low delay
CBT(D) CBTLV(D)
isolation can seriously impact the timing margin, and this isolation
can be a critical issue in certain designs, including large
synchronous backplane applications.

VCC = 5 V CBTD3384

CBT3384

OE

3 V CPU 5 V CPU

3V 5V
3 V MEMORY 5 V I/O

3V 5V

CBT/CBTD3384 switch application

24 NXP Logic selection guide 2016

High-voltage families

This section includes the following high-voltage logic families,

in ascending order of performance

HEF4000B logic 25
HC(T) logic 28
AHC(T) logic 38
VHC(T) logic 42
XC7 logic 43
NPIC logic 44
CBT(D) logic 45

HEF4000B LOGIC
The HEF4000B series may be one of the LS devices. Standard HEF4000B devices are
oldest CMOS logic families around, but fully rated from -40 to +85 °C. Packages for
it’s still a popular choice due to its ease of extended temperature range (-55 to +125 °C)
design-in, wide operating supply range, are available as HEC devices.
excellent noise immunity, and low power
consumption. Features and benefits
4 Supply range from 3 to 15 V
HEF4000B logic devices are specified over 3 4 Standard temperature range of -40 to
to 15 V and are optimized for 5, 10, and 15 V +85 °C
operation. Equipped with buffered outputs, 4 Available extended temperature range
HEF4000B devices exhibit lower static and (HEC) of -55 to +125 °C
dynamic noise than TTL devices. Buffered 8/12-bit shift registers can drive 20 mA
4 
outputs also result in symmetrical output and loads (HEF4x94B)
improved transfer characteristics as loads Nearly all parts available in TSSOP and SO
4 
increase. HEF4000B logic is pin-compatible packages
with older CMOS4000 and 14500 devices.
Due to the LOCMOS process flow, HEF4000B Applications
devices offer lower stray capacitances, Medical equipment
4 
smaller size, and higher packaging density. General industrial applications
4 
Other important features include built-in Consumer electronics
4 
ESD protection, overvoltage-tolerant inputs, Toys and games
4 
and higher guaranteed fan-out for TTL and Glue-logic applications
4 

NXP Logic selection guide 2016 25

HEF4000B selection table (cont.) SO TSSOP SSOP
Suffix Suffix Suffix
Type number Function Description
T TT TS
HEF4000B NOR gates dual 3-input NOR gate •

HEF4001B NOR gates quad 2-input NOR gate •

HEF4002B NOR gates dual 4-input NOR gate •

HEF4007UB Combination dual complementary pair and inverter •

HEF40098B Buffers/inverters/drivers hex inverter •

HEF40106BP Schmitt triggers hex inverter Schmitt trigger • •

HEF40106BTT Schmitt triggers hex inverter Schmitt trigger

HEF4011B NAND gates quad 2-input NAND gate •

HEF4011UB NAND gates quad 2-input NAND gate •

HEF4013B D-type flip-flops dual D-tye flip-flop with set and reset; positive-edge trigger • •

HEF4014B Shift registers 8-bit shift register with synchronous parallel enable •

HEF4015B Shift registers dual 4-bit serial-in/parallel-out shift register •

HEF4016B Analog switches quad single-pole, single-throw analog switch •

HEF40174B D-type flip-flops hex D-type flip-flop with reset; positive-edge trigger •

HEF40175B D-type flip-flops quad D-type flip-flop with reset; positive-edge trigger • •

HEF4017B BCD/decade counters Johnson decade counter with 10 decoded outputs •

presettable synchronous 4-bit binary up/down counter; separate up/
HEF40193B Binary counters/timers •
down clocks
HEF4020B Binary counters/timers 14-stage binary ripple counter •

HEF4021B Shift registers 8-bit shift register with asynchronous parallel load • •

HEF4023B NAND gates triple 3-input NAND gate •

HEF40240B Buffers/inverters/drivers octal inverter/line driver (3-state) •

HEF40244B Buffers/inverters/drivers octal buffer/line driver (3-state) •

HEF4024B Binary counters/timers 7-stage binary ripple counter •

HEF4025B NOR gates triple 3-input NOR gate •

HEF4027B J-K type flip-flops dual J-K flip-flop •

Decoders/
HEF4028B 1-of-10 Decoder •
demultiplexers
HEF4030B EXCLUSIVE-OR gates quad 2-input EXCLUSIVE-OR gate •
Latches/registered
HEF40373B octal D-type transparent latch (3-state) •
drivers
HEF40374B D-type flip-flops octal D-type flip-flop; positive-edge trigger (3-state) •

HEF4040B Binary counters/timers 12-stage binary ripple counter •

Latches/registered
HEF4043B quad R/S latch with set and reset (3-state) •
drivers
Latches/registered
HEF4044B quad R/S latch with set and reset (3-state) •
drivers
HEF4046B Phase locked loops phase-locked-loop with VCO •

HEF4047B Multivibrators monostable/astable multivibrator •

HEF4049B Buffers/inverters/drivers hex inverter/line driver •

HEF4050B Buffers/inverters/drivers hex buffer/line driver •

HEF4051B Analog switches single-pole, octal-throw analog switch • • •

HEF4052B Analog switches dual single-pole, quad-throw analog switch • •

26 NXP Logic selection guide 2016

HEF4000B selection table (cont.) SO TSSOP SSOP
Suffix Suffix Suffix
Type number Function Description
T TT TS
HEF4053B Analog switches triple single-pole, double-throw analog switch • •

HEF4059B Divider counters programmable divide-by-n counter •

HEF4060B Divider counters 14-stage binary ripple counter with oscillator •

HEF4066B Analog switches quad single-pole, single-throw analog switch •

HEF4067B Analog switches single-pole, 16-throw analog switch •

HEF4068B NAND gates 8-input NAND gate •

HEF4069UB Buffers/inverters/drivers hex inverter; unbuffered • •

HEF4070B EXCLUSIVE-OR gates quad 2-input EXCLUSIVE-OR gate •

HEF4071B OR gates quad 2-input OR gate •

HEF4072B OR gates dual 4-input OR gate •

HEF4073B AND gates triple 3-input AND gate •

HEF4075B OR gates triple 3-input OR gate •

HEF4077B EXCLUSIVE-NOR gates quad 2-input EXCLUSIVE-NOR gate •

HEF4081B AND gates quad 2-input AND gate •

HEF4082B AND gates dual 4-input AND gate •

HEF4093B Schmitt triggers quad 2-input NAND gate Schmitt trigger •

8-bit serial-in/serial or parallel-out shift register with output register
HEF4094B Shift registers • •
(3-state)
Level shifters/
HEF4104B quad low-to-high voltage translator (3-state) •
translators
Decoders/
HEF4511B BCD to 7-segment latch/decoder/driver with lamp test input •
demultiplexers
Decoders/
HEF4514B 4-to-16 decoder/demultiplexer with address latches •
demultiplexers
HEF4516B Binary counters/timers presettable synchronous 4-bit binary up/down counter •

HEF4517B Shift registers dual 64-bit serial-in/parallel-out shift register •

HEF4518B BCD/decade counters dual BCD counter •

HEF4520B Binary counters/timers dual 4-bit synchronous binary counter •

HEF4521B Binary counters/timers 24-stage frequency divider and oscillator •

HEF4526B Binary counters/timers programmable 4-bit binary down counter •

HEF4528B Multivibrators dual retriggerable monostable multivibrator with reset •

HEF4538B Multivibrators dual retriggerable precision monostable multivibrator •

HEF4541B Binary counters/timers programmable timer •

Decoders/
HEF4543B BCD to 7-segment latch/decoder/driver with phase input •
demultiplexers
Decoders/
HEF4555B dual 1-to-4 line decoder/demultiplexer •
demultiplexers
HEF4557B Shift registers 1-to-64 bit shift register with variable length •

HEF4585B Digital comparators 4-bit magnitude comparator •

8-bit serial-in/serial or parallel-out shift register with output register LED
HEF4794B Shift registers •
driver (3-state)
12-bit serial-in/serial or parallel-out shift register with output register LED
HEF4894B Shift registers •
driver (3-state)

NXP Logic selection guide 2016 27

HC(T) LOGIC
HC(T) devices are high-speed CMOS logic available in the Features and benefits
industry’s broadest range of functions. HC products are 4 9 ns typical propagation delay
for use in CMOS applications from 2.0 to 6.0 V and HCT 4 Output drive capability IOH / IOL = ±8 mA
products are for use in TTL applications from 4.5 to 5.5 V. All 4 Low power
HC(T) devices offer a balanced output drive of 8 mA and a 4 Input clamp diodes
typical propagation delay of 9 ns, and are fully specified from 4 Broad portfolio
-40 to +125 °C.
Applications
Industrial
4 
Consumer electronics
4 
Computer peripherals
4 

HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Type Suffix Suffix Suffix Suffix Suffix Suffix
Function Description GD, GM,
number DP, PW DC DB D BQ GW, GV
GT
74HC00 NAND gates quad 2-input NAND gate • • • •
quad 2-input NAND gate;
74HCT00 NAND gates • • • •
TTL-enabled
74HC02 NOR gates quad 2-input NOR gate • • • •

74HCT02 NOR gates quad 2-input NOR gate; TTL-enabled • • • •

74HC03 NAND gates quad 2-input NAND gate; open-drain • • •

quad 2-input NAND gate; open-drain;
74HCT03 NAND gates • • •
TTL-enabled
Buffers/inverters/
74HC04 hex inverter • • • •
drivers
Buffers/inverters/
74HCT04 hex inverter; TTL-enabled • • • •
drivers
74HC08 AND gates quad 2-input AND gate • • • •

74HCT08 AND gates quad 2-input AND gate; TTL-enabled • • • •

74HC10 NAND gates triple 3-input NAND gate • • •

triple 3-input NAND gate;
74HCT10 NAND gates • • •
TTL-enabled
dual J-K flip-flop with reset; negative-
74HC107 J-K type flip-flops • • •
edge trigger
dual J-K flip-flop with reset; negative-
74HCT107 J-K type flip-flops •
edge trigger; TTL-enabled
dual J-/K flip-flop with set and reset;
74HC109 J-K type flip-flops • •
positive-edge trigger
dual J-/K flip-flop with set and reset;
74HCT109 J-K type flip-flops • • •
positive-edge trigger; TTL-enabled
74HC11 AND gates triple 3-input AND gate • • •

74HCT11 AND gates triple 3-input AND gate; TTL-enabled • • •

dual J-K flip-flop with set and reset;
74HC112 J-K type flip-flops • • •
negative-edge trigger
dual J-K flip-flop with set and reset;
74HCT112 J-K type flip-flops • • •
negative-edge trigger; TTL-enabled
dual retriggerable monostable
74HC123 Multivibrators • • • •
multivibrator with reset
dual retriggerable monostable
74HCT123 Multivibrators • • • •
multivibrator with reset; TTL-enabled
Buffers/inverters/
74HC125 quad buffer/line driver (3-state) • • • •
drivers

28 NXP Logic selection guide 2016

HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Type Suffix Suffix Suffix Suffix Suffix Suffix
Function Description GD, GM,
number DP, PW DC DB D BQ GW, GV
GT
Buffers/inverters/ quad buffer/line driver (3-state);
74HCT125 • • •
drivers TTL-enabled
Buffers/inverters/
74HC126 quad buffer/line driver (3-state) • • •
drivers
Buffers/inverters/ quad buffer/line driver (3-state);
74HCT126 • • •
drivers TTL-enabled
quad 2-input NAND gate Schmitt
74HC132 Schmitt triggers • • •
trigger
quad 2-input NAND gate Schmitt
74HCT132 Schmitt triggers • • •
trigger; TTL-enabled
Decoders/ 3-to-8 line decoder/demultiplexer;
74HC138 • • • •
demultiplexers inverting
Decoders/ 3-to-8 line decoder/demultiplexer;
74HCT138 • • • •
demultiplexers inverting; TTL-enabled
Decoders/
74HC139 dual 2-to-4 line decoder/demultiplexer • • • •
demultiplexers
Decoders/ dual 2-to-4 line decoder/
74HCT139 • • • •
demultiplexers demultiplexer; TTL-enabled
74HC14 Schmitt triggers hex inverter Schmitt trigger • • • •
hex inverter Schmitt trigger;
74HCT14 Schmitt triggers • • • •
TTL-enabled
74HC147 Encoders 10-to-4 line priority encoder • •
10-to-4 line priority encoder;
74HCT147 Encoders •
TTL-enabled
74HC151 Digital multiplexers 8-input multiplexer • • •

74HCT151 Digital multiplexers 8-input multiplexer; TTL-enabled • • •

74HC153 Digital multiplexers dual 4-input multiplexer • • •

74HCT153 Digital multiplexers dual 4-input multiplexer; TTL-enabled • • •

Decoders/
74HC154 4-to-16 line decoder/demultiplexer • • • •
demultiplexers
Decoders/ 4-to-16 line decoder/demultiplexer;
74HCT154 • • • •
demultiplexers TTL-enabled
74HC157 Digital multiplexers quad 2-input multiplexer • • • •

74HCT157 Digital multiplexers quad 2-input multiplexer; TTL-enabled • • • •

BCD/decade presettable synchronous BCD decade
74HC160 • • •
counters counter; asynchronous reset
presettable synchronous BCD decade
BCD/decade
74HCT160 counter; asynchronous reset; • •
counters
TTL-enabled
Binary counters/ presettable synchronous 4-bit binary
74HC161 • • •
timers counter; asynchronous reset
presettable synchronous 4-bit binary
Binary counters/
74HCT161 counter; asynchronous reset; • • •
timers
TTL-enabled
Binary counters/ presettable synchronous 4-bit binary
74HC163 • • •
timers counter; synchronous reset
presettable synchronous 4-bit binary
Binary counters/
74HCT163 counter; synchronous reset; • • •
timers
TTL-enabled
74HC164 Shift registers 8-bit serial-in/parallel-out shift register • • • •
8-bit serial-in/parallel-out shift register;
74HCT164 Shift registers • • • •
TTL-enabled
8-bit parallel or serial-in/serial-out shift
74HC165 Shift registers • • • •
register
8-bit parallel or serial-in/serial-out shift
74HCT165 Shift registers • • • •
register; TTL-enabled

NXP Logic selection guide 2016 29

HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Type Suffix Suffix Suffix Suffix Suffix Suffix
Function Description GD, GM,
number DP, PW DC DB D BQ GW, GV
GT
8-bit parallel or serial-in/serial-out shift
74HC166 Shift registers • • •
register
8-bit parallel or serial-in/serial-out shift
74HCT166 Shift registers register; TTL-enabled • •

quad D-type flip-flop; positive-edge

74HC173 D-type flip-flops • • •
trigger (3-state)
hex D-type flip-flop with reset;
74HC174 D-type flip-flops • • •
positive-edge trigger
hex D-type flip-flop with reset;
74HCT174 D-type flip-flops • • •
positive-edge trigger; TTL-enabled
quad D-type flip-flop with reset;
74HC175 D-type flip-flops • • •
positive-edge trigger
quad D-type flip-flop with reset;
74HCT175 D-type flip-flops • • •
positive-edge trigger; TTL-enabled
Binary counters/ presettable synchronous 4-bit binary
74HC191 • • •
timers up/down counter
Binary counters/ presettable synchronous 4-bit binary
74HCT191 •
timers up/down counter; TTL-enabled
Binary counters/ presettable synchronous 4-bit binary
74HC193 • • •
timers up/down counter
Binary counters/ presettable synchronous 4-bit binary
74HCT193 • • •
timers up/down counter; TTL-enabled
4-bit bidirectional parallel or serial-in/
74HC194 Shift registers • •
parallel-out shift register
4-bit bidirectional parallel or serial-in/
74HCT194 Shift registers •
parallel-out shift register; TTL-enabled
74HC1G00 NAND gates single 2-input NAND gate •
single 2-input NAND gate;
74HCT1G00 NAND gates •
TTL-enabled
74HC1G02 NOR gates single 2-input NOR gate •

74HCT1G02 NOR gates single 2-input NOR gate; TTL-enabled •

Buffers/inverters/
74HC1G04 single inverter •
drivers
Buffers/inverters/
74HCT1G04 single inverter; TTL-enabled •
drivers
Buffers/inverters/
74HC1G08 single 2-input AND gate •
drivers
74HCT1G08 AND gates single 2-input AND gate: TTL-enabled •
Buffers/inverters/
74HC1G125 single buffer/line driver (3-state) •
drivers
Buffers/inverters/ single buffer/line driver; TTL-enabled
74HCT1G125 •
drivers (3-state)
Buffers/inverters/
74HC1G126 single buffer/line driver (3-state) •
drivers
Buffers/inverters/ single buffer/line driver; TTL-enabled
74HCT1G126 •
drivers (3-state)
74HC1G14 Schmitt triggers single inverter Schmitt trigger; •
single inverter Schmitt trigger;
74HCT1G14 Schmitt triggers •
TTL-enabled
74HC1G32 OR gates single 2-input OR gate •

74HCT1G32 OR gates single 2-input OR gate; TTL-enabled •

74HC1G66 Analog switches single-pole, single-throw analog switch •

single-pole, single-throw analog
74HCT1G66 Analog switches •
switch; TTL-enabled
EXCLUSIVE-OR
74HC1G86 single 2-input EXCLUSIVE-OR gate •
gates

30 NXP Logic selection guide 2016

HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Type Suffix Suffix Suffix Suffix Suffix Suffix
Function Description GD, GM,
number DP, PW DC DB D BQ GW, GV
GT
EXCLUSIVE-OR single 2-input EXCLUSIVE-OR gate;
74HCT1G86 •
gates TTL-enabled
74HC20 NAND gates dual 4-input NAND gate • • •

74HCT20 NAND gates dual 4-input NAND gate; TTL-enabled • •

dual non-retriggerable monostable
74HC221 Multivibrators • •
multivibrator with reset
dual non-retriggerable monostable
74HCT221 Multivibrators • •
multivibrator with reset; TTL-enabled
Decoders/
74HC238 3-to-8 decoder/demultiplexer • • •
demultiplexers
Decoders/ 3-to-8 decoder/demultiplexer;
74HCT238 • • •
demultiplexers TTL-enabled
Buffers/inverters/
74HC240 octal inverter/line driver (3-state) • • •
drivers
Buffers/inverters/ octal inverter/line driver (3-state);
74HCT240 • • •
drivers TTL-enabled
Buffers/inverters/
74HC241 octal buffer/line driver (3-state) • • •
drivers
Buffers/inverters/ octal buffer/line driver; TTL-enabled
74HCT241 • • •
drivers (3-state)
Buffers/inverters/
74HC244 octal buffer/line driver(3-state) • • • •
drivers
Buffers/inverters/ octal buffer/line driver; TTL-enabled
74HCT244 • • • •
drivers (3-state)
74HC245 Transceivers octal transceiver (3-state) • • • •

74HCT245 Transceivers octal transceiver (3-state); TTL-enabled • • • •

74HC251 Digital multiplexers 8-input multiplexer (3-State) • • •

8-input multiplexer (3-State);
74HCT251 Digital multiplexers • • •
TTL-enabled
74HC253 Digital multiplexers dual 4-input multiplexer (3-State) • •
dual 4-input multiplexer (3-State);
74HCT253 Digital multiplexers • •
TTL-enabled
74HC257 Digital multiplexers quad 2-input multiplexer (3-State) • • •
quad 2-input multiplexer (3-State);
74HCT257 Digital multiplexers • • •
TTL-enabled
Latches/registered
74HC259 8 bit addressable latch • • • •
drivers
Latches/registered
74HCT259 8 bit addressable latch; TTL-enabled • • • •
drivers
74HC27 NOR gates triple 3-input NOR gate • • • •

74HCT27 NOR gates triple 3-input NOR gate; TTL-enabled • • • •

octal D-type flip-flop with reset;
74HC273 D-type flip-flops • • • •
positive-edge trigger
octal D-type flip-flop with reset;
74HCT273 D-type flip-flops • • • •
positive-edge trigger; TTL-enabled
Parity generators/ 9-bit odd/even parity generator/
74HC280 •
checkers checker
Parity generators/ 9-bit odd/even parity generator/
74HCT280 • •
checkers checker; TTL-enabled
74HC299 Shift registers 8-bit universal shift register (3-state) • • •
8-bit universal shift register (3-state);
74HCT299 Shift registers • • •
TTL-enabled
74HC2G00 NAND gates dual 2-input NAND gate • • •

74HCT2G00 NAND gates dual 2-input NAND gate; TTL-enabled • • •

NXP Logic selection guide 2016 31

HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Type Suffix Suffix Suffix Suffix Suffix Suffix
Function Description GD, GM,
number DP, PW DC DB D BQ GW, GV
GT
74HC2G02 NOR gates dual 2-input NOR gate • • •

74HCT2G02 NOR gates dual 2-input NOR gate; TTL-enabled • • •

Buffers/inverters/
74HC2G04 dual inverter •
drivers
Buffers/inverters/
74HCT2G04 dual inverter; TTL-enabled •
drivers
74HC2G08 AND gates dual 2-Input AND gate • • •

74HCT2G08 AND gates dual 2-Input AND gate; TTL-enabled • • •

Buffers/inverters/
74HC2G125 dual buffer/line driver (3-state) • • •
drivers
Buffers/inverters/ dual buffer/line driver (3-state);
74HCT2G125 • • •
drivers TTL-enabled
Buffers/inverters/
74HC2G126 dual buffer/line driver (3-state) • • •
drivers
Buffers/inverters/ dual buffer/line driver (3-state);
74HCT2G126 • • •
drivers TTL-enabled
74HC2G14 Schmitt triggers dual inverter Schmitt trigger •
dual inverter Schmitt trigger;
74HCT2G14 Schmitt triggers •
TTL-enabled
74HC2G17 Schmitt triggers dual buffer Schmitt trigger •
dual buffer Schmitt trigger;
74HCT2G17 Schmitt triggers •
TTL-enabled
74HC2G32 OR gates dual 2-input OR gate • • •

74HCT2G32 OR gates dual 2-input OR gate; TTL-enabled • • •

Buffers/inverters/
74HC2G34 dual 2-input OR gate •
drivers
Buffers/inverters/
74HCT2G34 dual buffer; TTL-enabled •
drivers
dual single-pole, single-throw analog
74HC2G66 Analog switches • • •
switch
dual single-pole, single-throw analog
74HCT2G66 Analog switches • • •
switch; TTL-enabled
EXCLUSIVE-OR
74HC2G86 dual 2-input EXCLUSIVE-OR gate • • •
gates
EXCLUSIVE-OR dual 2-input EXCLUSIVE-OR gate;
74HCT2G86
gates TTL-enabled
74HC30 NAND gates 8-input NAND gate • • •

74HCT30 NAND gates 8-input NAND gate; TTL-enabled • • •

74HC32 OR gates quad 2-input OR gate • • • •

74HCT32 OR gates quad 2-input OR gate; TTL-enabled • • • •

Buffers/inverters/
74HC365 hex buffer/line driver (3-state) • • •
drivers
Buffers/inverters/ hex buffer/line driver (3-state);
74HCT365 • • •
drivers TTL-enabled
Buffers/inverters/ hex buffer/line driver; Inverting
74HC366 • •
drivers (3-state)
Buffers/inverters/ hex inverter/line driver (3-state);
74HCT366 • • •
drivers Inverting TTL-enabled
Buffers/inverters/
74HC367 hex inverter/line driver • • •
drivers
Buffers/inverters/ hex buffer/line driver (3-state);
74HCT367 • • •
drivers TTL-enabled
Buffers/inverters/ hex buffer/line driver; Inverting
74HC368 • •
drivers (3-state)

32 NXP Logic selection guide 2016

HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Type Suffix Suffix Suffix Suffix Suffix Suffix
Function Description GD, GM,
number DP, PW DC DB D BQ GW, GV
GT
Buffers/inverters/ hex inverter/line driver; Inverting
74HCT368 • • •
drivers (3-state); TTL-enabled
Latches/registered
74HC373 octal D-type transparent latch (3-state) • • • •
drivers
Latches/registered octal D-type transparent latch (3-state);
74HCT373 • • • •
drivers TTL-enabled
octal D-type flip-flop; positive-edge
74HC374 D-type flip-flops • • •
trigger (3-state)
octal D-type flip-flop; positive-edge
74HCT374 D-type flip-flops • • •
trigger (3-state); TTL-enabled
octal D-type flip-flop with data enable;
74HC377 D-type flip-flops • • •
positive-edge trigger
octal D-type flip-flop with data enable;
74HCT377 D-type flip-flops • • •
positive-edge trigger; TTL-enabled
BCD/decade
74HC390 dual decade ripple counter • • •
counters
BCD/decade dual decade ripple counter;
74HCT390 • • •
counters TTL-enabled
Binary counters/
74HC393 dual decade ripple counter • • • •
timers
Binary counters/ dual 4-bit binary ripple counter;
74HCT393 • • • •
timers TTL-enabled
Buffers/inverters/
74HC3G04 triple inverter • • •
drivers
Buffers/inverters/
74HCT3G04 triple inverter; TTL-enabled • • •
drivers
Buffers/inverters/
74HC3G06 triple inverter; open-drain • • •
drivers
Buffers/inverters/ triple inverter; open-drain;
74HCT3G06 • • •
drivers TTL-enabled
Buffers/inverters/
74HC3G07 triple buffer; open-drain • • •
drivers
Buffers/inverters/
74HCT3G07 triple buffer; open-drain; TTL-enabled • • •
drivers
74HC3G14 Schmitt triggers triple inverter Schmitt trigger • • •
triple inverter Schmitt trigger;
74HCT3G14 Schmitt triggers • • •
TTL-enabled
Buffers/inverters/
74HC3G34 triple buffer • • •
drivers
Buffers/inverters/
74HCT3G34 triple buffer; TTL-enabled • • •
drivers
74HC4002 NOR gates dual 4-input NOR gate • • •

74HCT4002 NOR gates dual 4-input NOR gate; TTL-enabled • •

74HC40105 FIFO registers 4-bit x 16-word FIFO register • • •

4-bit x 16-word FIFO register;
74HCT40105 FIFO registers • •
TTL-enabled
dual 4-bit serial-in/parallel-out shift
74HC4015 Shift registers • •
register
dual 4-bit serial-in/parallel-out shift
74HCT4015 Shift registers •
register; TTL-enabled
quad single-pole, single-throw analog
74HC4016 Analog switches • •
switch
quad single-pole, single-throw analog
74HCT4016 Analog switches •
switch; TTL-enabled
BCD/decade Johnson decade counter with 10
74HC4017 • • • •
counters decoded outputs
BCD/decade Johnson decade counter with 10
74HCT4017 • •
counters decoded outputs; TTL-enabled

NXP Logic selection guide 2016 33

HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Type Suffix Suffix Suffix Suffix Suffix Suffix
Function Description GD, GM,
number DP, PW DC DB D BQ GW, GV
GT
Binary counters/
74HC4020 14-stage binary ripple counter • • • •
timers
Binary counters/ 14-stage binary ripple counter;
74HCT4020 • • • •
timers TTL-enabled
Binary counters/
74HC4040 12-stage binary ripple counter • • • •
timers
Binary counters/ 12-stage binary ripple counter;
74HCT4040 • • • •
timers TTL-enabled
74HC4046A Phase locked loops phase-locked-loop with VCO • • •
phase-locked-loop with VCO;
74HCT4046A Phase locked loops • •
TTL-enabled
74HC4051 Analog switches single-pole, octal-throw analog switch • • • •
single-pole, octal-throw analog switch;
74HCT4051 Analog switches • • • •
TTL-enabled
dual single-pole, quad-throw analog
74HC4052 Analog switches • • • •
switch
dual single-pole, quad-throw analog
74HCT4052 Analog switches • • • •
switch; TTL-enabled
triple single-pole, double-throw
74HC4053 Analog switches • • • •
analog switch
triple single-pole, double-throw
74HCT4053 Analog switches • • • •
analog switch; TTL-enabled
74HC4059 Divider counters programmable divide-by-n counter • •
programmable divide-by-n counter;
74HCT4059 Divider counters •
TTL-enabled
Binary counters/ 14-stage binary ripple counter with
74HC4060 • • • •
timers oscillator
Binary counters/ 14-stage binary ripple counter with
74HCT4060 • • •
timers oscillator; TTL-enabled
quad single-pole, single-throw analog
74HC4066 Analog switches • • • •
switch
quad single-pole, single-throw analog
74HCT4066 Analog switches • • • •
switch; TTL-enabled
74HC4067 Analog switches single-pole, 16-throw analog switch • • • •
single-pole, 16-throw analog switch;
74HCT4067 Analog switches • • • •
TTL-enabled
74HC4075 OR gates triple 3-input OR gate • •

74HCT4075 OR gates triple 3-input OR gate; TTL-enabled • • •

8-bit serial-in/serial or parallel-out shift
74HC4094 Shift registers • • •
register with output register (3-state)
8-bit serial-in/serial or parallel-out shift
74HCT4094 Shift registers register with output register; • •
TTL-enabled (3-state)
Decoders/
74HC42 BCD to decimal decoder (1-of-10) •
demultiplexers
Decoders/ BCD to decimal decoder (1-of-10);
74HCT42 •
demultiplexers TTL-enabled
dual retriggerable monostable
74HC423 Multivibrators • •
multivibrator with reset
dual retriggerable monostable
74HCT423 Multivibrators • • • •
multivibrator with reset; TTL-enabled
quad single-pole, single-throw analog
74HC4316 Analog switches • • •
switch with translation
quad single-pole, single-throw analog
74HCT4316 Analog switches • •
switch with translation; TTL-enabled
single-pole, octal-throw analog switch
74HC4351 Analog switches • • •
with latch

34 NXP Logic selection guide 2016

HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Type Suffix Suffix Suffix Suffix Suffix Suffix
Function Description GD, GM,
number DP, PW DC DB D BQ GW, GV
GT
single-pole, octal-throw analog switch
74HCT4351 Analog switches • •
with latch; TTL-enabled
Triple 2-channel analog multiplexer/
74HCT4353 Analog switches •
demultiplexer with latch; TTL-enabled
Decoders/ BCD to 7-segment latch/decoder/
74HC4511 •
demultiplexers driver with lamp test input
BCD to 7-segment latch/decoder/
Decoders/
74HCT4511 driver with lamp test input; •
demultiplexers
TTL-enabled
Decoders/ 4-to-16 decoder/demultiplexer with
74HC4514 • • •
demultiplexers address latches
Decoders/ 4-to-16 decoder/demultiplexer with
74HCT4514 • • •
demultiplexers address latches; TTL-enabled
Decoders/ 4-to-16 decoder/demultiplexer with
74HC4515 •
demultiplexers address latches; inverting
4-to-16 decoder/demultiplexer with
Decoders/
74HCT4515 address latches; inverting; •
demultiplexers
TTL-enabled
Binary counters/
74HC4520 dual 4-bit synchronous binary counter • • •
timers
Binary counters/ dual 4-bit synchronous binary counter;
74HCT4520 • • •
timers TTL-enabled
dual retriggerable precision
74HC4538 Multivibrators • • •
monostable multivibrator
dual retriggerable precision
74HCT4538 Multivibrators • • •
monostable multivibrator; TTL-enabled
74HC4851 Analog switches single-pole, octal-throw analog switch • • •
single-pole, octal-throw analog switch;
74HCT4851 Analog switches • • •
TTL-enabled
dual single-pole, quad-throw analog
74HC4852 Analog switches • • •
switch
dual single-pole, quad-throw analog
74HCT4852 Analog switches • • •
switch; TTL-enabled
Buffers/inverters/
74HC540 octal inverter/line driver (3-state) • •
drivers
Buffers/inverters/ octal inverter/line driver; TTL-enabled
74HCT540 • •
drivers (3-state)
Buffers/inverters/
74HC541 octal buffer/line driver (3-state) • • •
drivers
Buffers/inverters/ octal buffer/line driver (3-state);
74HCT541 • • •
drivers TTL-enabled
Buffers/inverters/ programmable delay timer with
74HC5555 •
drivers oscillator
Binary counters/ programmable delay timer with
74HCT5555 •
timers oscillator; TTL-enabled
Latches/registered octal D-type transparent latch;
74HC563 •
drivers inverting (3-state)
Latches/registered octal D-type transparent latch;
74HCT563 • •
drivers inverting (3-state); TTL-enabled
Latches/registered octal D-type transparent latch;
74HC573 • • • •
drivers inverting (3-state)
Latches/registered octal D-type transparent latch (3-state);
74HCT573 • • • •
drivers TTL-enabled
octal D-type flip-flop; positive-edge
74HC574 D-type flip-flops • • •
trigger (3-state)
octal D-type flip-flop; positive-edge
74HCT574 D-type flip-flops • • •
trigger (3-state); TTL-enabled
8-bit serial-in/parallel-out shift register
74HC594 Shift registers • • •
with output storage register

NXP Logic selection guide 2016 35

HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Type Suffix Suffix Suffix Suffix Suffix Suffix
Function Description GD, GM,
number DP, PW DC DB D BQ GW, GV
GT
8-bit serial-in/parallel-out shift register
74HCT594 Shift registers with output storage register; • •
TTL-enabled
8-bit serial-in/parallel-out shift register
74HC595 Shift registers • • • •
with output storage register (3-state)
8-bit serial-in/parallel-out shift register
74HCT595 Shift registers with output storage register (3-state); • • • •
TTL-enabled
8-bit parallel or serial-in/parallel-out
74HC597 Shift registers shift register with parallel input storage • • •
register
8-bit parallel or serial-in/parallel-out
74HCT597 Shift registers shift register with parallel input storage • • •
register; TTL-enabled
Binary counters/ programmable ripple counter with
74HC6323A •
timers oscillator (3-state)
Binary counters/ programmable ripple counter with
74HC640 • •
timers oscillator (3-state)
Binary counters/ programmable ripple counter with
74HCT640 • •
timers oscillator (3-state); TTL-enabled
74HC652 Transceivers octal registered transceiver (3-state) • • •
octal registered transceiver (3-state);
74HCT652 Transceivers • •
TTL-enabled
Latches/registered
74HC670 4-bit x 4-word register (3-state) • •
drivers
Latches/registered 4-bit x 4-word register (3-state);
74HCT670 • •
drivers TTL-enabled
Digital
74HC688 8-bit magnitude comparator • • •
comparators
Digital 8-bit magnitude comparator;
74HCT688 • • •
comparators TTL-enabled
74HC7030 FIFO registers 9-bit x 64-word FIFO register (3-state) •
9-bit x 64-word FIFO register (3-state);
74HCT7030 FIFO registers •
TTL-enabled
74HCT7046A Phase locked loops PLL with lock detector; TTL-enabled •
dual D-type flip-flop with set and
74HC74 D-type flip-flops • • • •
reset; positive-edge trigger
dual D-type flip-flop with set and
74HCT74 D-type flip-flops reset; positive-edge trigger; • • • •
TTL-enabled
74HC7403 FIFO registers 4-bit x 16-word FIFO register (3-state) •
4-bit x 16-word FIFO register (3-state);
74HCT7403 FIFO registers •
TTL-enabled
octal inverter/line driver Schmitt
74HC7540 Schmitt triggers • •
trigger (3-State)
octal inverter/line driver Schmitt
74HCT7540 Schmitt triggers •
trigger (3-State); TTL-enabled
octal buffer/line driver Schmitt trigger
74HC7541 Schmitt triggers • • •
(3-State)
octal buffer/line driver Schmitt trigger
74HCT7541 Schmitt triggers • •
(3-State); TTL-enabled
74HC7731 Shift registers quad 64-bit shift register • •

74HCT7731 Shift registers quad 64-bit shift register; TTL-enabled •

Digital 4-bit magnitude comparator;
74HCT85 • •
comparators TTL-enabled
EXCLUSIVE-OR
74HC86 quad 2-input EXCLUSIVE-OR gate • • •
gates
EXCLUSIVE-OR quad 2-input EXCLUSIVE-OR gate;
74HCT86 • • •
gates TTL-enabled

36 NXP Logic selection guide 2016

HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Type Suffix Suffix Suffix Suffix Suffix Suffix
Function Description GD, GM,
number DP, PW DC DB D BQ GW, GV
GT
9-bit inverter Schmitt trigger; open-
74HC9114 Schmitt triggers •
drain (3-state)
9-bit inverter Schmitt trigger; open-
74HCT9114 Schmitt triggers •
drain (3-state); TTL-enabled
9-bit buffer Schmitt trigger; open-drain
74HC9115 Schmitt triggers •
(3-state)
9-bit buffer Schmitt trigger; open-drain
74HCT9115 Schmitt triggers •
(3-state); TTL-enabled
Binary counters/
74HC93 4-bit binary ripple counter • •
timers
Binary counters/ 4-bit binary ripple counter;
74HCT93 •
timers TTL-enabled
Buffers/inverters/
74HC05 hex inverter; open-drain • • •
drivers
Decoders/ 3-to-8 line decoder/demultiplexer with
74HC137 • • •
demultiplexers address latches; inverting
74HC158 Digital multiplexers quad 2-input multiplexer; inverting •
Buffers/inverters/
74HC1GU04 single inverter; unbuffered •
drivers
74HC21 AND gates dual 4-input AND gate • • •
Decoders/ 3-to-8 decoder/demultiplexer with
74HC237 • • •
demultiplexers address latches
74HC243 Transceivers quad transceiver (3-state) • •

74HC283 Full adders 4-bit binary full adder with fast carry • • •
Buffers/inverters/
74HC2GU04 Dual inverter; unbuffered •
drivers
Buffers/inverters/
74HC3GU04 Triple inverter; unbuffered • • •
drivers
Binary counters/
74HC40103 8-bit synchronous binary down counter • • •
timers
Binary counters/
74HC4024 7-stage binary ripple counter • • •
timers
Level shifters/
74HC4049 hex inverter with 15V tolerant inputs • • •
translators
Level shifters/
74HC4050 hex inverter with 15V tolerant inputs • • •
translators
octal D-type flip-flop; inverting;
74HC564 D-type flip-flops • •
positive-edge trigger (3-state)
74HC58 Combination dual AND-OR gate • •
Binary counters/ 8-bit binary counter with output
74HC590 • • •
timers register (3-state)
74HC7014 Schmitt triggers hex buffer precision Schmitt trigger • •
EXCLUSIVE-NOR
74HC7266 quad 2-input EXCLUSIVE-NOR gate • •
gates
dual J-K flip-flop with reset; negative-
74HC73 J-K type flip-flops • • •
edge trigger
Latches/registered
74HC75 Quad Bistable Transparent Latch • • •
drivers
octal D-type flip-flop; inverting;
74HCT534N D-type flip-flops positive-edge trigger; TTL-enabled •
(3-state)
octal D-type flip-flop; inverting;
74HCT7273 D-type flip-flops positive-edge trigger; TTL-enabled •
(3-state)
PLL with bandgap controlled VCO;
74HCT9046A Phase locked loops • •
TTL-enabled
Buffers/inverters/
74HCU04 hex inverter; unbuffered • • • •
drivers

NXP Logic selection guide 2016 37

AHC(T) LOGIC
AHC(T) devices are advanced high-speed CMOS logic. They Features and benefits
are upgrades of the HC(T) family, with overvoltage-tolerant 4 Typical propagation delay of 5 ns
inputs for true mixed-voltage applications. AHC devices are 4 Output drive capability IOH / IOL = ±8 mA
for use in CMOS applications from 2.0 to 6.0 V and AHCT 4 Low power
devices are for use in TTL applications from 4.5 to 5.5 V. All 4 5 V tolerant inputs
AHC(T) devices offer a balanced output drive of 8 mA and a 4 Low noise: VOLP = 0.8 V (max.)
typical propagation delay of 5 ns, and are fully specified from
-40 to +125 °C. Applications
Industrial
4 
Consumer electronics
4 
Computer peripherals
4 
Communications
4 

AHC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Suffix
Suffix Suffix Suffix Suffix Suffix GD, GF,
Type number Function Description DP, GW,
PW DC DB D BQ GM, GN,
GV
GS, GT
74AHC00 NAND gate Quad 2-input NAND gate • • •
Quad 2-input NAND gate;
74AHCT00 NAND gate • • •
TTL-enabled
74AHC02 NOR gate Quad 2-input NOR gate • • •
74AHCT02 NOR gate Quad 2-input NOR gate; TTL-enabled • • •
Buffer/inverter/
74AHC04 Hex inverter • • •
driver
Buffer/inverter/
74AHCT04 Hex inverter; TTL-enabled • • •
driver
74AHC08 AND gate Quad 2-input AND gate • • •
74AHCT08 AND gate Quad 2-input AND gate; TTL-enabled • • •
Dual retriggerable monostable
74AHC123A Multivibrator • • •
multivibrator with reset
Dual retriggerable monostable
74AHCT123A Multivibrator • • •
multivibrator with reset; TTL-enabled
Buffer/inverter/
74AHC125 Quad buffer/line driver (3-state) • • •
driver
Buffer/inverter/ Quad buffer/line driver; TTL-enabled
74AHCT125 • • •
driver (3-state)
Buffer/inverter/
74AHC126 Quad buffer/line driver (3-state) • • •
driver
Buffer/inverter/ Quad buffer/line driver; TTL-enabled
74AHCT126 • • •
driver (3-state)
Quad 2-input NAND gate Schmitt
74AHC132 Schmitt trigger • • •
trigger
Quad 2-input NAND gate Schmitt
74AHCT132 Schmitt trigger • • •
trigger; TTL-enabled
Decoder/ 3-to-8 line decoder/demultiplexer;
74AHC138 • • •
demultiplexer inverting
Decoder/ 3-to-8 line decoder/demultiplexer;
74AHCT138 • • •
demultiplexer inverting; TTL-enabled
Decoder/ Dual 2-to-4 line decoder/
74AHC139 • •
demultiplexer demultiplexer
Decoder/ Dual 2-to-4 line decoder/
74AHCT139 • •
demultiplexer demultiplexer; TTL-enabled
74AHC14 Schmitt trigger Hex inverter Schmitt trigger • • •

38 NXP Logic selection guide 2016

AHC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Suffix
Suffix Suffix Suffix Suffix Suffix GD, GF,
Type number Function Description DP, GW,
PW DC DB D BQ GM, GN,
GV
GS, GT
Hex inverter Schmitt trigger;
74AHCT14 Schmitt trigger • • •
TTL-enabled
Digital
74AHC157 Quad 2-input multiplexer • • •
multiplexer
Digital Quad 2-input multiplexer;
74AHCT157 • • •
multiplexer TTL-enabled
74AHC164 Shift register 8-bit serial-in/parallel-out shift register • • •
8-bit serial-in/parallel-out shift
74AHCT164 Shift register • • •
register; TTL-enabled
74AHC1G00 NAND gate Single 2-input NAND gate •
Single 2-input NAND gate;
74AHCT1G00 NAND gate •
TTL-enabled
74AHC1G02 NOR gate Single 2-input NOR gate •
Single 2-input NOR gate;
74AHCT1G02 NOR gate •
TTL-enabled
Buffer/inverter/
74AHC1G04 Single inverter •
driver
Buffer/inverter/
74AHCT1G04 Single inverter; TTL-enabled •
driver
Buffer/inverter/
74AHC1G06 Single inverter; open drain •
driver
Buffer/inverter/ Single inverter; open drain;
74AHCT1G06 •
driver TTL-enabled
Buffer/inverter/
74AHC1G07 Single buffer; open drain •
driver
Buffer/inverter/ Single buffer; open drain;
74AHCT1G07 •
driver TTL-enabled
74AHC1G08 AND gate Single 2-input AND gate •
Single 2-input AND gate;
74AHCT1G08 AND gate •
TTL-enabled
Buffer/inverter/
74AHC1G125 Single buffer/line driver (3-state) •
driver
Buffer/inverter/ Single buffer/line driver; TTL-enabled
74AHCT1G125 •
driver (3-state)
Buffer/inverter/
74AHC1G126 Single buffer/line driver (3-state) •
driver
Buffer/inverter/ Single buffer/line driver; TTL-enabled
74AHCT1G126 •
driver (3-state)
74AHC1G14 Schmitt trigger Single inverter Schmitt trigger •
Single inverter Schmitt trigger;
74AHCT1G14 Schmitt trigger •
TTL-enabled
74AHC1G17 Schmitt trigger Single buffer with Schmitt trigger •
Single buffer with Schmitt trigger;
74AHCT1G17 Schmitt trigger •
TTL-enabled
74AHC1G32 OR gate Single 2-input OR gate •
74AHCT1G32 OR gate Single 2-input OR gate •
Single-pole, Single-throw analog
74AHC1G66 Analog switch •
switch
Single-pole, Single-throw analog
74AHCT1G66 Analog switch •
switch; TTL-enabled
Single D-type flip-flop; positive-edge
74AHC1G79 D-type flip-flop •
trigger
Single D-type flip-flop; positive-edge
74AHCT1G79 D-type flip-flop •
trigger; TTL-enabled
EXCLUSIVE-
74AHC1G86 2-input EXCLUSIVE-OR gate •
OR gate

NXP Logic selection guide 2016 39

AHC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Suffix
Suffix Suffix Suffix Suffix Suffix GD, GF,
Type number Function Description DP, GW,
PW DC DB D BQ GM, GN,
GV
GS, GT
EXCLUSIVE- 2-input EXCLUSIVE-OR gate
74AHCT1G86 •
OR gate TTL-enabled
Buffer/inverter/
74AHC240 Octal inverter/line driver (3-state) •
driver
Buffer/inverter/ Octal inverter/line driver; TTL-
74AHCT240 • • •
driver enabled (3-state)
Buffer/inverter/
74AHC244 Octal buffer/line driver (3-state) • • •
driver
Buffer/inverter/ Octal buffer/line driver; TTL-enabled
74AHCT244 • • •
driver (3-state)
74AHC245 Transceiver Octal transceiver (3-state) • • •
Octal transceiver; TTL-enabled
74AHCT245 Transceiver • • •
(3-state)
Digital
74AHC257 Quad 2-input multiplexer (3-state) • •
multiplexer
Digital Quad 2-input multiplexer;
74AHCT257 • •
multiplexer TTL-enabled (3-state)
Latch/
74AHC259 registered 8 bit addressable latch • •
driver
Latch/
74AHCT259 registered 8-Bit addressable latch; TTL-enabled • •
driver
Octal D-type flip-flop with reset;
74AHC273 D-type flip-flop • • •
positive-edge trigger
Octal D-type flip-flop with reset;
74AHCT273 D-type flip-flop • • •
positive-edge trigger; TTL-enabled
74AHC2G00 NAND gate Dual 2-input NAND gate • • •
Dual 2-input NAND gate;
74AHCT2G00 NAND gate • • •
TTL-enabled
74AHC2G08 AND gate Dual 2-input AND gate • • •
74AHCT2G08 AND gate Dual 2-Input AND gate; TTL-enabled • • •
Buffer/inverter/
74AHC2G125 Dual buffer/line driver (3-state) • • •
driver
Buffer/inverter/ Dual buffer/line driver; TTL-enabled
74AHCT2G125 • • •
driver (3-state)
Buffer/inverter/
74AHC2G126 Dual buffer/line driver (3-state) • • •
driver
Buffer/inverter/ Dual buffer/line driver; TTL-enabled
74AHCT2G126 • • •
driver (3-state)
Buffer/inverter/
74AHC2G241 Dual buffer/line driver (3-state) • • •
driver
Buffer/inverter/ Dual buffer/line driver; TTL-enabled
74AHCT2G241 • • •
driver (3-state)
74AHC2G32 OR gate Dual 2-input OR gate • • •
74AHCT2G32 OR gate Dual 2-input OR gate • • •
74AHC30 NAND gate 8-input NAND gate • • •
74AHCT30 NAND gate 8-input NAND gate; TTL-enabled • • •
74AHC32 OR gate Quad 2-input OR gate • • •
74AHCT32 OR gate Quad 2-input OR gate; TTL-enabled • • •
Latch/
Octal D-type transparent latch
74AHC373 registered • •
(3-state)
driver
Latch/
Octal D-type transparent latch;
74AHCT373 registered • •
TTL-enabled (3-state)
driver

40 NXP Logic selection guide 2016

AHC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate
Suffix
Suffix
Suffix Suffix Suffix Suffix Suffix GD, GF,
Type number Function Description DP, GW,
PW DC DB D BQ GM, GN,
GV
GS, GT
Octal D-type flip-flop; positive-edge
74AHC374 D-type flip-flop • •
trigger (3-state)
Octal D-type flip-flop; positive-edge
74AHCT374 D-type flip-flop • •
trigger (3-state)
Octal D-type flip-flop with data
74AHC377 D-type flip-flop • •
enable; positive-edge trigger
Octal D-type flip-flop with data
74AHCT377 D-type flip-flop enable; positive-edge trigger; • •
TTL-enabled
Buffer/inverter/
74AHC3G04 Triple inverter • • •
driver
Buffer/inverter/
74AHCT3G04 Triple inverter; TTL-enabled • • •
driver
74AHC3G14 Schmitt trigger Triple inverter Schmitt trigger • • •
Triple inverter Schmitt trigger;
74AHCT3G14 Schmitt trigger • • •
TTL-enabled
Buffer/inverter/
74AHC541 Octal buffer/line driver (3-state) • • •
driver
Buffer/inverter/ Octal buffer/line driver; TTL-enabled
74AHCT541 • • •
driver (3-state)
Latch/
Octal D-type transparent latch
74AHC573 registered • • •
(3-state)
driver
Latch/
Octal D-type transparent latch;
74AHCT573 registered • • •
TTL-enabled (3-state)
driver
Octal D-type flip-flop; positive-edge
74AHC574 D-type flip-flop • • •
trigger (3-state)
Octal D-type flip-flop; positive-edge
74AHCT574 D-type flip-flop • • •
trigger; TTL-enabled (3-state)
8-bit serial-in/parallel-out shift register
74AHC594 Shift register • • • •
with output storage register
8-bit serial-in/parallel-out shift register
74AHCT594 Shift register with output storage register; • • • •
TTL-enabled
8-bit serial-in/parallel-out shift register
74AHC595 Shift register • • •
with output storage register (3-state)
8-bit serial-in/parallel-out shift register
74AHCT595 Shift register with output storage register; • • •
TTL-enabled (3-state)
Dual D-type flip-flop with set and
74AHC74 D-type flip-flop • • •
reset; positive-edge trigger
Dual D-type flip-flop with set and
74AHCT74 D-type flip-flop reset; positive-edge trigger; • • •
TTL-enabled
EXCLUSIVE-
74AHC86 Quad 2-input EXCLUSIVE-OR gate • • •
OR gate
EXCLUSIVE- Quad 2-input EXCLUSIVE-OR gate;
74AHCT86 • • •
OR gate TTL-enabled
74AHC1G09 AND gate Single 2-input AND gate; open drain •
Buffer/inverter/
74AHC1GU04 Single inverter; unbuffered •
driver
Buffer/inverter/
74AHC3GU04 Triple inverter; unbuffered • • •
driver
Buffer/inverter/
74AHCU04 Hex inverter; unbuffered • • •
driver

NXP Logic selection guide 2016 41

VHC(T) LOGIC
VHC and VHCT devices are high-speed CMOS logic. They are Features and benefits
upgrades of the HC(T) family, with overvoltage-tolerant inputs 4 Typical propagation delay of 5 ns
for true mixed-voltage applications. VHC products are for use 4 Balanced output drive IOH / IOL = ±8 mA
in CMOS applications from 2.0 to 6.0 V. VHCT products are for 4 Low power
use in TTL applications from 4.5 to 5.5 V. All VHC(T) devices 4 5 V tolerant inputs
offer balanced output drive of 8 mA and a typical propagation 4 Low noise: VOLP = 0.8 V (max.)
delay of 5 ns, and are fully specified from -40 to +125 °C.
Applications
4 Industrial
4 Consumer electronics
4 Computer peripherals
4 Communications
4 Mixed-voltage applications

VHC(T) selection table TSSOP SO QFN

Type number Function Description Suffix PW Suffix D Suffix BQ

74VHC02 NOR gates quad 2-input NOR gate • • •

74VHCT02 NOR gates quad 2-input NOR gate; TTL-enabled • • •

74VHC08 AND gates quad 2-input AND gate • • •

74VHCT08 AND gates quad 2-input AND gate; TTL-enabled • • •

74VHC125 Buffers/inverters/drivers quad buffer/line driver (3-state) • • •

74VHCT125 Buffers/inverters/drivers quad buffer/line driver (3-state) • • •

74VHC126 Buffers/inverters/drivers quad buffer/line driver (3-state) • • •

74VHCT126 Buffers/inverters/drivers quad buffer/line driver (3-state); TTL-enabled • • •

74VHC14 Schmitt triggers hex inverter Schmitt trigger • • •

74VHCT14 Schmitt triggers hex inverter Schmitt trigger; TTL-enabled • • •

74VHC244 Buffers/inverters/drivers octal inverter/line driver (3-state) • • •

74VHCT244 Buffers/inverters/drivers octal inverter/line driver (3-state); TTL-enabled • • •

74VHC245 Transceivers octal transceiver (3-state) • • •

74VHCT245 Transceivers octal transceiver; TTL-enabled (3-state) • • •

74VHC32 OR gates quad 2-input OR gate • • •

74VHCT32 OR gates quad 2-input OR gate; TTL-enabled • • •

74VHC541 Buffers/inverters/drivers octal buffer/line driver (3-state) • • •

74VHCT541 Buffers/inverters/drivers octal buffer/line driver (3-state); TTL-enabled • • •

8-bit serial-in/parallel-out shift register with output

74VHC595 Shift registers • • •
storage register (3-state)

8-bit serial-in/parallel-out shift register with output

74VHCT595 Shift registers • • •
storage register; TTL-enabled (3-state)

42 NXP Logic selection guide 2016

XC7 LOGIC
XC7 devices are very high-speed CMOS logic. They are Features and benefits
upgrades of the HC(T) family, with overvoltage-tolerant inputs 4 Typical propagation delay of 5 ns
for true mixed-voltage applications. XC7SH and XC7WH 4 Balanced output drive IOH / IOL = ±8 mA
products are for use in CMOS applications that range from 2.0 4 Low power
to 6.0 V. XC7SET products are for use in TTL applications from 4 5 V tolerant inputs
4.5 to 5.5 V. All XC7 devices offer a balanced output drive of 4 Low noise: VOLP = 0.8 V (max.)
8 mA and a typical propagation delay of 5 ns, and are fully
specified from -40 to +125 °C. Applications
Industrial
4 
Consumer electronics
4 
Computer peripherals
4 
Communications
4 
Mixed-voltage applications
4 

XC7 selection table MicroPak PicoGate VSSOP

Suffix Suffix DP,

Type number Function Description Suffix DC
GD, GM, GF, GT GW, GV

XC7SET02 NOR gates single 2-input NOR gate; TTL-enabled •

XC7SET04 Buffers/inverters/drivers single inverter; TTL-enabled •

XC7SET08 AND gates single 2-input AND gate; TTL-enabled •

single buffer/line driver; TTL-enabled

XC7SET125 Buffers/inverters/drivers • •
(3-state)

single inverter Schmitt trigger;

XC7SET14 Schmitt triggers •
TTL-enabled

XC7SET32 OR gates single 2-input OR gate; TTL-enabled •

XC7SET86 EXCLUSIVE-OR gates 2-input EXCLUSIVE-OR gate; TTL-enabled •

XC7SH02 NOR gates single 2-input NOR gate •

XC7SH04 Buffers/inverters/drivers single inverter •

XC7SH08 AND gates single 2-input AND gate •

XC7SH125 Buffers/inverters/drivers single buffer/line driver (3-state) • •

XC7SH14 Schmitt triggers single inverter Schmitt trigger •

XC7SH32 OR gates single 2-input OR gate •

XC7SH86 EXCLUSIVE-OR gates 2-input EXCLUSIVE-OR gate •

XC7SHU04 Buffers/inverters/drivers single inverter; unbuffered •

XC7WH126 Buffers/inverters/drivers dual buffer/line driver (3-state) • •

XC7WH14 Schmitt triggers triple inverter Schmitt trigger • • •

XC7WT14 Schmitt triggers triple inverter Schmitt trigger • • •

NXP Logic selection guide 2016 43

NPIC LOGIC
The NPIC family is a series of LED drivers based on shift Features and benefits
registers. When used for I/O expansion, they enable the use 4  33 V, 100 mA open-drain outputs
of a low-cost controller with a low pincount. The serial output 4  Simple 3.3 or 5 V control interface
supports cascading, making it possible for three controller 4  I/O expansion
I/O to control the state of 16, 24, or more LEDs. They are fully 4  High frequency
specified from -40 to +125 °C. 4 Cascadable

Applications
4 LED drivers
4 Displays
4 Control units

NPIC selection table TSSOP SO DQFN

Suffix Suffix Suffix

Type number Function Description
PW D BQ

12-bit serial-in/parallel-out shift register with output

NPIC6C4894 Shift register • •
storage register (3-state)

8-bit serial-in/parallel-out shift register with output

NPIC6C595 Shift register • • •
storage register (3-state)

8-bit serial-in/serial or parallel-out shift register with

NPIC6C596 Shift register/LED driver • • •
output register LED driver (3-state)

8-bit serial-in/serial or parallel-out shift register with

NPIC6C596A Shift register/LED driver • • •
output register LED driver (3-state)

44 NXP Logic selection guide 2016

CBT(D) LOGIC
CBT and CBTD bus switches are low-delay, single-transistor or Features and benefits
transmission-gate solutions for multiplexing data buses, hot- 4 5 -to-3.3 V level shifting
swapping boards in backplanes, memory interleaving, signal 4 3.3-to-1.8 V level shifting
conditioning, or unidirectional level shifting. They are fully 4 Low propagation delay
specified from either -40 to +85 °C or from -40 to +125 °C. 4 T TL control inputs

Applications
Telecommunications infrastructure
4 
Memory interleaving
4 
Industrial control
4 
Unidirectional level shifting
4 
Cell phones
4 

CBT(D) selection table TSSOP SSOP SO DQFN MicroPak

Suffix Suffix
Suffix Suffix Suffix
Type number Function Description DGG, GF, GM,
DS, DK D BQ
PW GN, GS
CBT16210 Bus switch 20-bit bus switch • •

CBT16211 Bus switch 24-bit bus switch • •

CBT16212 Bus switch 24-bit bus exchange switch • •

CBT16292 Bus switch 12-bit 2:1 mux/demux •

CBT3125 Bus switch Quad bus switch • • •

CBT3126 Bus switch Quad bus switch • • •

CBT3244A Bus switch Octal bus switch • • • •

CBT3245A Bus switch Octal bus switch • • • •

CBT3251 Bus switch 8:1 mux/demux • • •

CBT3253A Bus switch Dual 4:1 mux/demux • • •

CBT3257A Bus switch Quad 2:1 mux/demux • • • •

CBT3306 Bus switch Dual bus switch • • •

CBT3384 Bus switch 10-bit bus switch • • •

CBT3861 Bus switch 10-bit bus switch • • •

CBTD16210 Bus switch 20-bit bus switch level translator • •

CBTD3306 Bus switch Dual bus switch level translator • • •

CBTD3384 Bus switch 10-bit bus switch level translator • • •

CBTD3861 Bus switch 10-bit bus switch level translator • • •

NXP Logic selection guide 2016 45

 Low-voltage families

This section includes the following low-voltage logic families,

in ascending order of performance

LV logic 46
LVC logic 48
ALVC logic 54
LVT logic  56
ALVT logic 58
AVC(M) logic 59
AUP logic 60
AXP logic 63
CBTLV(D) logic 64

LV LOGIC
The LV family provides the performance of 5 V 4  Accepts TTL input levels between VCC = 2.7 V
HCMOS within the supply range of 3.0 to 3.6 and VCC = 3.6 V
V. The typical operating range is from 1.0 to 4 Typical output ground bounce < 0.8 V at
3.6 V, but many functions are specified from VCC = 3.3 V and Tamb = 25 °C
1.0 to 5.5 V, with low ground bounce and high 4 Typical high-level output voltage
reliability. Offering fully compatible TTL input 4 
( VOH) undershoot: > 2 V at VCC= 3.3 V and
levels and balanced propagation delays for Tamb = 25 °C
high speed, LV devices deliver higher output
drive and higher speed than 5 V HCMOS Applications
devices. The family is pin-compatible with 4 Industrial control (linear amplifiers, crystal
HC(T) devices and is fully specified from -40 to oscillators, etc.)
+125 °C. 4 Battery back-up systems (chargers, UPS
systems, etc.)
Features and benefits 4 Electronic data-processing peripherals
4 Wide operating voltage (1.0 to 5.5 V) 4 Automotive electrical systems
4 Optimized for low-voltage applications
(1.0 to 3.6 V)

46 NXP Logic selection guide 2016

LV selection table TSSOP SSOP SO DQFN

Suffix Suffix Suffix Suffix

Type number Function Description
PW DB D BQ
74LV00 NAND gate Quad 2-input NAND gate • • • •
74LV02 NOR gate Quad 2-input NOR gate • • •
74LV03 NAND gate Quad 2-input NAND gate; open drain •
74LV04 Buffer/inverter/driver Hex inverter •
74LV08 AND gate Quad 2-input AND gate • • •
74LV123 Multivibrator Dual retriggerable monostable multivibrator with reset • • • •
74LV125 Buffer/inverter/driver Quad buffer/line driver (3-state) • • •
74LV132 Schmitt trigger Quad 2-input NAND gate Schmitt trigger • • • •
74LV138 Decoder/demultiplexer 3-to-8 line decoder/demultiplexer; inverting • • • •
74LV139 Decoder/demultiplexer Dual 2-to-4 line decoder/demultiplexer • • • •
74LV14 Schmitt trigger Hex inverter Schmitt trigger • • • •
74LV153 Digital multiplexer Dual 4-input multiplexer • • •
74LV164 Shift register 8-bit serial-in/parallel-out shift register • • • •
74LV165 Shift register 8-bit parallel or serial-in/serial-out shift register • • •
74LV165A Shift register 8-bit parallel or serial-in/serial-out shift register • •
74LV174 D-type flip-flop Hex D-type flip-flop with reset; positive-edge trigger • • •
74LV241 Buffer/inverter/driver Octal buffer/line driver (3-state) • • •
74LV244 Buffer/inverter/driver Octal buffer/line driver (3-state) • • •
74LV245 Transceiver Octal transceiver (3-state) • • •
74LV251 Digital multiplexer 8-input multiplexer (3-state) • • •
74LV259 Latch/registered driver 8 bit addressable latch • • • •
74LV27 NOR gate Triple 3-input NOR gate •
74LV273 D-type flip-flop Octal D-type flip-flop with reset; positive-edge trigger • • •
74LV32 OR gate Quad 2-input OR gate • • • •
74LV365 Buffer/inverter/driver Hex buffer/line driver (3-state) • • •
74LV367 Buffer/inverter/driver Hex buffer/line driver (3-state) • • •
74LV373 Latch/registered driver Octal D-type transparent latch (3-state) • • •
74LV374 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • •
Octal D-type flip-flop with data enable; positive-edge
74LV377 D-type flip-flop • • •
trigger
74LV393 Binary counter/timer Dual 4-bit binary ripple counter • • •
74LV4020 Binary counter/timer 14-stage binary ripple counter • • •
74LV4051 Analog switch Single-pole, octal-throw analog switch • • • •
74LV4052 Analog switch Dual single-pole, quad-throw analog switch • • •
74LV4053 Analog switch Triple single-pole, double-throw analog switch • • • •
74LV4060 Binary counter/timer 14-stage binary ripple counter with oscillator • • •
74LV4066 Analog switch Quad single-pole, single-throw analog switch • • •
8-bit serial-in/serial or parallel-out shift register with output
74LV4094 Shift register • • •
register (3-state)
74LV541 Buffer/inverter/driver Octal buffer/line driver (3-state) • • •
74LV573 Latch/registered driver Octal D-type transparent latch (3-state) • • •
74LV574 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • •
8-bit serial-in/parallel-out shift register with output storage
74LV595 Shift register • • •
register (3-state)
Dual D-type flip-flop with set and reset; positive-edge
74LV74 D-type flip-flop • • •
trigger
74LV86 EXCLUSIVE-OR gate Quad 2-input EXCLUSIVE-OR gate • • • •
74LVU04 Buffer/inverter/driver Hex inverter; unbuffered • • • •

NXP Logic selection guide 2016 47

LVC LOGIC
LVC logic is specified over 1.65 to 3.6 V in standard formats, Live insertion/extraction permitted
4 
and from 1.65 to 5.5 V in PicoGate packages. With a balanced Buffers and drivers with 30 Ω integrated series termination
4 
output drive of 24 mA and a typical propagation delay of 2 ns, (optional)
and an extensive set of special features, the LVC family is well Bus hold on data inputs (optional)
4 
suited for parallel-interface applications. All LVC devices are Bus-interface functions in 16- and 32-bit versions
4 
fully specified from -40 to 125 °C.
Applications
Features and benefits STBs, DVD players, HDTVs
4 
4 Typical propagation delay of 2 ns Workstations
4 
4 Output drive capability IOH / IOL = ±24 mA Telecom and networking equipment
4 
4 Low power Advanced bus interfaces
4 
4 5 V-tolerant I/O Computer peripherals
4 

LVC selection table (cont.) TSSOP VSSOP SSOP SO DQFN BGA MicroPak PicoGate
Suffix
Suffix Suffix Suffix GD, GF, Suffix
Suffix Suffix Suffix
Type number Function Description DGG, DB, BQ, GM, GN, DP, GW,
DC D EC, EV
PW DL BX GS, GT, GV
GX
16-bit buffer/line driver with
Buffer/inverter/
74LVC162244A 30 Ω termination resistors • •
driver
(3-state)
16-bit buffer/line driver
Buffer/inverter/
74LVCH162244A with bus hold and 30 Ω • •
driver
termination resistors (3-state)
16-bit transceiver with 30 Ω
74LVC162245A Transceiver • •
termination resistors (3-state)
16-bit transceiver with bus
74LVCH162245A Transceiver hold and 30 Ω termination • •
resistors (3-state)
16-bit D-type transparent
Latch/registered
74LVC162373A latch with 30 Ω termination • •
driver
resistors (3-state)
16-bit D-type transparent
Latch/registered
74LVCH162373A latch with bus hold and 30 Ω • •
driver
termination resistors (3-state)
Buffer/inverter/ 16-bit buffer/line driver
74LVC16244A • • • •
driver (3-state)
Buffer/inverter/ 16-bit buffer/line driver with
74LVCH16244A •
driver bus hold (3-state)
74LVC16245A Transceiver 16-bit transceiver (3-state) • • •
16-bit transceiver with bus
74LVCH16245A Transceiver • • •
hold (3-state)
Latch/registered 16-bit D-type transparent
74LVC16373A • • •
driver latch (3-state)
Latch/registered 16-bit D-type transparent
74LVCH16373A • •
driver latch with bus hold (3-state)
16-bit D-type flip-flop;
74LVC16374A D-type flip-flop • • •
positive-edge trigger (3-state)
16-bit D-type flip-flop with
74LVCH16374A D-type flip-flop bus hold; positive-edge • • •
trigger (3-state)
Single dual-supply voltage-
Level shifter/
74LVC1T45 translating transceiver • •
translator
(3-state)

48 NXP Logic selection guide 2016

LVC selection table (cont.) TSSOP VSSOP SSOP SO DQFN BGA MicroPak PicoGate
Suffix
Suffix Suffix Suffix GD, GF, Suffix
Suffix Suffix Suffix
Type number Function Description DGG, DB, BQ, GM, GN, DP, GW,
DC D EC, EV
PW DL BX GS, GT, GV
GX
Single dual-supply voltage-
Level shifter/
74LVCH1T45 translating transceiver with • •
translator
bus hold (3-state)
Buffer/inverter/ Octal buffer/line driver
74LVC244A • • • •
driver (3-state)
Buffer/inverter/ Octal buffer/line driver with
74LVCH244A • • • •
driver bus hold (3-state)
74LVC245A Transceiver Octal transceiver (3-state) • • • •
Octal transceiver with bus
74LVCH245A Transceiver • • • •
hold (3-state)
Dual-bit dual-supply voltage-
Level shifter/
74LVC2T45 translating transceiver • •
translator
(3-state)
Dual-bit dual-supply voltage-
Level shifter/
74LVCH2T45 translating transceiver with • •
translator
bus hold (3-state)
8-bit dual-supply voltage-
Level shifter/
74LVC8T245 translating transceiver • •
translator
(3-state)
74LVC00A NAND gate Quad 2-input NAND gate • • • •
74LVC02A NOR gate Quad 2-input NOR gate • • • •
Buffer/inverter/
74LVC04A Hex inverter • • • •
driver
Buffer/inverter/
74LVC06A Hex inverter; open drain • • •
driver
Buffer/inverter/
74LVC07A Hex buffer; open drain • • •
driver
74LVC08A AND gate Quad 2-input AND gate • • • •
Dual J-/K flip-flop with set and
74LVC109 JK-type flip-flop • • •
reset; positive-edge trigger
74LVC10A NAND gate Triple 3-input NAND gate • • • •
74LVC11 AND gate Triple 3-input AND gate • • • •
Buffer/inverter/ Quad buffer/line driver
74LVC125A • • • •
driver (3-state)
Buffer/inverter/ Quad buffer/line driver
74LVC126A • • • •
driver (3-state)
Quad 2-input NAND gate
74LVC132A Schmitt trigger • • •
Schmitt trigger
Decoder/ 3-to-8 line decoder/
74LVC138A • • • •
demultiplexer demultiplexer; inverting
Decoder/ Dual 2-to-4 line decoder/
74LVC139 • • • •
demultiplexer demultiplexer
74LVC14A Schmitt trigger Hex inverter Schmitt trigger • • • •
Digital
74LVC157A Quad 2-input multiplexer • • • •
multiplexer
Presettable synchronous 4-bit
Binary counter/
74LVC161 binary counter; asynchronous • • • •
timer
reset
Buffer/inverter/ 16-bit inverter/line driver
74LVC16240A • •
driver (3-state)
Buffer/inverter/ 16-bit buffer/line driver
74LVC16241A • •
driver (3-state)
Presettable synchronous 4-bit
Binary counter/
74LVC163 binary counter; synchronous • • • •
timer
reset

NXP Logic selection guide 2016 49

LVC selection table (cont.) TSSOP VSSOP SSOP SO DQFN BGA MicroPak PicoGate
Suffix
Suffix Suffix Suffix GD, GF, Suffix
Suffix Suffix Suffix
Type number Function Description DGG, DB, BQ, GM, GN, DP, GW,
DC D EC, EV
PW DL BX GS, GT, GV
GX
Binary counter/ Presettable synchronous 4-bit
74LVC169 • • • •
timer binary up/down counter
74LVC1G00 NAND gate Single 2-input NAND gate • •
74LVC1G02 NOR gate Single 2-input NOR gate • •
Buffer/inverter/
74LVC1G04 Single inverter • •
driver
Buffer/inverter/
74LVC1G06 Single inverter; open drain • •
driver
Buffer/inverter/
74LVC1G07 Single buffer; open drain • •
driver
74LVC1G08 AND gate Single 2-input AND gate • •
74LVC1G10 NAND gate Single 3-input NAND gate • •
74LVC1G11 AND gate Single 3-input AND gate • •
Single retriggerable
74LVC1G123 Multivibrator • • •
monostable multivibrator
Buffer/inverter/ Single buffer/line driver
74LVC1G126 • •
driver (3-state)
74LVC1G14 Schmitt trigger Single inverter Schmitt trigger • •
Digital
74LVC1G157 Single 2-input multiplexer • •
multiplexer
74LVC1G17 Schmitt trigger Single buffer Schmitt trigger • •
Decoder/
74LVC1G18 1-to-2 demultiplexer (3-state) • •
demultiplexer
Decoder/
74LVC1G19 1-to-2 decoder/demultiplexer • •
demultiplexer
74LVC1G27 NOR gate Single 3-input NOR gate • •
Single-pole, double-throw
74LVC1G3157 Analog switch • •
analog switch
74LVC1G32 OR gate Single 2-input OR gate • •
74LVC1G332 OR gate Single 3-input OR gate • •
Buffer/inverter/
74LVC1G34 Single buffer • •
driver
Single 2-input NAND gate;
74LVC1G38 NAND gate • •
open drain
Single-pole, Single-throw
74LVC1G384 Analog switch • •
analog switch
EXCLUSIVE-OR Single 3-Input EXCLUSIVE-OR
74LVC1G386 • •
gate gate
Single-pole, double-throw
74LVC1G53 Analog switch • • •
analog switch
Configurable
Configurable gate; Schmitt
74LVC1G57 multi-function • •
trigger
gate
Configurable
Configurable gate; Schmitt
74LVC1G58 multi-function • •
trigger
gate
Single-pole, Single-throw
74LVC1G66 Analog switch • • •
analog switch
Single D-type flip-flop with
74LVC1G74 D-type flip-flop set and reset; positive-edge • • •
trigger
Single D-type flip-flop;
74LVC1G79 D-type flip-flop • • •
positive-edge trigger

50 NXP Logic selection guide 2016

LVC selection table (cont.) TSSOP VSSOP SSOP SO DQFN BGA MicroPak PicoGate
Suffix
Suffix Suffix Suffix GD, GF, Suffix
Suffix Suffix Suffix
Type number Function Description DGG, DB, BQ, GM, GN, DP, GW,
DC D EC, EV
PW DL BX GS, GT, GV
GX
Single D-type flip-flop;
74LVC1G80 D-type flip-flop • • •
positive-edge trigger
EXCLUSIVE-OR Single 2-input EXCLUSIVE-OR
74LVC1G86 • • •
gate gate
Configurable
Configurable gate; Schmitt
74LVC1G97 multi-function • • •
trigger
gate
Configurable
Configurable gate; Schmitt
74LVC1G98 multi-function • • •
trigger
gate
Configurable
Configurable gate; Schmitt
74LVC1G99 multi-function • • •
trigger
gate
Buffer/inverter/
74LVC1GU04 Single inverter; unbuffered • • •
driver
Octal buffer/line driver with
Buffer/inverter/
74LVC2244A 30 Ω termination resistors • • • •
driver
(3-state)
Octal transceiver with 30 Ω
74LVC2245A Transceiver • • • •
termination resistors (3-state)
Buffer/inverter/ Octal inverter/line driver
74LVC240A • • • •
driver (3-state)
Buffer/inverter/ Octal buffer/line driver
74LVC241A • • • •
driver (3-state)
Digital Quad 2-input multiplexer
74LVC257A • • • •
multiplexer (3-state)
74LVC27 NOR gate Triple 3-input NOR gate • • • •
Octal D-type flip-flop with
74LVC273 D-type flip-flop • • • •
reset; positive-edge trigger
Octal registered transceiver
74LVC2952A Transceiver with 30 Ω termination • • • •
resistors (3-state)
74LVC2G00 NAND gate Dual 2-input NAND gate • • • •
74LVC2G02 NOR gate Dual 2-input NOR gate • • • •
Buffer/inverter/
74LVC2G04 Dual inverter • • • •
driver
Buffer/inverter/
74LVC2G06 Dual inverter; open drain • • • •
driver
Buffer/inverter/
74LVC2G07 Dual buffer; open drain • • • •
driver
74LVC2G08 AND gate Dual 2-input AND gate • • • •
Buffer/inverter/ Dual buffer/line driver;
74LVC2G125 • • • •
driver TTL-enabled (3-state)
Buffer/inverter/ Dual buffer/line driver;
74LVC2G126 • • • •
driver TTL-enabled (3-state)
74LVC2G14 Schmitt trigger Dual inverter Schmitt trigger • • •
74LVC2G17 Schmitt trigger Dual buffer Schmitt trigger • • •
Buffer/inverter/ Dual inverter/line driver
74LVC2G240 • • • •
driver (3-state)
Buffer/inverter/ Dual buffer/line driver
74LVC2G241 • • • •
driver (3-state)
74LVC2G32 OR gate Dual 2-input OR gate • • • •
Buffer/inverter/
74LVC2G34 Dual buffer • • • •
driver

NXP Logic selection guide 2016 51

LVC selection table (cont.) TSSOP VSSOP SSOP SO DQFN BGA MicroPak PicoGate
Suffix
Suffix Suffix Suffix GD, GF, Suffix
Suffix Suffix Suffix
Type number Function Description DGG, DB, BQ, GM, GN, DP, GW,
DC D EC, EV
PW DL BX GS, GT, GV
GX
Dual 2-input NAND gate;
74LVC2G38 NAND gate • • • •
open drain
Single-pole, double-throw
74LVC2G53 Analog switch • • • •
analog switch
Dual single-pole, single-throw
74LVC2G66 Analog switch • • • •
analog switch
Single D-type flip-flop with
74LVC2G74 D-type flip-flop set and reset; positive-edge • • • •
trigger
EXCLUSIVE-OR Dual 2-input EXCLUSIVE-OR
74LVC2G86 • • • •
gate gate
Buffer/inverter/
74LVC2GU04 Dual inverter; unbuffered • • • •
driver
74LVC32245A Transceiver 32-bit transceiver (3-state) •
74LVC32A OR gate Quad 2-input OR gate • • • •
Latch/registered Octal D-type transparent latch
74LVC373A • • • •
driver (3-state)
Octal D-type flip-flop;
74LVC374A D-type flip-flop • • • •
positive-edge trigger (3-state)
Octal D-type flip-flop with
74LVC377 D-type flip-flop data enable; positive-edge • • •
trigger
Quad 2-input NAND gate;
74LVC38A NAND gate • • • •
open drain
Buffer/inverter/
74LVC3G04 Triple inverter • • •
driver
Buffer/inverter/
74LVC3G06 Triple inverter; open drain • • •
driver
Buffer/inverter/
74LVC3G07 Triple buffer; open drain • • •
driver
74LVC3G14 Schmitt trigger Triple inverter Schmitt trigger • • •
74LVC3G17 Schmitt trigger Triple buffer Schmitt trigger • • •
Buffer/inverter/
74LVC3G34 Triple buffer • • •
driver
Buffer/inverter/
74LVC3GU04 Triple inverter; unbuffered • • •
driver
Quad single-pole, single-
74LVC4066 Analog switch • • •
throw analog switch
8-bit dual-supply voltage-
Level shifter/
74LVC4245A translating transceiver • • •
translator
(3-state)
Buffer/inverter/ Octal buffer/line driver
74LVC541A • • • •
driver (3-state)
Octal registered transceiver
74LVC543A Transceiver • • • •
(3-state)
Octal registered transceiver;
74LVC544A Transceiver • • •
inverting (3-state)
Latch/registered Octal D-type transparent latch
74LVC573A • • •
driver (3-state)
Octal D-type flip-flop;
74LVC574A D-type flip-flop • • • •
positive-edge trigger (3-state)
8-bit serial-in/parallel-out shift
74LVC594A Shift register register with output storage • • •
register

52 NXP Logic selection guide 2016

LVC selection table (cont.) TSSOP VSSOP SSOP SO DQFN BGA MicroPak PicoGate
Suffix
Suffix Suffix Suffix GD, GF, Suffix
Suffix Suffix Suffix
Type number Function Description DGG, DB, BQ, GM, GN, DP, GW,
DC D EC, EV
PW DL BX GS, GT, GV
GX
8-bit serial-in/parallel-out shift
74LVC595A Shift register register with output storage • • •
register (3-state)
Octal transceiver with dual
74LVC623A Transceiver • • •
enable (3-state)
Octal registered transceiver
74LVC646A Transceiver • •
(3-state)
Dual D-type flip-flop with
74LVC74A D-type flip-flop set and reset; positive-edge • • • •
trigger
10-bit D-type flip-flop;
74LVC821A D-type flip-flop • • • •
positive-edge trigger (3-state)
Buffer/inverter/ 10-bit buffer/line driver
74LVC827A • • • •
driver (3-state)
Latch/registered 10-bit D-type transparent
74LVC841A • • • •
driver latch (3-state)
EXCLUSIVE-OR Quad 2-input EXCLUSIVE-OR
74LVC86A • • • •
gate gate
16-bit D-type flip-flop
with bus hold and 30 Ω
74LVCH162374A D-type flip-flop • •
termination resistors; positive-
edge trigger (3-state)
Buffer/inverter/ 16-bit buffer/line driver with
74LVCH16541A • •
driver bus hold (3-state)
32-bit buffer/line driver
Buffer/inverter/
74LVCH322244A with bus hold and 30 Ω •
driver
termination resistors (3-state)
32-bit transceiver with bus
74LVCH322245A Transceiver hold and 30 Ω termination •
resistors (3-state)
Buffer/inverter/ 32-bit buffer/line driver with
74LVCH32244A •
driver bus hold (3-state)
32-bit transceiver with bus
74LVCH32245A Transceiver •
hold (3-state)
Latch/registered 32-bit D-type transparent
74LVCH32373A •
driver latch (3-state)
32-bit D-type flip-flop with
74LVCH32374A D-type flip-flop bus hold; positive-edge •
trigger (3-state)
Buffer/inverter/
74LVCU04A Hex inverter; unbuffered • •
driver
Dual single-pole, single-throw
74LVCV2G66 Analog switch analog switch; overvoltage • •
tolerant

NXP Logic selection guide 2016 53

ALVC LOGIC
ALVC logic devices are specified over a voltage range of 1.65  uffers and drivers with 30 Ω integrated series termination
B
to 3.6 V. They have a balanced output drive of 24 mA (optional)
and a typical propagation delay of 2 ns, and are well suited Bus hold on data inputs (optional)
for parallel-interface applications. ALVC products are fully Bus-interface functions in 16- and 32-bit versions
specified from -40 to 85 °C.
Applications
Features and benefits STBs, DVD players, HDTVs
Typical propagation delay of 2 ns Workstations
Output drive capability IOH / IOL = ±24 mA Telecom and networking equipment
Low power Advanced bus interfaces
3.6 V-tolerant I/O Computer peripherals
Live insertion/extraction permitted

ALVC selection table (cont.) TSSOP SSOP QFN BGA

Suffix Suffix
Suffix Suffix
Type number Function Description DGG, BQ,
D, DL EC
PW BX

74ALVC16244 Buffer/inverter/driver 16-bit buffer/line driver (3-state) • •

74ALVCH16244 Buffer/inverter/driver 16-bit buffer/line driver with bus hold (3-state) • •

74ALVC16245 Transceiver 16-bit transceiver (3-state) • •

74ALVCH16245 Transceiver 16-bit transceiver with bus hold (3-state) • •

74ALVC00 NAND gate Quad 2-input NAND gate • • •

74ALVC02 NOR gate Quad 2-input NOR gate • • •

74ALVC04 Buffer/inverter/driver Hex inverter • • •

74ALVC08 AND gate Quad 2-input AND gate • • •

74ALVC125 Buffer/inverter/driver Quad buffer/line driver (3-state) • • •

74ALVC14 Schmitt trigger Hex inverter Schmitt trigger • • •

Latch/registered
74ALVC162334A 16-bit registered driver with 30 Ω termination resistors (3-state) • • •
driver

Latch/registered
74ALVC162834A 18-bit registered driver with 30 Ω termination resistors (3-state) • • •
driver

74ALVC164245 Level shifter/translator 16-bit dual-supply voltage-translating transceiver (3-state) • • •

Latch/registered
74ALVC16834A 18-bit registered driver (3-state) • • •
driver

Latch/registered
74ALVC16835A 18-bit registered driver (3-state) • • •
driver

Latch/registered
74ALVC16836A 20-bit registered driver (3-state) • • •
driver

74ALVC244 Buffer/inverter/driver Octal buffer/line driver (3-state) • • •

74ALVC245 Transceiver Octal transceiver (3-state) • • •

74ALVC32 OR gate Quad 2-input OR gate • • •

54 NXP Logic selection guide 2016

ALVC selection table (cont.) TSSOP SSOP QFN BGA

Suffix Suffix
Suffix Suffix
Type number Function Description DGG, BQ,
D, DL EC
PW BX

Latch/registered
74ALVC373 Octal D-type transparent latch (3-state) • • •
driver

74ALVC541 Buffer/inverter/driver Octal buffer/line driver (3-state) • • •

Latch/registered
74ALVC573 Octal D-type transparent latch (3-state) • • •
driver

74ALVC574 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • •

74ALVC74 D-type flip-flop Dual D-type flip-flop with set and reset; positive-edge trigger • • •

16-bit transceiver with bus hold and 30 Ω termination resistors

74ALVCH162245 Transceiver • •
(3-state)

18-bit universal bus transceiver with bus hold and 30 Ω termination

74ALVCH162601 Transceiver •
resistors; positive-edge trigger (3-state)

20-bit buffer/line driver with bus hold and 30 Ω termination resistors

74ALVCH162827 Buffer/inverter/driver •
(3-state)

Latch/registered
74ALVCH16373 16-bit D-type transparent latch with bus hold (3-state) • •
driver

74ALVCH16374 D-type flip-flop 16-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) • •

18-bit universal bus transceiver with bus hold; negative edge trigger
74ALVCH16500 Transceiver •
(3-state)

18-bit universal bus transceiver with bus hold; positive edge trigger
74ALVCH16501 Transceiver • •
(3-state)

74ALVCH16543 Transceiver 16-bit registered transceiver with bus hold (3-state) •

18-bit universal bus transceiver with bus hold; negative edge trigger
74ALVCH16600 Transceiver •
(3-state)

18-bit universal bus transceiver with bus hold; positive edge trigger
74ALVCH16601 Transceiver •
(3-state)

74ALVCH16646 Transceiver 16-bit registered transceiver with bus hold (3-state) •

74ALVCH16652 Transceiver 16-bit registered transceiver with bus hold (3-state) •

74ALVCH16821 D-type flip-flop 20-bit D-type flip-flop; positive-edge trigger (3-state) • •

74ALVCH16823 D-type flip-flop 18-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) • •

74ALVCH16825 Buffer/inverter/driver 18-bit buffer/line driver with bus hold (3-state) •

74ALVCH16827 Buffer/inverter/driver 20-bit buffer/line driver with bus hold (3-state) •

Latch/registered
74ALVCH16832 7-bit to 28-bit address register/driver (3-state) •
driver

Latch/registered
74ALVCH16841 20-bit D-type transparent latch with bus hold (3-state) •
driver

Latch/registered
74ALVCH16843 18-bit D-type transparent latch with bus hold (3-state) •
driver

74ALVCH16952 Transceiver 16-bit registered transceiver with bus hold (3-state) •

Latch/registered 16-bit transceiver and transparent D-type latch with 8 independent

74ALVCH32973 • •
driver buffers

NXP Logic selection guide 2016 55

LVT LOGIC
The LVT family combines the low power dissipation and low 4 5 V-tolerant I/O
noise of CMOS with the high speed and high output drive of 4 Bus hold on data inputs
bipolar products. LVT devices exhibit highly stable static and 4 Power-up/power-down 3-state
dynamic characteristics over a wide temperature range, are 4 Live insertion
specified over 2.7 to 3.6 V, and support live insertion. With 4 
Buffers and drivers with 30 Ω integrated series termination
output drive as high as 64 mA and typical propagation delay (optional)
of 2 ns, these devices are well suited for parallel-backplane
applications. They are fully specified from -40 °C to 85 °C. Applications
Backplane drivers
4 
Features and benefits Workstations
4 
4 Typical propagation delay of 2 ns Telecom and networking equipment
4 
4 Output drive capability IOH / IOL = -32/+64 mA Advanced bus interfaces
4 
4 Supply voltage range VCC = 2.7 to 3.6 V Computer peripherals
4 

LVT selection table (cont.) TSSOP SSOP SO QFN BGA

Suffix Suffix
Suffix Suffix Suffix
Type number Function Description DGG, BQ,
DB, DL D EC, EV
PW BX
74LVT125 Buffer/inverter/driver Quad buffer/line driver with bus hold (3-state) • • • •
74LVTH125 Buffer/inverter/driver Quad buffer/line driver with bus hold (3-state) • • • •
74LVT16244B Buffer/inverter/driver 16-bit buffer/line driver with bus hold (3-state) • • • •
74LVTH16244B Buffer/inverter/driver 16-bit buffer/line driver with bus hold (3-state) • • •
74LVT16245B Transceiver 16-bit transceiver with bus hold (3-state) • • • •
74LVTH16245B Transceiver 16-bit transceiver with bus hold (3-state) • • •
16-bit D-type flip-flop with bus hold; positive-edge trigger
74LVT16374A D-type flip-flop • • • •
(3-state)
16-bit D-type flip-flop with bus hold; positive-edge trigger
74LVTH16374A D-type flip-flop •
(3-state)
Octal transceiver with bus hold and 30 Ω termination
74LVT2245 Transceiver • • •
resistors (3-state)
Octal transceiver with bus hold and 30 Ω termination
74LVTH2245 Transceiver • • •
resistors (3-state)
74LVT244A Buffer/inverter/driver Octal buffer/line driver with bus hold (3-state) • • •
74LVTH244A Buffer/inverter/driver Octal buffer/line driver with bus hold (3-state) • • •
74LVT244B Buffer/inverter/driver Octal buffer/line driver with bus hold (3-state) • • •
74LVTH244B Buffer/inverter/driver Octal buffer/line driver with bus hold (3-state) • • •
74LVT574 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • •
74LVTH574 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • •
74LVT00 NAND gate Quad 2-input NAND gate • • •
74LVT02 NOR gate Quad 2-input NOR gate • • •
74LVT04 Buffer/inverter/driver Hex inverter • • •
74LVT08 AND gate Quad 2-input AND gate • • •
74LVT10 NAND gate Triple 3-input NAND gate • • •
74LVT126 Buffer/inverter/driver Quad buffer/line driver with bus hold (3-state) • • • •
74LVT14 Schmitt trigger Hex inverter Schmitt trigger • • • •
16-bit inverter/line driver with bus hold and 30 Ω
74LVT162240A Buffer/inverter/driver • •
termination (3-state)

56 NXP Logic selection guide 2016

LVT selection table (cont.) TSSOP SSOP SO QFN BGA

Suffix Suffix
Suffix Suffix Suffix
Type number Function Description DGG, BQ,
DB, DL D EC, EV
PW BX
16-bit buffer/line driver with bus hold and 30 Ω termination
74LVT162244B Buffer/inverter/driver • •
resistors (3-state)
16-bit transceiver with bus hold and 30 Ω termination
74LVT162245B Transceiver • •
resistors (3-state)
Latch/registered 16-bit D-type transparent latch with bus hold and 30 Ω
74LVT162373 • •
driver termination resistors (3-state)
16-bit D-type flip-flop with bus hold and 30 Ω termination
74LVT162374 D-type flip-flop • •
resistors; positive-edge trigger (3-state)
74LVT16240A Buffer/inverter/driver 16-bit inverter/line driver with bus hold (3-state) • •
Latch/registered
74LVT16373A 16-bit D-type transparent latch with bus hold (3-state) • •
driver
18-bit universal bus transceiver with bus hold; negative-
74LVT16500A Transceiver • •
edge trigger (3-state)
18-bit universal bus transceiver with bus hold; positive-
74LVT16501A Transceiver • •
edge trigger (3-state)
74LVT16543A Transceiver 16-bit registered transceiver with bus hold (3-state) • •
74LVT16646A Transceiver 16-bit registered transceiver with bus hold (3-state) • •
74LVT16652A Transceiver 16-bit registered transceiver with bus hold (3-state) • • •
Octal buffer/line driver with bus hold and 30 Ω termination
74LVT2241 Buffer/inverter/driver • • •
resistors (3-state)
Octal buffer/line driver with bus hold and 30 Ω termination
74LVT2244 Buffer/inverter/driver • • •
resistors (3-state)
74LVT240 Buffer/inverter/driver Octal inverter/line driver with bus hold (3-state) • • •
74LVT241 Buffer/inverter/driver Octal buffer/line driver with bus hold (3-state) • • • •
74LVT245B Transceiver Octal transceiver (3-state) • • • •
74LVT245 Transceiver Octal transceiver (3-state) • • • •
74LVT273 D-type flip-flop Octal D-type flip-flop with reset; positive-edge trigger • • • •
Octal registered transceiver with 30 Ω termination resistors
74LVT2952 Transceiver • • •
(3-state)
74LVT32 OR gate Quad 2-input OR gate • • •
32-bit D-type flip-flop with bus hold and 30 Ω termination
74LVT32374 D-type flip-flop •
resistors; positive-edge trigger (3-state)
74LVT373 D-type flip-flop Octal D-type transparent latch (3-state) • •
74LVT374 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • •
Octal D-type flip-flop; inverting; positive-edge trigger
74LVT534 D-type flip-flop • • •
(3-state)
74LVT543 Transceiver Octal registered transceiver (3-state) • • •
Latch/registered
74LVT573 Octal D-type transparent latch (3-state) • • • •
driver
74LVT640 Transceiver Octal transceiver with bus hold; inverting (3-state) • • •
74LVT646 Transceiver Octal registered transceiver with bus hold (3-state) • • •
74LVT652 Transceiver Octal registered transceiver with bus hold (3-state) • • •
Dual D-type flip-flop with set and reset; positive-edge
74LVT74 D-type flip-flop • • •
trigger
32-bit transceiver with bus hold and 30 Ω termination
74LVTH322245 Transceiver •
resistors (3-state)
74LVTH32245 Transceiver 32-bit transceiver with bus hold (3-state) •
74LVTN16244B Buffer/inverter/driver 16-bit buffer/line driver (3-state) • •
74LVTN16245B Transceiver 16-bit transceiver (3-state) • •

NXP Logic selection guide 2016 57

ALVT LOGIC
The ALVT family is a speed upgrade for the LVT family. It 4 5 V-tolerant I/O
combines the low power dissipation and low noise of CMOS 4 Bus hold on data inputs
with the high speed and high output drive of bipolar products. 4 Power-up/power-down 3-state
ALVT devices exhibit highly stable static and dynamic 4 Live insertion
characteristics over a wide temperature range, are specified 4 
Buffers and drivers with 30 Ω integrated series termination
over 2.7 to 3.6 V, and support live insertion. With output drive (optional)
as high as 64 mA and typical propagation delay of 2 ns, these
devices are well suited for parallel-backplane applications. Applications
They are fully specified from -40 °C to 85 °C. 4 Backplane drivers
4 Workstations
Features and benefits 4 Telecom and networking equipment
4 Typical propagation delay of 1.5 ns 4 Advanced bus interfaces
4 Output drive capability IOH / IOL = -32/+64 mA 4 Computer peripherals
4 Supply voltage range VCC = 2.7 to 3.6 V

ALVT selection table TSSOP SSOP

Type Suffix Suffix

Function Description
number DGG DL

74ALVT162240 Buffer/inverter/driver 16-bit inverter/line driver with bus hold and 30 Ω termination (3-state) • •

74ALVT162241 Buffer/inverter/driver 16-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • •

74ALVT162244 Buffer/inverter/driver 16-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • •

74ALVT162245 Transceiver 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) • •

74ALVT16240 Buffer/inverter/driver 16-bit inverter/line driver with bus hold (3-state) • •

74ALVT16241 Buffer/inverter/driver 16-bit buffer/line driver with bus hold (3-state) • •

74ALVT16244 Buffer/inverter/driver 16-bit buffer/line driver with bus hold (3-state) • •

74ALVT16245 Transceiver 16-bit transceiver with bus hold (3-state) • •

74ALVT16260 Latch/registered driver 12-bit to 24-bit multiplexed D-type latch with bus hold (3-state) • •

74ALVT162821 D-type flip-flop 20-bit D-type flip-flop; positive-edge trigger (3-state) • •

74ALVT162823 D-type flip-flop 18-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • •

74ALVT162827 Buffer/inverter/driver 20-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) • •

74ALVT16373 Latch/registered driver 16-bit D-type transparent latch with bus hold (3-state) • •

74ALVT16374 D-type flip-flop 16-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) • •

74ALVT16501 Transceiver 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) • •

74ALVT16543 Transceiver 16-bit registered transceiver with bus hold (3-state) • •

74ALVT16601 Transceiver 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) • •

74ALVT16652 Transceiver 16-bit registered transceiver with bus hold (3-state) • •

74ALVT16821 D-type flip-flop 20-bit D-type flip-flop; positive-edge trigger (3-state) • •

74ALVT16823 D-type flip-flop 18-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) • •

74ALVT16827 Buffer/inverter/driver 20-bit buffer/line driver with bus hold (3-state) • •

58 NXP Logic selection guide 2016

AVC(M) LOGIC
AVC and AVCM devices are advanced, very low-voltage CMOS 4 Wide supply range (1.2 to 3.6 V)
logic. With a typical propagation delay of 1.5 ns, AVC and 4 3.6 V-tolerant I/O
AVCM devices are some of the fastest logic devices in the 4 IOFF supports partial power-down mode
industry. To reduce under- and overshoots at outputs, the 4 
Buffers and drivers with 15 Ω integrated series termination
AVCM has a source-terminated, balanced drive of 12 mA drive. (optional)
AVCM devices also use dynamically controlled outputs (DCO) Bus hold on data inputs (optional)
4 
to increase output impedance after the output transition is Dual-supply level translation
4 
completed. The result is termination with a high signal rate. Bus-interface functions in 16-bit versions
4 
The parallel-interface products are fully specified from -40 to
+85 °C. The dual-supply transceivers for level translation are Applications
fully specified from -40 to +125 °C. 4 High-end workstations, servers, and desktop PCs
4 High-end telecommunications switching equipment
Features and benefits 4 Telecommunication basestations
4 Typical propagation delay of 1.5 ns 4 Memory modules
4 Dynamically controlled outputs 4 Voltage-level translation

AVC(M) selection table (cont.) TSSOP VSSOP SO QFN BGA MicroPak PicoGate
Suffix
Suffix
Suffix GD, GF, Suffix
Suffix Suffix BQ, Suffix
Type number Function Description DGG, GM, GN, DP, GW,
DC D BX, EC, EV
PW GS, GT, GV
GU
GX
74AVC16244 Buffer/inverter/driver 16-bit buffer/line driver (3-state) •
74AVC16334A Latch/registered driver 16-bit registered driver (3-state) •
16-bit D-type transparent latch
74AVC16373 Latch/registered driver •
(3-state)
16-bit D-type flip-flop; positive-
74AVC16374 D-type flip-flop •
edge trigger (3-state)
74AVC16834A Latch/registered driver 18-bit registered driver (3-state) •
74AVC16835A Latch/registered driver 18-bit registered driver (3-state) •
74AVC16836A Latch/registered driver 20-bit registered driver (3-state) •
16-bit dual-supply voltage-
74AVC16T245 Level shifter/translator • • •
translating transceiver (3-state)
Single dual-supply voltage-
74AVC1T45 Level shifter/translator • •
translating transceiver (3-state)
20-bit dual-supply voltage-
74AVC20T245 Level shifter/translator • •
translating transceiver (3-state)
Dual-bit dual-supply voltage-
74AVC2T45 Level shifter/translator • • • •
translating transceiver (3-state)
32-bit dual-supply voltage-
74AVC32T245 Level shifter/translator •
translating transceiver (3-state)
4-bit dual-supply voltage-
74AVC4T245 Level shifter/translator • •
translating transceiver (3-state)
4-bit dual-supply voltage-
74AVC4TD245 Level shifter/translator • •
translating transceiver (3-state)
8-bit dual-supply voltage-
74AVC8T245 Level shifter/translator • •
translating transceiver (3-state)
16-bit buffer/line driver with bus
74AVCH16244 Buffer/inverter/driver • • •
hold (3-state)
16-bit dual-supply voltage-
74AVCH16T245 Level shifter/translator translating transceiver with bus • •
hold (3-state)
Single dual-supply voltage-
74AVCH1T45 Level shifter/translator translating transceiver with bus •
hold (3-state)

NXP Logic selection guide 2016 59

AVC(M) selection table (cont.) TSSOP VSSOP SO QFN BGA MicroPak PicoGate
Suffix
Suffix
Suffix GD, GF, Suffix
Suffix Suffix BQ, Suffix
Type number Function Description DGG, GM, GN, DP, GW,
DC D BX, EC, EV
PW GS, GT, GV
GU
GX
20-bit dual-supply voltage-
74AVCH20T245 Level shifter/translator translating transceiver with bus •
hold (3-state)
Dual-bit dual-supply voltage-
74AVCH2T45 Level shifter/translator translating transceiver with bus • • •
hold (3-state)
4-bit dual-supply voltage-
74AVCH4T245 Level shifter/translator translating transceiver with bus • • •
hold (3-state)
8-bit dual-supply voltage-
74AVCH8T245 Level shifter/translator translating transceiver with bus • •
hold (3-state)
18-bit registered driver with 30 Ω
74AVCM162834 Latch/registered driver •
termination resistors (3-state)
18-bit registered driver with 15 Ω
74AVCM162835 Latch/registered driver •
termination resistors (3-state)
20-bit registered driver with 15 Ω
74AVCM162836 Latch/registered driver •
termination resistors (3-state)

AUP LOGIC
The AUP family is the industry standard for portable Schmitt-trigger action provides high noise immunity
4 
applications. It is manufactured in a CMOS process that Superior ESD protection
4 
results in lower static and dynamic power dissipation. It’s 3.6 Wide operating temperature of -40 to +125 °C
4 
V tolerance, low-threshold inputs (option) and IOFF features tPD of 3.2 ns and IOL of 2.2 mA at 1.8 V VCC
4 
make it suitable for use in mixed 1.8/3.3 V and partial power-
down applications. The family is fully specified from 1.1 to 3.6 Applications
V and is guaranteed for industrial and automotive operating Mobile phones
4 
temperatures. PDAs
4 
Digital cameras
4 
Features and benefits Media players
4 
4 Very low dynamic power dissipation (CPD) Portable medical devices
4 
4 Wide supply voltage VCC (0.8 to 3.6 V) Other handheld, power-sensitive applications
4 

AUP selection table (cont.) VSSOP MicroPak PicoGate

Suffix
Suffix GD, GF, Suffix
Type number Function Description
DC GM, GN, DP, GW, GV
GS, GT, GX

74AUP1G00 NAND gate Single 2-input NAND gate • •

74AUP1G04 Buffer/inverter/driver Single inverter • •

74AUP1G06 Buffer/inverter/driver Single inverter; open drain • •

74AUP1G07 Buffer/inverter/driver Single buffer; open drain • •

74AUP1G08 AND gate Single 2-input AND gate • •

74AUP1G0832 Combination gate Single 3-input AND-OR gate • •

74AUP1G09 AND gate Single 2-input AND gate; open drain • •

60 NXP Logic selection guide 2016

AUP selection table (cont.) VSSOP MicroPak PicoGate

Suffix
Suffix GD, GF, Suffix
Type number Function Description
DC GM, GN, DP, GW, GV
GS, GT, GX

74AUP1G11 AND gate Single 3-input AND gate • •

74AUP1G125 Buffer/inverter/driver Single buffer/line driver (3-state) • •

74AUP1G126 Buffer/inverter/driver Single buffer/line driver (3-state) • •

74AUP1G132 NAND gate Single 2-input NAND gate Schmitt trigger • •

74AUP1G14 Buffer/inverter/driver Single inverter; Schmitt trigger • •

74AUP1G157 Digital multiplexer Single 2-input multiplexer • •

74AUP1G158 Digital multiplexer Single 2-input multiplexer; inverting • •

74AUP1G17 Schmitt trigger Single buffer Schmitt trigger • •

74AUP1G175 D-type flip-flop Single D flip-flop with reset; positive-edge trigger • •

74AUP1G18 Decoder/demultiplexer 1-to-2 demultiplexer (3-state) • •

74AUP1G19 Decoder/demultiplexer 1-to-2 decoder/demultiplexer • •

74AUP1G240 Buffer/inverter/driver Single inverter/line driver (3-state) • •

74AUP1G32 OR gate Single 2-input OR gate • •

74AUP1G3208 Combination gate Single 3-input OR-AND gate • •

74AUP1G332 OR gate Single 3-input OR gate • •

74AUP1G34 Buffer/inverter/driver Single buffer • •

74AUP1G373 Latch/registered driver Single D-type transparent latch (3-state) • •

74AUP1G374 D-type flip-flop Single D-type flip-flop; positive-edge trigger (3-state) • •

74AUP1G38 NAND gate Single 2-input NAND gate; open drain • •

74AUP1G386 EXCLUSIVE-OR gate Single 3-input EXCLUSIVE-OR gate • •

Configurable multi-
74AUP1G57 Configurable gate; Schmitt trigger • •
function gate

Configurable multi-
74AUP1G58 Configurable gate; Schmitt trigger • •
function gate

Single D-type flip-flop with set and reset; positive-edge

74AUP1G74 D-type flip-flop • •
trigger

74AUP1G79 D-type flip-flop Single D-type flip-flop; positive-edge trigger • •

74AUP1G80 D-type flip-flop Single D-type flip-flop; positive-edge trigger • •

74AUP1G86 EXCLUSIVE-OR gate Single 2-input EXCLUSIVE-OR gate • •

74AUP1G885 Combination gate Dual function gate • •

Configurable multi-
74AUP1G97 Configurable gate; Schmitt trigger • •
function gate

Configurable multi-
74AUP1G98 Configurable gate; Schmitt trigger • •
function gate

74AUP1GU04 Buffer/inverter/driver Single inverter; unbuffered • •

74AUP1T34 Level shifter/translator Single dual-supply translating buffer • •

74AUP1T45 Level shifter/translator Single dual-supply voltage-translating transceiver (3-state) • •

Configurable multi-
74AUP1T57 Configurable gate with voltage level translation • •
function gate

NXP Logic selection guide 2016 61

AUP selection table (cont.) VSSOP MicroPak PicoGate

Suffix
Suffix GD, GF, Suffix
Type number Function Description
DC GM, GN, DP, GW, GV
GS, GT, GX

Configurable multi-
74AUP1T58 Configurable gate with voltage level translation • •
function gate

Configurable multi-
74AUP1T97 Configurable gate with voltage level translation • •
function gate

Configurable multi-
74AUP1T98 Configurable gate with voltage level translation • •
function gate

74AUP1Z04 Combination gate Crystal driver with enable and internal resistor • •

74AUP1Z125 Combination gate Crystal driver with enable and internal resistor (3-state) • •

74AUP2G00 NAND gate Dual 2-input NAND gate • • •

74AUP2G02 NOR gate Dual 2-input NOR gate • • •

74AUP2G04 Buffer/inverter/driver Dual inverter • •

74AUP2G06 Buffer/inverter/driver Dual inverter; open drain • •

74AUP2G0604 Combination gate Inverter with open drain and inverter • •

74AUP2G07 Buffer/inverter/driver Dual buffer; open drain • •

74AUP2G08 AND gate Dual 2-input AND gate • • •

74AUP2G125 Buffer/inverter/driver Dual buffer/line driver (3-state) • • •

74AUP2G126 Buffer/inverter/driver Dual buffer/line driver (3-state) • • •

74AUP2G132 Schmitt trigger Dual 2-input NAND gate Schmitt trigger • • •

74AUP2G14 Buffer/inverter/driver Dual inverter; Schmitt trigger • • •

74AUP2G157 Digital multiplexer Single 2-input multiplexer • • •

74AUP2G17 Schmitt trigger Dual buffer Schmitt trigger • • •

74AUP2G240 Buffer/inverter/driver Dual inverter/line driver (3-state) • • •

74AUP2G241 Buffer/inverter/driver Dual buffer/line driver (3-state) • • •

74AUP2G32 OR gate Dual 2-input OR gate • • •

74AUP2G34 Buffer/inverter/driver Dual buffer • • •

74AUP2G3404 Combination gate Buffer and inverter • • •

74AUP2G3407 Combination gate Buffer and buffer with open drain • • •

74AUP2G38 NAND gate Dual 2-input NAND gate; open drain • • •

74AUP2G79 D-type flip-flop Dual D-type flip-flop; positive-edge trigger • • •

74AUP2G80 D-type flip-flop Dual D-type flip-flop; positive-edge trigger • • •

74AUP2G86 EXCLUSIVE-OR gate Dual 2-input EXCLUSIVE-OR gate • • •

74AUP2GU04 Buffer/inverter/driver Dual inverter; unbuffered • • •

74AUP2T1326 Combination gate Dual supply buffer/line driver; 3-state • • •

74AUP3G04 Buffer/inverter/driver Triple inverter • • •

74AUP3G0434 Combination gate Dual inverter and single buffer • • •

74AUP3G3404 Combination gate Dual buffer and single inverter • • •

62 NXP Logic selection guide 2016

AXP LOGIC
As the first logic family fully specified at 0.8 V, the Advanced Features and benefits
eXtremely low voltage and Power (AXP) family is a speed 4 Very low dynamic power dissipation (CPD)
upgrade to the 1.8 V AUP family, but without an increase 4 Wide supply range (0.7 to 2.75 V)
in dynamic power dissipation. These devices are ultra-low- 4 Fully specified at 0.8 V
power, small-footprint solutions for use in 1.2 and 1.2/2.5 V 4 Wide operating temperature (-40 to 85 °C)
applications. Supporting a supply range from 0.75 to 2.75 V, 4 tpd of 4.6 ns and IO of ±4.5 mA at 1.2 V supply
AXP logic supports the trend toward lower-voltage nodes of
1.2 and 0.8 V. All are fully specified from -40 to 85 °C. Applications
4 Smartphones, tablets
4 Digital cameras
4 Portable medical devices
4 Other power-sensitive applications

AXP selection table MicroPak MicroPak MicroPak MicroPak

Suffix Suffix Suffix Suffix
Type number Function Description
GM GN GS GX
74AXP1G06 Buffer/inverter/driver Single inverter; open drain • • • •
74AXP1G08 AND gate Single 2-input AND gate • • • •
74AXP1G125 Buffer/inverter/driver Single buffer/line driver (3-state) • • • •
74AXP1G57 Configurable multi-function gate Configurable gate; Schmitt trigger • • •
74AXP1G58 Configurable multi-function gate Configurable gate; Schmitt trigger • • •
74AXP1G97 Configurable multi-function gate Configurable gate; Schmitt trigger • • • •
74AXP1G98 Configurable multi-function gate Configurable gate; Schmitt trigger • • • •
single 2-input NAND gate, Low-power
74AXP1G00 NAND Gate • •
2-input NAND gate
single 2-input NOR gate, Low-power
74AXP1G02 NOR Gate • •
2-input NOR gate
74AXP1G04 Buffer/inverter/driver single inverter, Low-power inverter • •
Low Power Buffer with Open Drain
74AXP1G07 Buffer/inverter/driver • •
Outputs
Low-power 2-input AND gate with open-
74AXP1G09 AND Gate • •
drain
74AXP1G10 NAND Gate Low Power 3-input NAND Gate •
74AXP1G11 AND Gate Low Power 3-input AND Gate •
single inverter Schmitt trigger, Low-power
74AXP1G14 Schmitt Triggers • • • •
Schmitt trigger inverter
74AXP1G157 Multiplexer Single 2-input Multiplexer •
Low-power Schmitt trigger, Low-power
74AXP1G17 Schmitt Triggers • •
Schmitt trigger
Single 2-input OR gate, Low-power
74AXP1G32 OR Gates • •
2-input OR gate
74AXP1G86 EX-OR Gate Low-power 2-input EXCLUSIVE-OR gate • •
Low-power dual buffer with open-drain
74AXP2G07 Buffer/inverter/driver output, Low-power dual buffer with • • • •
open-drain output
Low-power dual Schmitt trigger inverter,
74AXP2G14 Buffer/inverter/driver • • • •
Low-power dual Schmitt Trigger Inverter
74AXP2G17 Buffer/inverter/driver Low-power dual Schmitt trigger •
74AXP2G34 Buffer Low-power dual Buffer •
74AXP2G3404 Buffer and Inverter Low power buffer and inverter •

NXP Logic selection guide 2016 63

CBTLV(D) LOGIC
CBTLV and CBTLVD bus switches are low-delay, single- Features and benefits
transistor or transmission-gate solutions for multiplexing 4 5 -to-3.3 V level shifting
data buses, hot-swapping boards in backplanes, memory 4 3.3-to-1.8 V level shifting
interleaving, signal conditioning, or unidirectional level 4 Low propagation delay
shifting. They are fully specified from either -40 to +85 °C or 4 T TL control inputs
from -40 to +125 °C.
Applications
Telecommunications infrastructure
4 
Memory interleaving
4 
Industrial control
4 
Unidirectional level shifting
4 
Cell phones
4 

CBTLV(D) selection table TSSOP SSOP SO DQFN Micro PicoGate

Suffix Suffix
Suffix Suffix Suffix Suffix
Type number Function Description DGG, GF, GM,
DK, DS D BQ GV, GW
DGV, PW GN, GS

74CBTLV16211 Bus switch 24-bit bus switch •

74CBTLV1G125 Bus switch Single bus switch • •

74CBTLV3125 Bus switch Quad bus switch • • •

74CBTLV3126 Bus switch Quad bus switch • • •

74CBTLV3244 Bus switch Octal bus switch • • •

74CBTLV3245 Bus switch Octal bus switch • • •

74CBTLV3253 Mux/demux Dual 4:1 mux/demux • • • •

74CBTLV3257 Mux/demux Quad 2:1 mux/demux • • • •

74CBTLV3384 Bus switch 10-bit bus switch • • •

74CBTLV3861 Bus switch 10-bit bus switch • • •

74CBTLVD3244 Bus switch level shifter Octal bus switch level translator • • •

74CBTLVD3245 Bus switch level shifter Octal bus switch level translator • • •

74CBTLVD3384 Bus switch level shifter 10-bit bus switch level translator • • •

74CBTLVD3861 Bus switch level shifter 10-bit bus switch level translator • • •

64 NXP Logic selection guide 2016

Product listing by function

Analog switches 66
Buffers/inverters/drivers 68
Bus switches 75
Counters/frequency dividers 76
Decoders/demultiplexers 78
Digital comparators 80
Digital multiplexers 80
Encoders 81
FIFO registers 82
Flip-flops 82
Full adders 86
Gates 87
AND gates 87
Combination gates 88
EXCLUSIVE-OR gates 89
EXCLUSIVE-NOR gates 89
NAND gates 90
NOR gates 92
OR gates 93
Latches / registered drivers 94
Level shifters/translators 96
Multivibrators 98
Parity generators/checkers 99
Phase-locked loops 99
Schmitt triggers 100
Shift registers/LED drivers 102
Transceivers 104

NXP Logic selection guide 2016 65

ANALOG SWITCHES
Features and benefits Applications
4 Reduced signal attenuation for low switching losses Audio/video source selection
4 
4 Reduced THD for high-quality audio switching Analog sensor multiplexing
4 
4 Fewer ADCs with analog sensor multiplexing GPIO expansion
4 
4 Integrated level shifting Bus isolation
4 
4 Low ON resistance, ON flatness Sample-and-hold circuits
4 
4 Low switch leakage
4 Wide supply voltage
4 Options for low input threshold
4 Overvoltage-tolerant options
4 High ESD protection per IEC 61000 standard

Analog switches (cont.)

Logic
VCC RON RON(FLAT) f(-3dB) THD Xtalk Tamb
Type number Description switching
(V) (Ω) (Ω) (MHz) (%) (dB) (°C)
levels
Single-pole, single-throw analog
74AHC1G66 2.0 to 5.5 CMOS 40 14 280 0.015 -40 to +125
switch
Single-pole, single-throw analog
74AHCT1G66 4.5 to 5.5 TTL 40 14 280 0.015 -40 to +125
switch; TTL-enabled
Single-pole, single-throw analog
74HC1G66 2.0 to 9.0 CMOS 105 23 200 0.02 -40 to +125
switch
Single-pole, single-throw analog
74HCT1G66 4.5 to 5.5 TTL 118 23 180 0.04 -40 to +125
switch; TTL-enabled
Dual single-pole, single-throw
74HC2G66 2.0 to 9.0 CMOS 105 23 200 0.02 -60 -40 to +125
analog switch
Dual single-pole, single-throw
74HCT2G66 4.5 to 5.5 TTL 118 23 180 0.04 -60 -40 to +125
analog switch; TTL-enabled
Quad single-pole, single-throw
74HC4016 2.0 to 10.0 CMOS 300 80 160 0.4 -60 -40 to +125
analog switch
Quad single-pole, single-throw
74HCT4016 4.5 to 5.5 TTL 400 50 150 0.8 -60 -40 to +125
analog switch; TTL-enabled
Single-pole, octal-throw analog
74HC4051 2.0 to 10.0 CMOS 200 20 180 0.02 -40 to +125
switch
Single-pole, octal-throw analog
74HCT4051 4.5 to 5.5 TTL 225 20 170 0.04 -40 to +125
switch; TTL-enabled
Dual single-pole, quad-throw
74HC4052 2.0 to 10.0 CMOS 200 20 180 0.02 -60 -40 to +125
analog switch
Dual single-pole, quad-throw
74HCT4052 4.5 to 5.5 TTL 225 20 170 0.04 -60 -40 to +125
analog switch; TTL-enabled
Triple single-pole, double-throw
74HC4053 2.0 to 10.0 CMOS 200 20 170 0.02 -40 to +125
analog switch
Triple single-pole, double-throw
74HCT4053 4.5 to 5.5 TTL 225 20 160 0.04 -40 to +125
analog switch; TTL-enabled
Quad single-pole, single-throw
74HC4066 2.0 to 10.0 CMOS 105 23 200 0.02 -60 -40 to +125
analog switch
Quad single-pole, single-throw
74HCT4066 4.5 to 5.5 TTL 118 23 180 0.04 -60 -40 to +125
analog switch; TTL-enabled
Single-pole, 16-throw analog
74HC4067 2.0 to 10.0 CMOS 200 25 100 0.02 -40 to +125
switch
Single-pole, 16-throw analog
74HCT4067 4.5 to 5.5 TTL 225 25 90 0.04 -40 to +125
switch; TTL-enabled
Quad single-pole, single-throw
74HC4316 2.0 to 10.0 CMOS 300 80 160 0.4 -60 -40 to +125
analog switch with translation

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

66 NXP Logic selection guide 2016

Analog switches (cont.)
Logic
VCC RON RON(FLAT) f(-3dB) THD Xtalk Tamb
Type number Description switching
(V) (Ω) (Ω) (MHz) (%) (dB) (°C)
levels
Quad single-pole, single-throw
74HCT4316 analog switch with translation; 4.5 to 5.5 TTL 400 50 150 0.8 -60 -40 to +125
TTL-enabled
Single-pole, octal-throw analog
74HC4351 2.0 to 10.0 CMOS 200 20 180 0.02 -40 to +125
switch with latch
Single-pole, octal-throw analog
74HCT4351 4.5 to 5.5 TTL 225 20 170 0.04 -40 to +125
switch with latch; TTL-enabled
Triple single-pole, double-throw
74HC4353 4.5 to 5.5 TTL 225 20 160 0.04 -60 -40 to +125
analog switch with latch
Triple single-pole, double-throw
74HCT4353 analog switch with latch; 4.5 to 5.5 TTL 225 20 160 0.04 -60 -40 to +125
TTL-enabled
Single-pole, octal-throw analog
74HC4851 2.0 to 10.0 CMOS 220 -40 to +125
switch
Single-pole, octal-throw analog
74HCT4851 4.5 to 5.5 TTL 240 -40 to +125
switch; TTL-enabled
Dual single-pole, quad-throw
74HC4852 2.0 to 10.0 CMOS 220 -40 to +125
analog switch; TTL-enabled
Dual single-pole, quad-throw
74HCT4852 4.5 to 5.5 TTL 240 -40 to +125
analog switch; TTL-enabled
Single-pole, octal-throw analog
74LV4051 1.0 to 6.0 TTL 135 35 200 0.4 -60 -40 to +125
switch
Dual single-pole, quad-throw
74LV4052 1.0 to 6.0 TTL 125 15 180 0.4 -60 -40 to +125
analog switch
Triple single-pole, double-throw
74LV4053 1.0 to 6.0 TTL 150 30 180 0.4 -60 -40 to +125
analog switch
Quad single-pole, single-throw
74LV4066 1.0 to 6.0 TTL 50 3 180 0.02 -60 -40 to +125
analog switch
Single-pole, double-throw analog CMOS/
74LVC1G3157 1.65 to 5.5 15 1,5 300 0.078 -40 to +125
switch LVTTL
Single-pole, single-throw analog CMOS/
74LVC1G384 1.65 to 5.5 15 1,5 440 0.001 -40 to +125
switch LVTTL
Single-pole, double-throw analog CMOS/
74LVC1G53 1.65 to 5.5 15 1,5 300 0.078 -40 to +125
switch LVTTL
Single-pole, single-throw analog CMOS/
74LVC1G66 1.65 to 5.5 15 1,5 440 0.001 -40 to +125
switch LVTTL
Single-pole, double-throw analog CMOS/
74LVC2G53 1.65 to 5.5 15 1,5 300 0.078 -40 to +125
switch LVTTL
Dual single-pole, single-throw CMOS/
74LVC2G66 1.65 to 5.5 15 1,5 440 0.005 -40 to +125
analog switch LVTTL
Quad single-pole, single-throw CMOS/
74LVC4066 1.65 to 5.5 15 1,5 440 0.005 -40 to +125
analog switch LVTTL
Dual single-pole, single-throw
CMOS/
74LVCV2G66 analog switch; overvoltage 2.3 to 5.5 15 3 210 0.01 -40 to +125
LVTTL
tolerant
Quad single-pole, single-throw
HEF4016 4.5 to 15.5 CMOS 350 65 90 0.04 -50 -40 to +85
analog switch
Single-pole, octal-throw analog
HEF4051 4.5 to 15.5 CMOS 175 30 70 0.04 -50 -40 to +85
switch
Dual single-pole, quad-throw
HEF4052 4.5 to 15.5 CMOS 175 30 70 0.04 -50 -40 to +85
analog switch
Triple single-pole, double-throw
HEF4053 4.5 to 15.5 CMOS 175 30 70 0.04 -50 -40 to +85
analog switch
Quad single-pole, single-throw
HEC4066 4.5 to 15.5 CMOS 175 20 90 0.04 -50 -40 to +85
analog switch
Single-pole, 16-throw analog
HEF4067 4.5 to 15.5 CMOS 175 20 13 0.04 -50 -40 to +85
switch

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 67

BUFFERS/INVERTERS/DRIVERS
Features and benefits Applications
4 Improved current drive and signal levels 4 STBs
4 Improved signal integrity in complex layouts 4 LCD TVs
4 Widths from one to 32 bits 4 Cell phones
4 Inverting, non-inverting variants 4 Industrial monitoring
4 Mixed 3.3/5 V applications
4 Wide range of supply voltages
4 Low propagation delay
4 O ptional TTL inputs, 3-state outputs, overvoltage-tolerant
inputs, bus hold

Buffers-inverters-drivers (cont.)
Output
Logic Output
VCC drive tpd fmax Tamb
Type number Description switching Load
(V) capability (ns) (MHz) (°C)
levels CL (Typ)
(mA)
74AHC04 Hex inverter 2.0 to 5.5 CMOS ±8 50 pF 3 60 -40 to +125

74AHCT04 Hex inverter; TTL-enabled 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125

74AHC125 Quad buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3 60 -40 to +125

74AHCT125 Quad buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125

74AHC126 Quad buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.3 60 -40 to +125

74AHCT126 Quad buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125

74AHC1G04 Single inverter 2.0 to 5.5 CMOS ±8 50 pF 3.1 60 -40 to +125

74AHCT1G04 Single inverter; TTL-enabled 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125

74AHC1G06 Single inverter; open drain 2.0 to 5.5 CMOS 8 50 pF 2.7 60 -40 to +125

74AHCT1G06 Single inverter; open drain; TTL-enabled 4.5 to 5.5 TTL 8 50 pF 3 60 -40 to +125

74AHC1G07 Single buffer; open drain 2.0 to 5.5 CMOS 8 50 pF 2.5 60 -40 to +125

74AHCT1G07 Single buffer; open drain; TTL-enabled 4.5 to 5.5 TTL 8 50 pF 2.8 60 -40 to +125

74AHC1G125 Single buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125

74AHCT1G125 Single buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125

74AHC1G126 Single buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125

74AHCT1G126 Single buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125

74AHC1G17 Single buffer with Schmitt-trigger inputs 2.0 to 5.5 CMOS ±8 50 pF 3.2 60 -40 to +125
Single buffer with Schmitt-trigger inputs;
74AHCT1G17 4.5 to 5.5 TTL ±8 50 pF 4.1 60 -40 to +125
TTL-enabled
74AHC240 Octal inverter/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 2.8 60 -40 to +125

74AHCT240 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125

74AHC244 Octal buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.5 60 -40 to +125

74AHCT244 Octal buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.5 60 -40 to +125

74AHC2G125 Dual buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125

74AHCT2G125 Dual buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125

74AHC2G126 Dual buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

68 NXP Logic selection guide 2016

Buffers-inverters-drivers (cont.)
Output
Logic Output
VCC drive tpd fmax Tamb
Type number Description switching Load
(V) capability (ns) (MHz) (°C)
levels CL (Typ)
(mA)
74AHCT2G126 Dual buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125

74AHC2G241 Dual buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125

74AHCT2G241 Dual buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125

74AHC3G04 Triple inverter 2.0 to 5.5 CMOS ±8 50 pF 3.1 60 -40 to +125

74AHCT3G04 Triple inverter; TTL-enabled 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125

74AHC541 Octal buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.5 60 -40 to +125

74AHCT541 Octal buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.5 60 -40 to +125

74AHC1GU04 Single inverter; unbuffered 2.0 to 5.5 CMOS ±8 50 pF 2.6 60 -40 to +125

74AHC3GU04 Triple inverter; unbuffered 2.0 to 5.5 CMOS ±8 50 pF 2.5 60 -40 to +125

74AHCU04 Hex inverter; unbuffered 2.0 to 5.5 CMOS ±8 50 pF 2.4 60 -40 to +125

74ALVC16244 16-bit buffer/line driver (3-state) 1.2 to 3.6 LVTTL ±24 50 pF 1.9 150 -40 to +85

74ALVCH16244 16-bit buffer/line driver with bus hold (3-state) 1.2 to 3.6 LVTTL ±24 30 pF 1.9 150 -40 to +85

74ALVC04 Hex inverter 1.65 to 3.6 LVTTL ±24 30 pF 2 150 -40 to +85

74ALVC125 Quad buffer/line driver (3-state) 1.65 to 3.6 LVTTL ±24 30 pF 1.8 145 -40 to +85

74ALVC244 Octal buffer/line driver (3-state) 1.65 to 3.6 LVTTL ±24 30 pF 2.9 130 -40 to +85

74ALVC541 Octal buffer/line driver (3-state) 1.65 to 3.6 LVTTL ±24 30 pF 2.3 130 -40 to +85
16-bit buffer/line driver with bus hold and
74ALVCH162244 2.3 to 3.6 LVTTL ±12 30 pF 2.7 150 -40 to +85
30 Ω termination resistors (3-state)
20-bit buffer/line driver with bus hold and
74ALVCH162827 2.3 to 3.6 LVTTL ±12 30 pF 2.9 150 -40 to +85
30 Ω termination resistors (3-state)
74ALVCH16825 18-bit buffer/line driver with bus hold (3-state) 2.3 to 3.6 LVTTL ±24 30 pF 2 150 -40 to +85

74ALVCH16827 20-bit buffer/line driver with bus hold (3-state) 2.3 to 3.6 LVTTL ±24 30 pF 2 150 -40 to +85
16-bit inverter/line driver with bus hold and
74ALVT162240 2.3 to 3.6 LVTTL ±12 50 pF 2.6 75 -40 to +85
30 Ω termination (3-state)
16-bit buffer/line driver with bus hold and
74ALVT162241 2.3 to 3.6 LVTTL ±12 50 pF 2.2 75 -40 to +85
30 Ω termination resistors (3-state)
16-bit buffer/line driver with bus hold and
74ALVT162244 2.3 to 3.6 LVTTL ±12 50 pF 2.2 75 -40 to +85
30 Ω termination resistors (3-state)
16-bit inverter/line driver with bus hold
74ALVT16240 2.3 to 3.6 LVTTL -32 / +64 50 pF 1.7 200 -40 to +85
(3-state)
74ALVT16241 16-bit buffer/line driver with bus hold (3-state) 2.3 to 3.6 LVTTL -32 / +64 50 pF 1.3 200 -40 to +85

74ALVT16244 16-bit buffer/line driver with bus hold (3-state) 2.3 to 3.6 LVTTL -32 / +64 50 pF 1.5 200 -40 to +85
20-bit buffer/line driver with bus hold and
74ALVT162827 2.3 to 3.6 LVTTL ±12 50 pF 2.2 75 -40 to +85
30 Ω termination resistors (3-state)
74ALVT16827 20-bit buffer/line driver with bus hold (3-state) 2.3 to 3.6 LVTTL -32 / +64 50 pF 1.3 200 -40 to +85

74AUP1G04 Single inverter 1.1 to 3.6 CMOS ±1.9 30 pF 4 70 -40 to +125

74AUP1G06 Single inverter; open drain 1.1 to 3.6 CMOS 1,9 30 pF 4.5 70 -40 to +125

74AUP1G07 Single buffer; open drain 1.1 to 3.6 CMOS 1,9 30 pF 4.4 70 -40 to +125

74AUP1G125 Single buffer/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.3 70 -40 to +125

74AUP1G126 Single buffer/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.3 70 -40 to +125

74AUP1G14 Single inverter; Schmitt trigger 1.1 to 3.6 CMOS ±1.9 30 pF 4.7 70 -40 to +125

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 69

Buffers-inverters-drivers (cont.)
Output
Logic Output
VCC drive tpd fmax Tamb
Type number Description switching Load
(V) capability (ns) (MHz) (°C)
levels CL (Typ)
(mA)
74AUP1G240 Single inverter/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.2 70 -40 to +125

74AUP1G34 Single buffer 1.1 to 3.6 CMOS ±1.9 30 pF 3.9 70 -40 to +125

74AUP1GU04 Single inverter; unbuffered 1.1 to 3.6 CMOS ±1.9 30 pF 2.3 70 -40 to +125

74AUP2G04 Dual inverter 1.1 to 3.6 CMOS ±1.9 30 pF 4 70 -40 to +125

74AUP2G06 Dual inverter; open drain 1.1 to 3.6 CMOS 1,9 30 pF 4.5 70 -40 to +125

74AUP2G07 Dual buffer; open drain 1.1 to 3.6 CMOS 1,9 30 pF 4.4 70 -40 to +125

74AUP2G125 Dual buffer/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.3 70 -40 to +125

74AUP2G126 Dual buffer/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.3 70 -40 to +125

74AUP2G14 Dual inverter; Schmitt trigger 1.1 to 3.6 CMOS ±1.9 30 pF 4.7 70 -40 to +125

74AUP2G240 Dual inverter/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.2 70 -40 to +125

74AUP2G241 Dual buffer/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.3 70 -40 to +125

74AUP2G34 Dual buffer 1.1 to 3.6 CMOS ±1.9 30 pF 3.9 70 -40 to +125

74AUP2GU04 Dual inverter; unbuffered 1.1 to 3.6 CMOS ±1.9 30 pF 2.3 70 -40 to +125

74AUP3G04 Triple inverter 1.1 to 3.6 CMOS ±1.9 30 pF 4 70 -40 to +125

CMOS/
74AVC16244 16-bit buffer/line driver (3-state) 0.8 to 3.6 ±12 30 pF 2 200 -40 to +85
LVTTL
CMOS/
74AVCH16244 16-bit buffer/line driver with bus hold (3-state) 0.8 to 3.6 ±12 30 pF 2 200 -40 to +85
LVTTL
74AXP1G06 Single inverter; open drain 0.7 to 2.75 CMOS 4,5 5pF 3.5 70 -40 to +85

74AXP1G125 Single buffer/line driver (3-state) 0.7 to 2.75 CMOS ±4.5 5pF 2.7 70 -40 to +85

74HC04 Hex inverter 2.0 to 6.0 CMOS ±5.2 50 pF 7 36 -40 to +125

74HCT04 Hex inverter; TTL-enabled 4.5 to 5.5 TTL ±4.0 50 pF 8 36 -40 to +125

74HC125 Quad buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125

74HCT125 Quad buffer/line driver (3-state) 4.5 to 5.5 TTL ±6 50 pF 12 36 -40 to +125

74HC126 Quad buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125

74HCT126 Quad buffer/line driver (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125

74HC1G04 Single inverter 2.0 to 6.0 CMOS ±2.6 50 pF 7 36 -40 to +125

74HCT1G04 Single inverter; TTL-enabled 4.5 to 5.5 TTL ±2.0 50 pF 8 36 -40 to +125

74HC1G125 Single buffer/line driver (3-state) 2.0 to 6.0 CMOS ±2.6 50 pF 9 36 -40 to +125

74HCT1G125 Single buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±2.0 50 pF 10 36 -40 to +125

74HC1G126 Single buffer/line driver (3-state) 2.0 to 6.0 CMOS ±2.6 50 pF 9 36 -40 to +125

74HCT1G126 Single buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±2.0 50 pF 10 36 -40 to +125

74HC240 Octal inverter/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125

74HCT240 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 9 36 -40 to +125

74HCT240 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 9 36 -40 to +125

74HCT240 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 9 36 -40 to +125

74HC241 Octal buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 7 36 -40 to +125

74HCT241 Octal buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

70 NXP Logic selection guide 2016

Buffers-inverters-drivers (cont.)
Output
Logic Output
VCC drive tpd fmax Tamb
Type number Description switching Load
(V) capability (ns) (MHz) (°C)
levels CL (Typ)
(mA)
74HC244 Octal buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125

74HCT244 Octal buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125

74HC2G04 Dual inverter 2.0 to 6.0 CMOS ±5.2 50 pF 8 36 -40 to +125

74HCT2G04 Dual inverter; TTL-enabled 4.5 to 5.5 TTL ±4.0 50 pF 10 36 -40 to +125

74HC2G125 Dual buffer/line driver (3-state) 2.0 to 6.0 CMOS ±5.2 50 pF 10 36 -40 to +125

74HCT2G125 Dual buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±4.0 50 pF 12 36 -40 to +125

74HC2G126 Dual buffer/line driver (3-state) 2.0 to 6.0 CMOS ±5.2 50 pF 10 36 -40 to +125

74HC2G34 Dual buffer 2.0 to 6.0 CMOS ±5.2 50 pF 9 36 -40 to +125

74HCT2G34 Dual buffer; TTL-enabled 4.5 to 5.5 TTL ±4 50 pF 10 32 -40 to +125

74HC365 Hex buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125

74HCT365 Hex buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125

74HC366 Hex inverter/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 10 36 -40 to +125

74HCT366 Hex inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125

74HC367 Hex buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 8 36 -40 to +125

74HCT367 Hex buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125

74HC368 Hex inverter/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125

74HCT368 Hex inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125

74HC3G04 Triple inverter 2.0 to 6.0 CMOS ±5.2 50 pF 8 36 -40 to +125

74HCT3G04 Triple inverter; TTL-enabled 4.5 to 5.5 TTL ±4.0 50 pF 10 36 -40 to +125

74HC3G06 Triple inverter; open drain 2.0 to 6.0 CMOS 5,2 50 pF 9 36 -40 to +125

74HCT3G06 Triple inverter; open drain; TTL-enabled 4.5 to 5.5 TTL 4 50 pF 9 36 -40 to +125

74HC3G07 Triple buffer; open drain 2.0 to 6.0 CMOS 5,2 50 pF 9 36 -40 to +125

74HCT3G07 Triple buffer; open drain; TTL-enabled 4.5 to 5.5 TTL 4 50 pF 9 36 -40 to +125

74HC3G34 Triple buffer 2.0 to 6.0 CMOS ±5.2 50 pF 9 36 -40 to +125

74HCT3G34 Triple buffer; TTL-enabled 4.5 to 5.5 TTL ±4.0 50 pF 10 36 -40 to +125

74HC540 Octal inverter/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125

74HCT540 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125

74HC541 Octal buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 10 36 -40 to +125

74HCT541 Octal buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 12 36 -40 to +125

74HC05 Hex inverter; open drain 2.0 to 6.0 CMOS 5,2 50 pF 11 36 -40 to +125

74HC1GU04 Single inverter; unbuffered 2.0 to 6.0 CMOS ±2.6 50 pF 5 36 -40 to +125

74HC2GU04 Single inverter; unbuffered 2.0 to 6.0 CMOS ±2.6 50 pF 5 36 -40 to +125

74HC3GU04 Triple inverter; unbuffered 2.0 to 6.0 CMOS ±5.2 50 pF 6 36 -40 to +125

74HC3GU04 Triple inverter; unbuffered 2.0 to 6.0 CMOS ±5.2 50 pF 6 36 -40 to +125

74HCU04 Hex inverter; unbuffered 2.0 to 6.0 CMOS ±5.2 50 pF 5 36 -40 to +125

74LV04 Hex inverter 1.0 to 5.5 CMOS ±12 50 pF 6 30 -40 to +125

74LV125 Quad buffer/line driver (3-state) 1.0 to 5.5 CMOS ±16 50 pF 9 30 -40 to +125

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 71

Buffers-inverters-drivers (cont.)
Output
Logic Output
VCC drive tpd fmax Tamb
Type number Description switching Load
(V) capability (ns) (MHz) (°C)
levels CL (Typ)
(mA)
74LV241 Octal buffer/line driver (3-state) 1.0 to 5.5 CMOS ±8 50 pF 8 30 -40 to +125

74LV244 Octal buffer/line driver (3-state) 1.0 to 5.5 CMOS ±16 50 pF 8 30 -40 to +125

74LV365 Hex buffer/line driver (3-state) 1.0 to 3.6 CMOS ±8 50 pF 9 30 -40 to +125

74LV367 Hex buffer/line driver (3-state) 1.0 to 3.6 CMOS ±8 50 pF 8 30 -40 to +125

74LV541 Octal buffer/line driver (3-state) 1.0 to 3.6 CMOS ±8 50 pF 10 30 -40 to +125
16-bit buffer/line driver with 30 Ω termination CMOS/
74LVC162244 1.2 to 3.6 ±24 50 pF 2.9 175 -40 to +125
resistors (3-state) LVTTL
16-bit buffer/line driver with bus hold and CMOS/
74LVCH162244 1.2 to 3.6 ±12 50 pF 2.9 175 -40 to +125
30 Ω termination resistors (3-state) LVTTL
CMOS/
74LVC16244 16-bit buffer/line driver (3-state) 1.2 to 3.6 ±24 50 pF 3 175 -40 to +125
LVTTL
CMOS/
74LVCH16244 16-bit buffer/line driver with bus hold (3-state) 1.2 to 3.6 ±24 50 pF 3 175 -40 to +125
LVTTL
CMOS/
74LVC244 Octal buffer/line driver (3-state) 1.2 to 3.6 ±24 50 pF 2.8 175 -40 to +125
LVTTL
CMOS/
74LVCH244 Octal buffer/line driver with bus hold (3-state) 1.2 to 3.6 ±24 50 pF 2.8 175 -40 to +125
LVTTL
CMOS/
74LVC04 Hex inverter 1.65 to 5.5 ±24 50 pF 2 175 -40 to +125
LVTTL
CMOS/
74LVC06 Hex inverter; open drain 1.65 to 5.5 32 50 pF 2.2 175 -40 to +125
LVTTL
CMOS/
74LVC07 Hex buffer; open drain 1.65 to 5.5 32 50 pF 2.2 175 -40 to +125
LVTTL
CMOS/
74LVC125 Quad buffer/line driver (3-state) 1.2 to 3.6 ±24 50 pF 2.4 175 -40 to +125
LVTTL
CMOS/
74LVC126 Quad buffer/line driver (3-state) 1.2 to 3.6 ±24 50 pF 2.4 175 -40 to +125
LVTTL
CMOS/
74LVC16240 16-bit inverter/line driver (3-state) 1.2 to 3.6 ±24 50 pF 2.7 175 -40 to +125
LVTTL
CMOS/
74LVC16241 16-bit buffer/line driver (3-state) 1.2 to 3.6 ±24 50 pF 2.9 175 -40 to +125
LVTTL
CMOS/
74LVC1G04 Single inverter 1.65 to 5.5 ±32 50 pF 2 175 -40 to +125
LVTTL
CMOS/
74LVC1G06 Single inverter; open drain 1.65 to 5.5 32 50 pF 2.3 175 -40 to +125
LVTTL
CMOS/
74LVC1G07 Single buffer; open drain 1.65 to 5.5 32 50 pF 2.2 175 -40 to +125
LVTTL
CMOS/
74LVC1G125 Single buffer/line driver; TTL-enabled (3-state) 1.65 to 5.5 ±32 50 pF 2.1 175 -40 to +125
LVTTL
CMOS/
74LVC1G126 Single buffer/line driver; TTL-enabled (3-state) 1.65 to 5.5 ±32 50 pF 2 175 -40 to +125
LVTTL
CMOS/
74LVC1G34 Single buffer 1.65 to 5.5 ±32 50 pF 2 175 -40 to +125
LVTTL
CMOS/
74LVC1GU04 Single inverter; unbuffered 1.65 to 5.5 ±32 50 pF 1.6 175 -40 to +125
LVTTL
Octal buffer/line driver with 30 Ω termination CMOS/
74LVC2244 1.2 to 3.6 ±12 50 pF 3.1 175 -40 to +125
resistors (3-state) LVTTL
CMOS/
74LVC240 Octal inverter/line driver (3-state) 1.2 to 3.6 ±24 50 pF 3.5 175 -40 to +125
LVTTL
CMOS/
74LVC241 Octal buffer/line driver (3-state) 1.2 to 3.6 ±24 50 pF 3.2 175 -40 to +125
LVTTL
CMOS/
74LVC2G04 Dual inverter 1.65 to 5.5 ±32 50 pF 2.7 175 -40 to +125
LVTTL

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

72 NXP Logic selection guide 2016

Buffers-inverters-drivers (cont.)
Output
Logic Output
VCC drive tpd fmax Tamb
Type number Description switching Load
(V) capability (ns) (MHz) (°C)
levels CL (Typ)
(mA)
CMOS/
74LVC2G06 Dual inverter; open drain 1.65 to 5.5 32 50 pF 2.3 175 -40 to +125
LVTTL
CMOS/
74LVC2G07 Dual buffer; open drain 1.65 to 5.5 32 50 pF 2.6 175 -40 to +125
LVTTL
CMOS/
74LVC2G125 Dual buffer/line driver; TTL-enabled (3-state) 1.65 to 5.5 ±32 50 pF 2.3 175 -40 to +125
LVTTL
CMOS/
74LVC2G126 Dual buffer/line driver; TTL-enabled (3-state) 1.65 to 5.5 ±32 50 pF 2.4 175 -40 to +125
LVTTL
CMOS/
74LVC2G240 Dual inverter/line driver (3-state) 1.65 to 5.5 ±32 50 pF 2.5 175 -40 to +125
LVTTL
CMOS/
74LVC2G241 Dual buffer/line driver (3-state) 1.65 to 5.5 ±32 50 pF 2.6 175 -40 to +125
LVTTL
CMOS/
74LVC2G34 Dual buffer 1.65 to 5.5 ±32 50 pF 2.2 175 -40 to +125
LVTTL
CMOS/
74LVC2GU04 Dual inverter; unbuffered 1.65 to 5.5 ±32 50 pF 2.3 175 -40 to +125
LVTTL
CMOS/
74LVC3G04 Triple inverter 1.65 to 5.5 ±32 50 pF 2.7 175 -40 to +125
LVTTL
CMOS/
74LVC3G06 Triple inverter; open drain 1.65 to 5.5 32 50 pF 2 175 -40 to +125
LVTTL
CMOS/
74LVC3G07 Triple buffer; open drain 1.65 to 5.5 32 50 pF 2.1 175 -40 to +125
LVTTL
CMOS/
74LVC3G34 Triple buffer 1.65 to 5.5 ±32 50 pF 2.2 175 -40 to +125
LVTTL
CMOS/
74LVC3GU04 Triple inverter; unbuffered 1.65 to 5.5 ±32 50 pF 2.3 175 -40 to +125
LVTTL
CMOS/
74LVC541 Octal buffer/line driver (3-state) 1.2 to 3.6 ±24 50 pF 3.3 175 -40 to +125
LVTTL
CMOS/
74LVC827 10-bit buffer/line driver (3-state) 1.2 to 3.6 ±24 50 pF 4 175 -40 to +125
LVTTL
CMOS/
74LVCH16541 16-bit buffer/line driver with bus hold (3-state) 1.2 to 3.6 ±24 50 pF 2.7 175 -40 to +125
LVTTL
32-bit buffer/line driver with bus hold and CMOS/
74LVCH322244 1.2 to 3.6 ±12 50 pF 2 175 -40 to +125
30 Ω termination resistors (3-state) LVTTL
CMOS/
74LVCH32244 32-bit buffer/line driver with bus hold (3-state) 1.2 to 3.6 ±24 50 pF 3 175 -40 to +125
LVTTL
CMOS/
74LVCU04 Hex inverter; unbuffered 1.2 to 3.6 ±24 50 pF 2 175 -40 to +125
LVTTL
74LVT125 Quad buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2.9 150 -40 to +85

74LVTH125 Quad buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2.9 150 -40 to +85

74LVT16244 16-bit buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 1.8 150 -40 to +85

74LVTH16244 16-bit buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 1.8 150 -40 to +85

74LVT244 Octal buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2.6 150 -40 to +85

74LVTH244 Octal buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2.6 150 -40 to +85

74LVT244 Octal buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2 150 -40 to +85

74LVTH244 Octal buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2 150 -40 to +85

74LVT04 Hex inverter 2.7 to 3.6 TTL -20 / +32 50 pF 2.6 150 -40 to +85

74LVT126 Quad buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2.4 150 -40 to +85
16-bit inverter/line driver with bus hold and
74LVT162240 2.7 to 3.6 TTL ±12 50 pF 2.6 150 -40 to +85
30 Ω termination (3-state)

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 73

Buffers-inverters-drivers (cont.)
Output
Logic Output
VCC drive tpd fmax Tamb
Type number Description switching Load
(V) capability (ns) (MHz) (°C)
levels CL (Typ)
(mA)
16-bit buffer/line driver with bus hold and
74LVT162244 2.7 to 3.6 TTL ±12 50 pF 2.8 150 -40 to +85
30 Ω termination resistors (3-state)
16-bit inverter/line driver with bus hold
74LVT16240 2.7 to 3.6 TTL -32 / +64 50 pF 2 150 -40 to +85
(3-state)
Octal buffer/line driver with bus hold and 30 Ω
74LVT2241 2.7 to 3.6 TTL ±12 50 pF 3.3 150 -40 to +85
termination resistors (3-state)
Octal buffer/line driver with bus hold and 30 Ω
74LVT2244 2.7 to 3.6 TTL ±12 50 pF 2.9 150 -40 to +85
termination resistors (3-state)
Octal inverter/line driver with bus hold
74LVT240 2.7 to 3.6 TTL -32 / +64 50 pF 2.5 150 -40 to +85
(3-state)
74LVT241 Octal buffer/line driver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 2.8 150 -40 to +85

74LVTN16244 16-bit buffer/line driver (3-state) 2.7 to 3.6 TTL -32 / +64 50 pF 1.8 150 -40 to +85

74LVU04 Hex inverter; unbuffered 1.0 to 5.5 CMOS -12 / +12 50 pF 6 30 -40 to +125

74VHC125 Quad buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3 60 -40 to +125

74VHCT125 Quad buffer/line driver (3-state) 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125

74VHC126 Quad buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.3 60 -40 to +125

74VHCT126 Quad buffer/line driver (3-state) 4.5 to 5.5 TTL ±8 50 pF 3 60 -40 to +125

74VHC244 Octal inverter/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.5 60 -40 to +125

74VHCT244 Octal inverter/line driver (3-state) 4.5 to 5.5 TTL ±8 50 pF 5 60 -40 to +125

74VHC541 Octal buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.5 60 -40 to +125

74VHCT541 Octal buffer/line driver (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.5 60 -40 to +125

HEF40098 Hex inverter 3.0 to 15.0 CMOS -10 / +20 50 pF 25 10 -40 to +125

HEF40240 Octal inverter/line driver (3-state) 3.0 to 15.0 CMOS -50 / +45 50 pF 30 10 -40 to +125

HEF40244 Octal buffer/line driver (3-state) 3.0 to 15.0 CMOS -62 / +45 50 pF 30 10 -40 to +125

HEF4049 Hex inverter/line driver 3.0 to 15.0 CMOS -3 / +20 50 pF 20 10 -40 to +125

HEF4050 Hex buffer/line driver 3.0 to 15.0 CMOS -3 / +20 50 pF 40 10 -40 to +125

HEF4069 Hex inverter; unbuffered 3.0 to 15.0 CMOS ±3.4 50 pF 15 10 -40 to +125

XC7SET04 Single inverter; TTL-enabled 4.5 to 5.5 TTL ±8 50 pF 3.5 60 -40 to +125

XC7SET125 Single buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.4 60 -40 to +125

XC7SH04 Single inverter 2.0 to 5.5 CMOS ±8 50 pF 3.5 60 -40 to +125

XC7SH125 Single buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125

XC7SHU04 Single inverter; unbuffered 2.0 to 5.5 CMOS ±8 50 pF 3.5 60 -40 to +125

XC7WH126 Dual buffer/line driver (3-state) 2.0 to 5.5 CMOS ±8 50 pF 3.4 60 -40 to +125

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

74 NXP Logic selection guide 2016

BUS SWITCHES
Features and benefits Applications
4 Level shifting (1.8/3.3 or 3.3/5 V) 4 Telecommunications infrastructure
4 Low propagation delay 4 Industrial control
4 T TL control inputs 4 Cell phones
4 Unidirectional level shifting
4 Backplane hotswap
4 Memory interleaving
4 Signal conditioning

Bus switches
VCC VPASS Logic RON f(-3dB) Number tpd Tamb
Type number Description
(V) (V) switching levels (Ω) (MHz) of bits (ns) (°C)
74CBTLV16211 24-bit bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 10 0.2 -40 to +125
74CBTLV1G125 Single bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 1 0.2 -40 to +125
74CBTLV3125 Quad bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 4 0.2 -40 to +125
74CBTLV3126 Quad bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 4 0.2 -40 to +125
74CBTLV3244 Octal bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 8 0.2 -40 to +125
74CBTLV3245 Octal bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 8 0.2 -40 to +125
74CBTLV3253 Dual 4:1 mux/demux 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 2 0.2 -40 to +125
74CBTLV3257 Quad 2:1 mux/demux 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 4 0.2 -40 to +125
74CBTLV3384 10-bit bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 10 0.2 -40 to +125
74CBTLV3861 10-bit bus switch 2.3 to 3.6 3,3 CMOS / LVTTL 7 400 10 0.2 -40 to +125
74CBTLVD3244 Octal bus switch level translator 3.0 to 3.6 1,8 CMOS / LVTTL 7 400 8 0.2 -40 to +125
74CBTLVD3245 Octal bus switch level translator 3.0 to 3.6 1,8 CMOS / LVTTL 7 400 8 0.2 -40 to +125
74CBTLVD3384 10-bit bus switch level translator 3.0 to 3.6 1,8 CMOS / LVTTL 7 400 10 0.2 -40 to +125
74CBTLVD3861 10-bit bus switch level translator 3.0 to 3.6 1,8 CMOS / LVTTL 7 400 10 0.2 -40 to +125
CBT16210 20-bit bus switch 4.5 to 5.5 3,9 TTL 7 300 20 0.25 -40 to +85
CBT16211 24-bit bus switch 4.5 to 5.5 3,9 TTL 7 300 24 0.25 -40 to +85
CBT16212 24-bit bus exchange switch 4.5 to 5.5 3,9 TTL 7 300 24 0.25 -40 to +85
CBT16292 12-bit 2:1 mux/demux 4.5 to 5.5 3,9 TTL 8 300 12 0.4 -40 to +85
CBT3125 Quad bus switch 4.5 to 5.5 3,9 TTL 7 300 4 0.25 -40 to +85
CBT3126 Quad bus switch 4.5 to 5.5 3,9 TTL 7 300 4 0.25 -40 to +85
CBT3244 Octal bus switch 4.5 to 5.5 3,9 TTL 7 300 8 0.25 -40 to +85
CBT3245 Octal bus switch 4.5 to 5.5 3,9 TTL 7 300 8 0.25 -40 to +85
CBT3251 8:1 mux/demux 4.5 to 5.5 3,9 TTL 7 300 8 0.25 -40 to +85
CBT3253 Dual 4:1 mux/demux 4.5 to 5.5 3,9 TTL 7 300 2 0.25 -40 to +85
CBT3257 Quad 2:1 mux/demux 4.5 to 5.5 3,9 TTL 7 300 4 0.25 -40 to +85
CBT3306 Dual bus switch 4.5 to 5.5 3,9 TTL 7 300 2 0.25 -40 to +85
CBT3384 10-bit bus switch 4.5 to 5.5 3,9 TTL 7 300 10 0.25 -40 to +85
CBT3861 10-bit bus switch 4.5 to 5.5 3,9 TTL 7 300 10 0.25 -40 to +85
CBTD16210 20-bit bus switch level translator 4.5 to 5.5 3,3 TTL 7 300 20 0.25 -40 to +85
CBTD16211 24-bit bus switch level translator 4.5 to 5.5 3,3 TTL 7 300 24 0.25 -40 to +85
CBTD3306 Dual bus switch level translator 4.5 to 5.5 3,3 TTL 7 300 2 0.25 -40 to +85
CBTD3384 10-bit bus switch level translator 4.5 to 5.5 3,3 TTL 7 300 10 0.25 -40 to +85
CBTD3861 10-bit bus switch level translator 4.5 to 5.5 3,3 TTL 7 300 10 0,25 -40 to +85

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 75

COUNTERS/FREQUENCY DIVIDERS
Features and benefits Applications
4 Integrated oscillator 4 Generate clock signals
4 Low-power CMOS 4 Frequency-divide external clock signals
4 T TL-compatible inputs 4 Initiate events after a pre-set number of clock pulses

Counters/frequency dividers (cont.)

Output
Logic Output
Type drive tpd fmax
Description VCC (V) switching Load Tamb (°C)
number capability (ns) (MHz)
levels CL (Typ)
(mA)
Presettable synchronous BCD decade counter;
74HC160 2.0 to 6.0 ±5.2 CMOS 18 50 pF 55 -40 to +125
asynchronous reset
Presettable synchronous BCD decade counter;
74HCT160 4.5 to 5.5 ±4.0 TTL 21 50 pF 28 -40 to +125
asynchronous reset; TTL-enabled
Presettable synchronous 4-bit binary counter;
74HC161 2.0 to 6.0 ±5.2 CMOS 19 50 pF 48 -40 to +125
asynchronous reset
Presettable synchronous 4-bit binary counter;
74HCT161 4.5 to 5.5 ±4.0 TTL 20 50 pF 41 -40 to +125
asynchronous reset; TTL-enabled
Presettable synchronous 4-bit binary counter;
74HC163 2.0 to 6.0 ±5.2 CMOS 17 50 pF 50 -40 to +125
synchronous reset
Presettable synchronous 4-bit binary counter;
74HCT163 4.5 to 5.5 ±4.0 TTL 20 50 pF 50 -40 to +125
synchronous reset; TTL-enabled
74HC191 Presettable synchronous 4-bit binary up/down counter 2.0 to 6.0 ±5.2 CMOS 22 50 pF 36 -40 to +125
Presettable synchronous 4-bit binary up/down counter;
74HCT191 4.5 to 5.5 ±4.0 TTL 22 50 pF 39 -40 to +125
TTL-enabled
Presettable synchronous 4-bit binary up/down counter;
74HC193 2.0 to 6.0 ±5.2 CMOS 20 50 pF 49 -40 to +125
separate up/down clocks
Presettable synchronous 4-bit binary up/down counter;
74HCT193 4.5 to 5.5 ±4.0 TTL 20 50 pF 43 -40 to +125
separate up/down clocks; TTL-enabled
74HC390 Dual decade ripple counter 2.0 to 6.0 ±5.2 CMOS 14 50 pF 60 -40 to +125

74HCT390 Dual decade ripple counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 18 50 pF 55 -40 to +125

74HC393 Dual 4-bit binary ripple counter 2.0 to 6.0 ±5.2 CMOS 12 50 pF 107 -40 to +125

74HCT393 Dual 4-bit binary ripple counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 20 50 pF 53 -40 to +125

74HC4017 Johnson decade counter with 10 decoded outputs 2.0 to 6.0 ±5.2 CMOS 18 50 pF 77 -40 to +125
Johnson decade counter with 10 decoded outputs;
74HCT4017 4.5 to 5.5 ±4.0 TTL 21 50 pF 67 -40 to +125
TTL-enabled
74HC4020 14-stage binary ripple counter 2.0 to 6.0 ±5.2 CMOS 11 50 pF 52 -40 to +125

74HCT4020 14-stage binary ripple counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 15 50 pF 52 -40 to +125

74HC4040 12-stage binary ripple counter 2.0 to 6.0 ±5.2 CMOS 14 50 pF 90 -40 to +125

74HCT4040 12-stage binary ripple counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 16 50 pF 79 -40 to +125

74HC4059 Programmable divide-by-n counter 2.0 to 6.0 ±5.2 CMOS 17 50 pF 43 -40 to +125

74HCT4059 Programmable divide-by-n counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 20 50 pF 40 -40 to +125

74HC4060 14-stage binary ripple counter with oscillator 2.0 to 6.0 ±5.2 CMOS 31 50 pF 95 -40 to +125
14-stage binary ripple counter with oscillator;
74HCT4060 4.5 to 5.5 ±4.0 TTL 31 50 pF 88 -40 to +125
TTL-enabled

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

76 NXP Logic selection guide 2016

Counters/frequency dividers (cont.)
Output
Logic Output
Type drive tpd fmax
Description VCC (V) switching Load Tamb (°C)
number capability (ns) (MHz)
levels CL (Typ)
(mA)
74HC4520 Dual 4-bit synchronous binary counter 2.0 to 6.0 ±5.2 CMOS 24 50 pF 64 -40 to +125

74HCT4520 Dual 4-bit synchronous binary counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 24 50 pF 64 -40 to +125

74HC5555 Programmable delay timer with oscillator 2.0 to 6.0 - 20/ + 25 CMOS 89 50 pF 24 -40 to +125

74HCT5555 Programmable delay timer with oscillator; TTL-enabled 4.5 to 5.5 ±20 TTL 75 50 pF 24 -40 to +125

74HC6323 Programmable ripple counter with oscillator (3-state) 2.0 to 6.0 ±7.8 CMOS 17 50 pF 100 -40 to +125
Programmable ripple counter with oscillator (3-state);
74HCT6323 4.5 to 5.5 ±4.0 TTL 17 50 pF 85 -40 to +125
TTL-enabled
74HC93 4-bit binary ripple counter 2.0 to 6.0 ±5.2 CMOS 12 50 pF 100 -40 to +125

74HCT93 4-bit binary ripple counter; TTL-enabled 4.5 to 5.5 ±4.0 TTL 15 50 pF 77 -40 to +125

74HC40103 8-bit synchronous binary down counter 2.0 to 6.0 ±5.2 CMOS 15 50 pF 14 -40 to +125

74HC4024 7-stage binary ripple counter 2.0 to 6.0 ±5.2 CMOS 14 50 pF 90 -40 to +125

74HC590 8-bit binary counter with output register (3-state) 2.0 to 6.0 ±5.2 CMOS 19 50 pF 61 -40 to +125

74LV393 Dual 4-bit binary ripple counter 1.0 to 3.6 ±6 TTL 12 50 pF 90 -40 to +125

74LV4020 14-stage binary ripple counter 1.0 to 5.5 ±6 TTL 16 50 pF 100 -40 to +125

74LV4060 14-stage binary ripple counter with oscillator 1.0 to 5.5 ±6 TTL 29 50 pF 100 -40 to +125
Presettable synchronous 4-bit binary counter; CMOS/
74LVC161 1.2 to 3.6 ±24 4.9 50 pF 200 -40 to +125
asynchronous reset LVTTL
Presettable synchronous 4-bit binary counter; CMOS/
74LVC163 1.2 to 3.6 ±24 4.9 50 pF 200 -40 to +125
synchronous reset LVTTL
HEF4017 Johnson decade counter with 10 decoded outputs 4.5 to 15 ±2.4 CMOS 40 50 pF 30 -40 to +85
Presettable synchronous 4-bit binary up/down counter;
HEF40193 4.5 to 15.5 ±2.4 CMOS 60 50 pF 18 -40 to +85
separate up/down clocks
HEF4020 14-stage binary ripple counter 4.5 to 15.5 ±2.4 CMOS 35 50 pF 35 -40 to +85

HEF4024 7-stage binary ripple counter 4.5 to 15.5 ±2.4 CMOS 30 50 pF 35 -40 to +85

HEF4040 12-stage binary ripple counter 4.5 to 15.5 ±2.4 CMOS 35 50 pF 50 -40 to +85

HEF4059 Programmable divide-by-n counter 4.5 to 15.5 -7/+20 CMOS 40 50 pF 20 -40 to +85

HEF4060 14-stage binary ripple counter with oscillator 4.5 to 15.5 ±2.4 CMOS 50 50 pF 30 -40 to +85

HEF4516 Presettable synchronous 4-bit binary up/down counter 4.5 to 15.5 ±2.4 CMOS 45 50 pF 18 -40 to +85

HEF4518 Dual BCD counter 4.5 to 15 ±2.4 CMOS 40 50 pF 40 -40 to +85

HEF4520 Dual 4-bit synchronous binary counter 4.5 to 15.5 ±2.4 CMOS 15 50 pF 40 -40 to +85

HEF4521 24-stage frequency divider and oscillator 4.5-15.5 V ±2.4 CMOS 220 50 pF 35 -40 to +85

HEF4526 Programmable 4-bit binary down counter 4.5 to 15.5 ±2.4 CMOS 50 50 pF 32 -40 to +85

HEF4541 Programmable timer 4.5 to 15.5 - 4/ + 2.7 CMOS 38 50 pF 150 -40 to +85

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 77

DECODERS/DEMULTIPLEXERS
4 
Optional overvoltage-tolerant inputs, inverting and non-
Features and benefits inverting outputs, and 3-stage outputs
4  Multiple input enable for easy expansion, independent
controls Applications
4  Integrated input latch for storing decoder-line addresses 4 Selection of memory banks and peripherals
4  A synchronous and synchronous load options 4 I/O expansion
4  Can be cascaded 4 
Memory addressing in automotive (display clusters, GPS,
4 High frequency keyless entry)
4 
Bus-width reduction

Decoders demultiplexers (cont.)

Output
Logic Output
Type drive tpd
Description VCC (V) switching Load Tamb (°C)
number capability (ns)
levels CL (Typ)
(mA)

74AHC138 3-to-8 line decoder/demultiplexer; inverting 2.0 to 5.5 CMOS ±8 4.4 50 pF -40 to +125

74AHCT138 3-to-8 line decoder/demultiplexer; inverting; TTL-enabled 4.5 to 5.5 TTL ±8 4.4 50 pF -40 to +125

74AHC139 Dual 2-to-4 line decoder/demultiplexer 2.0 to 5.5 CMOS ±8 3.9 50 pF -40 to +125

74AHCT139 Dual 2-to-4 line decoder/demultiplexer; TTL-enabled 4.5 to 5.5 TTL ±8 3.6 50 pF -40 to +125

74AUP1G18 1-to-2 demultiplexer (3-state) 1.1 to 3.6 CMOS 1.9/-1.9 3.2 30 pF -40 to +125

74AUP1G19 1-to-2 decoder/demultiplexer 1.1 to 3.6 CMOS 1.9/-1.9 3 30 pF -40 to +125

74HC138 3-to-8 line decoder/demultiplexer; inverting 2.0 to 6.0 CMOS ±5.2 12 50 pF -40 to +125

74HCT138 3-to-8 line decoder/demultiplexer; inverting; TTL-enabled 4.5 to 5.5 TTL ±4 19 50 pF -40 to +125

74HC139 Dual 2-to-4 line decoder/demultiplexer 2.0 to 6.0 CMOS ±5.2 14 50 pF -40 to +125

74HCT139 Dual 2-to-4 line decoder/demultiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 16 50 pF -40 to +125

74HC154 4-to-16 line decoder/demultiplexer 2.0 to 6.0 CMOS ±5.2 11 50 pF -40 to +125

74HCT154 4-to-16 line decoder/demultiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 13 50 pF -40 to +125

74HC238 3-to-8 decoder/demultiplexer 2.0 to 6.0 CMOS ±5.2 14 50 pF -40 to +125

74HCT238 3-to-8 decoder/demultiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 18 50 pF -40 to +125

74HC42 BCD to decimal decoder (1-of-10) 2.0 to 6.0 CMOS ±5.2 17 50 pF -40 to +125

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

78 NXP Logic selection guide 2016

Decoders demultiplexers (cont.)
Output
Logic Output
Type drive tpd
Description VCC (V) switching Load Tamb (°C)
number capability (ns)
levels CL (Typ)
(mA)

74HCT42 BCD to decimal decoder (1-of-10); TTL-enabled 4.5 to 5.5 TTL ±4 20 50 pF -40 to +125

BCD to 7-segment latch/decoder/driver with lamp test

74HC4511 2.0 to 6.0 CMOS -10 28 50 pF -40 to +125
input

BCD to 7-segment latch/decoder/driver with lamp test

74HCT4511 4.5 to 5.5 TTL -10 28 50 pF -40 to +125
input; TTL-enabled

74HC4514 4-to-16 decoder/demultiplexer with address latches 2.0 to 6.0 CMOS ±5.2 27 50 pF -40 to +125

4-to-16 decoder/demultiplexer with address latches;

74HCT4514 4.5 to 5.5 TTL ±4 30 50 pF -40 to +125
TTL-enabled

4-to-16 decoder/demultiplexer with address latches;

74HC4515 2.0 to 6.0 CMOS ±5.2 29 50 pF -40 to +125
inverting

4-to-16 decoder/demultiplexer with address latches;

74HCT4515 4.5 to 5.5 TTL ±4 30 50 pF -40 to +125
inverting; TTL-enabled

3-to-8 line decoder/demultiplexer with address latches;

74HC137 2.0 to 6.0 CMOS ±5.2 18 50 pF -40 to +125
inverting

74HC237 3-to-8 decoder/demultiplexer with address latches 2.0 to 6.0 CMOS ±5.2 18 50 pF -40 to +125

74LV138 3-to-8 line decoder/demultiplexer; inverting 1.0 to 5.5 TTL ±12 12 50 pF -40 to +125

CMOS/
74LVC138 3-to-8 line decoder/demultiplexer; inverting 1.2 to 3.6 ±24 2.7 50 pF -40 to +125
LVTTL

74LV139 Dual 2-to-4 line decoder/demultiplexer 1.0 to 5.5 TTL ±12 11 50 pF -40 to +125

CMOS/
74LVC139 Dual 2-to-4 line decoder/demultiplexer 1.2 to 3.6 ±24 2.5 50 pF -40 to +125
LVTTL

CMOS/
74LVC1G18 1-to-2 demultiplexer (3-state) 1.65 to 5.5 ±32 2.3 50 pF -40 to +125
LVTTL

HEF4028 1-of-10 decoder 4.5 to 15 CMOS ±2.4 30 50 pF -40 to +85

BCD to 7-segment latch/decoder/driver with lamp test

HEF4511 4.5 to 15 CMOS -25/2.4 40 50 pF -40 to +85
input

HEF4514 4-to-16 decoder/demultiplexer with address latches 4.5 to 15 CMOS ±2.4 65 50 pF -40 to +85

HEF4543 BCD to 7-segment latch/decoder/driver with phase input 4.5 to 15 CMOS ±2.4 55 50 pF -40 to +85

HEF4555 Dual 1-to-4 line decoder/demultiplexer 4.5 to 15 CMOS ±2.4 30 50 pF -40 to +85

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 79

DIGITAL COMPARATORS
Features and benefits Applications
4 Magnitude comparison of any binary words 4 Process controllers
4 Serial or parallel expansion without extra gating 4 Servo-motor control
4 Low-power CMOS
4 CMOS or TTL inputs

Digital comparators
Output
Logic Output
drive tpd Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) of bits
levels CL (Typ)
(mA)
74HC688 8-bit magnitude comparator 2.0 to 6.0 CMOS ±5.2 17 50 pF 8 -40 to +125

74HCT688 8-bit magnitude comparator; TTL-enabled 4.5 to 5.5 TTL ±4.0 17 50 pF 8 -40 to +125

74HC85 4-bit magnitude comparator 2.0 to 6.0 CMOS ±5.2 23 50 pF 4 -40 to +125

74HCT85 4-bit magnitude comparator; TTL-enabled 4.5 to 5.5 TTL ±4.0 26 50 pF 4 -40 to +125

HEF4585 4-bit magnitude comparator 4.5 to 15.5 CMOS ±2.4 65 50 pF 4 -40 to +85

DIGITAL MULTIPLEXERS
Features and benefits Applications
4 Mixed 3.3/5 V applications 4 Power windows, power locks, power mirror control
4 Bus-width reduction 4 Advanced diagnostics and engine control modules
4 High noise immunity 4 Industrial control systems
4 Low power consumption 4 Decision-making via voltage sensing in portable
4 Wide range of supply voltages electronics
4 Low propagation delay 4 I/O expansion
4 
Optional overvoltage-tolerant inputs, complementary
outputs

Digital multiplexers (cont.)

Output
Logic Output
drive tpd
Type number Description VCC (V) switching Load CL Tamb (°C)
capability (ns)
levels (Typ)
(mA)

74AHC157 Quad 2-input multiplexer 2.0 to 5.5 CMOS ±8 50 pF 3.2

74AHCT157 Quad 2-input multiplexer; TTL-enabled 4.5 to 5.5 TTL ±8 50 pF 3.2 -40 to +125

74AHC257 Quad 2-input multiplexer (3-state) 2.0 to 5.5 CMOS ±8 50 pF 2.9 -40 to +125

74AHCT257 Quad 2-input multiplexer; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 50 pF 3.7 -40 to +125

74AUP1G157 Single 2-input multiplexer 1.1 to 3.6 CMOS 1.9/-1.9 30 pF 3.2 -40 to +125

74AUP1G158 Single 2-input multiplexer; inverting 1.1 to 3.6 CMOS 1.9/-1.9 30 pF 3.2 -40 to +125

74AUP2G157 Single 2-input multiplexer 1.1 to 3.6 CMOS 1.9/-1.9 30 pF 3.4 -40 to +125

74HC151 8-input multiplexer 2.0 to 6.0 CMOS ±5.2 50 pF 17 -40 to +125

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

80 NXP Logic selection guide 2016

Digital multiplexers (cont.)
Output
Logic Output
drive tpd
Type number Description VCC (V) switching Load CL Tamb (°C)
capability (ns)
levels (Typ)
(mA)

74HCT151 8-input multiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 50 pF 19 -40 to +125

74HC153 Dual 4-input multiplexer 2.0 to 6.0 CMOS ±5.2 50 pF 17 -40 to +125

74HCT153 Dual 4-input multiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 50 pF 19 -40 to +125

74HC157 Quad 2-input multiplexer 2.0 to 6.0 CMOS ±5.2 50 pF 11 -40 to +125

74HCT157 Quad 2-input multiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 50 pF 13 -40 to +125

74HC251 8-input multiplexer (3-state) 2.0 to 6.0 CMOS ±5.2 50 pF 18 -40 to +125

74HCT251 8-input multiplexer; TTL-enabled (3-state) 4.5 to 5.5 TTL ±4 50 pF 22 -40 to +125

74HC253 Dual 4-input multiplexer (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 17 -40 to +125

74HCT253 Dual 4-input multiplexer; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 17 -40 to +125

74HC257 Quad 2-input multiplexer (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 11 -40 to +125

74HCT257 Quad 2-input multiplexer; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 13 -40 to +125

74HC158 Quad 2-input multiplexer; inverting 2.0 to 6.0 CMOS ±5.2 50 pF 12 -40 to +125

74LV153 Dual 4-input multiplexer 1.0 to 3.6 TTL ±6 50 pF 14 -40 to +125

74LV251 8-input multiplexer (3-state) 1.0 to 3.6 TTL ±6 50 pF 17 -40 to +125

CMOS/
74LVC157 Quad 2-input multiplexer 1.2 to 3.6 ±24 50 pF 2,5 -40 to +125
LVTTL

1.65 to CMOS/
74LVC1G157 Single 2-input multiplexer ±32 50 pF 2,2 -40 to +125
5.5 LVTTL

CMOS/
74LVC257 Quad 2-input multiplexer (3-state) 1.2 to 3.6 ±24 50 pF 2,4 -40 to +125
LVTTL

ENCODERS
Features and benefits 4 LED, LCD, incandescent, fluorescent, or gas-discharge
4 Encode 10-line decimal to 4-line BCD displays
Standard output capability
4  4 10-position switch encoding
Applications
4  4 Code converters, generators

Encoders
Output
Logic
Type drive tpd Number Package
Description VCC (V) switching Tamb (°C)
number capability (ns) of bits name
levels
(mA)
74HCT147 10-to-4 line priority encoder; TTL-enabled 4.5 to 5.5 TTL ±4 17 10 -40 to +125 SOT109-1

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 81

FIFO REGISTERS
Features and benefits Applications
4 Wide range of supply voltages Data buffers
4 
4 
Independent asynchronous and synchronous inputs and
outputs
Cascadable
4 
Optional TTL inputs, 3-state outputs
4 

FIFO registers
Output
Logic Output
drive tpd fmax
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz)
levels CL (Typ)
(mA)

74HC40105 4-bit x 16-word FIFO register 2.0 to 6.0 CMOS Low 15 50 pF 30 -40 to +125

74HCT40105 4-bit x 16-word FIFO register; TTL-enabled 4.5 to 5.5 TTL ±4 mA 18 50 pF 28 -40 to +125

74HC7030 9-bit x 64-word FIFO register (3-state) 2.0 to 6.0 CMOS ±5.2 mA 36 50 pF 33 -40 to +125

74HCT7030 9-bit x 64-word FIFO register; TTL-enabled (3-state) 4.5 to 5.5 TTL ±4 mA 26 50 pF 29 -40 to +125

74HC7403 4-bit x 16-word FIFO register (3-state) 2.0 to 6.0 CMOS ±5.2 mA 15 50 pF 30 -40 to +125

74HCT7403 4-bit x 16-word FIFO register; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 mA 17 50 pF 30 -40 to +125

FLIP-FLOPS
Features and benefits 4 
Optional overvoltage-tolerant inputs, integrated source-
4 Mixed 3.3/5 V applications termination resistors, bus hold
4 Improved signal integrity with integrated termination
resistors Applications
4 Flow-through pinout for easy layout Frequency division
4 
4 Wide range of supply voltage Controlled delays
4 
4 Low propagation delay Interface between asynchronous and synchronous systems
4 

Flip-flops (cont.)
Output
Logic Output
drive tpd fmax
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz)
levels CL (Typ)
(mA)
74AHC1G79 Single D-type flip-flop; positive-edge trigger 2.0 to 5.5 CMOS ±8 3,5 50 pF 90 -40 to +125
Single D-type flip-flop; positive-edge trigger;
74AHCT1G79 4.5 to 5.5 TTL ±8 3,5 50 pF 90 -40 to +125
TTL-enabled
Octal D-type flip-flop with reset; positive-edge
74AHC273 2.0 to 5.5 CMOS ±8 4,2 50 pF 165 -40 to +125
trigger
Octal D-type flip-flop with reset; positive-edge
74AHCT273 4.5 to 5.5 TTL ±8 4 50 pF 120 -40 to +125
trigger; TTL-enabled

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

82 NXP Logic selection guide 2016

Flip-flops (cont.)
Output
Logic Output
drive tpd fmax
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz)
levels CL (Typ)
(mA)
Octal D-type flip-flop; positive-edge trigger
74AHC374 2.0 to 5.5 CMOS ±8 4,4 50 pF 185 -40 to +125
(3-state)
Octal D-type flip-flop; positive-edge trigger
74AHCT374 4.5 to 5.5 TTL ±8 4,3 50 pF 140 -40 to +125
(3-state)
Octal D-type flip-flop with data enable; positive-
74AHC377 2.0 to 5.5 CMOS ±8 3,9 50 pF 175 -40 to +125
edge trigger
Octal D-type flip-flop with data enable; positive-
74AHCT377 4.5 to 5.5 TTL ±8 4 50 pF 140 -40 to +125
edge trigger; TTL-enabled
Octal D-type flip-flop; positive-edge trigger
74AHC574 2.0 to 5.5 CMOS ±8 4,4 50 pF 130 -40 to +125
(3-state)
Octal D-type flip-flop; positive-edge trigger;
74AHCT574 4.5 to 5.5 TTL ±8 4,4 50 pF 130 -40 to +125
TTL-enabled (3-state)
Dual D-type flip-flop with set and reset; positive-
74AHC74 2.0 to 5.5 CMOS ±8 3,7 50 pF 170 -40 to +125
edge trigger
Dual D-type flip-flop with set and reset; positive-
74AHCT74 4.5 to 5.5 TTL ±8 3,3 50 pF 160 -40 to +125
edge trigger; TTL-enabled
Octal D-type flip-flop; positive-edge trigger
74ALVC374 1.65 to 3.6 TTL ±24 2,5 50 pF 300 -40 to +85
(3-state)
Octal D-type flip-flop; positive-edge trigger
74ALVC574 1.65 to 3.6 TTL ±24 2,5 50 pF 300 -40 to +85
(3-state)
Dual D-type flip-flop with set and reset; positive-
74ALVC74 1.65 to 3.6 TTL ±24 2,3 50 pF 425 -40 to +85
edge trigger
16-bit D-type flip-flop with bus hold; positive-
74ALVCH16374 1.2 to 3.6 TTL ±24 2,3 50 pF 350 -40 to +85
edge trigger (3-state)
20-bit D-type flip-flop; positive-edge trigger
74ALVCH16821 2.3 to 3.6 TTL ±24 2,5 50 pF 350 -40 to +85
(3-state)
18-bit D-type flip-flop with bus hold; positive-
74ALVCH16823 1.2 to 3.6 TTL ±24 2,1 50 pF 350 -40 to +85
edge trigger (3-state)
20-bit D-type flip-flop; positive-edge trigger
74ALVT162821 2.3 to 3.6 TTL ±12 3,2 50 pF 150 -40 to +85
(3-state)
18-bit buffer/line driver with bus hold and 30 Ω
74ALVT162823 2.3 to 3.6 TTL ±12 3 50 pF 150 -40 to +85
termination resistors (3-state)
16-bit D-type flip-flop with bus hold; positive-
74ALVT16374 2.3 to 3.6 TTL -32/+64 2,3 50 pF 250 -40 to +85
edge trigger (3-state)
20-bit D-type flip-flop; positive-edge trigger
74ALVT16821 2.3 to 3.6 TTL -32/+64 1,8 50 pF 150 -40 to +85
(3-state)
18-bit D-type flip-flop with bus hold; positive-
74ALVT16823 2.3 to 3.6 TTL -32/+64 1,9 50 pF 250 -40 to +85
edge trigger (3-state)
Single D flip-flop with reset; positive-edge
74AUP1G175 1.1 to 3.6 CMOS ±1.9 7,4 30 pF 70 -40 to +125
trigger
Single D-type flip-flop; positive-edge trigger
74AUP1G374 1.1 to 3.6 CMOS ±1.9 7,9 30 pF 400 -40 to +125
(3-state)
Single D-type flip-flop with set and reset;
74AUP1G74 1.1 to 3.6 CMOS ±1.9 9,2 30 pF 400 -40 to +125
positive-edge trigger
74AUP1G79 Single D-type flip-flop; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 9,1 30 pF 400 -40 to +125
74AUP1G80 Single D-type flip-flop; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 9,1 30 pF 400 -40 to +125
74AUP2G79 Dual D-type flip-flop; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 8,5 30 pF 400 -40 to +125
74AUP2G80 Dual D-type flip-flop; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 9,1 30 pF 400 -40 to +125
16-bit D-type flip-flop; positive-edge trigger
74AVC16374 1.2 to 3.6 CMOS ±12 1,5 30 pF 350 -40 to +85
(3-state)

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 83

Flip-flops (cont.)
Output
Logic Output
drive tpd fmax
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz)
levels CL (Typ)
(mA)
Dual JK-type flip-flop with reset; negative-edge
74HC107 2.0 to 6.0 CMOS ±5.2 16 50 pF 78 -40 to +125
trigger
Dual JK-type flip-flop with reset; negative-edge
74HCT107 4.5 to 5.5 TTL ±4 16 50 pF 73 -40 to +125
trigger; TTL-enabled
Dual JK-type flip-flop with set and reset;
74HC109 2.0 to 6.0 CMOS ±5.2 15 50 pF 75 -40 to +125
positive-edge trigger
Dual JK-type flip-flop with set and reset;
74HCT109 4.5 to 5.5 TTL ±4 17 50 pF 61 -40 to +125
positive-edge trigger; TTL-enabled
Dual JK-type flip-flop with set and reset;
74HC112 2.0 to 6.0 CMOS ±5.2 15 50 pF 66 -40 to +125
negative-edge trigger
Dual JK-type flip-flop with set and reset;
74HCT112 4.5 to 5.5 TTL ±4 19 50 pF 70 -40 to +125
negative-edge trigger; TTL-enabled
Quad D-type flip-flop; positive-edge trigger
74HC173 2.0 to 6.0 CMOS ±7.8 17 50 pF 88 -40 to +125
(3-state)
Quad D-type flip-flop; positive-edge trigger;
74HCT173 4.5 to 5.5 TTL ±6 17 50 pF 88 -40 to +125
TTL-enabled (3-state)
Hex D-type flip-flop with reset; positive-edge
74HC174 2.0 to 6.0 CMOS ±5.2 17 50 pF 99 -40 to +125
trigger
Hex D-type flip-flop with reset; positive-edge
74HCT174 4.5 to 5.5 TTL ±4 18 50 pF 69 -40 to +125
trigger; TTL-enabled
Quad D-type flip-flop with reset; positive-edge
74HC175 2.0 to 6.0 CMOS ±5.2 17 50 pF 83 -40 to +125
trigger
Quad D-type flip-flop with reset; positive-edge
74HCT175 4.5 to 5.5 TTL ±4 16 50 pF 54 -40 to +125
trigger; TTL-enabled
Octal D-type flip-flop with reset; positive-edge
74HC273 2.0 to 6.0 CMOS ±5.2 15 50 pF 122 -40 to +125
trigger
Octal D-type flip-flop with reset; positive-edge
74HCT273 4.5 to 5.5 TTL ±4 15 50 pF 36 -40 to +125
trigger; TTL-enabled
Octal D-type flip-flop; positive-edge trigger
74HC374 2.0 to 6.0 CMOS ±7.8 14 50 pF 83 -40 to +125
(3-state)
Octal D-type flip-flop; positive-edge trigger;
74HCT374 4.5 to 5.5 TTL ±6 13 50 pF 48 -40 to +125
TTL-enabled (3-state)
Octal D-type flip-flop with data enable; positive-
74HC377 2.0 to 6.0 CMOS ±7.8 13 50 pF 83 -40 to +125
edge trigger
Octal D-type flip-flop with data enable; positive-
74HCT377 4.5 to 5.5 TTL ±6 14 50 pF 53 -40 to +125
edge trigger; TTL-enabled
Octal D-type flip-flop; positive-edge trigger
74HC574 2.0 to 6.0 CMOS ±7.8 14 50 pF 133 -40 to +125
(3-state)
Octal D-type flip-flop; positive-edge trigger;
74HCT574 4.5 to 5.5 TTL ±6 15 50 pF 76 -40 to +125
TTL-enabled (3-state)
Dual D-type flip-flop with set and reset; positive-
74HC74 2.0 to 6.0 CMOS ±5.2 14 50 pF 82 -40 to +125
edge trigger
Dual D-type flip-flop with set and reset; positive-
74HCT74 4.5 to 5.5 TTL ±4 15 50 pF 59 -40 to +125
edge trigger; TTL-enabled
Dual JK-type flip-flop with reset; negative-edge
74HC73 2.0 to 6.0 CMOS ±5.2 16 50 pF 77 -40 to +125
trigger
Octal D-type flip-flop; inverting; positive-edge
74HCT534 4.5 to 5.5 TTL ±6 13 50 pF 40 -40 to +125
trigger; TTL-enabled (3-state)
Octal D-type flip-flop with reset; positive edge-
74HCT7273 4.5 to 5.5 TTL 4 16 50 pF 56 -40 to +125
trigger; open drain outputs; TTL-enabled

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

84 NXP Logic selection guide 2016

Flip-flops (cont.)
Output
Logic Output
drive tpd fmax
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz)
levels CL (Typ)
(mA)
Hex D-type flip-flop with reset; positive-edge
74LV174 1.0 to 5.5 TTL ±12 16 50 pF 77 -40 to +125
trigger
Octal D-type flip-flop with reset; positive-edge
74LV273 1.0 to 5.5 TTL ±12 12 50 pF 110 -40 to +125
trigger
Octal D-type flip-flop; positive-edge trigger
74LV374 1.0 to 5.5 TTL ±16 14 50 pF 77 -40 to +125
(3-state)
Octal D-type flip-flop with data enable; positive-
74LV377 1.0 to 3.6 TTL ±6 13 50 pF 77 -40 to +125
edge trigger
Octal D-type flip-flop; positive-edge trigger
74LV574 1.0 to 5.5 TTL ±16 13 50 pF 77 -40 to +125
(3-state)
Dual D-type flip-flop with set and reset; positive-
74LV74 1.0 to 5.5 TTL ±12 11 50 pF 75 -40 to +125
edge trigger
16-bit D-type flip-flop; positive-edge trigger CMOS/
74LVC16374 1.2 to 3.6 ±24 3,8 50 pF 150 -40 to +125
(3-state) LVTTL
16-bit D-type flip-flop with bus hold; positive- CMOS/
74LVCH16374 1.2 to 3.6 ±24 3,8 50 pF 150 -40 to +125
edge trigger (3-state) LVTTL
Dual JK-type flip-flop with set and reset; CMOS/
74LVC109 1.2 to 3.6 ±24 4 50 pF 330 -40 to +125
positive-edge trigger LVTTL
Single D flip-flop with reset; positive-edge CMOS/
74LVC1G175 1.65 to 5.5 ±32 3,1 50 pF 300 -40 to +125
trigger LVTTL
Single D-type flip-flop with set and reset; CMOS/
74LVC1G74 1.65 to 5.5 ±32 3,5 50 pF 280 -40 to +125
positive-edge trigger LVTTL
CMOS/
74LVC1G79 Single D-type flip-flop; positive-edge trigger 1.65 to 5.5 ±32 2,2 50 pF 450 -40 to +125
LVTTL
CMOS/
74LVC1G80 Single D-type flip-flop; positive-edge trigger 1.65 to 5.5 ±32 2,4 50 pF 450 -40 to +125
LVTTL
Octal D-type flip-flop with reset; positive-edge CMOS/
74LVC273 1.2 to 3.6 ±24 6 50 pF 230 -40 to +125
trigger LVTTL
Single D-type flip-flop with set and reset; CMOS/
74LVC2G74 1.65 to 5.5 ±32 3,5 50 pF 280 -40 to +125
positive-edge trigger LVTTL
Octal D-type flip-flop; positive-edge trigger CMOS/
74LVC374 1.2 to 3.6 ±24 2,7 50 pF 100 -40 to +125
(3-state) LVTTL
Octal D-type flip-flop with data enable; positive- CMOS/
74LVC377 1.2 to 3.6 ±24 6 50 pF 230 -40 to +125
edge trigger LVTTL
Octal D-type flip-flop; positive-edge trigger CMOS/
74LVC574 1.2 to 3.6 ±24 3,2 50 pF 150 -40 to +125
(3-state) LVTTL
Dual D-type flip-flop with set and reset; positive- CMOS/
74LVC74 1.2 to 3.6 ±24 2,5 50 pF 250 -40 to +125
edge trigger LVTTL
10-bit D-type flip-flop; positive-edge trigger CMOS/
74LVC821 1.2 to 3.6 ±24 5,4 50 pF 150 -40 to +125
(3-state) LVTTL
9-bit D-type flip-flop; positive-edge trigger CMOS/
74LVC823 1.2 to 3.6 ±24 5,4 50 pF 150 -40 to +125
(3-state) LVTTL
16-bit D-type flip-flop with bus hold and
CMOS/
74LVCH162374 30 Ω termination resistors; positive-edge trigger 1.2 to 3.6 ±24 3,8 50 pF 150 -40 to +125
LVTTL
(3-state)
32-bit D-type flip-flop with bus hold; positive- CMOS/
74LVCH32374 1.2 to 3.6 ±24 3,8 50 pF 150 -40 to +125
edge trigger (3-state) LVTTL
16-bit D-type flip-flop with bus hold; positive-
74LVT16374 2.7 to 3.6 TTL -32/+64 3 50 pF 150 -40 to +85
edge trigger (3-state)
16-bit D-type flip-flop with bus hold; positive-
74LVTH16374 2.7 to 3.6 TTL -32/+64 3 50 pF 150 -40 to +85
edge trigger (3-state)

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 85

Flip-flops (cont.)
Output
Logic Output
drive tpd fmax
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz)
levels CL (Typ)
(mA)
Octal D-type flip-flop; positive-edge trigger
74LVT574 2.7 to 3.6 TTL -32/+64 4,3 50 pF 150 -40 to +85
(3-state)
Octal D-type flip-flop; positive-edge trigger
74LVTH57 2.7 to 3.6 TTL -32/+64 4,3 50 pF 150 -40 to +85
(3-state)
Octal D-type flip-flop; positive-edge trigger
74LVTH574 2.7 to 3.6 TTL -32/+64 4,3 50 pF 150 -40 to +85
(3-state)
16-bit D-type flip-flop with bus hold and
74LVT162374 30 Ω termination resistors; positive-edge trigger 2.7 to 3.6 TTL ±12 3 50 pF 150 -40 to +85
(3-state)
Octal D-type flip-flop with reset; positive-edge
74LVT273 2.7 to 3.6 TTL -32/+64 3,5 50 pF 150 -40 to +85
trigger
32-bit D-type flip-flop with bus hold and
74LVT32374 30 Ω termination resistors; positive-edge trigger 2.7 to 3.6 TTL -32/+64 3 50 pF 150 -40 to +85
(3-state)
74LVT373 Octal D-type transparent latch (3-state) 2.7 to 3.6 TTL -32/+64 3 50 pF -40 to +85
Octal D-type flip-flop; positive-edge trigger
74LVT374 2.7 to 3.6 TTL -32/+64 3,5 50 pF 200 -40 to +85
(3-state)
Octal D-type flip-flop; inverting; positive-edge
74LVT534 2.7 to 3.6 TTL -32/+64 3,5 50 pF 150 -40 to +85
trigger (3-state)
Dual D-type flip-flop with set and reset; positive-
74LVT74 2.7 to 3.6 TTL -20/+32 3,6 50 pF 345 -40 to +85
edge trigger
Dual D-type flip-flop with set and reset; positive-
HEF4013 4.5 to 15.5 CMOS ±2.4 30 50 pF 40 -40 to +85
edge trigger
Hex D-type flip-flop with reset; positive-edge
HEF40174 4.5 to 15.5 CMOS ±2.4 20 50 pF 45 -40 to +85
trigger
Quad D-type flip-flop with reset; positive-edge
HEF40175 4.5 to 15.5 CMOS ±2.4 25 50 pF 45 -40 to +85
trigger
HEF4027 Dual JK-type flip-flop 4.5 to 15.5 CMOS ±2.4 30 50 pF 30 -40 to +85
Octal D-type flip-flop; positive-edge trigger
HEF40374 4.5 to 15.5 CMOS -50/+62 40 50 pF 17 -40 to +85
(3-state)

FULL ADDERS
Features and benefits Applications
4 Cascadable High-speed 4-bit binary addition
4 
4 Low power dissipation
4 Positive or negative logic
4 Wide range of supply voltages

Full adders
Output Output
Logic
drive drive Number
Type number Description VCC (V) switching tpd (ns) Tamb (°C)
capability capability of bits
levels
(mA) (mA)

74HC283 4-bit binary full adder with fast carry 2.0 to 6.0 CMOS ±5.2 21 50 pF 4 -40 to +125

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

86 NXP Logic selection guide 2016

GATES
This section includes AND gates, combination gates (one 4  Low-power CMOS
package, two or more different functions), configurable 4  Optional overvoltage-tolerant inputs, low input threshold
multi-function gates (one package, nine or more functions), 4 Comprehensive range: AND, EXCLUSIVE-NOR,
EXCLUSIVE-NOR gates, EXCLUSIVE-OR gates, NOR gates, EXCLUSIVE-OR, NAND, NOR, OR
and OR gates. 4 
Combination gates and configurable multi-function gates
for lower pincount, device count, system cost, assembly-
Features and benefits related expenses
4 Mixed 3.3/5 V applications
4 Reduced time-to-market for complex designs Applications
4 Reduced board space 4 Control/glue logic
4 Improved signal integrity in complex layouts 4 PCB miniaturization
4 Wide range of supply voltages 4 Routing simplification
4 Low propagation delay 4 Discrete replacement

Gates - AND (cont.)

Output
Logic Output
drive tpd fmax Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ)
(mA)
74AHC08 Quad 2-input AND gate 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 4 -40 to +125
74AHC1G08 Single 2-input AND gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125
Single 2-input AND gate;
74AHC1G09 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125
open drain
74AHC2G08 Dual 2-input AND gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 2 -40 to +125
Quad 2-input AND gate;
74AHCT08 4.5 to 5.5 TTL ±8 5 50 pF 60 4 -40 to +125
TTL-enabled
Single 2-input AND gate;
74AHCT1G08 4.5 to 5.5 TTL ±8 3.6 50 pF 60 1 -40 to +125
TTL-enabled
Dual 2-Input AND gate;
74AHCT2G08 4.5 to 5.5 TTL ±8 3.6 50 pF 60 2 -40 to +125
TTL-enabled
74ALVC08 Quad 2-input AND gate 1.65 to 3.6 TTL ±24 2 50 pF 145 4 -40 to +85
74AUP1G08 Single 2-input AND gate 1.1 to 3.6 CMOS ±1.9 8.2 30 pF 70 1 -40 to +125
Single 2-input AND gate;
74AUP1G09 1.1 to 3.6 CMOS 1,9 8.5 30 pF 70 1 -40 to +125
open drain
74AUP1G11 Single 3-input AND gate 1.1 to 3.6 CMOS ±1.9 6.9 30 pF 70 1 -40 to +125
74AUP2G08 Dual 2-input AND gate 1.1 to 3.6 CMOS ±1.9 8.2 30 pF 70 2 -40 to +125
74AXP1G08 Single 2-input AND gate 0.7 to 2.75 CMOS ±4.5 2.6 5pF 70 1 -40 to +85
74HC08 Quad 2-input AND gate 2.0 to 6.0 CMOS ±5.2 7 50 pF 36 4 -40 to +125
74HC11 Triple 3-input AND gate 2.0 to 6.0 CMOS ±5.2 10 50 pF 36 3 -40 to +125
74HC1G08 Single 2-input AND gate 2.0 to 6.0 CMOS ±5.2 7 50 pF 36 1 -40 to +125
74HC21 Dual 4-input AND gate 2.0 to 6.0 CMOS ±5.2 10 50 pF 36 2 -40 to +125
74HC2G08 Dual 2-input AND gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 -40 to +125
Quad 2-input AND gate;
74HCT08 4.5 to 5.5 TTL ±4 11 50 pF 36 4 -40 to +125
TTL-enabled
74HCT11 Triple 3-input AND gate 4.5 to 5.5 TTL ±4 11 50 pF 36 3 -40 to +125
Single 2-input AND gate;
74HCT1G08 4.5 to 5.5 TTL ±2 11 50 pF 36 1 -40 to +125
TTL-enabled
Single 2-input AND gate;
74HCT1G08 4.5 to 5.5 TTL ±2 11 50 pF 36 1 -40 to +125
TTL-enabled

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 87

Gates - AND (cont.)
Output
Logic Output
drive tpd fmax Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ)
(mA)
Dual 2-Input AND gate;
74HCT2G08 4.5 to 5.5 TTL ±4 14 50 pF 36 2 -40 to +125
TTL-enabled
74LV08 Quad 2-input AND gate 1.0 to 5.5 TTL ±12 7 50 pF 30 4 -40 to +125
74LVC08 Quad 2-input AND gate 1.2 to 3.6 TTL ±24 2.1 50 pF 150 4 -40 to +125
74LVC11 Triple 3-input AND gate 1.2 to 3.6 TTL ±24 3.7 50 pF 150 3 -40 to +125
CMOS /
74LVC1G08 Single 2-input AND gate 1.65 to 5.5 ±24 2.1 50 pF 150 1 -40 to +125
LVTTL
CMOS /
74LVC1G11 Single 3-input AND gate 1.65 to 5.5 ±24 2.6 50 pF 150 1 -40 to +125
LVTTL
CMOS /
74LVC2G08 Dual 2-input AND gate 1.65 to 5.5 ±24 2.1 50 pF 150 2 -40 to +125
LVTTL
74LVT08 Quad 2-input AND gate 2.7 to 3.6 TTL -32/+64 3.4 50 pF 150 4 -40 to +85
74VHC08 Quad 2-input AND gate 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 4 -40 to +125
Quad 2-input AND gate;
74VHCT08 4.5 to 5.5 TTL ±8 5 50 pF 60 4 -40 to +125
TTL-enabled
HEF4073 Triple 3-input AND gate 4.5 to 15.5 CMOS ±2.4 20 50 pF 10 3 -40 to +85
HEF4081 Quad 2-input AND gate 4.5 to 15.5 CMOS ±2.4 20 50 pF 10 4 -40 to +85
HEF4082 Dual 4-input AND gate 4.5 to 15.5 CMOS ±2.4 25 50 pF 10 2 -40 to +85
Single 2-input AND gate;
XC7SET08 4.5 to 5.5 TTL ±8 3.6 50 pF 60 1 -40 to +125
TTL-enabled
XC7SH08 Single 2-input AND gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125

Gates - Combination
Output
Logic Output
drive tpd fmax Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ)
(mA)
74AUP1G0832 Single 3-input AND-OR gate 1.1 to 3.6 CMOS ±1.9 6.7 30 pF 70 1 -40 to +125

74AUP1G3208 Single 3-input OR-AND gate 1.1 to 3.6 CMOS ±1.9 7.4 30 pF 70 1 -40 to +125

74AUP1G885 Dual function gate 1.1 to 3.6 CMOS ±1.9 7.6 30 pF 70 1 -40 to +125
Crystal driver with enable and
74AUP1Z04 1.1 to 3.6 CMOS ±1.9 5.6 30 pF 70 1 -40 to +125
internal resistor
Crystal driver with enable and
74AUP1Z125 1.1 to 3.6 CMOS ±1.9 4.7 30 pF 70 1 -40 to +125
internal resistor (3-state)
Inverter with open drain and
74AUP2G0604 1.1 to 3.6 CMOS ±1.9 4 30 pF 70 2 -40 to +125
inverter
74AUP2G3404 Buffer and inverter 1.1 to 3.6 CMOS ±1.9 4 30 pF 70 2 -40 to +125

74AUP2G3407 Buffer and buffer with open drain 1.1 to 3.6 CMOS ±1.9 4.1 30 pF 70 2 -40 to +125
Dual supply buffer/line driver;
74AUP2T1326 1.1 to 3.6 CMOS ±1.9 3.8 30 pF 70 2 -40 to +125
3-state
74AUP3G0434 Dual inverter and single buffer 1.1 to 3.6 CMOS ±1.9 4 30 pF 70 3 -40 to +125

74AUP3G3404 Dual buffer and single inverter 1.1 to 3.6 CMOS ±1.9 4 30 pF 70 3 -40 to +125

74HC58 Dual AND-OR gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 -40 to +125
CMOS /
74LVC1GX04 Crystal driver 1.65 to 5.5 ±24 2.8 50 pF 150 1 -40 to +125
LVTTL
HEF4000 Dual 3-input NOR gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 2 -40 to +85
Dual complementary pair and
HEF4007 4.5 to 15.5 CMOS ±3.4 15 50 pF 10 2 -40 to +85
inverter

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

88 NXP Logic selection guide 2016

Gates - Configurable
Output
Logic Output
drive tpd fmax Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ)
(mA)
74AUP1G57 Configurable gate; Schmitt trigger 1.1 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125

74AUP1G58 Configurable gate; Schmitt trigger 1.1 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125

74AUP1G97 Configurable gate; Schmitt trigger 1.1 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125

74AUP1G98 Configurable gate; Schmitt trigger 1.1 to 3.6 CMOS 1.9 / -1.9 8.9 30 pF 70 1 -40 to +125
Configurable gate with voltage-
74AUP1T57 2.3 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125
level translation
Configurable gate with voltage-
74AUP1T58 2.3 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125
level translation
Configurable gate with voltage-
74AUP1T97 2.3 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125
level translation
Configurable gate with voltage-
74AUP1T98 2.3 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125
level translation
74AXP1G57 Configurable gate; Schmitt trigger 0.7 to 2.75 CMOS 4.5 / -4.5 4.6 5pF 70 1 -40 to +85

74AXP1G58 Configurable gate; Schmitt trigger 0.7 to 2.75 CMOS 4.5 / -4.5 4.5 5pF 70 1 -40 to +85

74AXP1G97 Configurable gate; Schmitt trigger 0.7 to 2.75 CMOS 4.5 / -4.5 4.5 5pF 70 1 -40 to +85

74AXP1G98 Configurable gate; Schmitt trigger 0.7 to 2.75 CMOS 4.5 / -4.5 4.5 5pF 70 1 -40 to +85

74LVC1G57 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 6.3 50 pF 150 1 -40 to +125

74LVC1G58 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 6.3 50 pF 150 1 -40 to +125

74LVC1G97 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 6.3 50 pF 150 1 -40 to +125

74LVC1G98 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 6.3 50 pF 150 1 -40 to +125

74LVC1G99 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 8.4 50 pF 150 1 -40 to +125

Gates - EXCLUSIVE-NOR
Output
Logic Output
drive tpd fmax
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz)
levels CL (Typ)
(mA)
74HC7266 Quad 2-input EXCLUSIVE-NOR gate 2.0 to 6.0 CMOS ±5.2 11 50 pF 36 -40 to +125

HEF4077 Quad 2-input EXCLUSIVE-NOR gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 -40 to +85

Gates - EXCLUSIVE-OR (cont.)

Output
Logic Output
drive tpd fmax Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ)
(mA)
74AHC1G86 2-input EXCLUSIVE-OR gate 2.0 to 5.5 CMOS ±8 3.4 50 pF 60 1 -40 to +125
2-input EXCLUSIVE-OR gate;
74AHCT1G86 4.5 to 5.5 TTL ±8 3.5 50 pF 60 1 -40 to +125
TTL-enabled
74AHC86 Quad 2-input EXCLUSIVE-OR gate 2.0 to 5.5 CMOS ±8 3.4 50 pF 60 4 -40 to +125
Quad 2-input EXCLUSIVE-OR gate;
74AHCT86 4.5 to 5.5 TTL ±8 3.4 50 pF 60 4 -40 to +125
TTL-enabled
74AUP1G386 Single 3-input EXCLUSIVE-OR gate 1.1 to 3.6 CMOS 1.9/-1.9 8.6 30 pF 70 1 -40 to +125
74AUP2G86 Dual 2-input EXCLUSIVE-OR gate 1.1 to 3.6 CMOS 1.9/-1.9 9 30 pF 70 2 -40 to +125
74HC1G86 Single 2-input EXCLUSIVE-OR gate 2.0 to 6.0 CMOS ±2.6 9 50 pF 36 1 -40 to +125

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 89

Gates - EXCLUSIVE-OR (cont.)
Output
Logic Output
drive tpd fmax Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ)
(mA)
Single 2-input EXCLUSIVE-OR gate;
74HCT1G86 4.5 to 5.5 TTL ±2.0 10 50 pF 36 1 -40 to +125
TTL-enabled
74HC2G86 Dual 2-input EXCLUSIVE-OR gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 -40 to +125
Dual 2-input EXCLUSIVE-OR gate;
74HCT2G86 4.5 to 5.5 TTL ±4.0 11 50 pF 36 2 -40 to +125
TTL-enabled
74HC86 Quad 2-input EXCLUSIVE-OR gate 2.0 to 6.0 CMOS ±5.2 11 50 pF 36 4 -40 to +125
Quad 2-input EXCLUSIVE-OR gate;
74HCT86 4.5 to 5.5 TTL ±4 14 50 pF 36 4 -40 to +125
TTL-enabled
74LV86 Quad 2-input EXCLUSIVE-OR gate 1.0 to 5.5 TTL ±12 11 50 pF 30 4 -40 to +125
CMOS/
74LVC1G386 Single 3-Input EXCLUSIVE-OR gate 1.65 to 5.5 ±32 4.5 50 pF 150 1 -40 to +125
LVTTL
CMOS/
74LVC1G86 Single 2-input EXCLUSIVE-OR gate 1.65 to 5.5 ±32 2.4 50 pF 150 1 -40 to +125
LVTTL
CMOS/
74LVC2G86 Dual 2-input EXCLUSIVE-OR gate 1.65 to 5.5 ±32 2.3 50 pF 150 2 -40 to +125
LVTTL
CMOS/
74LVC86 Quad 2-input EXCLUSIVE-OR gate 1.2 to 3.6 ±24 3 50 pF 150 4 -40 to +125
LVTTL
HEF4030 Quad 2-input EXCLUSIVE-OR gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 4 -40 to +85
HEF4070 Quad 2-input EXCLUSIVE-OR gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 4 -40 to +85
2-input EXCLUSIVE-OR gate;
XC7SET86 4.5 to 5.5 TTL ±8 3.5 50 pF 60 1 -40 to +125
TTL-enabled
XC7SH86 2-input EXCLUSIVE-OR gate 2.0 to 5.5 CMOS ±8 3,4 50 pF 60 1 -40 to +125

Gates - NAND (cont.)

Output
Logic Output
drive tpd fmax Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ)
(mA)
74AHC00 Quad 2-input NAND gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 4 -40 to +125
Quad 2-input NAND gate;
74AHCT00 4.5 to 5.5 TTL ±8 3.3 50 pF 60 4 -40 to +125
TTL-enabled
74AHC1G00 Single 2-input NAND gate 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 1 -40 to +125
Single 2-input NAND gate;
74AHCT1G00 4.5 to 5.5 TTL ±8 3.6 50 pF 60 1 -40 to +125
TTL-enabled
74AHC2G00 Dual 2-input NAND gate 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 2 -40 to +125
Dual 2-input NAND gate;
74AHCT2G00 4.5 to 5.5 TTL ±8 3.6 50 pF 60 2 -40 to +125
TTL-enabled
74AHC30 8-input NAND gate 2.0 to 5.5 CMOS ±8 3.6 50 pF 60 1 -40 to +125

74AHCT30 8-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.3 50 pF 60 1 -40 to +125

74ALVC00 Quad 2-input NAND gate 1.65-3.6 TTL ±24 2.1 50 pF 145 4 -40 to +85

74AUP1G00 Single 2-input NAND gate 1.1 to 3.6 CMOS 1.9/-1.9 8.3 30 pF 70 1 -40 to +125
Single 2-input NAND gate Schmitt
74AUP1G132 1.1 to 3.6 CMOS 1.9/-1.9 10 30 pF 70 1 -40 to +125
trigger
Single 2-input NAND gate; open
74AUP1G38 1.1 to 3.6 CMOS 1,9 8.5 30 pF 70 1 -40 to +125
drain
74AUP2G00 Dual 2-input NAND gate 1.1 to 3.6 CMOS 1.9/-1.9 8.3 30 pF 70 2 -40 to +125

74AUP2G38 Dual 2-input NAND gate; open drain 1.1 to 3.6 CMOS 1,9 8.5 30 pF 70 2 -40 to +125

74HC00 Quad 2-input NAND gate 2.0 to 6.0 CMOS ±5.2 7 50 pF 36 4 -40 to +125
Quad 2-input NAND gate;
74HCT00 4.5 to 5.5 TTL ±4 10 50 pF 36 4 -40 to +125
TTL-enabled

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

90 NXP Logic selection guide 2016

Gates - NAND (cont.)
Output
Logic Output
drive tpd fmax Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ)
(mA)
Quad 2-input NAND gate; open
74HC03 2.0 to 6.0 CMOS 5,2 8 50 pF 36 4 -40 to +125
drain
Quad 2-input NAND gate; open
74HCT03 4.5 to 5.5 TTL ±4 10 50 pF 36 4 -40 to +125
drain; TTL-enabled
74HC10 Triple 3-input NAND gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 3 -40 to +125
Triple 3-input NAND gate;
74HCT10 4.5 to 5.5 TTL ±4 11 50 pF 36 3 -40 to +125
TTL-enabled
74HC1G00 Single 2-input NAND gate 2.0 to 6.0 CMOS ±2.6 7 50 pF 36 1 -40 to +125
Single 2-input NAND gate;
74HCT1G00 4.5 to 5.5 TTL ±2 10 50 pF 36 1 -40 to +125
TTL-enabled
74HC20 Dual 4-input NAND gate 2.0 to 6.0 CMOS ±5.2 8 50 pF 36 2 -40 to +125
Dual 4-input NAND gate;
74HCT20 4.5 to 5.5 TTL ±4 13 50 pF 36 2 -40 to +125
TTL-enabled
74HC2G00 Dual 2-input NAND gate 2.0 to 6.0 CMOS ±5.6 9 50 pF 36 2 -40 to +125
Dual 2-input NAND gate;
74HCT2G00 4.5 to 5.5 TTL ±4 12 50 pF 36 2 -40 to +125
TTL-enabled
74HC30 8-input NAND gate 2.0 to 6.0 CMOS ±5.2 12 50 pF 36 1 -40 to +125

74HCT30 8-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±4 12 50 pF 36 1 -40 to +125

74LV00 Quad 2-input NAND gate 1.0 to 5.5 TTL ±12 7 50 pF 30 4 -40 to +125
Quad 2-input NAND gate; open
74LV03 1.0 to 5.5 TTL ±12 8 50 pF 30 4 -40 to +125
drain
CMOS/
74LVC00 Quad 2-input NAND gate 1.2 to 3.6 ±24 2.1 50 pF 150 4 -40 to +125
LVTTL
CMOS/
74LVC10 Triple 3-input NAND gate 1.2 to 3.6 ±24 3.9 50 pF 150 3 -40 to +125
LVTTL
CMOS/
74LVC1G00 Single 2-input NAND gate 1.65 to 5.5 ±32 2.2 50 pF 175 1 -40 to +125
LVTTL
CMOS/
74LVC1G10 Single 3-input NAND gate 1.65 to 5.5 ±32 2.6 50 pF 175 1 -40 to +125
LVTTL
Single 2-input NAND gate; open CMOS/
74LVC1G38 1.65 to 5.5 32 2.3 50 pF 175 1 -40 to +125
drain LVTTL
CMOS/
74LVC2G00 Dual 2-input NAND gate 1.65 to 5.5 ±32 2.2 50 pF 175 2 -40 to +125
LVTTL
CMOS/
74LVC2G38 Dual 2-input NAND gate; open drain 1.65 to 5.5 32 2.1 50 pF 175 2 -40 to +125
LVTTL
CMOS/
74LVC30 8-input NAND gate 1.65 to 5.6 24 3.6 50 pF 175 1 -40 to +125
LVTTL
Quad 2-input NAND gate; open CMOS/
74LVC38 1.2 to 3.6 24 2.2 50 pF 175 4 -40 to +125
drain LVTTL
74LVT00 Quad 2-input NAND gate 2.7 to 3.6 TTL -32/+64 2.7 50 pF 150 4 -40 to +85

74LVT10 Triple 3-input NAND gate 2.7 to 3.6 TTL -32/+64 3.8 50 pF 150 3 -40 to +85

HEF4011 Quad 2-input NAND gate 4.5 to 15.5 CMOS ±2.4 20 50 pF 10 4 -40 to +85

HEF4023 Triple 3-input NAND gate 4.5 to 15.5 CMOS ±2.4 25 50 pF 10 3 -40 to +85

HEF4068 8-input NAND gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 1 -40 to +85

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 91

Gates - NOR
Output
Logic Output
drive tpd fmax Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ)
(mA)
Quad 2-input NOR gate;
74AHCT02 4.5 to 5.5 TTL ±8 3.8 50 pF 60 4 -40 to +125
TTL-enabled
74AHC1G02 Single 2-input NOR gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125
Single 2-input NOR gate;
74AHCT1G02 4.5 to 5.5 TTL ±8 3.5 50 pF 60 1 -40 to +125
TTL-enabled
74ALVC02 Quad 2-input NOR gate 1.65 to 3.6 TTL ±24 2.2 50 pF 150 4 -40 to +85

74AUP1G02 Single 2-input NOR gate 1.1 to 3.6 CMOS 1.9/-1.9 8.3 30 pF 70 1 -40 to +125

74AUP2G02 Dual 2-input NOR gate 1.1 to 3.6 CMOS 1.9/-1.9 8.3 30 pF 70 2 -40 to +125

74HC02 Quad 2-input NOR gate 2.0 to 6.0 CMOS ±5.2 7 50 pF 36 4 -40 to +125
Quad 2-input NOR gate;
74HCT02 4.5 to 5.5 TTL ±4 9 50 pF 36 4 -40 to +125
TTL-enabled
74HC1G02 Single 2-input NOR gate 2.0 to 6.0 CMOS ±2.6 7 50 pF 36 1 -40 to +125
Single 2-input NOR gate;
74HCT1G02 4.5 to 5.5 TTL ±2.0 9 50 pF 36 1 -40 to +125
TTL-enabled
74HC27 Triple 3-input NOR gate 2.0 to 6.0 CMOS ±5.2 8 50 pF 36 3 -40 to +125
Triple 3-input NOR gate;
74HCT27 4.5 to 5.5 TTL ±4 10 50 pF 36 3 -40 to +125
TTL-enabled
74HC2G02 Dual 2-input NOR gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 -40 to +125
Dual 2-input NOR gate;
74HCT2G02 4.5 to 5.5 TTL ±4 12 50 pF 36 2 -40 to +125
TTL-enabled
74HC4002 Dual 4-input NOR gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 -40 to +125
Dual 4-input NOR gate;
74HCT4002 4.5 to 5.5 TTL ±4 11 50 pF 36 2 -40 to +125
TTL-enabled
Dual 2-input NOR gate;
74HCT2G02 4.5 to 5.5 TTL ±4 12 50 pF 36 2 -40 to +125
TTL-enabled
74LV02 Quad 2-input NOR gate 1.0 to 5.5 TTL ±12 6 50 pF 30 4 -40 to +125

74LV27 Triple 3-input NOR gate 1.0 to 5.5 TTL ±12 8 50 pF 30 3 -40 to +125

74LVC02 Quad 2-input NOR gate 1.2 to 3.6 TTL ±24 2.1 50 pF 150 4 -40 to +125
CMOS/
74LVC1G02 Single 2-input NOR gate 1.65 to 5.5 ±32 2.1 50 pF 150 1 -40 to +125
LVTTL
CMOS/
74LVC1G27 Single 3-input NOR gate 1.65 to 5.5 ±32 2.6 50 pF 150 1 -40 to +125
LVTTL
74LVC27 Triple 3-input NOR gate 1.2 to 3.6 TTL ±24 3.4 50 pF 150 3 -40 to +125
CMOS/
74LVC2G02 Dual 2-input NOR gate 1.65 to 5.5 ±32 2.4 50 pF 150 2 -40 to +125
LVTTL
74LVT02 Quad 2-input NOR gate 2.7 to 3.6 TTL -32/+64 2.8 50 pF 4 -40 to +85

74VHC02 Quad 2-input NOR gate 2.0 to 5.5 CMOS ±8 2.9 50 pF 60 4 -40 to +125
Quad 2-input NOR gate;
74VHCT02 4.5 to 5.5 TTL ±8 3.8 50 pF 60 4 -40 to +125
TTL-enabled
HEF4001 Quad 2-input NOR gate 4.5 to 15.5 CMOS ±2.4 20 50 pF 10 4 -40 to +85

HEF4002 Dual 4-input NOR gate 4.5 to 15.5 CMOS ±2.4 20 50 pF 10 4 -40 to +85

HEF4025 Triple 3-input NOR gate 4.5 to 15.5 CMOS ±2.4 40 50 pF 10 3 -40 to +85
Single 2-input NOR gate;
XC7SET02 4.5 to 5.5 TTL ±8 3.5 50 pF 60 1 -40 to +125
TTL-enabled
XC7SH02 Single 2-input NOR gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

92 NXP Logic selection guide 2016

Gates - OR (cont.)
Output
Logic Output Power
drive tpd fmax Number
Type number Description VCC (V) switching Load dissipation Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ) considerations
(mA)
Single 2-input OR
74AHC1G32 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 low -40 to +125
gate
Single 2-input OR
74AHCT1G32 4.5 to 5.5 TTL ±8 3.3 50 pF 60 1 low -40 to +125
gate
Dual 2-input OR
74AHC2G32 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 2 low -40 to +125
gate
Dual 2-input OR
74AHCT2G32 4.5 to 5.5 TTL ±8 3.3 50 pF 60 2 low -40 to +125
gate
Quad 2-input OR
74AHC32 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 4 low -40 to +125
gate
Quad 2-input OR
74AHCT32 4.5 to 5.5 TTL ±8 5 50 pF 60 4 low -40 to +125
gate; TTL-enabled
Quad 2-input OR
74ALVC32 1.65 to 3.6 TTL ±24 2 50 pF 150 4 low -40 to +125
gate
Single 2-input OR
74AUP1G32 1.1 to 3.6 CMOS 1.9/-1.9 7.9 30 pF 70 1 ultra low -40 to +125
gate
Single 3-input OR
74AUP1G332 1.1 to 3.6 CMOS 1.9/-1.9 6.8 30 pF 70 1 ultra low -40 to +125
gate
Dual 2-input OR
74AUP2G32 1.1 to 3.6 CMOS 1.9/-1.9 7.9 30 pF 70 2 ultra low -40 to +125
gate
Single 2-input OR
74HC1G32 2.0 to 6.0 CMOS ±2.6 8 50 pF 36 1 low -40 to +125
gate
Single 2-input OR
74HCT1G32 4.5 to 5.5 TTL ±2.0 10 50 pF 36 1 low -40 to +125
gate; TTL-enabled
Dual 2-input OR
74HC2G32 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 low -40 to +125
gate
Dual 2-input OR
74HCT2G32 4.5 to 5.5 TTL ±4.0 13 50 pF 36 2 low -40 to +125
gate; TTL-enabled
Quad 2-input OR
74HC32 2.0 to 6.0 CMOS ±5.2 6 50 pF 36 4 low -40 to +125
gate
Quad 2-input OR
74HCT32 4.5 to 5.5 TTL ±4.0 9 50 pF 36 4 low -40 to +125
gate
Triple 3-input OR
74HC4075 2.0 to 6.0 CMOS ±5.2 8 50 pF 36 3 low -40 to +125
gate
Triple 3-input OR
74HCT4075 4.5 to 5.5 TTL ±4 10 50 pF 36 3 low -40 to +125
gate; TTL-enabled
Quad 2-input OR
74LV32 1.0 to 5.5 TTL ±12 6 50 pF 30 4 low -40 to +125
gate
Single 2-input OR CMOS/
74LVC1G32 1.65 to 5.5 ±32 2.1 50 pF 150 1 low -40 to +125
gate LVTTL
Single 3-input OR CMOS/
74LVC1G332 1.65 to 5.5 ±32 50 pF 150 1 low -40 to +125
gate LVTTL
Dual 2-input OR CMOS/
74LVC2G32 1.65 to 5.5 ±32 2.2 50 pF 150 2 low -40 to +125
gate LVTTL
Quad 2-input OR CMOS/
74LVC32 1.2 to 3.6 ±24 2.1 50 pF 150 4 low -40 to +125
gate LVTTL
Triple 3-input OR CMOS/
74LVC332 1.2 to 3.6 ±24 2.4 50 pF 150 3 low -40 to +125
gate LVTTL
Quad 2-input OR
74LVT32 2.7 to 3.6 TTL -20/+32 3.2 50 pF 4 medium -40 to +125
gate
Quad 2-input OR
74VHC32 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 4 low -40 to +125
gate
Quad 2-input OR
74VHCT32 4.5 to 5.5 TTL ±8 5 50 pF 60 4 low -40 to +125
gate; TTL-enabled
Quad 2-input OR
HEF4071 4.5 to 15.5 CMOS ±2.4 20 50 pF 10 4 low -40 to +125
gate

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 93

Gates - OR (cont.)
Output
Logic Output Power
drive tpd fmax Number
Type number Description VCC (V) switching Load dissipation Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ) considerations
(mA)
Dual 4-input OR
HEF4072 4.5 to 15.5 CMOS ±2.4 25 50 pF 10 2 low -40 to +85
gate
Triple 3-input OR
HEF4075 4.5 to 15.5 CMOS ±2.4 25 50 pF 10 3 low -40 to +85
gate
Single 2-input OR
XC7SET32 4.5 to 5.5 TTL ±8 3.3 50 pF 60 1 low -40 to +125
gate; TTL-enabled
Single 2-input OR
XC7SH32 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 low -40 to +125
gate

LATCHES / REGISTERED DRIVERS

Features and benefits 4 Low propagation delay
4  Improved synchronous operation, with reduced signal  
4 Low-power CMOS
loads, elimination of timing delays and waveform distortion 4 
Optional overvoltage-tolerant inputs, source termination,
4 Mixed 3.3/5 V applications low input threshold
4  Reduced board space
4  Low-cost interface solutions Applications
4 Improved signal integrity in complex layouts Memory controllers
4 
4 
Wide range of supply voltages Backplane interfaces
4 

Latches-registered drivers (cont.)

Output
Logic Output
drive tpd Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) of bits
levels CL (Typ)
(mA)
74AHC259 8-bit addressable latch 2.0 to 5.5 CMOS ±8 4.1 50 pF 8 -40 to +125

74AHCT259 8-bit addressable latch; TTL-enabled 4.5 to 5.5 TTL ±8 4.1 50 pF 8 -40 to +125

74AHC373 Octal D-type transparent latch (3-state) 2.0 to 5.5 CMOS ±8 4.3 50 pF 8 -40 to +125
Octal D-type transparent latch; TTL-enabled
74AHCT373 4.5 to 5.5 TTL ±8 4.3 50 pF 8 -40 to +125
(3-state)
74AHC573 Octal D-type transparent latch (3-state) 2.0 to 5.5 CMOS ±8 4.2 50 pF 8 -40 to +125
Octal D-type transparent latch; TTL-enabled
74AHCT573 4.5 to 5.5 TTL ±8 3.9 50 pF 8 -40 to +125
(3-state)
16-bit registered driver with 30 Ω
74ALVC162334 1.65 to 3.6 LVTTL ±24 6 50 pF 16 -40 to +85
termination resistors (3-state)
18-bit registered driver with 30 Ω
74ALVC162834 1.65 to 3.6 LVTTL ±24 6 50 pF 18 -40 to +85
termination resistors (3-state)
18-bit registered driver with 30 Ω
74ALVC162835 1.65 to 3.6 LVTTL ±24 6 50 pF 18 -40 to +85
termination resistors (3-state)
20-bit registered driver with 30 Ω
74ALVC162836 1.65 to 3.6 LVTTL ±24 6 50 pF 20 -40 to +85
termination resistors (3-state)
74ALVC16834 18-bit registered driver (3-state) 1.65 to 3.6 LVTTL ±24 4 50 pF 18 -40 to +85

74ALVC16835 18-bit registered driver (3-state) 1.65 to 3.6 LVTTL ±24 4 50 pF 18 -40 to +85

74ALVC16836 20-bit registered driver (3-state) 1.65 to 3.6 LVTTL ±24 4 50 pF 20 -40 to +85

74ALVC373 Octal D-type transparent latch (3-state) 1.65 to 3.6 LVTTL ±24 2.2 50 pF 8 -40 to +85

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

94 NXP Logic selection guide 2016

Latches-registered drivers (cont.)
Output
Logic Output
drive tpd Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) of bits
levels CL (Typ)
(mA)
74ALVC573 Octal D-type transparent latch (3-state) 1.65 to 3.6 LVTTL ±24 2.2 50 pF 8 -40 to +85
16-bit D-type transparent latch with bus
74ALVCH16373 2.3 to 3.6 LVTTL ±24 2.1 50 pF 16 -40 to +85
hold (3-state)
7-bit to 28-bit address register/driver
74ALVCH16832 2.3 to 3.6 LVTTL ±24 4 50 pF 7 -40 to +85
(3-state)
20-bit D-type transparent latch with bus
74ALVCH16841 2.3 to 3.6 LVTTL ±24 2.4 50 pF 20 -40 to +85
hold (3-state)
18-bit D-type transparent latch with bus
74ALVCH16843 2.3 to 3.6 LVTTL ±24 2.1 50 pF 18 -40 to +85
hold (3-state)
16-bit transceiver and transparent D-type
74ALVCH32973 1.8 to 3.6 LVTTL ±24 2.5 50 pF 16 -40 to +85
latch with 8 independent buffers
12-bit to 24-bit multiplexed D-type latch
74ALVT16260 2.3 to 3.6 TTL -32 / +64 2.8 50 pF 12 -40 to +85
with bus hold (3-state)
16-bit D-type transparent latch with bus
74ALVT16373 2.3 to 3.6 TTL -32 / +64 1.8 50 pF 16 -40 to +85
hold (3-state)
74AUP1G373 Single D-type transparent latch (3-state) 1.1 to 3.6 CMOS 1.9 / -1.9 8.5 30 pF 1 -40 to +125

74AVC16334 16-bit registered driver (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 16 -40 to +85

74AVC16373 16-bit D-type transparent latch (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 16 -40 to +85

74AVC16834 18-bit registered driver (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 18 -40 to +85

74AVC16835 18-bit registered driver (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 18 -40 to +85

74AVC16836 20-bit registered driver (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 20 -40 to +85
18-bit registered driver with 30 Ω
74AVCM162834 1.2 to 3.6 CMOS ±12 2 30 pF 18 -40 to +85
termination resistors (3-state)
18-bit registered driver with 15 Ω
74AVCM162835 1.2 to 3.6 CMOS ±12 2 30 pF 18 -40 to +85
termination resistors (3-state)
20-bit registered driver with 15 Ω
74AVCM162836 1.2 to 3.6 CMOS ±12 2 30 pF 20 -40 to +85
termination resistors (3-state)
74HC259 8-bit addressable latch 2.0 to 6.0 CMOS ±5.2 18 50 pF 8 -40 to +125

74HCT259 8-bit addressable latch; TTL-enabled 4.5 to 5.5 TTL ±4 20 50 pF 8 -40 to +125

74HC373 Octal D-type transparent latch (3-state) 2.0 to 6.0 CMOS ±7.8 12 50 pF 8 -40 to +125
Octal D-type transparent latch; TTL-enabled
74HCT373 4.5 to 5.5 TTL ±6 14 50 pF 8 -40 to +125
(3-state)
Octal D-type transparent latch; inverting;
74HCT563 4.5 to 5.5 TTL ±6 16 50 pF 8 -40 to +125
TTL-enabled (3-state)
74HC573 Octal D-type transparent latch (3-state) 2.0 to 6.0 CMOS ±7.8 14 50 pF 8 -40 to +125
Octal D-type transparent latch; TTL-enabled
74HCT573 4.5 to 5.5 TTL ±6 17 50 pF 8 -40 to +125
(3-state)
74HC670 4-bit x 4-word register (3-state) 2.0 to 6.0 CMOS ±7.8 17 50 pF 4 -40 to +125

74HCT670 4-bit x 4-word register; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 23 50 pF 4 -40 to +125

74HC75 Quad bistable transparent latch 2.0 to 6.0 CMOS ±5.2 11 50 pF 4 -40 to +125

74HC75 Quad bistable transparent latch 2.0 to 6.0 CMOS ±5.2 11 50 pF 4 -40 to +125

74LV259 8-bit addressable latch 1.0 to 3.6 CMOS ±6 17 50 pF 8 -40 to +125

74LV373 Octal D-type transparent latch (3-state) 1.0 to 5.5 CMOS ±16 10 50 pF 8 -40 to +125

74LV573 Octal D-type transparent latch (3-state) 1.0 to 5.5 CMOS ±16 12 50 pF 8 -40 to +125
16-bit D-type transparent latch with 30 Ω
74LVC162373 1.2 to 3.6 TTL ±12 3.2 50 pF 16 -40 to +125
termination resistors (3-state)
16-bit D-type transparent latch with bus
74LVCH162373 1.2 to 3.6 TTL ±24 3.2 50 pF 16 -40 to +125
hold and 30 Ω termination resistors (3-state)

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 95

Latches-registered drivers (cont.)
Output
Logic Output
drive tpd Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) of bits
levels CL (Typ)
(mA)
74LVC16373 16-bit D-type transparent latch (3-state) 1.2 to 3.6 TTL ±24 3 50 pF 16 -40 to +125
16-bit D-type transparent latch with bus
74LVCH16373 1.2 to 3.6 TTL ±24 3 50 pF 16 -40 to +125
hold (3-state)
74LVC373 Octal D-type transparent latch (3-state) 1.2 to 3.6 TTL ±24 3 50 pF 8 -40 to +125

74LVC573 Octal D-type transparent latch (3-state) 1.2 to 3.6 TTL ±24 3.4 50 pF 8 -40 to +125

74LVC841 10-bit D-type transparent latch (3-state) 1.2 to 3.6 TTL ±24 4.5 50 pF 10 -40 to +125

74LVCH32373 32-bit D-type transparent latch (3-state) 1.2 to 3.6 TTL ±24 3 50 pF 32 -40 to +125
16-bit D-type transparent latch with bus
74LVT162373 2.7 to 3.6 TTL ±12 2.5 50 pF 16 -40 to +85
hold and 30 Ω termination resistors (3-state)
16-bit D-type transparent latch with bus
74LVT16373 2.7 to 3.6 TTL -32 / +64 1.9 50 pF 16 -40 to +85
hold (3-state)
74LVT573 Octal D-type transparent latch (3-state) 2.7 to 3.6 TTL -32 / +64 2.7 50 pF 8 -40 to +85

HEF40373 Octal D-type transparent latch (3-state) 4.5 to 15.5 CMOS -50 / +62 40 50 pF 8 -40 to +85

HEF4043 Quad R/S latch with set and reset (3-state) 4.5 to 15 CMOS ±2.4 25 50 pF 4 -40 to +85

HEF4044 Quad R/S latch with set and reset (3-state) 4.5 to 15 CMOS ±2.4 30 50 pF 4 -40 to +85

LEVEL SHIFTERS/TRANSLATORS
Features and benefits
4 
Bidirectional operation Applications
Widths from 1 to 32 bits
4  Mixed-voltage systems
4 
Wide range of supply voltages
4  I2C bus
4 
Low propagation delay
4  Mobile, portable
4 
Low-power suspend mode
4  Industrial
4 
Auto-direction sensing
4  Consumer entertainment
4 
Optional overvoltage-tolerant inputs, 3-state outputs
4  Computing
4 

Level shifters-translators (cont.)

Output
Logic Output
drive tpd Number
Type number Description VCC(A) (V) VCC(B) (V) switching Load Tamb (°C)
capability (ns) of bits
levels CL (Typ)
(mA)
16-bit dual-supply voltage- CMOS/
74ALVC164245 1.5 to 5.5 1.5 to 3.6 ±24 2.9 50 16 -40 to +85
translating transceiver (3-state) LVTTL

74AUP1T34 Single dual-supply translating buffer 1.1 to 3.6 1.1 to 3.6 CMOS ±1.9 15.2 30 1 -40 to +125

Single dual-supply voltage-

74AUP1T45 1.1 to 3.6 1.1 to 3.6 CMOS ±1.9 15.6 30 1 -40 to +125
translating transceiver (3-state)
16-bit dual-supply voltage- CMOS/
74AVC16T245 0.8 to 3.6 0.8 to 3.6 ±12 2.1 30 16 -40 to +125
translating transceiver (3-state) LVTTL
Single dual-supply voltage- CMOS/
74AVC1T45 0.8 to 3.6 0.8 to 3.6 ±12 2.1 30 1 -40 to +125
translating transceiver (3-state) LVTTL
20-bit dual-supply voltage- CMOS/
74AVC20T245 0.8 to 3.6 0.8 to 3.6 ±12 3.5 30 20 -40 to +125
translating transceiver (3-state) LVTTL

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

96 NXP Logic selection guide 2016

Level shifters-translators (cont.)
Output
Logic Output
drive tpd Number
Type number Description VCC(A) (V) VCC(B) (V) switching Load Tamb (°C)
capability (ns) of bits
levels CL (Typ)
(mA)
Dual-bit dual-supply voltage- CMOS/
74AVC2T45 0.8 to 3.6 0.8 to 3.6 ±12 2.1 30 2 -40 to +125
translating transceiver (3-state) LVTTL
32-bit dual-supply voltage- CMOS/
74AVC32T245 0.8 to 3.6 0.8 to 3.6 ±12 2.1 30 32 -40 to +125
translating transceiver (3-state) LVTTL
4-bit dual-supply voltage-translating CMOS/
74AVC4T245 0.8 to 3.6 0.8 to 3.6 ±12 2.1 30 4 -40 to +125
transceiver (3-state) LVTTL
4-bit dual-supply voltage-translating CMOS/
74AVC4TD245 0.8 to 3.6 0.8 to 3.6 ±12 2.1 30 4 -40 to +125
transceiver (3-state) LVTTL
8-bit dual-supply voltage-translating CMOS/
74AVC8T245 0.8 to 3.6 0.8 to 3.6 ±12 2.1 30 8 -40 to +125
transceiver (3-state) LVTTL
16-bit dual-supply voltage-
CMOS/
74AVCH16T245 translating transceiver with bus hold 0.8 to 3.6 0.8 to 3.6 ±12 2.1 30 16 -40 to +125
LVTTL
(3-state)
Single dual-supply voltage-
CMOS/
74AVCH1T45 translating transceiver with bus hold 0.8 to 3.6 0.8 to 3.6 ±12 2.1 30 1 -40 to +125
LVTTL
(3-state)
20-bit dual-supply voltage-
CMOS/
74AVCH20T245 translating transceiver with bus hold 0.8 to 3.6 0.8 to 3.6 ±12 3.5 30 20 -40 to +125
LVTTL
(3-state)
Dual-bit dual-supply voltage-
CMOS/
74AVCH2T45 translating transceiver with bus hold 0.8 to 3.6 0.8 to 3.6 ±12 2.1 30 2 -40 to +125
LVTTL
(3-state)
4-bit dual-supply voltage-translating CMOS/
74AVCH4T245 0.8 to 3.6 0.8 to 3.6 ±12 2.1 30 4 -40 to +125
transceiver with bus hold (3-state) LVTTL
Hex inverter with 15 V-tolerant
74HC4049 2.0 to 6.0 N/A CMOS ±5.2 8 50 6 -40 to +125
inputs

74HC4050 Hex buffer with 15 V-tolerant inputs 2.0 to 6.0 N/A CMOS ±5.2 7 50 6 -40 to +125

Single dual-supply voltage- CMOS/

74LVC1T45 1.2 to 5.5 1.2 to 5.5 ±24 2.5 50 1 -40 to +125
translating transceiver (3-state) LVTTL
Single dual-supply voltage-
CMOS/
74LVCH1T45 translating transceiver with bus hold 1.2 to 5.5 1.2 to 5.5 ±24 2.5 50 1 -40 to +125
LVTTL
(3-state)
Dual-bit dual-supply voltage- CMOS/
74LVC2T45 1.2 to 5.5 1.2 to 5.5 ±24 2.5 50 2 -40 to +125
translating transceiver (3-state) LVTTL
Dual-bit dual-supply voltage-
CMOS/
74LVCH2T45 translating transceiver with bus hold 1.2 to 5.5 1.2 to 5.5 ±24 2.5 50 2 -40 to +125
LVTTL
(3-state)
8-bit dual-supply voltage-translating CMOS/
74LVC8T245 1.2 to 5.5 1.2 to 5.5 ±24 3.5 50 8 -40 to +125
transceiver (3-state) LVTTL
8-bit dual-supply voltage-translating CMOS/
74LVCH8T245 1.2 to 5.5 1.2 to 5.5 ±24 3.5 50 8 -40 to +125
transceiver with bus hold (3-state) LVTTL
8-bit dual-supply voltage-translating CMOS/
74LVC4245 1.2 to 5.5 1.2 to 5.5 ±24 3.5 50 8 -40 to +125
transceiver (3-state) LVTTL
Quad low-to-high voltage translator 3.0 to
HEF4104 3.0 to 15.0 CMOS ±2.4 340 50 16 -40 to +85
(3-state) 15.0
Schmitt-trigger inputs, Dual supply
74AXP1T57 0.7 to 2.75 1.2 to 5.5 1.2 to 5.5 CMOS ±12 4.8 1 -40 to +85
configurable multiple function gate

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 97

MULTIVIBRATORS
Features and benefits Applications
4 Simple control interface Timing delays in synchronous control circuits
4 
4 Power-on reset
4 Dual devices with separate reset inputs
4 Negative or positive edge triggered
4 Low-power CMOS

Multivibrators
Output
Logic Output
drive tpd
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns)
levels CL (Typ)
(mA)
74AHC123 Dual retriggerable monostable multivibrator with reset 2.0 to 5.5 CMOS ±8 5.1 50 pF -40 to +125

Dual retriggerable monostable multivibrator with reset;

74AHCT123 4.5 to 5.5 TTL ±8 5 50 pF -40 to +125
TTL-enabled

74HC123 Dual retriggerable monostable multivibrator with reset 2.0 to 6.0 CMOS ±7.8 9 50 pF -40 to +125

Dual retriggerable monostable multivibrator with reset;

74HCT123 4.5 to 5.5 TTL ±4 26 50 pF -40 to +125
TTL-enabled

74HC221 dual non-retriggerable monostable multivibrator with reset 2.0 to 6.0 CMOS ±5.2 29 50 pF -40 to +125

dual non-retriggerable monostable multivibrator with reset;

74HCT221 4.5 to 5.5 TTL ±4 32 50 pF -40 to +125
TTL-enabled

74HC423 Dual retriggerable monostable multivibrator with reset 2.0 to 6.0 CMOS ±5.2 23 50 pF -40 to +125

Dual retriggerable monostable multivibrator with reset;

74HCT423 4.5 to 5.5 TTL ±4 26 50 pF -40 to +125
TTL-enabled

74HC4538 Dual retriggerable precision monostable multivibrator 2.0 to 6.0 CMOS ±5.2 27 50 pF -40 to +125

Dual retriggerable precision monostable multivibrator;

74HCT4538 4.5 to 5.5 TTL ±4 30 50 pF -40 to +125
TTL-enabled

74LV123 Dual retriggerable monostable multivibrator with reset 1.0 to 5.5 TTL ±12 20 50 pF -40 to +125

CMOS/
74LVC1G123 Single retriggerable monostable multivibrator 1.65 to 5.5 ±32 3.5 50 pF -40 to +125
LVTTL

HEF4047 Monostable/astable multivibrator 4.5 to 15.5 CMOS ±2.4 50 50 pF -40 to +85

HEF4528 Dual retriggerable monostable multivibrator with reset 4.5 to 15.5 CMOS ±2.4 40 50 pF -40 to +85

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

98 NXP Logic selection guide 2016

PARITY GENERATORS/CHECKERS
Features and benefits Applications
4 
Simple control interface Error detection
4 
Power-on reset
4 
Dual devices with separate reset inputs
4 
Negative or positive edge triggered
4 
Low-power CMOS
4 

Parity generators-checkers
Output
Logic Output
drive tpd
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns)
levels CL (Typ)
(mA)
74HC280 9-bit odd/even parity generator/checker 2.0 to 6.0 CMOS ±5.2 17 50 pF -40 to +125

74HCT280 9-bit odd/even parity generator/checker; TTL-enabled 4.5 to 5.5 TTL ±4 18 50 pF -40 to +125

PHASE-LOCKED LOOPS
Features and benefits Applications
4 
Phase comparator, loop filter, and VCO 4 FM modulation and demodulation
Wide range of supply voltages
4  4 Frequency synthesis and multiplication
Maximum frequency to 17 MHz (typ)
4  4 Clock recovery
Low power consumption
4  4 Data synchronization and conditioning
E xcellent VCO frequency linearity
4  4 Voltage-to-frequency conversion
Choice of phase comparators
4  4 Motor-speed control interface
User configurable
4 

Phase-locked loops
Output
Logic Output
drive
Type number Description VCC (V) switching tpd (ns) Load Tamb (°C)
capability
levels CL (Typ)
(mA)
74HC4046 Phase-locked loop with VCO 3.0 to 6.0 CMOS ±5.2 18 50 pF 21
74HCT4046 Phase-locked loop with VCO; TTL-enabled 4.5 to 5.5 TTL ±4 23 50 pF 19
74HC7046 Phase-locked loop with lock detector 3.0 to 6.0 CMOS ±5.2 17 50 pF 19
74HCT7046 Phase-locked loop with lock detector; TTL-enabled 4.5 to 5.5 TTL ±4 21 50 pF 19
Phase-locked loop with bandgap controlled VCO;
74HCT9046 4.5 to 5.5 TTL ±4 23 50 pF 19
TTL-enabled
HEF4046 Phase-locked loop with VCO 4.5 to 15.5 CMOS ±2.4 50 pF 2.7

Printer interfaces
Output
Logic Output
drive
Type number Description VCC (V) switching tpd (ns) Load Tamb (°C)
capability
levels CL (Typ)
(mA)
PDI1284P11 Parallel interface transceiver/buffer 3.0 to 3.6 LVTTL - 14 / 14 13.9 50 pF 0 to +70

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 99

SCHMITT TRIGGERS
Features and benefits Applications
4 
Transform slowly changing input signals into sharply 4 Convert sine waves to square waves
defined, jitter-free output signals 4 Interface between analog and digital environments
Improve noisy signals
4  4 Invoice noise immunity
Reshape signals in complex layouts
4  4 Relaxation oscillators
Mixed 3.3/5 V applications
4 
Wide range of supply voltages
4 
Input hysteresis
4 
CMOS and TTL variants
4 
Optional open-drain outputs, overvoltage-tolerant inputs
4 

Schmitt triggers (cont.)

Output
Logic Output
drive tpd fmax Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ)
(mA)
Quad 2-input NAND gate Schmitt
74AHC132 2.0 to 5.5 CMOS ±8 3.3 50 pF 60 4 -40 to +125
trigger
Quad 2-input NAND gate Schmitt
74AHCT132 4.5 to 5.5 TTL ±8 3.5 50 pF 60 4 -40 to +125
trigger; TTL-enabled
74AHC14 Hex inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 6 -40 to +125
Hex inverter Schmitt trigger;
74AHCT14 4.5 to 5.5 TTL ±8 4 50 pF 60 6 -40 to +125
TTL-enabled
74AHC1G14 Single inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125
Single inverter Schmitt trigger;
74AHCT1G14 4.5 to 5.5 TTL ±8 4.1 50 pF 60 1 -40 to +125
TTL-enabled
74AHC3G14 Triple inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 3 -40 to +125
Triple inverter Schmitt trigger;
74AHCT3G14 4.5 to 5.5 TTL ±8 4.1 50 pF 60 3 -40 to +125
TTL-enabled
74ALVC14 Hex inverter Schmitt trigger 1.65 to 3.6 TTL ±24 2.4 50 pF 150 6 -40 to +85
74AUP1G17 Single buffer Schmitt trigger 1.1 to 3.6 CMOS ±1.9 7.8 30 pF 70 1 -40 to +125
dual 2-input NAND gate Schmitt
74AUP2G132 1.1 to 3.6 CMOS ±1.9 10 30 pF 70 2 -40 to +125
trigger
74AUP2G14 dual inverter Schmitt trigger 1.1 to 3.6 CMOS ±1.9 4.7 30 pF 70 2 -40 to +125
74AUP2G17 dual buffer Schmitt trigger 1.1 to 3.6 CMOS ±1.9 7.8 30 pF 70 2 -40 to +125
Quad 2-input NAND gate Schmitt
74HC132 2.0 to 6.0 CMOS ±5.2 11 50 pF 36 4 -40 to +125
trigger
Quad 2-input NAND gate Schmitt
74HCT132 4.5 to 5.5 TTL ±4 17 50 pF 36 4 -40 to +125
trigger; TTL-enabled
74HC14 Hex inverter Schmitt trigger 2.0 to 6.0 CMOS ±5.2 12 50 pF 36 6 -40 to +125
Hex inverter Schmitt trigger;
74HCT14 4.5 to 5.5 TTL ±4 17 50 pF 36 6 -40 to +125
TTL-enabled
74HC1G14 Single inverter Schmitt trigger 2.0 to 6.0 CMOS ±2.6 10 50 pF 36 1 -40 to +125
Single inverter Schmitt trigger;
74HCT1G14 4.5 to 5.5 TTL ±2.0 15 50 pF 36 1 -40 to +125
TTL-enabled
74HC2G14 Dual inverter Schmitt trigger 2.0 to 6.0 CMOS ±5.2 16 50 pF 36 2 -40 to +125
Dual inverter Schmitt trigger;
74HCT2G14 4.5 to 5.5 TTL ±4.0 21 50 pF 36 2 -40 to +125
TTL-enabled
74HC2G17 Dual buffer Schmitt trigger 2.0 to 6.0 CMOS ±5.2 12 50 pF 36 2 -40 to +125
Dual buffer Schmitt trigger;
74HCT2G17 4.5 to 5.5 TTL ±4.0 21 50 pF 36 2 -40 to +125
TTL-enabled

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

100 NXP Logic selection guide 2016

Schmitt triggers (cont.)
Output
Logic Output
drive tpd fmax Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ)
(mA)
74HC3G14 Triple inverter Schmitt trigger 2.0 to 6.0 CMOS ±5.2 16 50 pF 36 3 -40 to +125
Triple inverter Schmitt trigger;
74HCT3G14 4.5 to 5.5 TTL ±4.0 21 50 pF 36 3 -40 to +125
TTL-enabled
Octal inverter/line driver Schmitt
74HC7540 2.0 to 6.0 CMOS ±7.8 11 50 pF 36 8 -40 to +125
trigger (3-state)
Octal inverter/line driver Schmitt
74HCT7540 4.5 to 5.5 TTL ±6 16 50 pF 36 8 -40 to +125
trigger; TTL-enabled (3-state)
Octal buffer/line driver Schmitt
74HC7541 2.0 to 6.0 CMOS ±7.8 11 50 pF 36 8 -40 to +125
trigger (3-state)
Octal buffer/line driver Schmitt
74HCT7541 4.5 to 5.5 TTL ±6 16 50 pF 36 8 -40 to +125
trigger; TTL-enabled (3-state)
9-bit inverter Schmitt trigger; open
74HC9114 2.0 to 6.0 CMOS 5,2 12 50 pF 36 9 -40 to +125
drain (3-state)
9-bit inverter Schmitt trigger; open
74HCT9114 4.5 to 5.5 TTL 4 13 50 pF 36 9 -40 to +125
drain; TTL-enabled (3-state)
9-bit buffer Schmitt trigger; open
74HC9115 2.0 to 6.0 CMOS 5,2 12 50 pF 36 9 -40 to +125
drain (3-state)
9-bit buffer Schmitt trigger; open
74HCT9115 4.5 to 5.5 TTL 4 13 50 pF 36 9 -40 to +125
drain; TTL-enabled (3-state)
74HC7014 Hex buffer precision Schmitt trigger 2.0 to 6.0 CMOS ±5.2 27 50 pF 36 6 -40 to +125
Quad 2-input NAND gate Schmitt
74LV132 1.0 to 5.5 TTL ±12 10 50 pF 30 4 -40 to +125
trigger
74LV14 Hex inverter Schmitt trigger 1.0 to 5.5 TTL ±12 13 50 pF 30 6 -40 to +125
Quad 2-input NAND gate Schmitt CMOS/
74LVC132 1.2 to 3.6 ±24 3.4 50 pF 175 4 -40 to +125
trigger LVTTL
CMOS/
74LVC14 Hex inverter Schmitt trigger 1.2 to 3.6 ±24 3.2 50 pF 175 6 -40 to +125
LVTTL
CMOS/
74LVC1G14 Single inverter Schmitt trigger 1.65 to 5.5 ±32 3 50 pF 175 1 -40 to +125
LVTTL
CMOS/
74LVC1G17 Single buffer Schmitt trigger 1.65 to 5.5 ±32 3 50 pF 175 1 -40 to +125
LVTTL
CMOS/
74LVC2G14 Dual inverter Schmitt trigger 1.65 to 5.5 ±32 3.9 50 pF 175 2 -40 to +125
LVTTL
CMOS/
74LVC2G17 Dual buffer Schmitt trigger 1.65 to 5.5 ±32 3.6 50 pF 175 2 -40 to +125
LVTTL
CMOS/
74LVC3G14 Triple inverter Schmitt trigger 1.65 to 5.5 ±32 3.2 50 pF 175 3 -40 to +125
LVTTL
CMOS/
74LVC3G17 Triple buffer Schmitt trigger 1.65 to 5.5 ±32 3.6 50 pF 175 3 -40 to +125
LVTTL
74LVT14 Hex inverter Schmitt trigger 2.7 to 3.6 TTL -32 / +64 3.8 50 pF 150 6 -40 to +125
Hex inverter Schmitt trigger;
74VHCT14 4.5 to 5.5 TTL ±8 4.1 50 pF 60 6 -40 to +125
TTL-enabled
HEF40106 Hex inverter Schmitt trigger 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 6 -40 to +85
Quad 2-input NAND gate Schmitt
HEF4093 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 4 -40 to +125
trigger
Single inverter Schmitt trigger;
XC7SET14 4.5 to 5.5 TTL ±8 4.1 50 pF 60 1 -40 to +125
TTL-enabled
XC7SH14 Single inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125
XC7WH14 Triple inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 3 -40 to +125
Triple inverter Schmitt trigger;
XC7WT14 4.5 to 5.5 TTL ±8 4.1 50 pF 60 3 -40 to +125
TTL-enabled

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 101

SHIFT REGISTERS/LED DRIVERS
Features and benefits Applications
4 
Simple control interface 4 LED displays
A synchronous and synchronous load options
4  4 Control units
High frequency
4  4 I/O expansion
Cascadable
4 

Shift registers - LED drivers (cont.)

Output
Logic Output
drive tpd fmax Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ)
(mA)
74AHC164 8-bit serial-in/parallel-out shift register 2.0 to 5.5 CMOS ±8 4.5 50 pF 115 8 -40 to +125
8-bit serial-in/parallel-out shift
74AHCT164 4.5 to 5.5 TTL ±8 3.4 50 pF 115 8 -40 to +125
register; TTL-enabled
8-bit serial-in/parallel-out shift register
74AHC594 2.0 to 5.5 CMOS ±8 4.1 50 pF 160 8 -40 to +125
with output storage register
8-bit serial-in/parallel-out shift register
74AHCT594 with output storage register; 4.5 to 5.5 TTL ±8 3.8 50 pF 160 8 -40 to +125
TTL-enabled
8-bit serial-in/parallel-out shift register
74AHC595 2.0 to 5.5 CMOS ±8 4 50 pF 170 8 -40 to +125
with output storage register (3-state)
8-bit serial-in/parallel-out shift register
74AHCT595 with output storage register; 4.5 to 5.5 TTL ±8 3.8 50 pF 170 8 -40 to +125
TTL-enabled (3-state)
74HC164 8-bit serial-in/parallel-out shift register 2.0 to 6.0 CMOS ±5.2 12 50 pF 78 8 -40 to +125
8-bit serial-in/parallel-out shift
74HCT164 2.0 to 6.0 CMOS ±5.2 12 50 pF 78 8 -40 to +125
register; TTL-enabled
8-bit parallel or serial-in/serial-out
74HC165 2.0 to 6.0 CMOS ±5.2 16 50 pF 56 8 -40 to +125
shift register
8-bit parallel or serial-in/serial-out
74HCT165 4.5 to 5.5 TTL ±4 14 50 pF 48 8 -40 to +125
shift register; TTL-enabled
8-bit parallel or serial-in/serial-out
74HC166 2.0 to 6.0 CMOS ±5.2 15 50 pF 63 8 -40 to +125
shift register
8-bit parallel or serial-in/serial-out
74HCT166 4.5 to 5.5 TTL ±4.0 23 50 pF 50 8 -40 to +125
shift register; TTL-enabled
4-bit bidirectional parallel or serial-in/
74HC194 2.0 to 6.0 CMOS ±5.2 14 50 pF 102 4 -40 to +125
parallel-out shift register
4-bit bidirectional parallel or serial-in/
74HCT194 4.5 to 5.5 TTL ±4 15 50 pF 77 4 -40 to +125
parallel-out shift register; TTL-enabled
74HC299 8-bit universal shift register (3-state) 2.0 to 6.0 CMOS ±7.8 19 50 pF 54 8 -40 to +125
8-bit universal shift register;
74HCT299 4.5 to 5.5 TTL ±6 19 50 pF 46 8 -40 to +125
TTL-enabled (3-state)
Dual 4-bit serial-in/parallel-out shift
74HC4015 2.0 to 6.0 CMOS ±5.2 15 50 pF 85 4 -40 to +125
register
Dual 4-bit serial-in/parallel-out shift
74HCT4015 4.5 to 5.5 TTL ±4 18 50 pF 74 4 -40 to +125
register; TTL-enabled
8-bit serial-in/serial or parallel-out
74HC4094 shift register with output register 2.0 to 6.0 CMOS ±5.2 15 50 pF 95 8 -40 to +125
(3-state)
8-bit serial-in/serial or parallel-out
74HCT4094 shift register with output register; 4.5 to 5.5 TTL ±4 19 50 pF 86 8 -40 to +125
TTL-enabled (3-state)
8-bit serial-in/parallel-out shift register
74HC594 2.0 to 6.0 CMOS ±7.8 14 50 pF 109 8 -40 to +125
with output storage register
8-bit serial-in/parallel-out shift register
74HCT594 with output storage register; 4.5 to 5.5 TTL ±6 15 50 pF 100 8 -40 to +125
TTL-enabled

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

102 NXP Logic selection guide 2016

Shift registers - LED drivers (cont.)
Output
Logic Output
drive tpd fmax Number
Type number Description VCC (V) switching Load Tamb (°C)
capability (ns) (MHz) of bits
levels CL (Typ)
(mA)
8-bit serial-in/parallel-out shift register
74HC595 2.0 to 6.0 CMOS ±7.8 16 50 pF 108 8 -40 to +125
with output storage register (3-state)
8-bit serial-in/parallel-out shift register
74HCT595 with output storage register; 4.5 to 5.5 TTL ±6 25 50 pF 57 8 -40 to +125
TTL-enabled (3-state)
8-bit parallel or serial-in/parallel-
74HC597 out shift register with parallel input 2.0 to 6.0 CMOS ±5.2 16 50 pF 108 8 -40 to +125
storage register
8-bit parallel or serial-in/parallel-
74HCT597 out shift register with parallel input 4.5 to 5.5 TTL ±4 20 50 pF 83 8 -40 to +125
storage register; TTL-enabled
74HC7731 Quad 64-bit shift register 2.0 to 6.0 CMOS ±5.2 15 50 pF 100 64 -40 to +125
Quad 64-bit shift register;
74HCT7731 4.5 to 5.5 TTL ±4 20 50 pF 100 64 -40 to +125
TTL-enabled
74LV164 8-bit serial-in/parallel-out shift register 1.0 to 5.5 TTL ±12 12 50 pF 78 8 -40 to +125
8-bit parallel or serial-in/serial-out
74LV165 1.0 to 5.5 TTL ±12 18 50 pF 78 8 -40 to +125
shift register
8-bit serial-in/serial or parallel-out
74LV4094 shift register with output register 1.0 to 3.6 TTL ±6 14 50 pF 95 8 -40 to +125
(3-state)
8-bit serial-in/parallel-out shift register
74LV595 1.0 to 3.6 TTL ±8 15 50 pF 77 8 -40 to +125
with output storage register (3-state)
8-bit serial-in/parallel-out shift register CMOS/
74LVC594 1.2 to 5.5 ±24 3.1 50 pF 180 8 -40 to +125
with output storage register LVTTL
8-bit serial-in/parallel-out shift register CMOS/
74LVC595 1.2 to 5.5 ±24 4 50 pF 180 8 -40 to +125
with output storage register (3-state) LVTTL
8-bit serial-in/parallel-out shift register
74VHC595 2.0 to 5.5 CMOS ±8 4 50 pF 170 8 -40 to +125
with output storage register (3-state)
8-bit serial-in/parallel-out shift register
74VHCT595 with output storage register; 4.5 to 5.5 TTL ±8 3.8 50 pF 170 8 -40 to +125
TTL-enabled (3-state)
8-bit shift register with synchronous
HEF4014 4.5 to 15 CMOS ±2.4 40 50 pF 40 8 -40 to +85
parallel enable
dual 4-bit serial-in/parallel-out shift
HEF4015 4.5 to 15 CMOS ±2.4 40 50 pF 44 4 -40 to +85
register
8-bit shift register with asynchronous
HEF4021 4.5 to 15 CMOS ±2.4 40 50 pF 40 8 -40 to +85
parallel load
8-bit serial-in/serial or parallel-out
HEF4094 shift register with output register 4.5 to 15 CMOS ±2.4 50 50 pF 28 8 -40 to +85
(3-state)
Dual 64-bit serial-in/parallel-out shift
HEF4517 4.5 to 15 CMOS ±2.4 60 50 pF 16 64 -40 to +85
register
1-to-64-bit shift register with variable
HEF4557 4.5 to 15 CMOS ±2.4 65 50 pF 20 64 -40 to +85
length
8-bit serial-in/serial or parallel-out
HEF4794 shift register with output register LED 4.5 to 15 CMOS -20 45 50 pF 28 8 -40 to +85
driver (3-state)
12-bit serial-in/serial or parallel-out
HEF4894 shift register with output register LED 4.5 to 15 CMOS 20 45 50 pF 28 12 -40 to +85
driver (3-state)
12-bit serial-in/parallel-out shift
NPIC6C4894 register with output storage register 4.5 to 5.5 CMOS 100 90 30 pF 10 12 -40 to +125
(3-state)
8-bit serial-in/parallel-out shift register
NPIC6C595 4.5 to 5.5 CMOS 100 90 30 pF 10 8 -40 to +125
with output storage register (3-state)
8-bit serial-in/serial or parallel-out
NPIC6C596 shift register with output register LED 4.5 to 5.5 CMOS 100 90 30 pF 10 8 -40 to +125
driver (3-state)

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 103

TRANSCEIVERS
Features and benefits 4 
Optional TTL inputs, source-termination resistors,
Bidirectional operation
4  overvoltage-tolerant inputs, bus hold
Mixed 3.3/5 V applications
4 
Widths from 4 to 32 bits
4  Applications
Improve the current drive and signal levels
4  4 Parallel backplanes
Improve signal integrity in complex layouts
4  4 Telecommunications infrastructure
Wide range of supply voltages
4  4 Industrial control
Low propagation delay
4  4 Test systems
Registered options
4 

Transceivers (cont.)

Logic Output Output

tpd Number fmax
Type number Description VCC (V) switching drive Load
(ns) of bits (MHz)
levels capability CL (Typ)

74AHC245 Octal transceiver (3-state) 2.0 to 5.5 CMOS ±8 3.5 8 60 50 pF

74AHCT245 Octal transceiver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 5 8 60 50 pF

74ALVC16245 16-bit transceiver (3-state) 1.65 to 3.6 TTL ±24 1.9 16 150 50 pF

74ALVCH16245 16-bit transceiver with bus hold (3-state) 1.65 to 3.6 TTL ±24 1.9 16 150 50 pF

74ALVC245 Octal transceiver (3-state) 1.65 to 3.6 TTL ±24 2.3 8 130 50 pF

16-bit transceiver with bus hold and 30 Ω

74ALVCH162245 1.65 to 3.6 TTL ±12 2.4 16 150 50 pF
termination resistors (3-state)

18-bit universal bus transceiver with bus hold and

74ALVCH162601 30 Ω termination resistors; positive-edge trigger 1.65 to 3.6 TTL ±12 3.1 18 150 50 pF
(3-state)

18-bit universal bus transceiver with bus hold;

74ALVCH16500 1.65 to 3.6 TTL ±24 2.9 18 150 50 pF
negative edge trigger (3-state)

18-bit universal bus transceiver with bus hold;

74ALVCH16501 1.65 to 3.6 TTL ±24 2.8 18 150 50 pF
positive edge trigger (3-state)

74ALVCH16543 16-bit registered transceiver with bus hold (3-state) 1.65 to 3.6 TTL ±24 3.8 16 150 50 pF

18-bit universal bus transceiver with bus hold;

74ALVCH16600 1.65 to 3.6 TTL ±24 2.8 18 150 50 pF
negative edge trigger (3-state)

18-bit universal bus transceiver with bus hold;

74ALVCH16601 1.65 to 3.6 TTL ±24 2.8 18 150 50 pF
positive edge trigger (3-state)

74ALVCH16646 16-bit registered transceiver with bus hold (3-state) 1.65 to 3.6 TTL ±24 2.6 16 150 50 pF

74ALVCH16952 16-bit registered transceiver with bus hold (3-state) 1.65 to 3.6 TTL ±24 3.2 16 150 50 pF

16-bit transceiver with bus hold and 30 Ω

74ALVT162245 2.3 to 3.6 TTL ±12 2.3 16 75 50 pF
termination resistors (3-state)

74ALVT16245 16-bit transceiver with bus hold (3-state) 2.3 to 3.6 TTL -32 / +64 1.5 16 200 50 pF

18-bit universal bus transceiver with bus hold;

74ALVT16501 2.3 to 3.6 TTL -32 / +64 1.8 18 150 50 pF
positive edge trigger (3-state)

74ALVT16543 16-bit registered transceiver with bus hold (3-state) 2.3 to 3.6 TTL -32 / +64 1.8 16 200 50 pF

18-bit universal bus transceiver with bus hold;

74ALVT16601 2.3 to 3.6 TTL -32 / +64 1.9 18 200 50 pF
positive edge trigger (3-state)

74ALVT16652 16-bit registered transceiver with bus hold (3-state) 2.3 to 3.6 TTL -32 / +64 2.4 16 150 50 pF

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

104 NXP Logic selection guide 2016

Transceivers (cont.)

Logic Output Output

tpd Number fmax
Type number Description VCC (V) switching drive Load
(ns) of bits (MHz)
levels capability CL (Typ)

74AVC16245 16-bit transceiver (3-state) 1.2 to 3.6 CMOS ±12 2 16 200 30 pF

74AVCH16245 16-bit transceiver with bus hold (3-state) 1.2 to 3.6 CMOS ±12 2 16 200 30 pF

74HC245 Octal transceiver (3-state) 2.0 to 6.0 CMOS ±7.8 7 8 36 50 pF

74HCT245 Octal transceiver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 10 8 36 50 pF

74HC640 Octal transceiver; inverting (3-state) 2.0 to 6.0 CMOS ±7.8 9 8 36 50 pF

74HCT640 Octal transceiver; inverting; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 9 8 36 50 pF

74HC652 Octal registered transceiver (3-state) 2.0 to 6.0 CMOS ±7.8 13 8 36 50 pF

74HCT652 Octal registered transceiver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 13 8 36 50 pF

74LV245 Octal transceiver (3-state) 1.0 to 5.5 TTL ±16 7 8 30 50 pF

16-bit transceiver with 30 Ω termination resistors CMOS/

74LVC162245 1.2 to 3.6 ±12 3.3 16 175 50 pF
(3-state) LVTTL

16-bit transceiver with bus hold and 30 Ω CMOS/

74LVCH162245 1.2 to 3.6 ±12 3.3 16 175 50 pF
termination resistors (3-state) LVTTL

CMOS/
74LVC16245 16-bit transceiver (3-state) 1.2 to 3.6 ±24 3 16 175 50 pF
LVTTL

CMOS/
74LVCH16245 16-bit transceiver with bus hold (3-state) 1.2 to 3.6 ±24 3 16 175 50 pF
LVTTL

CMOS/
74LVC245 Octal transceiver (3-state) 1.2 to 3.6 ±24 2.9 8 175 50 pF
LVTTL

CMOS/
74LVCH245 Octal transceiver with bus hold (3-state) 1.2 to 3.6 ±24 2.9 8 175 50 pF
LVTTL

Octal transceiver with 30 Ω termination resistors CMOS/

74LVC2245 1.2 to 3.6 ±12 3.3 8 175 50 pF
(3-state) LVTTL

Octal registered transceiver with 30 Ω termination CMOS/

74LVC2952 1.2 to 3.6 ±24 4.3 8 175 50 pF
resistors (3-state) LVTTL

CMOS/
74LVC32245 32-bit transceiver (3-state) 1.2 to 3.6 ±24 2.2 32 175 50 pF
LVTTL

CMOS/
74LVC543 Octal registered transceiver (3-state) 1.2 to 3.6 ±24 3.3 8 175 50 pF
LVTTL

CMOS/
74LVC544 Octal registered transceiver; inverting (3-state) 1.2 to 3.6 ±24 4 8 175 50 pF
LVTTL

CMOS/
74LVC623 Octal transceiver with dual enable (3-state) 1.2 to 3.6 ±24 3.3 8 175 50 pF
LVTTL

CMOS/
74LVC646 Octal registered transceiver (3-state) 1.2 to 3.6 ±24 3.9 8 175 50 pF
LVTTL

32-bit transceiver with bus hold and 30 Ω CMOS/

74LVCH322245 1.2 to 3.6 ±12 3.3 32 175 50 pF
termination resistors (3-state) LVTTL

CMOS/
74LVCH32245 32-bit transceiver with bus hold (3-state) 1.2 to 3.6 ±24 3 32 175 50 pF
LVTTL

74LVT16245 16-bit transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF

74LVTH16245 16-bit transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF

Octal transceiver with bus hold and 30 Ω termination

74LVT2245 2.7 to 3.6 TTL ±12 3.2 8 150 50 pF
resistors (3-state)

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

NXP Logic selection guide 2016 105

 Transceivers (cont.)

Logic Output Output

tpd Number fmax
Type number Description VCC (V) switching drive Load
(ns) of bits (MHz)
levels capability CL (Typ)

Octal transceiver with bus hold and 30 Ω termination

74LVTH2245 2.7 to 3.6 TTL ±12 3.2 8 150 50 pF
resistors (3-state)

16-bit transceiver with bus hold and 30 Ω

74LVT162245 2.7 to 3.6 TTL ±12 2.5 16 150 50 pF
termination resistors (3-state)

18-bit universal bus transceiver with bus hold;

74LVT16500 2.7 to 3.6 TTL -32 / +64 1.9 18 150 50 pF
negative-edge trigger (3-state)

18-bit universal bus transceiver with bus hold;

74LVT16501 2.7 to 3.6 TTL -32 / +64 1.9 18 150 50 pF
positive-edge trigger (3-state)

74LVT16543 16-bit registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 2.2 16 150 50 pF

74LVT16646 16-bit registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF

74LVT16652 16-bit registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF

74LVT245 Octal transceiver (3-state) 2.7 to 3.6 TTL -32 / +64 2.4 8 150 50 pF

Octal registered transceiver with 30 Ω termination

74LVT2952 2.7 to 3.6 TTL -32 / +64 3.8 8 150 50 pF
resistors (3-state)

74LVT543 Octal registered transceiver (3-state) 2.7 to 3.6 TTL -32 / +64 3 8 150 50 pF

74LVT543 Octal registered transceiver (3-state) 2.7 to 3.6 TTL -32 / +64 3 8 150 50 pF

74LVT640 Octal transceiver with bus hold; inverting (3-state) 2.7 to 3.6 TTL -32 / +64 2.4 8 150 50 pF

74LVT646 Octal registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 3.8 8 150 50 pF

74LVT652 Octal registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 3.7 8 150 50 pF

32-bit transceiver with bus hold and 30 Ω

74LVTH322245 2.7 to 3.6 TTL ±12 2.5 32 150 50 pF
termination resistors (3-state)

74LVTH32245 32-bit transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 32 150 50 pF

74LVTN16245 16-bit transceiver (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF

74VHC245 Octal transceiver (3-state) 2.0 to 5.5 CMOS ±8 3.5 8 60 50 pF

74VHCT245 Octal transceiver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 5 8 60 50 pF

Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.

106 NXP Logic selection guide 2016

 Q100 Standard Logic functions & packages

Standard logic functions include options suitable for use at supply voltage between 1.0 V and 15 V. They provide a wide range of
functions such as analog switches, buffers/inverters, bus switches, counters, decoders/de-multiplexers, multiplexers, flip-flops,
gates, latches, level shifters, multivibrators, Schmitt triggers, shift registers and transceivers. Q100 Standard logic is available in
leaded SO and TSSOP packages as well as the innovative leadless DQFN package. NXP’s DQFN packages include side-wettable
flanks, making them suitable for automated optical inspection. The package suffixes used in the tables are for all logic families
with the exception of HEF4000B. The suffixes for HEF4000B can be found under Standard Logic Packages.

Analog switches
Features Package (suffix)

SOT402-1 (PW)

SOT403-1 (PW)
SOT762-1 (BQ)

SOT763-1 (BQ)
Configuration

SOT108-1 (D)

SOT109-1 (D)

SOT137-1 (D)
RON (FLAT) (W)

Tamb (°C)
RON (W)
VCC (V)
Type number Description

74HC4051-Q100 Single-pole, octal-throw analog switch SP8T-Z 2.0 - 10.0 200 20 -40~125 • • •

Single-pole, octal-throw analog switch;

74HCT4051-Q100 SP8T-Z 4.5 - 5.5 225 20 -40~125 • • •
TTL-enabled

74HC4052-Q100 Dual single-pole, quad-throw analog switch SP4T-Z 2.0 - 10.0 200 20 -40~125 • • •

Dual single-pole, quad-throw analog switch;

74HCT4052-Q100 SP4T-Z 4.5 - 5.5 200 20 -40~125 • • •
TTL-enabled

Triple single-pole, double-throw analog

74HC4053-Q100 SP8T-Z 2.0 - 10.0 200 20 -40~125 • • •
switch

Triple single-pole, double-throw analog

74HCT4053-Q100 SP8T-Z 4.5 - 5.5 200 20 -40~125 • • •
switch; TTL-enabled

74HC4066-Q100 Quad single-pole, single-throw analog switch SPST-NO 2.0 - 10.0 105 23 -40~125 • • •

Quad single-pole, single-throw analog

74HCT4066-Q100 SPST-NO 4.5 - 5.5 118 23 -40~125 • • •
switch; TTL-enabled

74HC4851-Q100 Single-pole, octal-throw analog switch SP8T-Z 2.0 - 10.0 220 - -40~125 • • •

Single-pole, octal-throw analog switch;

74HCT4851-Q100 SP8T-Z 4.5 - 5.5 240 - -40~125 • • •
TTL-enabled

74HC4852-Q100 Dual single-pole, quad-throw analog switch SP4T-Z 2.0 - 10.0 220 - -40~125 • • •

Dual single-pole, quad-throw analog switch;

74HCT4852-Q100 SP4T-Z 4.5 - 5.5 240 - -40~125 • • •
TTL-enabled

74LV4052-Q100 Dual single-pole, quad-throw analog switch SP4T-Z 1.0 - 6.0 125 15 -40~125 • •

Triple single-pole, double-throw analog

74LV4053-Q100 SPDT-Z 1.0 - 6.0 150 30 -40~125 • • •
switch

74LVC4066-Q100 Quad single-pole, single-throw analog switch SPST-NO 1.65 - 5.5 15 1.5 -40~125 • • •

HEF4051B-Q100 Single-pole, octal-throw analog switch SP8T-Z 4.5 - 15.5 175 30 -40~85 • •

HEF4052B-Q100 Dual single-pole, quad-throw analog switch SP4T-Z 4.5 - 15.5 175 30 -40~85 • •

Triple single-pole, double-throw analog

HEF4053B-Q100 SPDT-Z 4.5 - 15.5 175 30 -40~85 • •
switch

HEF4066B-Q100 Quad single-pole, single-throw analog switch SPST-NO 4.5 - 15.5 175 20 -40~85 •

HEF4067B-Q100 Single-pole, 16-throw analog switch SP16T-Z 4.5 - 15.5 175 20 -40~85 •

NXP Logic selection guide 2016 107

 Buffers/inverters (cont.)
Features Package (suffix)

SOT362-1 (DGG)
SOT402-1 (PW)

SOT403-1 (PW)

SOT360-1 (PW)
SOT762-1 (BQ)

SOT764-1 (BQ)
SOT337-1 (DB)

SOT339-1 (DB)
SOT108-1 (D)

SOT109-1 (D)

SOT163-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description
74AHC04-Q100 Hex inverter 2.0 - 5.5 ±8 3 -40~125 • • •
74AHCT04-Q100 Hex inverter; TTL-enabled 4.5 - 5.5 ±8 3 -40~125 • • •
74AHC125-Q100 Quad buffer/line driver (3-state) 2.0 - 5.5 ±8 3 -40~125 • • •
Quad buffer/line driver;
74AHCT125-Q100 4.5 - 5.5 ±8 3 -40~125 • • •
TTL-enabled (3-state)
74AHC126-Q100 Quad buffer/line driver (3-state) 2.0 - 5.5 ±8 3.3 -40~125 • • •
Quad buffer/line driver;
74AHCT126-Q100 4.5 - 5.5 ±8 3 -40~125 • • •
TTL-enabled (3-state)
Octal inverter/line driver
74AHC240-Q100 2.0 - 5.5 ±8 2.8 -40~125 • • •
(3-state)
Octal inverter/line driver;
74AHCT240-Q100 4.5 - 5.5 ±8 3 -40~125 • • •
TTL-enabled (3-state)
74AHC244-Q100 Octal buffer/line driver (3-state) 2.0 - 5.5 ±8 3.5 -40~125 • • •
Octal buffer/line driver;
74AHCT244-Q100 4.5 - 5.5 ±8 3.5 -40~125 • • •
TTL-enabled (3-state)
74AHC541-Q100 Octal buffer/line driver (3-state) 2.0 - 5.5 ±8 3.5 -40~125 • • •
Octal buffer/line driver;
74AHCT541-Q100 4.5 - 5.5 ±8 3.5 -40~125 • • •
TTL-enabled (3-state)
74AHCU04-Q100 Hex inverter; unbuffered 2.0 - 5.5 ±8 2.4 -40~125 • • •
74ALVC125-Q100 Quad buffer/line driver (3-state) 1.65 - 3.6 ± 24 1.8 -40~85 • • •
74ALVC541-Q100 Octal buffer/line driver (3-state) 1.65 - 3.6 ± 24 2.3 -40~85 • • •
74HC05-Q100 Hex inverter; open-drain 2.0 - 6.0 5.2 11 -40~125 • • •
74HC04-Q100 Hex inverter 2.0 - 6.0 ± 5.2 7 -40~125 • • • •
74HCT04-Q100 Hex inverter; TTL-enabled 4.5 - 5.5 ± 4.0 8 -40~125 • • •
74HC125-Q100 Quad buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 9 -40~125 • •
Quad buffer/line driver;
74HCT125-Q100 4.5 - 5.5 ±6 12 -40~125 • •
TTL-enabled (3-state)
74HC126-Q100 Quad buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 9 -40~125 • •
Quad buffer/line driver;
74HCT126-Q100 4.5 - 5.5 ±6 11 -40~125 • •
TTL-enabled (3-state)
Octal inverter/line driver
74HC240-Q100 2.0 - 6.0 ± 7.8 9 -40~125 • • •
(3-state)
Octal inverter/line driver;
74HCT240-Q100 4.5 - 5.5 ±6 9 -40~125 • • •
TTL-enabled (3-state)
74HC244-Q100 Octal buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 9 -40~125 • • •
Octal buffer/line driver;
74HCT244-Q100 4.5 - 5.5 ±6 11 -40~125 • • •
TTL-enabled (3-state)
74HC365-Q100 Hex buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 9 -40~125 • •
Hex buffer/line driver;
74HCT365-Q100 4.5 - 5.5 ±6 11 -40~125 • •
TTL-enabled (3-state)
74HC366-Q100 Hex inverter/line driver (3-state) 2.0 - 6.0 ± 7.8 10 -40~125 • •
Hex inverter/line driver;
74HCT366-Q100 4.5 - 5.5 ±6 11 -40~125 • •
TTL-enabled (3-state)

108 NXP Logic selection guide 2016

Buffers/inverters (cont.)
Features Package (suffix)

SOT362-1 (DGG)
SOT402-1 (PW)

SOT403-1 (PW)

SOT360-1 (PW)
SOT762-1 (BQ)

SOT764-1 (BQ)
SOT337-1 (DB)

SOT339-1 (DB)
SOT108-1 (D)

SOT109-1 (D)

SOT163-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description
Octal inverter/line driver
74HC540-Q100 2.0 - 6.0 ± 7.8 9 -40~125 •
(3-state)
Octal inverter/line driver;
74HCT540-Q100 4.5 - 5.5 ±6 11 -40~125 •
TTL-enabled (3-state)
74HC541-Q100 Octal buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 10 -40~125 • •
Octal buffer/line driver;
74HCT541-Q100 4.5 - 5.5 ±6 12 -40~125 • •
TTL-enabled (3-state)
74HCU04-Q100 Hex inverter; unbuffered 2.0 - 6.0 ± 5.2 5 -40~125 • • •
74LV244-Q100 Octal buffer/line driver (3-state) 1.0 - 5.5 ± 16 8 -40~125 • •
74LVC04A-Q100 Hex inverter 1.65 - 5.5 ± 24 2 -40~125 • • •
74LVC06A-Q100 Hex inverter; open-drain 1.65 - 5.5 32 2.2 -40~125 • • •
74LVC07A-Q100 Hex buffer; open-drain 1.65 - 5.5 32 2.2 -40~125 • • •
74LVC125A-Q100 Quad buffer/line driver (3-state) 1.2 - 3.6 ± 24 2.4 -40~125 • • •
74LVC126A-Q100 Quad buffer/line driver (3-state) 1.2 - 3.6 ± 24 2.4 -40~125 • • •
74LVC541A-Q100 Octal buffer/line driver (3-state) 1.2 - 3.6 ± 24 3.3 -40~125 • • •
16-bit inverter/line driver
74LVC16240A-Q100 1.2 - 3.6 ± 24 2.7 -40~125 •
(3-state)
74LVC244A-Q100 Octal buffer/line driver (3-state) 1.2 - 3.6 ± 24 2.8 -40~125 • • • •
Octal buffer/line driver with bus
74LVCH244A-Q100 1.2 - 3.6 ± 24 2.8 -40~125 • • •
hold (3-state)
74LVC16244A-Q100 16-bit buffer/line driver (3-state) 1.2 - 3.6 ± 24 3 -40~125 •
16-bit buffer/line driver with
74LVCH16244A-Q100 1.2 - 3.6 ± 24 3 -40~125 •
bus hold (3-state)
74LVT04-Q100 Hex inverter 2.7 - 3.6 -20 / +32 2.6 -40~85 • • •
Octal buffer/line driver with bus
74LVT244A-Q100 2.7 - 3.6 -32 / +64 2.6 -40~85 • •
hold (3-state)
Octal buffer/line driver with bus
74LVTH244A-Q100 2.7 - 3.6 -32 / +64 2.6 -40~85 • •
hold (3-state)
74VHC126-Q100 Quad buffer/line driver (3-state) 2.0 - 5.5 ±8 3.3 -40~125 • • •
Quad buffer/line driver;
74VHCT126-Q100 4.5 - 5.5 ±8 3 -40~125 • • •
TTL-enabled (3-state)
74VHC541-Q100 Octal buffer/line driver (3-state) 2.0 - 5.5 ±8 3.5 -40~125 • • •
Octal buffer/line driver;
74VHCT541-Q100 4.5 - 5.5 ±8 3.5 -40~125 • • •
TTL-enabled (3-state)
HEF4049B-Q100 Hex inverter/line driver 3.0 - 15.0 -3 / +20 20 -40~85 •
HEF4050B-Q100 Hex buffer/line driver 3.0 - 15.0 -3 / +20 40 -40~85 •
HEF4069UB-Q100 Hex inverter; unbuffered 3.0 - 15.0 ± 3.4 15 -40~85 • •

NXP Logic selection guide 2016 109

 Bus switches
Features Package (suffix)

SOT402-1 (PW)

SOT403-1 (PW)

SOT360-1 (PW)
SOT762-1 (BQ)

SOT763-1 (BQ)

SOT764-1 (BQ)
SOT519-1 (DS)
SOT109-1 (D)

SOT163-1 (D)
Tamb (°C)
VPASS (V)

RON (W)
VCC (V)
Type number Description

74CBTLV3126-Q100 Quad bus switch 2.3 - 3.6 3.3 7 -40~125 • •

74CBTLV3253-Q100 Dual 4:1 mux/demux 2.3 - 3.6 3.3 7 -40~125 • • •

74CBTLV3257-Q100 Quad 2:1 mux/demux 2.3 - 3.6 3.3 7 -40~125 • • • •

CBT3245A-Q100 Octal bus switch 4.5 - 5.5 3.9 7 -40~85 • • •

Counters/frequency dividers (cont.)

Features Package (suffix)

SOT402-1 (PW)

SOT403-1 (PW)
SOT762-1 (BQ)

SOT763-1 (BQ)
SOT338-1 (DB)
SOT108-1 (D)

SOT109-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)

Type number Description

74HC4024-Q100 7-stage binary ripple counter 2.0 - 6.0 ± 5.2 14 -40~125 • •

Presettable synchronous 4-bit binary counter;

74HC163-Q100 2.0 - 6.0 ± 5.2 17 -40~125 • •
synchronous reset

Presettable synchronous 4-bit binary counter;

74HCT163-Q100 4.5 - 5.5 ± 4.0 20 -40~125 • •
synchronous reset; TTL-enabled

Presettable synchronous 4-bit binary up/down

74HC193-Q100 2.0 - 6.0 ± 5.2 20 -40~125 • • •
counter

Presettable synchronous 4-bit binary up/down

74HCT193-Q100 4.5 - 5.5 ± 4.0 20 -40~125 • • •
counter; TTL-enabled

74HC393-Q100 Dual 4-bit binary ripple counter 2.0 - 6.0 ± 5.2 12 -40~125 • • •

74HCT393-Q100 Dual 4-bit binary ripple counter; TTL-enabled 4.5 - 5.5 ± 4.0 20 -40~125 • • •

74HC4017-Q100 Johnson decade counter with 10 decoded outputs 2.0 - 6.0 ± 5.2 18 -40~125 • • •

Johnson decade counter with 10 decoded outputs;

74HCT4017-Q100 4.5 - 5.5 ± 4.0 21 -40~125 • •
TTL-enabled

74HC4020-Q100 14-stage binary ripple counter 2.0 - 6.0 ± 5.2 11 -40~125 • • •

74HCT4020-Q100 14-stage binary ripple counter; TTL-enabled 4.5 - 5.5 ± 4.0 15 -40~125 • • •

74HC4040-Q100 12-stage binary ripple counter 2.0 - 6.0 ± 5.2 14 -40~125 • • • •

74HCT4040-Q100 12-stage binary ripple counter; TTL-enabled 4.5 - 5.5 ± 4.0 16 -40~125 • • • •

74HC4060-Q100 14-stage binary ripple counter with oscillator 2.0 - 6.0 ± 5.2 31 -40~125 • • •

14-stage binary ripple counter with oscillator;

74HCT4060-Q100 4.5 - 5.5 ± 4.0 31 -40~125 • •
TTL-enabled

74HC4520-Q100 Dual 4-bit synchronous binary counter 2.0 - 6.0 ± 5.2 24 -40~125 • •

74HCT4520-Q100 Dual 4-bit synchronous binary counter; TTL-enabled 4.5 - 5.5 ± 4.0 24 -40~125 •

74LV393-Q100 Dual 4-bit binary ripple counter 1.0 - 3.6 ±6 12 -40~125 • •

110 NXP Logic selection guide 2016

Counters/frequency dividers (cont.)
Features Package (suffix)

SOT402-1 (PW)

SOT403-1 (PW)
SOT762-1 (BQ)

SOT763-1 (BQ)
SOT338-1 (DB)
SOT108-1 (D)

SOT109-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description

HEF4017B-Q100 5-stage Johnson decade counter 4.5 - 15.5 ± 2.4 40 -40~85 •

HEF4020B-Q100 14-stage binary ripple counter 4.5 - 15.5 ± 2.4 30 -40~85 •

HEF4040B-Q100 12-stage binary ripple counter 4.5 - 15.5 ± 2.4 35 -40~85 •

HEF4060B-Q100 14-stage binary ripple counter with oscillator 4.5 - 15.5 ± 2.4 50 -40~85 •

HEF4541B-Q100 programmable timer 4.5 - 15.5 - 4/ + 2.7 38 -40~85 •

Digital decoders/demultiplexers
Features Package (suffix)

SOT403-1 (PW)

SOT763-1 (BQ)
SOT338-1 (DB)
SOT109-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description

74AHC138-Q100 3-to-8 line decoder/demultiplexer; inverting 2.0 - 5.5 ±8 4.4 -40~125 • • •

74AHCT138-Q100 3-to-8 line decoder/demultiplexer; inverting; TTL-enabled 4.5 - 5.5 ±8 4.4 -40~125 • • •

74AHC139-Q100 Dual 2-to-4 line decoder/demultiplexer 2.0 - 5.5 ±8 3.9 -40~125 • •

74AHCT139-Q100 Dual 2-to-4 line decoder/demultiplexer; TTL-enabled 4.5 - 5.5 ±8 3.6 -40~125 • •

74HC237-Q100 3-to-8 decoder/demultiplexer with address latches 2.0 - 6.0 ± 5.2 18 -40~125 •

74HC138-Q100 3-to-8 line decoder/demultiplexer; inverting 2.0 - 6.0 ± 5.2 12 -40~125 • • •

74HCT138-Q100 3-to-8 line decoder/demultiplexer; inverting; TTL-enabled 4.5 - 5.5 ±4 19 -40~125 • • •

74HC139-Q100 Dual 2-to-4 line decoder/demultiplexer 2.0 - 6.0 ± 5.2 14 -40~125 • • •

74HCT139-Q100 Dual 2-to-4 line decoder/demultiplexer; TTL-enabled 4.5 - 5.5 ±4 16 -40~125 • • •

74HC238-Q100 3-to-8 decoder/demultiplexer 2.0 - 6.0 ± 5.2 14 -40~125 • • •

74HCT238-Q100 3-to-8 decoder/demultiplexer; TTL-enabled 4.5 - 5.5 ±4 18 -40~125 • • •

74LVC138A-Q100 3-to-8 line decoder/demultiplexer; inverting 1.2 - 3.6 ± 24 2.7 -40~125 • • •

HEF4555B-Q100 Dual 1-to-4 line decoder/demultiplexer 4.5 - 15 ± 2.4 30 -40~85 •

NXP Logic selection guide 2016 111

 Digital multiplexers
Features Package (suffix)

SOT403-1 (PW)

SOT763-1 (BQ)
SOT338-1 (DB)
SOT109-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description
74AHC157-Q100 Quad 2-input multiplexer 2.0 - 5.5 ±8 3.2 -40~125 • • •
74AHCT157-Q100 Quad 2-input multiplexer; TTL-enabled 4.5 - 5.5 ±8 3.2 -40~125 • • •
74AHC257-Q100 Quad 2-input multiplexer (3-State) 2.0 - 5.5 ±8 2.9 -40~125 • •
74AHCT257-Q100 Quad 2-input multiplexer; TTL-enabled (3-State) 4.5 - 5.5 ±8 3.7 -40~125 • •
74HC151-Q100 8-input multiplexer 2.0 - 6.0 ± 5.2 17 -40~125 • •
74HCT151-Q100 8-input multiplexer; TTL-enabled 4.5 - 5.5 ±4 19 -40~125 • •
74HC153-Q100 Dual 4-input multiplexer 2.0 - 6.0 ± 5.2 17 -40~125 • •
74HCT153-Q100 Dual 4-input multiplexer; TTL-enabled 4.5 - 5.5 ±4 19 -40~125 • •
74HC157-Q100 Quad 2-input multiplexer 2.0 - 6.0 ± 5.2 11 -40~125 • • •
74HCT157-Q100 Quad 2-input multiplexer; TTL-enabled 4.5 - 5.5 ±4 13 -40~125 • • •
74HC251-Q100 8-input multiplexer (3-State) 2.0 - 6.0 ± 5.2 18 -40~125 • •
74HCT251-Q100 8-input multiplexer; TTL-enabled (3-State) 4.5 - 5.5 ±4 22 -40~125 • •
74HC253-Q100 Dual 4-input multiplexer (3-State) 2.0 - 6.0 ± 7.8 17 -40~125 •
74HCT253-Q100 Dual 4-input multiplexer; TTL-enabled (3-State) 4.5 - 5.5 ±6 17 -40~125 •
74LVC157A-Q100 Quad 2-input multiplexer 1.2 - 3.6 ± 24 2.5 -40~125 • • • •

Flip-flops (cont.)
Features Package (suffix)

SOT362-1 (DGG)
SOT402-1 (PW)

SOT403-1 (PW)

SOT360-1 (PW)
SOT762-1 (BQ)

SOT764-1 (BQ)
SOT337-1 (DB)

SOT339-1 (DB)
SOT108-1 (D)

SOT109-1 (D)

SOT162-1 (D)

SOT163-1 (D)
Tamb (°C)
IO (mA)
VCC (V)

tpd (ns)

Type number Description

Dual D-type flip-flop with

74AHC74-Q100 set and reset; positive-edge 2.0 - 5.5 ±8 3.7 -40~125 • • •
trigger

Dual D-type flip-flop with

74AHCT74-Q100 set and reset; positive-edge 4.5 - 5.5 ±8 3.3 -40~125 • • •
trigger; TTL-enabled

Octal D-type flip-flop with

74AHC273-Q100 2.0 - 5.5 ±8 4.2 -40~125 • • •
reset; positive-edge trigger

Octal D-type flip-flop with

74AHCT273-Q100 reset; positive-edge trigger; 4.5 - 5.5 ±8 4 -40~125 • • •
TTL-enabled

Octal D-type flip-flop; positive-

74AHC374-Q100 2.0 - 5.5 ±8 4.4 -40~125 • •
edge trigger

Octal D-type flip-flop; positive-

74AHCT374-Q100 edge trigger (3-state); 4.5 - 5.5 ±8 4.3 -40~125 • •
TTL-enabled (3-state)

Octal D-type flip-flop with

74AHC377-Q100 data enable; positive-edge 2.0 - 5.5 ±8 3.9 -40~125 •
trigger

112 NXP Logic selection guide 2016

Flip-flops (cont.)
Features Package (suffix)

SOT362-1 (DGG)
SOT402-1 (PW)

SOT403-1 (PW)

SOT360-1 (PW)
SOT762-1 (BQ)

SOT764-1 (BQ)
SOT337-1 (DB)

SOT339-1 (DB)
SOT108-1 (D)

SOT109-1 (D)

SOT162-1 (D)

SOT163-1 (D)
Tamb (°C)
IO (mA)
VCC (V)

tpd (ns)
Type number Description

Octal D-type flip-flop with

74AHCT377-Q100 data enable; positive-edge 4.5 - 5.5 ±8 4 -40~125 • •
trigger; TTL-enabled

16-bit D-type flip-flop;

74AVC16374-Q100 1.2 - 3.6 ± 12 1.5 -40~85 •
positive-edge trigger (3-state)

Dual D-type flip-flop with

74HC74-Q100 set and reset; positive-edge 2.0 - 6.0 ± 5.2 14 -40~125 • • •
trigger

Dual D-type flip-flop with

74HCT74-Q100 set and reset; positive-edge 4.5 - 5.5 ±4 15 -40~125 • • •
trigger; TTL-enabled

Dual J-K flip-flop with reset;

74HC107-Q100 2.0 - 6.0 ± 5.2 16 -40~125 • •
negative-edge trigger

Dual J-K flip-flop with reset;

74HCT107-Q100 negative-edge trigger; 4.5 - 5.5 ±4 16 -40~125 •
TTL-enabled

Hex D-type flip-flop with reset;

74HC174-Q100 2.0 - 6.0 ± 5.2 17 -40~125 • •
positive-edge trigger

Hex D-type flip-flop with reset;

74HCT174-Q100 positive-edge trigger; 4.5 - 5.5 ±4 18 -40~125 • •
TTL-enabled

Quad D-type flip-flop with

74HC175-Q100 2.0 - 6.0 ± 5.2 17 -40~125 • •
reset; positive-edge trigger

Quad D-type flip-flop with

74HCT175-Q100 reset; positive-edge trigger; 4.5 - 5.5 ±4 16 -40~125 • •
TTL-enabled

Octal D-type flip-flop with

74HC273-Q100 2.0 - 6.0 ± 5.2 15 -40~125 • • •
reset; positive-edge trigger

Octal D-type flip-flop with

74HCT273-Q100 reset; positive-edge trigger; 4.5 - 5.5 ±4 15 -40~125 • • •
TTL-enabled

Octal D-type flip-flop with

74HC377-Q100 data enable; positive-edge 2.0 - 6.0 ± 7.8 13 -40~125 • • •
trigger

Octal D-type flip-flop with

74HCT377-Q100 data enable; positive-edge 4.5 - 5.5 ±6 14 -40~125 • • •
trigger; TTL-enabled

Octal D-type flip-flop; positive-

74HC574-Q100 2.0 - 6.0 ± 7.8 14 -40~125 • •
edge trigger (3-state)

Octal D-type flip-flop; positive-

74HCT574-Q100 edge trigger; TTL-enabled 4.5 - 5.5 ±6 15 -40~125 • •
(3-state)

Dual D-type flip-flop with

74LV74-Q100 set and reset; positive-edge 1.0 - 5.5 ± 12 11 -40~125 • •
trigger

NXP Logic selection guide 2016 113

 Flip-flops (cont.)
Features Package (suffix)

SOT362-1 (DGG)
SOT402-1 (PW)

SOT403-1 (PW)

SOT360-1 (PW)
SOT762-1 (BQ)

SOT764-1 (BQ)
SOT337-1 (DB)

SOT339-1 (DB)
SOT108-1 (D)

SOT109-1 (D)

SOT162-1 (D)

SOT163-1 (D)
Tamb (°C)
IO (mA)
VCC (V)

tpd (ns)
Type number Description

Dual D-type flip-flop with

74LVC74A-Q100 set and reset; positive-edge 1.2 - 3.6 ± 24 2.5 -40~125 • • •
trigger

Octal D-type flip-flop with

74LVC273-Q100 1.2 - 3.6 ± 24 6 -40~125 • • •
reset; positive-edge trigger

Octal D-type flip-flop; positive-

74LVC374A-Q100 1.2 - 3.6 ± 24 2.7 -40~125 • • •
edge trigger (3-state)

Octal D-type transparent latch

74LVC573A-Q100 1.2 - 3.6 ± 24 3.4 -40~125 • • •
(3-state)

16-bit D-type flip-flop;

74LVC16374A-Q100 1.2 - 3.6 ± 24 3.8 -40~125 •
positive-edge trigger (3-state)

16-bit D-type flip-flop with bus

74LVCH16374A-Q100 hold; positive-edge trigger 1.2 - 3.6 ± 24 3.8 -40~125 •
(3-state)

Dual D-type flip-flop with

HEF4013B-Q100 set and reset; positive-edge 4.5 - 15.5 ± 2.4 30 -40~85 • •
trigger

HEF4027B-Q100 Dual J-K flip-flop 4.5 - 15.5 ± 2.4 30 -40~85 •

Gates (cont.)
Features Package (suffix)

SOT402-1 (PW)

SOT762-1 (BQ)
SOT337-1 (DB)
SOT108-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)

Type number Description

74AHC00-Q100 Quad 2-input NAND gate 2.0 - 5.5 ±8 3.2 -40~125 • • •

74AHCT00-Q100 Quad 2-input NAND gate; TTL-enabled 4.5 - 5.5 ±8 3.3 -40~125 • • •

74AHC02-Q100 Quad 2-input NOR gate 2.0 - 5.5 ±8 2.9 -40~125 • • •

74AHCT02-Q100 Quad 2-input NOR gate; TTL-enabled 4.5 - 5.5 ±8 3.8 -40~125 • • •

74AHC08-Q100 Quad 2-input AND gate 2.0 - 5.5 ±8 3.5 -40~125 • • •

74AHCT08-Q100 Quad 2-input AND gate; TTL-enabled 4.5 - 5.5 ±8 5 -40~125 • • •

74AHC30-Q100 8-input NAND gate 2.0 - 5.5 ±8 3.6 -40~125 • • •

74AHCT30-Q100 8-input NAND gate; TTL-enabled 4.5 - 5.5 ±8 3.3 -40~125 • • •

74AHC32-Q100 Quad 2-input OR gate 2.0 - 5.5 ±8 3.5 -40~125 • • •

74AHCT32-Q100 Quad 2-input OR gate; TTL-enabled 4.5 - 5.5 ±8 5 -40~125 • • •

74AHC86-Q100 Quad 2-input EXCLUSIVE-OR gate 2.0 - 5.5 ±8 3.4 -40~125 • • •

74AHCT86-Q100 Quad 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 - 5.5 ±8 3.4 -40~125 • • •

114 NXP Logic selection guide 2016

Gates (cont.)
Features Package (suffix)

SOT402-1 (PW)

SOT762-1 (BQ)
SOT337-1 (DB)
SOT108-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description

74ALVC00-Q100 Quad 2-input NAND gate 1.65-3.6 ± 24 2.1 -40~85 • • •

74ALVC32-Q100 Quad 2-input OR gate 1.65 - 3.6 ± 24 2 -40~125 • • •

74HC00-Q100 Quad 2-input NAND gate 2.0 - 6.0 ± 5.2 7 -40~125 • • •

74HCT00-Q100 Quad 2-input NAND gate; TTL-enabled 4.5 - 5.5 ±4 10 -40~125 • • •

74HC02-Q100 Quad 2-input NOR gate 2.0 - 6.0 ± 5.2 7 -40~125 • • •

74HCT02-Q100 Quad 2-input NOR gate; TTL-enabled 4.5 - 5.5 ±4 9 -40~125 • • •

74HC03-Q100 Quad 2-input NAND gate; open-drain 2.0 - 6.0 5.2 8 -40~125 • • •

Quad 2-input NAND gate; open-drain;

74HCT03-Q100 4.5 - 5.5 ±4 10 -40~125 • •
TTL-enabled

74HC08-Q100 Quad 2-input AND gate 2.0 - 6.0 ± 5.2 7 -40~125 • • •

74HCT08-Q100 Quad 2-input AND gate; TTL-enabled 4.5 - 5.5 ±4 11 -40~125 • • •

74HC10-Q100 Triple 3-input NAND gate 2.0 - 6.0 ± 5.2 9 -40~125 • •

74HCT10-Q100 Triple 3-input NAND gate; TTL-enabled 4.5 - 5.5 ±4 11 -40~125 • •

74HC11-Q100 Triple 3-input AND gate 2.0 - 6.0 ± 5.2 10 -40~125 • •

74HCT11-Q100 Triple 3-input AND gate; TTL-enabled 4.5 - 5.5 ±4 11 -40~125 • •

74HC20-Q100 Dual 4-input NAND gate 2.0 - 6.0 ± 5.2 8 -40~125 • •

74HCT20-Q100 Dual 4-input NAND gate; TTL-enabled 4.5 - 5.5 ±4 13 -40~125 • •

74HC27-Q100 Triple 3-input NOR gate 2.0 - 6.0 ± 5.2 8 -40~125 • • •

74HCT27-Q100 Triple 3-input NOR gate; TTL-enabled 4.5 - 5.5 ±4 10 -40~125 • • •

74HC30-Q100 8-input NAND gate 2.0 - 6.0 ± 5.2 12 -40~125 • •

74HCT30-Q100 8-input NAND gate; TTL-enabled 4.5 - 5.5 ±4 12 -40~125 • •

74HC32-Q100 Quad 2-input OR gate 2.0 - 6.0 ± 5.2 6 -40~125 • • •

74HCT32-Q100 Quad 2-input OR gate; TTL-enabled 4.5 - 5.5 ± 4.0 9 -40~125 • • •

74HC86-Q100 Quad 2-input EXCLUSIVE-OR gate 2.0 - 6.0 ± 5.2 11 -40~125 • •

74HCT86-Q100 Quad 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 - 5.5 ±4 14 -40~125 • •

74HC4002-Q100 Dual 4-input NOR gate 2.0 - 6.0 ± 5.2 9 -40~125 • •

74HC4075-Q100 Triple 3-input OR gate 2.0 - 6.0 ± 5.2 8 -40~125 • •

74HCT4075-Q100 Triple 3-input OR gate; TTL-enabled 4.5 - 5.5 ±4 10 -40~125 • •

74LV08-Q100 Quad 2-input AND gate 1.0 - 5.5 ± 12 7 -40~125 • •

74LVC00A-Q100 Quad 2-input NAND gate 1.2 - 3.6 ± 24 2.1 -40~125 • • •

74LVC02A-Q100 Quad 2-input NOR gate 1.2 - 3.6 ± 24 2.1 -40~125 • • •

74LVC08A-Q100 Quad 2-input AND gate 1.2 - 3.6 ± 24 2.1 -40~125 • • •

74LVC32A-Q100 Quad 2-input OR gate 1.2 - 3.6 ± 24 2.1 -40~125 • • • •

74VHC02-Q100 Quad 2-input NOR gate 2.0 - 5.5 ±8 2.9 -40~125 • • •

74VHCT02-Q100 Quad 2-input NOR gate; TTL-enabled 4.5 - 5.5 ±8 3.8 -40~125 • • •

NXP Logic selection guide 2016 115

 Gates (cont.)
Features Package (suffix)

SOT402-1 (PW)

SOT762-1 (BQ)
SOT337-1 (DB)
SOT108-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description

74VHC08-Q100 Quad 2-input AND gate 2.0 - 5.5 ±8 3.5 -40~125 • •

74VHCT08-Q100 Quad 2-input AND gate; TTL-enabled 4.5 - 5.5 ±8 5 -40~125 • • •
74VHC32-Q100 Quad 2-input OR gate 2.0 - 5.5 ±8 3.5 -40~125 • •
74VHCT32-Q100 Quad 2-input OR gate; TTL-enabled 4.5 - 5.5 ±8 5 -40~125 • • •
HEF4001B-Q100 Quad 2-input NOR gate 4.5 - 15.5 ± 2.4 20 -40~85 •
HEF4011B-Q100 Quad 2-input NAND gate 4.5 - 15.5 ± 2.4 20 -40~85 •
HEF4030B-Q100 Quad 2-input EXCLUSIVE-OR gate 4.5 - 15.5 ± 2.4 30 -40~85 •
HEF4070B-Q100 Quad 2-input EXCLUSIVE-OR gate 4.5 - 15.5 ± 2.4 30 -40~85 •
HEF4081B-Q100 Quad 2-input AND gate 4.5 - 15.5 ± 2.4 20 -40~85 •

Latches/registered drivers
Features Package (suffix)

SOT362-1 (DGG)
SOT403-1 (PW)

SOT360-1 (PW)
SOT763-1 (BQ)

SOT764-1 (BQ)
SOT339-1 (DB)
SOT109-1 (D)

SOT163-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)

Type number Description

74AHC573-Q100 Octal D-type transparent latch (3-state) 2.0 - 5.5 ±8 4.2 -40~125 • • •
Octal D-type transparent latch; TTL-enabled
74AHCT573-Q100 4.5 - 5.5 ±8 3.9 -40~125 • • •
(3-state)
74HC4060-Q100 14-stage binary ripple counter with oscillator 2.0 - 6.0 ± 5.2 31 -40~125 •
74HC259-Q100 8 bit addressable latch 2.0 - 6.0 ± 5.2 18 -40~125 • • •
74HCT259-Q100 8-Bit addressable latch; TTL-enabled 4.5 - 5.5 ±4 20 -40~125 • • •
74HC373-Q100 Octal D-type transparent latch (3-state) 2.0 - 6.0 ± 7.8 12 -40~125 • • •
Octal D-type transparent latch; TTL-enabled
74HCT373-Q100 4.5 - 5.5 ±6 14 -40~125 • • •
(3-state)
74HC573-Q100 Octal D-type transparent latch (3-state) 2.0 - 6.0 ± 7.8 14 -40~125 • • • •
Octal D-type transparent latch; TTL-enabled
74HCT573-Q100 4.5 - 5.5 ±6 17 -40~125 • • •
(3-state)
74LVC373A-Q100 Octal D-type transparent latch (3-state) 1.2 - 3.6 ± 24 3 -40~125 • • • •
74LVC16373A-Q100 16-bit D-type transparent latch (3-state) 1.2 - 3.6 ± 24 2.4 -40~125 •
16-bit D-type transparent latch with bushold
74LVCH16373A-Q100 1.2 - 3.6 ± 24 2.4 -40~125 •
(3-state)
HEF4043B-Q100 Quad R/S latch with set and reset (3-state) 4.5 - 15 ± 2.4 25 -40~85 •

116 NXP Logic selection guide 2016

Level shifters/translators
Features Package (suffix)

SOT362-1 (DGG)

SOT480-1 (DGV)
SOT403-1 (PW)

SOT355-1 (PW)
SOT763-1 (BQ)

SOT815-1 (BQ)
SOT109-1 (D)

SOT137-1 (D)
VCC(A) (V)

VCC(B) (V)

Tamb (°C)
IO (mA)
Type number Description
16-bit dual-supply voltage level translating
74ALVC164245-Q100 1.5 - 3.6 1.5 - 5.5 ± 24 -40~125 •
transceiver (3-state)
4-bit dual-supply voltage level translating
74AVC4T245-Q100 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 • • •
transceiver (3-state)
8-bit dual-supply voltage level translating
74AVC8T245-Q100 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 • •
transceiver (3-state)
16-bit dual-supply voltage level translating
74AVC16T245-Q100 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 •
transceiver (3-state)
4-bit dual-supply voltage translating
74AVCH4T245-Q100 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 • • •
transceiver with bus hold (3-state)
74HC4050-Q100 Hex buffer with 15V tolerant inputs 2.0 - 6.0 n.a ± 5.2 -40~125 • •
8-bit dual-supply voltage translating
74LVC4245A-Q100 1.5 - 5.5 1.5 - 3.6 ± 24 -40~125 • • •
transceiver (3-state)
8-bit dual-supply voltage translating
74LVC8T245-Q100 1.2 - 5.5 1.2 - 5.5 ± 24 -40~125 • •
transceiver (3-state)
8-bit dual-supply voltage translating
74LVCH8T245-Q100 1.2 - 5.5 1.2 - 5.5 ± 24 -40~125 • •
transceiver with bus hold (3-state)
3.0 - 3.0 -
HEF4104B-Q100 Quad low-to-high voltage translator (3-state) ± 2.4 -40~85 •
15.0 15.0

Multivibrators
Features Package (suffix)

SOT403-1 (PW)

SOT763-1 (BQ)
SOT109-1 (D)
Tamb (°C)
IO (mA)
VCC (V)

tpd (ns)

Type number Description

74AHC123A-Q100 Dual retriggerable monostable multivibrator with reset 2.0 - 5.5 ±8 5.1 -40~125 • • •

Dual retriggerable monostable multivibrator with reset;

74AHCT123A-Q100 4.5 - 5.5 ±8 5 -40~125 • • •
TTL-enabled

74HC123-Q100 Dual retriggerable monostable multivibrator with reset 2.0 - 6.0 ± 7.8 9 -40~125 • • •

Dual retriggerable monostable multivibrator with reset;

74HCT123-Q100 4.5 - 5.5 ±4 26 -40~125 • •
TTL-enabled

74HC4538-Q100 Dual retriggerable precision monostable multivibrator 2.0 - 6.0 ± 5.2 27 -40~125 • •

Dual retriggerable precision monostable multivibrator;

74HCT4538-Q100 4.5 - 5.5 ±4 30 -40~125 • •
TTL-enabled

HEF4538B-Q100 Dual retriggerable precision monostable multivibrator 4.5 - 15.5 ± 2.4 60 -40~85 •

NXP Logic selection guide 2016 117

 Schmitt triggers
Features Package (suffix)

SOT402-1 (PW)

SOT360-1 (PW)
SOT762-1 (BQ)
SOT108-1 (D)

SOT163-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description

74AHC14-Q100 Hex inverter Schmitt trigger 2.0 - 5.5 ±8 3.2 -40~125 • • •

74AHCT14-Q100 Hex inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ±8 4 -40~125 • • •

74AHC132-Q100 Quad 2-input NAND gate Schmitt trigger 2.0 - 5.5 ±8 3.3 -40~125 • • •

74AHCT132-Q100 Quad 2-input NAND gate Schmitt trigger; TTL-enabled 4.5 - 5.5 ±8 3.5 -40~125 • • •

74HC7014-Q100 Hex buffer precision Schmitt trigger 2.0 - 6.0 ± 5.2 27 -40~125 •

74HC14-Q100 Hex inverter Schmitt trigger 2.0 - 6.0 ± 5.2 12 -40~125 • • •

74HCT14-Q100 Hex inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ±4 17 -40~125 • • •

74HC132-Q100 Quad 2-input NAND gate Schmitt trigger 2.0 - 6.0 ± 5.2 11 -40~125 • •

74HCT132-Q100 Quad 2-input NAND gate Schmitt trigger; TTL-enabled 4.5 - 5.5 ±4 17 -40~125 • •

74HC7541-Q100 Octal buffer/line driver Schmitt trigger (3-State) 2.0 - 6.0 ± 7.8 11 -40~125 • •

Octal buffer/line driver Schmitt trigger; TTL-enabled

74HCT7541-Q100 4.5 - 5.5 ±6 16 -40~125 • •
(3-State)

74LV132-Q100 Quad 2-input NAND gate Schmitt trigger 1.0 - 5.5 ± 12 10 -40~125 • • •

74LVC14A-Q100 Hex inverter Schmitt trigger 1.2 - 3.6 ± 24 3.2 -40~125 • • •

74LVC132A-Q100 Quad 2-input NAND gate Schmitt trigger 1.2 - 3.6 ± 24 3.4 -40~125 • • •

HEF40106B-Q100 Hex inverter Schmitt trigger 4.5 - 15.5 ± 2.4 30 -40~85 • •

Shift registers (cont.)

Features Package (suffix)
SOT402-1 (PW)

SOT403-1 (PW)

SOT360-1 (PW)
SOT762-1 (BQ)

SOT763-1 (BQ)
SOT338-1 (DB)
SOT108-1 (D)

SOT109-1 (D)

SOT163-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)

Type number Description

74AHC164-Q100 8-bit serial-in/parallel-out shift register 2.0 - 5.5 ±8 4.5 -40~125 • • •

8-bit serial-in/parallel-out shift register;

74AHCT164-Q100 4.5 - 5.5 ±8 3.4 -40~125 • • •
TTL-enabled

8-bit serial-in/parallel-out shift register with

74AHC594-Q100 2.0 - 5.5 ±8 4.1 -40~125 • • • •
output register

8-bit serial-in/parallel-out shift register with

74AHCT594-Q100 4.5 - 5.5 ±8 3.8 -40~125 • • • •
output register; TTL-enabled

8-bit serial-in/parallel-out shift register with

74AHC595-Q100 2.0 - 5.5 ±8 4 -40~125 • • •
output register (3-state)

8-bit serial-in/parallel-out shift register with

74AHCT595-Q100 4.5 - 5.5 ±8 3.8 -40~125 • • •
output storage; TTL-enabled (3-state)

74HC164-Q100 8-bit serial-in/parallel-out shift register 2.0 - 6.0 ± 5.2 12 -40~125 • • •

118 NXP Logic selection guide 2016

Shift registers (cont.)
Features Package (suffix)

SOT402-1 (PW)

SOT403-1 (PW)

SOT360-1 (PW)
SOT762-1 (BQ)

SOT763-1 (BQ)
SOT338-1 (DB)
SOT108-1 (D)

SOT109-1 (D)

SOT163-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description

8-bit serial-in/parallel-out shift register;

74HCT164-Q100 4.5 - 5.5 ±4 12 -40~125 • • •
TTL-enabled

8-bit parallel or serial-in/serial-out shift

74HC165-Q100 2.0 - 6.0 ± 5.2 16 -40~125 • • •
register

8-bit parallel or serial-in/serial-out shift

74HCT165-Q100 4.5 - 5.5 ±4 14 -40~125 • • •
register; TTL-enabled

8-bit parallel or serial-in/serial-out shift

74HC166-Q100 2.0 - 6.0 ± 5.2 15 -40~125 • •
register

8-bit parallel or serial-in/serial-out shift

74HCT166-Q100 4.5 - 5.5 ±4 23 -40~125 •
register; TTL-enabled

8-bit serial-in/parallel-out shift register with

74HC594-Q100 2.0 - 6.0 ± 7.8 14 -40~125 •
output storage register

8-bit serial-in/parallel-out shift register with

74HCT594-Q100 4.5 - 5.5 ±6 15 -40~125 •
output storage register; TTL-enabled

8-bit serial-in/parallel-out shift register with

74HC595-Q100 2.0 - 6.0 ± 7.8 16 -40~125 • • • •
output storage register (3-state)

8-bit serial-in/parallel-out shift register

74HCT595-Q100 with output storage register; TTL-enabled 4.5 - 5.5 ±6 25 -40~125 • • •
(3-state)

8-bit parallel or serial-in/parallel-out shift

74HC597-Q100 2.0 - 6.0 ± 5.2 16 -40~125 • •
register with parallel input register

8-bit parallel or serial-in/parallel-out shift

74HCT597-Q100 register with parallel input register; 4.5 - 5.5 ±4 20 -40~125 •
TTL-enabled

8-bit serial-in/serial or parallel-out shift

74HC4094-Q100 2.0 - 6.0 ± 5.2 15 -40~125 • • •
register with output register (3-state)

8-bit serial-in/serial or parallel-out shift

74HCT4094-Q100 register with output register; TTL-enabled 4.5 - 5.5 ±4 19 -40~125 • •
(3-state)

74LV164-Q100 8-bit serial-in/parallel-out shift register 1.0 - 5.5 ± 12 12 -40~125 • • •

8-bit parallel or serial-in/serial-out shift

74LV165-Q100 1.0 - 5.5 ± 12 18 -40~125 • •
register

8-bit parallel or serial-in/serial-out shift

74LV165A-Q100 1.0 - 5.5 ± 12 7.5 -40~125 • •
register

74LV4060-Q100 14-stage binary ripple counter with oscillator 1.0 - 5.5 ±6 29 -40~125 • •

8-bit serial-in/parallel-out shift register with

74LVC594A-Q100 1.2 - 5.5 ± 24 3.1 -40~125 • • •
output storage register

8-bit serial-in/parallel-out shift register with

74VHC595-Q100 2.0 - 5.5 ±8 4 -40~125 • • •
output storage register (3-state)

8-bit serial-in/parallel-out shift register

74VHCT595-Q100 with output storage register; TTL-enabled 4.5 - 5.5 ±8 3.8 -40~125 • • •
(3-state)

8-bit shift register with synchronous parallel

HEF4014B-Q100 4.5 - 15 ± 2.4 40 -40~85 •
enable

NXP Logic selection guide 2016 119

 Shift registers (cont.)
Features Package (suffix)

SOT402-1 (PW)

SOT403-1 (PW)

SOT360-1 (PW)
SOT762-1 (BQ)

SOT763-1 (BQ)
SOT338-1 (DB)
SOT108-1 (D)

SOT109-1 (D)

SOT163-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description

8-bit shift register with asynchronous parallel

HEF4021B-Q100 4.5 - 15 ± 2.4 40 -40~85 • •
load
8-bit serial-in/serial or parallel-out shift
HEF4094B-Q100 4.5 - 15 ± 2.4 50 -40~85 • •
register with output register (3-state)
8-bit serial-in/serial or parallel-out shift
HEF4794B-Q100 register with output register LED driver 4.5 - 15 -20 45 -40~85 •
(3-state)
12-bit serial-in/serial or parallel-out shift
HEF4894B-Q100 register with output register LED driver 4.5 - 15 -20 45 -40~85 • •
(3-state)
8-bit serial-in/parallel-out shift register with
NPIC6C595-Q100 4.5 - 5.5 -100 90 -40~125 • • •
output storage register (3-state)
8-bit serial-in/serial or parallel-out shift
NPIC6C596-Q100 register with output register LED driver 4.5 - 5.5 -100 90 -40~125 • • •
(3-state)
8-bit serial-in/serial or parallel-out shift
NPIC6C596A-Q100 register with output register LED driver 2.3 - 5.5 -100 90 -40~125 • • •
(3-state)
12-bit serial-in/serial or parallel-out shift
NPIC6C4894-Q100 register with output register LED driver 4.5 - 5.5 -100 105 -40~125 • •
(3-state)

Transceivers
Features Package (suffix)

SOT362-1 (DGG)
SOT360-1 (PW)

SOT764-1 (BQ)

SOT702-1 (EV)
SOT163-1 (D)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)

Type number Description

74AHC245-Q100 Octal transceiver (3-state) 2.0 - 5.5 ±8 3.5 -40~125 • • •

74AHCT245-Q100 Octal transceiver; TTL-enabled (3-state) 4.5 - 5.5 ±8 5 -40~125 • • •

74AVC16245-Q100 16-bit transceiver (3-state) 1.2 - 3.6 ± 12 2 -40~85 •

74HC245-Q100 Octal transceiver (3-state) 2.0 - 6.0 ± 7.8 7 -40~125 • • •

74HCT245-Q100 Octal transceiver; TTL-enabled (3-state) 4.5 - 5.5 ±6 10 -40~125 • • •

74LVC245A-Q100 Octal transceiver (3-state) 1.2 - 3.6 ± 24 2.9 -40~125 • • •

74LVCH245A-Q100 Octal transceiver with bus hold (3-state) 1.2 - 3.6 ± 24 2.9 -40~125 • • •

74LVC16245A-Q100 16-bit transceiver (3-state) 1.2 - 3.6 ± 24 3 -40~125 • •

74LVCH16245A-Q100 16-bit transceiver with bus hold (3-state) 1.2 - 3.6 ± 24 3 -40~125 • •

120 NXP Logic selection guide 2016

Standard logic packages
Package
D DB PW BQ D DB PW BQ
suffix
14-pin 14-pin 14-pin 14-pin 16-pin 16-pin 16-pin 16-pin

Package SOT108-1 SOT337-1 SOT402-1 SOT762-1 SOT109-1 SOT338-1 SOT403-1 SOT763-1

Width (mm) 6.00 7.75 6.40 2.50 6.00 7.75 6.40 2.50
Length (mm) 8.65 6.20 5.00 3.00 9.90 6.20 5.00 3.50
Height (mm) 1.75 2.00 1.10 1.00 1.75 2.00 1.10 1.00
Pitch (mm) 1.27 0.65 0.65 0.50 1.27 0.65 0.65 0.50

Package
D DB PW BQ D PW DGG EV
suffix
20-pin 20-pin 20-pin 20-pin 24-pin 24-pin 48-pin 56-pin

Package SOT163-1 SOT339-1 SOT360-1 SOT764-1 SOT137-1 SOT355-1 SOT362-1 SOT702-1

Width (mm) 10.30 7.75 6.40 2.50 10.30 6.40 8.10 4.50
Length (mm) 12.80 7.20 6.50 4.50 15.40 7.80 12.50 7.00
Height (mm) 2.65 2.00 1.10 1.00 2.65 1.10 1.20 1.00
Pitch (mm) 1.27 0.65 0.65 0.5 1.27 0.65 0.50 0.65
Note: The HEF4000B family uses different package suffixes than the other families. Package suffix D corresponds to HEF4000B package suffix T, DB to TS and
PW to TT.

NXP Logic selection guide 2016 121

Q100 Mini Logic functions & packages

Mini logic functions are small footprint logic devices with 10 pins or less suitable for use at supply voltage between 1.1 V to
6.0 V. They provide a wide range of functions including analog switches, buffers/inverters, bus switches, decoders/de-
multiplexers, multiplexers, flip-flops, gates, configurable logic and level shifters. Q100 Mini logic functions are available in
leaded TSSOP and VSSOP packages as well as innovative leadless XSON packages.

Analog switches
Features Package (suffix)

SOT353-1 (GW)

SOT765-1 (DC)
SOT505-2 (DP)
Configuration

SOT363 (GW)
RON(FLAT) (W)

SOT753 (GV)

SOT457 (GV)
Tamb (°C)
RON (W)
VCC (V)
Type number Description

74AHC1G66-Q100 Single-pole, single-throw analog switch SPST-NO 2.0 - 5.5 40 5 -40~125 • •

Single-pole, single-throw analog switch;

74AHCT1G66-Q100 SPST-NO 4.5 - 5.5 40 5 -40~125 • •
TTL-enabled

74HC1G66-Q100 Single-pole, single-throw analog switch SPST-NO 2.0 - 9.0 105 23 -40~125 • •

Single-pole, single-throw analog switch;

74HCT1G66-Q100 SPST-NO 4.5 - 5.5 118 23 -40~125 • •
TTL-enabled

74HC2G66-Q100 Dual single-pole, single-throw analog switch SPST-NO 2.0 - 9.0 105 23 -40~125 • •

Dual single-pole, single-throw analog switch;

74HCT2G66-Q100 SPST-NO 4.5 - 5.5 118 23 -40~125 • •
TTL-enabled

74LVC1G53-Q100 Single-pole, double-throw analog switch SPDT-Z 1.65 - 5.5 15 1.5 -40~125 • •

74LVC1G66-Q100 Single-pole, single-throw analog switch SPST-NO 1.65 - 5.5 15 1.5 -40~125 • •

74LVC1G384-Q100 Single-pole, single-throw analog switch SPST-NC 1.65 - 5.5 15 1.5 -40~125 • •

74LVC1G3157-Q100 Single-pole, double-throw analog switch SPDT 1.65 - 5.5 15 1.5 -40~125 • •

74LVC2G66-Q100 Dual single-pole, single-throw analog switch SPST-NO 1.65 - 5.5 15 1.5 -40~125 • •

Bus switches
Features Package (suffix)
SOT96-1 (D)

SOT530-1
Tamb (°C)
VPASS (V)

RON (W)
VCC (V)

(PW)

Type number Description

CBT3306-Q100 Dual bus switch 4.5 - 5.5 3.9 7 -40~85 • •

122 NXP Logic selection guide 2016

Buffers/inverters (cont.)
Features Package (suffix)

SOT353-1 (GW)

SOT996-2 (GD)
SOT765-1 (DC)
SOT505-2 (DP)
SOT363 (GW)
SOT753 (GV)

SOT457 (GV)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description

74AHC1GU04-Q100 Single inverter; unbuffered 2.0 - 5.5 ±8 2.6 -40~125 • •

74AHC3GU04-Q100 Triple inverter; unbuffered 2.0 - 5.5 ±8 2.5 -40~125 • •

74AHC1G04-Q100 Single inverter 2.0 - 5.5 ±8 3.1 -40~125 • •

74AHCT1G04-Q100 Single inverter; TTL-enabled 4.5 - 5.5 ±8 3.4 -40~125 • •

74AHC1G07-Q100 Single buffer; open-drain 2.0 - 5.5 8 4.2 -40~125 • •

74AHC1G125-Q100 Single buffer/line driver (3-state) 2.0 - 5.5 ±8 3.4 -40~125 • •

Single buffer/line driver; TTL-enabled

74AHCT1G125-Q100 4.5 - 5.5 ±8 3.4 -40~125 • •
(3-state)

74AHC1G126-Q100 Single buffer/line driver (3-state) 2.0 - 5.5 ±8 3.4 -40~125 • •

Single buffer/line driver; TTL-enabled

74AHCT1G126-Q100 4.5 - 5.5 ±8 3.4 -40~125 • •
(3-state)

74AHC2G125-Q100 Dual buffer/line driver (3-state) 2.0 - 5.5 ±8 3.4 -40~125 • •

Dual buffer/line driver; TTL-enabled

74AHCT2G125-Q100 4.5 - 5.5 ±8 3.4 -40~125 • •
(3-state)

74AHC2G126-Q100 Dual buffer/line driver (3-state) 2.0 - 5.5 ±8 3.4 -40~125 • •

Dual buffer/line driver; TTL-enabled

74AHCT2G126-Q100 4.5 - 5.5 ±8 3.4 -40~125 • •
(3-state)

74AHC2G241-Q100 Dual buffer/line driver (3-state) 2.0 - 5.5 ±8 3.4 -40~125 • •

Dual buffer/line driver; TTL-enabled

74AHCT2G241-Q100 4.5 - 5.5 ±8 3.4 -40~125 • •
(3-state)

74AHC3G04-Q100 Triple inverter 2.0 - 5.5 ±8 3.1 -40~125 • •

74AHCT3G04-Q100 Triple inverter; TTL-enabled 4.5 - 5.5 ±8 3 -40~125 • •

74AUP1G04-Q100 Single inverter 1.1 - 3.6 ± 1.9 4 -40~125 • •

74AUP1G06-Q100 Single inverter; open-drain 1.1 - 3.6 1.9 4.5 -40~125 •

74AUP1G34-Q100 Single buffer 1.1 - 3.6 ± 1.9 3.9 -40~125 •

74AUP1G125-Q100 Single buffer/line driver (3-state) 1.1 - 3.6 ± 1.9 4.3 -40~125 •

74AUP2GU04-Q100 Dual inverter; unbuffered 1.1 - 3.6 ± 1.9 2.3 -40~125 •

74HC1GU04-Q100 Single inverter; unbuffered 2.0 - 6.0 ± 2.6 5 -40~125 • •

74HC2GU04-Q100 Dual inverter; unbuffered 2.0 - 6.0 ± 5.2 5 -40~125 • •

74HC3GU04-Q100 Triple inverter; unbuffered 2.0 - 6.0 ± 5.2 6 -40~125 • •

74HC1G04-Q100 Single inverter 2.0 - 6.0 ± 2.6 7 -40~125 • •

74HCT1G04-Q100 Single inverter; TTL-enabled 4.5 - 5.5 ± 2.0 8 -40~125 • •

74HC1G125-Q100 Single buffer/line driver (3-state) 2.0 - 6.0 ± 2.6 9 -40~125 • •

Single buffer/line driver; TTL-enabled

74HCT1G125-Q100 4.5 - 5.5 ± 2.0 10 -40~125 • •
(3-state)

74HC2G04-Q100 Dual inverter 2.0 - 6.0 ± 5.2 8 -40~125 • •

74HCT2G04-Q100 Dual inverter; TTL-enabled 4.5 - 5.5 ± 4.0 10 -40~125 • •

74HC2G34-Q100 Dual buffer 2.0 - 6.0 ± 5.2 9 -40~125 • •

74HCT2G34-Q100 Dual buffer; TTL-enabled 4.5 - 5.5 ± 4.0 10 -40~125 • •

74HC2G125-Q100 Dual buffer/line driver (3-state) 2.0 - 6.0 ± 5.2 10 -40~125 • •

NXP Logic selection guide 2016 123

 Buffers/inverters (cont.)
Features Package (suffix)

SOT353-1 (GW)

SOT996-2 (GD)
SOT765-1 (DC)
SOT505-2 (DP)
SOT363 (GW)
SOT753 (GV)

SOT457 (GV)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description

Dual buffer/line driver; TTL-enabled

74HCT2G125-Q100 4.5 - 5.5 ± 4.0 12 -40~125 • •
(3-state)

74HC3G04-Q100 Triple inverter 2.0 - 6.0 ± 5.2 8 -40~125 • • •

74HCT3G04-Q100 Triple inverter; TTL-enabled 4.5 - 5.5 ± 4.0 10 -40~125 • • •

74HC3G07-Q100 Triple buffer; open-drain 2.0 - 6.0 5.2 9 -40~125 • •

74HCT3G07-Q100 Triple buffer; open-drain; TTL-enabled 4.5 - 5.5 4 9 -40~125 • •

74HC3G34-Q100 Triple buffer 2.0 - 6.0 ± 5.2 9 -40~125 • •

74HCT3G34-Q100 Triple buffer; TTL-enabled 4.5 - 5.5 ± 4.0 10 -40~125 •

1.65 -
74LVC1G04-Q100 Single inverter ± 32 2 -40~125 • •
5.5

1.65 -
74LVC1G06-Q100 Single inverter; open-drain 32 2.3 -40~125 • •
5.5

1.65 -
74LVC1G07-Q100 Single buffer; open-drain 32 2.2 -40~125 • •
5.5

1.65 -
74LVC1G34-Q100 Single buffer ± 32 2 -40~125 • •
5.5

1.65 -
74LVC1G125-Q100 Single buffer/line driver (3-state) ± 32 2.1 -40~125 • •
5.5

1.65 -
74LVC1G126-Q100 Single buffer/line driver (3-state) ± 32 2 -40~125 • •
5.5

1.65 -
74LVC1GU04-Q100 Single inverter; unbuffered ± 32 1.6 -40~125 • •
5.5

1.65 -
74LVC2G04-Q100 Dual inverter ± 32 2.7 -40~125 • •
5.5

1.65 -
74LVC2G06-Q100 Dual inverter; open-drain 32 2.3 -40~125 • •
5.5

1.65 -
74LVC2G07-Q100 Dual buffer; open-drain 32 2.6 -40~125 • •
5.5

1.65 -
74LVC2G125-Q100 Dual buffer/line driver (3-state) ± 32 2.3 -40~125 • •
5.5

1.65 -
74LVC2G240-Q100 Dual inverter/line driver (3-state) ± 32 2.5 -40~125 • •
5.5

1.65 -
74LVC2G241-Q100 Dual buffer/line driver (3-state) ± 32 2.6 -40~125 • •
5.5

1.65 -
74LVC2GU04-Q100 Dual inverter; unbuffered ± 32 2.3 -40~125 • •
5.5

1.65 -
74LVC3G04-Q100 Triple inverter ± 32 2.7 -40~125 • •
5.5

1.65 -
74LVC3G07-Q100 Triple buffer; open-drain 32 2.1 -40~125 • •
5.5

1.65 -
74LVC3G34-Q100 Triple buffer ± 32 2.2 -40~125 • •
5.5

124 NXP Logic selection guide 2016

Digital decoders/demultiplexers
Package
Features
(suffix)

SOT363 (GW)

SOT457 (GV)
Tamb (°C)
IO (mA)
VCC (V)

tpd (ns)
Type number Description

74LVC1G18-Q100 1-to-2 demultiplexer (3-state) 1.65 - 5.5 ± 32 2.3 -40~125 • •

Digital multiplexers
Features Package (suffix)

SOT363 (GW)

SOT457 (GV)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description
74LVC1G157-Q100 Single 2-input multiplexer 1.65 - 5.5 ± 32 2.2 -40~125 • •

Flip-flops
Features Package (suffix)

SOT353-1 (GW)

SOT996-2 (GD)
SOT765-1 (DC)
SOT505-2 (DP)
SOT363 (GW)
SOT753 (GV)

SOT457 (GV)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)

Type number Description

74AHC1G79-Q100 Single D-type flip-flop; positive-edge trigger 2.0 - 5.5 ±8 3.5 -40~125 • •

Single D-type flip-flop; positive-edge trigger;

74AHCT1G79-Q100 4.5 - 5.5 ±8 3.5 -40~125 • •
TTL-enabled

74AUP1G175-Q100 Single D flip-flop with reset; positive-edge trigger 1.1 - 3.6 ± 1.9 7.4 -40~125 •

74AUP1G374-Q100 Single D-type flip-flop; positive-edge trigger (3-state) 1.1 - 3.6 ± 1.9 7.9 -40~125 •

74AUP2G79-Q100 Dual D-type flip-flop; positive-edge trigger 1.1 - 3.6 ± 1.9 8.5 -40~125 •

Single D-type flip-flop with set and reset; positive-

74LVC1G74-Q100 1.65 - 5.5 ± 32 3.5 -40~125 • • •
edge trigger

74LVC1G80-Q100 Single D-type flip-flop; positive-edge trigger 1.65 - 5.5 ± 32 2.4 -40~125 • •

74LVC1G175-Q100 Single D flip-flop with reset; positive-edge trigger 1.65 - 5.5 ± 32 3.1 -40~125 • •

Single D-type flip-flop with set and reset; positive-

74LVC2G74-Q100 1.65 - 5.5 ± 32 3.5 -40~125 • •
edge trigger

NXP Logic selection guide 2016 125

 Gates (cont.)
Features Package (suffix)

SOT353-1 (GW)

SOT765-1 (DC)
SOT505-2 (DP)
SOT363 (GW)
SOT753 (GV)

SOT457 (GV)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description

74AHC1G09-Q100 Single 2-input AND gate; open-drain 2.0 - 5.5 ±8 3.2 -40~125 • •

74AHC1G00-Q100 Single 2-input NAND gate 2.0 - 5.5 ±8 3.5 -40~125 • •

74AHCT1G00-Q100 Single 2-input NAND gate; TTL-enabled 4.5 - 5.5 ±8 3.6 -40~125 • •

74AHC1G02-Q100 Single 2-input NOR gate 2.0 - 5.5 ±8 3.2 -40~125 • •

74AHCT1G02-Q100 Single 2-input NOR gate; TTL-enabled 4.5 - 5.5 ±8 3.5 -40~125 • •

74AHC1G08-Q100 Single 2-input AND gate 2.0 - 5.5 ±8 3.2 -40~125 • •

74AHCT1G08-Q100 Single 2-input AND gate; TTL-enabled 4.5 - 5.5 ±8 3.6 -40~125 • •

74AHC1G32-Q100 Single 2-input OR gate 2.0 - 5.5 ±8 3.2 -40~125 • •

74AHCT1G32-Q100 Single 2-input OR gate; TTL-enabled 4.5 - 5.5 ±8 3.3 -40~125 • •

74AHC1G86-Q100 2-input EXCLUSIVE-OR gate 2.0 - 5.5 ±8 3.4 -40~125 • •

74AHCT1G86-Q100 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 - 5.5 ±8 3.5 -40~125 • •

74AHC2G00-Q100 Dual 2-input NAND gate 2.0 - 5.5 ±8 3.5 -40~125 • •

74AHCT2G00-Q100 Dual 2-input NAND gate; TTL-enabled 4.5 - 5.5 ±8 3.6 -40~125 • •

74AHC2G08-Q100 Dual 2-input AND gate 2.0 - 5.5 ±8 3.2 -40~125 • •

74AHCT2G08-Q100 Dual 2-Input AND gate; TTL-enabled 4.5 - 5.5 ±8 3.6 -40~125 • •

74AHC2G32-Q100 Dual 2-input OR gate 2.0 - 5.5 ±8 3.2 -40~125 • •

74AHCT2G32-Q100 Dual 2-input OR gate; TTL-enabled 4.5 - 5.5 ±8 3.3 -40~125 • •

74AUP1G02-Q100 Single 2-input NOR gate 1.1 - 3.6 ± 1.9 8.2 -40~125 •

74AUP1G08-Q100 Single 2-input AND gate 1.1 - 3.6 ± 1.9 8.2 -40~125 •

74AUP1G32-Q100 Single 2-input OR gate 1.1 - 3.6 ±1.9 7.9 -40~125 •

74AUP1G86-Q100 Single 2-input EXCLUSIVE-OR gate 1.1 - 3.6 ± 1.9 3.3 -40~125 •

Configurable gate with voltage level

74AUP1T98-Q100 2.3-3.6 V ±1.9 8.7 -40~125 •
translation

74HC1G86-Q100 Single 2-input EXCLUSIVE-OR gate 2.0 - 6.0 ± 2.6 9 -40~125 • •

74HC1GU04-Q100 Single inverter; unbuffered 2.0 - 6.0 ± 2.6 5 -40~125 •

74HC1G00-Q100 Single 2-input NAND gate 2.0 - 6.0 ± 2.6 7 -40~125 •

74HCT1G00-Q100 Single 2-input NAND gate; TTL-enabled 4.5 - 5.5 ±2 10 -40~125 • •

74HC1G02-Q100 Single 2-input NOR gate 2.0 - 6.0 ± 2.6 7 -40~125 • •

74HCT1G02-Q100 Single 2-input NOR gate; TTL-enabled 4.5 - 5.5 ± 2.0 9 -40~125 • •

74HC1G08-Q100 Single 2-input AND gate 2.0 - 6.0 ± 5.2 7 -40~125 • •

74HCT1G08-Q100 Single 2-input AND gate; TTL-enabled 4.5 - 5.5 ±2 11 -40~125 • •

74HC1G32-Q100 Single 2-input OR gate 2.0 - 6.0 ± 2.6 8 -40~125 • •

74HCT1G32-Q100 Single 2-input OR gate; TTL-enabled 4.5 - 5.5 ± 2.0 10 -40~125 • •

74HC2G00-Q100 Dual 2-input NAND gate 2.0 - 6.0 ± 5.6 9 -40~125 • •

126 NXP Logic selection guide 2016

Gates (cont.)
Features Package (suffix)

SOT353-1 (GW)

SOT765-1 (DC)
SOT505-2 (DP)
SOT363 (GW)
SOT753 (GV)

SOT457 (GV)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)
Type number Description

74HCT2G00-Q100 Dual 2-input NAND gate; TTL-enabled 4.5 - 5.5 ±4 12 -40~125 • •

74HC2G02-Q100 Dual 2-input NOR gate 2.0 - 6.0 ± 5.2 9 -40~125 • •

74HCT2G02-Q100 Dual 2-input NOR gate; TTL-enabled 4.5 - 5.5 ±4 12 -40~125 • •

74HC2G08-Q100 Dual 2-input AND gate 2.0 - 6.0 ± 5.2 9 -40~125 • •

74HCT2G08-Q100 Dual 2-Input AND gate; TTL-enabled 4.5 - 5.5 ±4 14 -40~125 • •

74HC2G32-Q100 Dual 2-input OR gate 2.0 - 6.0 ± 5.2 9 -40~125 • •

74HCT2G32-Q100 Dual 2-input OR gate; TTL-enabled 4.5 - 5.5 ± 4.0 13 -40~125 • •

74HC2G86-Q100 Dual 2-input EXCLUSIVE-OR gate 2.0 - 6.0 ± 5.2 9 -40~125 • •

Dual 2-input EXCLUSIVE-OR gate;

74HCT2G86-Q100 4.5 - 5.5 ± 4.0 11 -40~125 • •
TTL-enabled

Single 2-input EXCLUSIVE-OR gate;

74HCT1G86-Q100 4.5 - 5.5 ± 2.0 10 -40~125 • •
TTL-enabled

74LVC1G00-Q100 Single 2-input NAND gate 1.65 - 5.5 ± 32 2.2 -40~125 • •

74LVC1G02-Q100 Single 2-input NOR gate 1.65 - 5.5 ± 32 2.1 -40~125 • •

74LVC1G08-Q100 Single 2-input AND gate 1.65 - 5.5 ± 32 2.1 -40~125 • •

74LVC1G11-Q100 Single 3-input AND gate 1.65 - 5.5 ± 32 2.6 -40~125 • •

74LVC1G32-Q100 Single 2-input OR gate 1.65 - 5.5 ± 32 2.1 -40~125 • •

74LVC1G38-Q100 Single 2-input NAND gate; open-drain 1.65 - 5.5 32 2.3 -40~125 • •

74LVC1G57-Q100 Configurable gate; Schmitt trigger 1.65 - 5.5 ± 32 3.8 -40~125 • •

74LVC1G58-Q100 Configurable gate; Schmitt trigger 1.65 - 5.5 ± 32 3.8 -40~125 • •

74LVC1G86-Q100 Single 2-input EXCLUSIVE-OR gate 1.65 - 5.5 ± 32 2.4 -40~125 • •

74LVC1G332-Q100 Single 3-input OR gate 1.65 - 5.5 ± 32 2.6 -40~125 • •

74LVC1GX04-Q100 Crystal driver 1.65 - 5.5 ± 24 2.8 -40~125 • •

74LVC2G02-Q100 Dual 2-input NOR gate 1.65 - 5.5 ± 32 2.4 -40~125 • •

74LVC2G08-Q100 Dual 2-input AND gate 1.65 - 5.5 ± 24 2.1 -40~125 • •

74LVC2G32-Q100 Dual 2-input OR gate 1.65 - 5.5 ± 32 2.2 -40~125 • •

74LVC2G34-Q100 Dual buffer 1.65 - 5.5 ± 32 2.2 -40~125 • •

74LVC2G86-Q100 Dual 2-input EXCLUSIVE-OR gate 1.65 - 5.5 ± 32 2.3 -40~125 • •

NXP Logic selection guide 2016 127

 Latches/registered drivers
Package
Features
(suffix)

Type number Description VCC (V) IO (mA) tpd (ns) Tamb (°C) SOT363 (GW)

74AUP1G373-Q100 single D-type transparent latch (3-state) 1.1 - 3.6 ±1.9 8.5 -40~125 •

Multivibrators
Features Package (suffix)

SOT505-2
VCC (V) IO (mA) tpd (ns) Tamb (°C) SOT765-1 (DC)
Type number Description (DP)

single retriggerable monostable

74LVC1G123-Q100 1.65 - 5.5 ± 32 3.5 -40~125 • •
multivibrator

Schmitt triggers
Features Package (suffix)

SOT353-1 (GW)

SOT996-2 (GD)
SOT765-1 (DC)
SOT505-2 (DP)
SOT363 (GW)
SOT753 (GV)

SOT457 (GV)
Tamb (°C)
IO (mA)

tpd (ns)
VCC (V)

Type number Description

74AHC1G14-Q100 Single inverter Schmitt trigger 2.0 - 5.5 ±8 3.2 -40~125 • •

74AHCT1G14-Q100 Single inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ±8 4.1 -40~125 • •

74AHC3G14-Q100 Triple inverter Schmitt trigger 2.0 - 5.5 ±8 3.2 -40~125 • • •

74AHCT3G14-Q100 Triple inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ±8 4.1 -40~125 • • •

74HC1G14-Q100 Single inverter Schmitt trigger 2.0 - 6.0 ± 2.6 10 -40~125 • •

74HCT1G14-Q100 Single inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ± 2.0 15 -40~125 • •

74HC2G14-Q100 Dual inverter Schmitt trigger 2.0 - 6.0 ± 5.2 16 -40~125 • •

74HCT2G14-Q100 Dual inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ± 4.0 21 -40~125 • •

74HC2G17-Q100 Dual buffer Schmitt trigger 2.0 - 6.0 ± 5.2 12 -40~125 • •

74HCT2G17-Q100 Dual buffer Schmitt trigger; TTL-enabled 4.5 - 5.5 ± 4.0 21 -40~125 • •

74HC3G14-Q100 Triple inverter Schmitt trigger 2.0 - 6.0 ± 5.2 16 -40~125 • •

74HCT3G14-Q100 Triple inverter Schmitt trigger; TTL-enabled 4.5 - 5.5 ± 4.0 21 -40~125 • •

74LVC1G14-Q100 Single inverter Schmitt trigger 1.65 - 5.5 ± 32 3 -40~125 • •

74LVC1G17-Q100 Single buffer Schmitt trigger 1.65 - 5.5 ± 32 3 -40~125 • •

74LVC2G14-Q100 Dual inverter Schmitt trigger 1.65 - 5.5 ± 32 3.9 -40~125 • •

74LVC2G17-Q100 Dual buffer Schmitt trigger 1.65 - 5.5 ± 32 3.6 -40~125 • •

74LVC3G17-Q100 Triple buffer Schmitt trigger 1.65 - 5.5 ± 32 3.6 -40~125 • •

128 NXP Logic selection guide 2016

Level shifters/translators
Features Package (suffix)

SOT353-1 (GW)

SOT996-2 (GD)
SOT765-1 (DC)
SOT505-2 (DP)
SOT363 (GW)
VCC(A) (V)

VCC(B) (V)

Tamb (°C)
IO (mA)
Type number Description

74AUP1T34-Q100 Single dual supply translating buffer 1.1 - 3.6 1.1 - 3.6 ± 1.9 -40~125 •

Single dual-supply voltage level translating transceiver

74AVC1T45-Q100 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 •
(3-state)

Dual-bit dual-supply voltage level translating transceiver

74AVC2T45-Q100 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 • • •
(3-state)

Single dual-supply voltage translating transceiver with bus

74AVCH1T45-Q100 0.8 - 3.6 0.8 - 3.6 ± 12 -40~125 •
hold (3-state)

Single dual-supply voltage level translating transceiver

74LVC1T45-Q100 1.2 - 5.5 1.2 - 5.5 ± 24 -40~125 •
(3-state)

Single dual-supply voltage translating transceiver with bus

74LVCH1T45-Q100 1.2 - 5.5 1.2 - 5.5 ± 24 -40~125 •
hold (3-state)

Dual-bit dual-supply voltage level translating transceiver

74LVC2T45-Q100 1.2 - 5.5 1.2 - 5.5 ± 24 -40~125 •
(3-state)

Dual-bit dual-supply voltage level translating transceiver

74LVCH2T45-Q100 1.2 - 5.5 1.2 - 5.5 ± 24 -40~125 •
with bus hold (3-state)

Mini Logic packages

Package suffix GW GV GW GV D DP PW DC GD

5-pin 5-pin 6-pin 6-pin 8-pin 8-pin 8-pin 8-pin 8-pin

Package SOT353-1 SOT753 SOT363 SOT457 SOT96-1 SOT505-2 SOT530-1 SOT765-1 SOT996-2
Width (mm) 2.10 2.75 2.10 2.75 6.00 4.00 3.00 3.10 3.00
Length (mm) 2.00 2.90 2.00 2.90 4.90 3.00 6.40 2.00 2.00
Height (mm) 1.00 1.00 1.00 1.00 1.75 1.10 1.10 1.00 0.50
Pitch (mm) 0.65 0.95 0.65 0.95 1.27 0.65 0.65 0.50 0.50

NXP Logic selection guide 2016 129

 Packages

Industry-leading size, performance, and selection NXP is a recognized leader in

packaging technology and has, over the years, driven the evolution to smaller, higher-
performance formats. We were one of the first to offer leadless packages, and continue
to break new ground with unique options like the Diamond package, the world’s
smallest general-purpose logic package. Delivering industry firsts like the Diamond
package underscores NXP’s commitment to leadership, innovation, and understanding
of a market that is driven by the need for smaller, cheaper, more reliable solutions.

Superior selection Support for legacy formats

We deliver improved electrical and mechanical We may have our eye on the future of packaging, but
performance, smaller size, higher board-level reliability, we also understand the importance of maintaining
and lower cost. We support wider temperature ranges technologies for as long as they’re needed. We know
(-40 to +125 °C), and offer packages that are automotive that larger packages, such as SO and TSSOP, still have
qualified according to the AEC-Q100 standard. Our their place in some designs, and continue to support
roadmap guides the way to the lowest profile and the these tried-and-true solutions.
smallest pitch.

The journey to smaller formats

130 NXP Logic selection guide 2016

The leadless advantage Our products comply with the following:
Today’s ultra-compact designs can be a challenge when it European Union Restriction on Hazardous Substances
4 
comes to squeezing more functionality into a smaller space. (RoHS) directive
Tiny leadless packages can deliver a significant advantage End of Life Vehicle (ELV) directive
4 
here – with options like DQFN, MicroPak, and Diamond China RoHS
4 
packages offering a smaller footprint with improved
mechanical performance. NXP was one of the earliest semiconductor companies to
address environmental concerns over packaging, and we
Leadless packages use pads instead of leads. The pads have worked quickly to reduce or eliminate the presence of
present a bigger solderable area, so they create a stronger lead, mercury, chromium, and poly-brominated compounds.
bond with the PCB. The result is a design that is more We follow the guidelines for compliance with environmental
compact, and also more durable. NXP’s DQFN, MicroPak, and directives, such as RoHS, and go beyond the baseline
Diamond packages perform better in mechanical tests like requirements by reducing the limits of antimony oxides
pull, shear, drop, and bend. (Sb2O3, Sb2O5), as well as chlorinated and brominated flame
retardants. Our “Dark Green” packages are RoHS compliant
The NXP portfolio includes more than 50 leadless and also free of halogen and antimony.
packages, and all are qualified for use in automotive-grade
environments. Our LVC, AUP, and AXP logic functions are Our Dark Green products have less impact on the environment
available in leadless DQFN, MicroPak, and Diamond packages, and, as an added bonus, are more resistant to moisture. Dark
so it’s easy to find the right mix of features, footprint, and Green packages don’t require dry-pack processing, which
cost. involves drying the package and sealing it in plastic, and this
delivers an added saving on energy and resources. The latest
When transitioning to leadless formats, consider the following Dark Green products also use smaller ICs, so they can be
guidelines: housed in smaller packages. The result is lower cost, fewer
4 
For gates, octals, and other logic functions with 10 or more materials, lower power consumption and, of course, a reduced
pins, choose the DQFN package. It uses the same die as a environmental footprint.
TSSOP, but the footprint is up to 76 percent smaller.
4 
For single-, dual-, and triple-gate functions, which typically Definitions of Green and Dark Green
use fewer than 10 pins, choose the MicroPak package. It
Green = RoHS compliant
uses the same die as a PicoGate, but the footprint is up to
Substance(s) Limit
62 percent smaller.
Pb < 1000 ppm
Hg, Cr6+, PBB, PBDE < 1000 ppm
Recommended replacements for leaded packages Cd < 100 ppm
Leaded Leadless Best for
Space savings
package equivalent functions of
Dark Green = RoHS compliant and free of antimony and halogen
TSSOP DQFN Up to 76% smaller 10+ pins Substances Limit
MicroPak Up to 62% smaller 6 to 10 pins Antimony oxides (Sb2O3, Sb2O5) < 900 ppm
PicoGate 25% smaller than smallest Chlorinated and brominated flame
Diamond 5 pins ∑ < 900 ppm
MicroPak (XSON6) retardants

Note: substances above are not intentionally added, but might be present as an
impurity with an upper limit according to the listed values. The plastic materials
are classified according to UL94V-0.
Environmental compliance
Respect for the environment is one of the guiding principles
Online access to all chemical contents
of the NXP Sustainability Policy. Our ongoing commitment to
We were the very first to list all the chemical contents in our
excellence in this area means we continuously move toward
products on an easy-to-access web page that also shows
best-in-class environmental standards, and supply products
compliance with legislative requirements (www.nxp.com/
that use fewer hazardous or restricted substances and can be
chemical-content/search/). Search results can be downloaded
recycled or disposed of in an environmentally sound way.
to an Excel or Zip file.

NXP Logic selection guide 2016 131

Package selection matrix
Width Pitch
Suffix 5 6 8 10 12 14 16 20 24 28 48 56 60 96/144
(mm) (mm)

3.9 1.27 D/T

SOT108-1 SOT109-1
SOIC

7.5 1.27 D/T

SOT163 SOT137-1 SOT136-1

DS /
3.9 0.635
DK
SOT519-1 SOT724-1 SOT556-1
SSOP

5.3 0.65 DB
SOT337-1 SOT338-1 SOT339-1 SOT340-1 SOT341-1

7.5 0.635 DL
SOT370-1 SOT371-1
TSOP

2.8 0.95 GV
SOT753 SOT457

2.1 0.65 GW
SOT353 SOT363
TSSOP

PW /
4.4 0.65
TT
SOT402-1 SOT403-1 SOT360-1 SOT355-1 SOT361-1

6.1 0.5 DGG

SOT362-1 SOT364-1

BQ/
2.5 0.5
BX
DQFN

SOT762-1 SOT763-1 SOT764-1

3.5 0.5 BQ
SOT815-1
HUQFN

4 0.5 BX
SOT1025-1
TVSOP

4.4 0.4 DGV

SOT480-1 SOT481-2
LFBGA

5.5 0.8 BC
SOT536-1
VFBGA

4.5 0.65 EV
SOT702-1

0.8 0.5 GX
SOT1226

GM/
1.0 0.5
GT
SOT886 SOT833

1.0 0.35 GS
SOT1202 SOT1203
XSON

1.0 0.3 GN
SOT1115 SOT1116

2 0.5 GD
SOT996

1 0.35 GF
SOT891 SOT1081

1 0.35 DP
SOT1089

1.6 0.5 GM
XQFN

SOT902 SOT1049 SOT1174

1.7 0.5 GU
SOT1161

132 NXP Logic selection guide 2016

Nomenclature

NXP's naming convention embeds the package type in the product number. Our
nomenclature diagrams list all items alphabetically.

Nomenclature for standard logic functions Nomenclature for mini logic functions

74 XXX XXX XXX 74 XXX XG XXX XXX

XT

Logic Function Package Logic Gate Function Package

family number type family format number type
AHC(T) BQ DQFN AHC(T) 1G Single-gate DC PicoGate
ALVC BX DQFN AUP 2G Dual-gate DP PicoGate
ALVT D SO AVC(M) 3G Triple-gate GD MicroPak
AUP DB SSOP AXP GF MicroPak
AVC(M) DC VSSOP CBT(D) Translator GM MicroPak
CBT(D) DG TSSOP CBTLV(D) format GN MicroPak
CBTLV(D) DGG TSSOP HC(T) GS MicroPak
HC(T) DL SSOP LVC 1T Single-translator GT MicroPak
HEF4000B DP TSSOP XC7 2T Dual-translator GV PicoGate
LV FC BGA 3T Triple-translator GW PicoGate
LVC EV BGA 4T Quad-translator GX MicroPak
LVT GU DQFN
NPIC P TSSOP
VHC(T) T SO
XC7 TS SSOP
TT TSSOP

NXP Logic selection guide 2016 133

 Package diagrams

SOT353 GW SOT363 GW

Pinout Pinout

5 4
6 5 4

1 2 3
1 2 3

Package dimensions Package dimensions

2.2 1.1
2.25 1.1 1.8 0.8
0.60 1.85
0.1 0.45
0.15 6 5 4
0.0 0.15
5 4 0.46
0.21

2.2 1.35
2.25 1.35 2.0 1.15 pin 1
2.00 1.15 index

1 2 3
1 2 3 0.3 0.25
0.65
0.30 0.25 0.2 0.10
0.65 1.3
0.15 0.08
1.3
Dimensions in mm 14-10-03
Dimensions in mm 14-10-01

Solder footprint Solder footprint

134 NXP Logic selection guide 2016

SOT457 GV SOT505-2 DP

Pinout Pinout

8 5
6 5 4

1 2 3 1 4

Package dimensions Package dimensions

3.1 1.1
3.1 1.1 2.9 max
0.15
2.7 0.9
0.00
6 5 4 0.6 8 5
0.2
0.47
0.33
3.0 1.7 4.1 3.1
2.5 1.3 pin 1 index 3.9 2.9

1 2 3
1 4
0.40 0.26 0.18
0.95 0.38 0.08
0.25 0.10 0.65
1.9 0.22
Dimensions in mm 14-10-01
Dimensions in mm 14-10-03
Footprint information for reflow soldering of TSSOP8 package SOT505-2

Solder footprint Solder footprint

Hx

Gx

P2
(0.125) (0.125)

Hy Gy By Ay

D2 (4x) P1 D1

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

NXP Logic selection guide 2016 135

DIMENSIONS in mm

P1 P2 Ay By C D1 D2 Gx Gy Hx Hy
 SOT650-1 TK SOT753-1 GV

Pinout Pinout

10 6

5 4

1 2 3

1 5
Transparent top view

Package dimensions Package dimensions

3.1 1.1
3.1
2.7 0.9
2.9
2.0 1.0 5 4 0.6
0.30 0.05 0.2
0.5
0.18 0.00
1 5
3.0 1.7
2.5 1.3
0.55
3.1 0.30 1.75
2.9 1.45
1 2 3
0.40 0.26
0.95
0.25 0.10
10 6 1.9
2.55
2.15 Dimensions in mm 14-10-03
Dimensions in mm 14-10-01

Footprint information for reflow soldering of HVSON10 package SOT650-1

Solder footprint Solder footprint

Gx

D P (0.105)

nSPx SPx

SPy
SPy tot

Hy Gy SLy By Ay
nSPy

SPx tot

SLx

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

solder paste deposit

solder land plus solder paste

occupied area

DIMENSIONS in mm

P Ay By C D SLx SLy SPx tot SPy tot SPx SPy Gx Gy Hy nSPx nSPy

0.500 4.000 2.200 0.900 0.240 2.400 1.500 1.400 0.650 0.550 0.650 3.300 3.300 4.250 2 1
09-12-29
Issue date sot650-1_fr
09-12-29

136 NXP Logic selection guide 2016

 SOT765-1 DC SOT833-1 GT

Pinout Pinout
8 5

8 7 6 5

1 2 3 4
Transparent top view
1 4

Package dimensions Package dimensions

2.1 1.0
1.9 max 2.0
0.15 0.5
1.9 0.25
0.00
0.17 0.04
8 5 1 2 3 4

0.40 0.40
0.15 0.32
1.05
3.2 2.4 0.6 0.35
0.95
3.0 2.2 0.27

8 7 6 5
1 4 0.5 0.5 0.5
0.23
0.27
0.5 of VSSOP8 package
Footprint information for reflow soldering 0.08 SOT765-1
0.17 Dimensions in mm 14-09-30
Dimensions in mm 14-10-01

Solder footprint Solder footprint

Hx

Gx
P2
D1 (0.125)

Hy Gy By Ay

(0.175) (0.125)

D2 (4x) P1

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ay By C D1 D2 Gx Gy Hx Hy

0.500 0.550 3.500 2.000 0.750 0.300 0.400 2.250 1.750 3.075 3.750
sot765-1_fr

NXP Logic selection guide 2016 137

 SOT886 GM SOT891 GF

Pinout Pinout

6 5 4 1 2 3

1 2 3 6 5 4
Transparent bottom view
top view

Package dimensions Package dimensions

1.05 0.5
1.05 0.50 0.95 max
0.95 max 0.04
0.04 0.55
0.6 max
max

0.25 3 4
3 4
0.17
0.35
0.5 0.20
1.05 0.12
1.5 2 5
2 5 0.95
1.4
0.35
0.5
1 6
1 6

0.40 0.35
0.40 0.35 0.32 0.27
0.32 0.27
Dimensions in mm 14-10-03
Dimensions in mm 14-10-03

Solder footprint Solder footprint

138 NXP Logic selection guide 2016

 SOT902-2 GM SOT996 GD

Pinout Pinout

3 5
4 5

2 6

7 1 8
1
8

Package dimensions Package dimensions

2.1
1.65 1.9
0.5
1.55
0.25 0.05 1.5 0.5
0.15 0.00 0.35 0.05
4 0.5
0.15 0.00
1 4
3 5

0.5
1.65 0.6
2 6
1.55 3.1 0.4
2.9
0.5
1 7 0.3

0.35 8
0.25of XQFN8 package
Footprint information for reflow soldering 0.55 SOT902-2 8 5
Dimensions in mm 14-09-30 Dimensions in mm 14-09-30

Solder footprint Solder footprint

Hx

D
0.025
(8×)

0.025

C (7×)

Hy Ay SLy 1.000

0.110

0.320

SLx

1.200

solder land

solder paste deposit

solder land plus solder paste

occupied area

DIMENSIONS in mm

Ay C D SLx SLy Hx Hy

1.2 0.22 0.4 0.5 0.5 1.9 1.9

12-02-23
Issue date sot902-2_fr
12-12-18
NXP Logic selection guide 2016 139
 SOT1049-3 GM SOT1081-1/2 GF

Pinout Pinout

4 6 10 6

1 5
1 9
Transparent top view
10

Package dimensions Package dimensions

1.65 1.8
0.5 1.6
1.45
0.25 0.05 1.4 0.5
0.15 0.00
5 0.20 0.05
0.35
0.10 0.00
4 6 1 5

0.45
0.35
2.1
1.5 1.1
1.9 0.33 0.2
0.9
0.23
0.5 0.4
1 9 0.3
10 6
10
0.4 0.48
0.3 0.38 Dimensions in mm 14-09-30
Dimensions in mm 14-10-01

Solder footprint Solder footprint

140 NXP Logic selection guide 2016

SOT1089 GF SOT1202 GS

Pinout Pinout

6 5 4
8 7 6 5

1 2 3 4
Transparent top view 1 2 3
Transparent top view

Package dimensions Package dimensions

1.05
1.05 0.35
0.5 0.95
0.95
0.20
0.20 0.04
0.55 0.04 0.12
0.12 1 2 3

4 5 0.35
0.40
0.35 0.32 0.27

1.40 1.05
0.55
1.30 0.95

1 8
6 5 4
0.40 0.35 0.35 0.35
0.32 0.27
Dimensions in mm 14-10-01 Dimensions in mm
Footprint information for reflow soldering of SOT1202 package
14-09-29
SOT1202

Solder footprint Solder footprint

0.25 (6x)

0.15 (6x)

0.6 0.5
(6x) (6x)

0.7 1.4

0.35 0.35

1.05

occupied area solder resist

solder paste = solder lands

10-09-10
Issue date Dimensions in mm sot1202_fr
14-01-06

NXP Logic selection guide 2016 141

 SOT1203 GS SOT1226 GX

Pinout Pinout

8 7 6 5 1 5

3
GND

2 4

1 2 3 4 aaa-018998

Transparent top view

Package dimensions Package dimensions

1.40
0.35
1.30
0.20
0.04
0.12
1 2 3 4

0.40 0.35
0.32 0.27

1.05
0.55
0.95

8 7 6 5
0.35 0.35 0.35
Dimensions in mm 14-09-30

Solder footprint Solder footprint

142 NXP Logic selection guide 2016

SOT815-1 BQ SOT402-1 PW

Pinout Pinout

24
1
2 23
3 22
1 14
4 21
2 13
5 20
3 12
6 19 4 11
7 18 5 10
8 17 6 9
7 8
9 16
10 GND(1) 15
aaa-019003
11 14
12

13

aaa-019005

Package dimensions Package dimensions

Solder footprint Solder footprint

NXP Logic selection guide 2016 143

 SOT403-1 PW SOT360-1 PW

Pinout Pinout

1 20
1 16 2 19
2 15 3 18
3 14 4 17
4 13 5 16
5 12 6 15
6 11 7 14
7 10 8 13
8 9 9 12

aaa-019012 10 11

aaa-019015

Package dimensions Package dimensions

Solder footprint Solder footprint

144 NXP Logic selection guide 2016

SOT337-1 DB SOT338-1 DB

Pinout Pinout

1 16
1 14 2 15
2 13 3 14
3 12
4 13
4 11
5 12
5 10
6 11
6 9
7 10
7 8
8 9
aaa-018999 aaa-019007

Package dimensions Package dimensions

1 14

7 8

Dimensions in mm 15-05-26

Solder footprint Solder footprint

NXP Logic selection guide 2016 145

 SOT339-1 DB SOT519-1 DS

Pinout Pinout

1 20
2 19 1 16
3 18 2 15
4 17 3 14
5 16 4 13
6 15 5 12
7 14
6 11
8 13
7 10
9 12
8 9
10 11
aaa-019013
aaa-009314

Package dimensions Package dimensions

Solder footprint Solder footprint

146 NXP Logic selection guide 2016

SOT724-1 DS SOT1174 GM

Pinout Pinout

1 20

12
1 11
2 19
3 18
2 10
4 17
5 16
3 9
6 15
7 14
4 8
8 13
9 12
5 7
10 11

6
aaa-019000

aaa-019016

Package dimensions Package dimensions

Solder footprint Solder footprint

NXP Logic selection guide 2016 147

 SOT1161 GU SOT137-1 D

Pinout Pinout

VCC(A) 1 24 VCC(B)

16

15

14

13
DIR 2 23 VCC(B)
A0 3 22 OE
1 12 A1 4 21 B0
A2 5 20 B1
2 11 A3 6 19 B2
A4 7 18 B3
3 10
A5 8 17 B4
A6 9 16 B5
4 9
A7 10 15 B6
GND 11 14 B7
GND 12 13 GND
5

8
aaa-019008 aaa-019011

Package dimensions Package dimensions

Dimensions in mm 15-05-26

Solder footprint Solder footprint

148 NXP Logic selection guide 2016

SOT556-1 DK SOT340-1 DB

Pinout Pinout

1 24 1 24
2 23 2 23
3 22 3 22
4 21 4 21
5 20 5 20
6 19 6 19
7 18 7 18
8 17 8 17
9 16 9 16
10 15 10 15
11 14 11 14
12 13 12 13

aaa-019014 aaa-019017

Package dimensions Package dimensions

Solder footprint Solder footprint

NXP Logic selection guide 2016 149

 SOT355-1 PW SOT815-1 BQ

Pinout Pinout

1 24

24
1
2 23
2 23
3 22
3 22
4 21
4 21
5 20
5 20
6 19
6 19
7 18
7 18
8 17
8 17
9 16
9 16
10 15
10 GND(1) 15
11 14
11 14
12 13

12

13
aaa-019001 aaa-019005

Package dimensions Package dimensions

Solder footprint Solder footprint

150 NXP Logic selection guide 2016

Design tools

NXP is committed to making the design process as easy as possible. We offer

a range of design tools that make it easier to select the right product for a
design, verify performance, explore functionality, and begin prototyping. The
result is a smoother development process, and faster time-to-market.

This section includes the following:

Breakout boards for use with breadboard sockets
4 
Evaluation boards for standard and configurable logic
4 
Demo board for AXP configurable logic
4 
Packaging linecard
4 

How to order
To order a breakout board, an evaluation board, or a package linecard, contact your local NXP sales
office or distributor (www.nxp.com/about/sales-offices-distributors), or NXP technical support
(www.nxp.com/technicalsupport).

The 74AXP1G57 demo board can be ordered online, at www.nxp.com/logic.

Breakout boards for use with breadboard sockets

Using breadboards is a quick way to create prototypes or experiment with a device, but today’s small-
scale packages don’t always fit in
breadboard sockets. NXP’s breakout
boards are compact PCBs that convert
the latest, smallest leadless packages
into bigger DIP sockets, providing easy
access to all the device I/O.

TSSOP, PicoGate, MicroPak, DQFN

4 
4 
Accommodate packages with 5, 6, 8,
10, 12, 14, or 16 pins/pads
4 
Test pins available for supply pins,
I/O access, and measurement
Coated with solder paste, for easy
4 
mounting
Pre-assembled versions available
4 
with specific functions

NXP Logic selection guide 2016 151

Breakout boards Evaluation boards for standard and configurable logic
GEN1 (1.15 x 0.60 inches) Our evaluation boards enable quick prototyping by providing
SOT number Package type No. of pins Pitch (mm) access to the I/O and supply-voltage pins. They are a
convenient way to verify behavior, confirm static and dynamic
353 TSSOP 5 0.65
characteristics under different loads, compare features, and
753 SO5 5 0.95
benchmark against the competition. Each board is equipped
363 TSSOP 6 0.65
for easy test and verification of the device’s most important
457 TSOP6 6 0.95 features.
886 XSON6 6 0.50

891 XSON6 6 0.35 Evaluation boards for standard logic

Product
505 TSSOP8 8 0.65 Description Board features
number
530 TSSOP8 8 0.65 Binary
2/4/8/16 clock division, up/down
74LVC169 counter/
765 VSSOP8 8 0.50 counting
timer
833 XSON8 8 0.50 Switch high-frequency signals with
Dual SPST
74LVC2G66 overvoltage-tolerant control inputs up
902 XQFN8U 8 0.50 switch
to 5 V
GEN2 (1.10 x 0.60 inches) Switch high-frequency signals with
Dual SPST
74LVCV2G66 overvoltage-tolerant control and data
OVT switch
SOT number Package type No. of pins Pitch (mm) inputs up to 5 V
363 TSSOP 6 0.65 Combines buffered and unbuffered
Low-power
74AUP1Z04 inverters and demonstrates standby
crystal driver
457 TSOP6 6 0.95 mode

1202 XSON6 6 0.35

Evaluation boards for configurable logic
1115 XSON6 6 0.30
Configurable logic offers nine or more functions in a single
96 SO8 8 1.27
PicoGate or MicroPak package. The pin configuration
996 XSON8U 8 0.50
determines which logic function the device performs, so you
1089 XSON8 8 0.35 can use just one device type to perform multiple functions
1116 XSON8 8 0.30 in your system. Each evaluation board for configurable logic
1203 XSON8 8 0.35 measures just 2.5 x 3 inches, and includes four sections with
the same configurable logic device mounted on each section.
GEN3 (1.60 x 0.60 inches)
The user can configure each device to perform one of seven
SOT number Package type No. of pins Pitch (mm)
unique functions.
650 HVSON10 10 0.50

1049 XQFN10U 10 0.50 Available for AXP, AUP, and LVC configurable-logic devices
1160 XQFN10 10 0.40 Power-supply decoupling provided on-board
4 
1174 XQFN12 12 0.40 4 
Supports external supply voltage of 0.7 to 2.75 V (AXP), 0.8

762 DHVQFN14 14 0.50

to 3.6 V (AUP), or 1.65 to 5.5 V (LVC)
Test points at all I/O pins
4 
402 TSSOP14 14 0.65
Each board section can be connected or detached via
4 
763 DHVQFN16 16 0.50
jumpers
1039 HXQFN16U 16 0.50 Supports cascading of multiple devices
4 
1161 XQFN16 16 0.40

GEN4 (1.12 x 0.62 inches)

SOT number Package type No. of pins Pitch (mm)

1226 XSON5 5 0.48

1340-1 HXSON4 4 0.50

1255 XSON6 6 0.50

1348-1 TDQFN6 6 0.65

152 NXP Logic selection guide 2016

Evaluation board for configurable logic

Demo board for AXP configurable logic The AXP1G57GM demo board is also available as
The AXP1G57GM demo board gives designers a a sample kit, which includes sample devices, a USB
quick, easy way to demonstrate the configurable drive with data sheets and other literature, and an
logic functions. optional A-to-B USB cable. The sample kit can be
Seven 74AXP1G57 devices, each configured as a
4  ordered through the e-sample center, located at
unique function https://extranet.nxp.com.
One 74AVC8T245 device, for translation from
4 
1.2 to 3.3 V Packaging linecard
Three push-button switches to toggle the A, B,
4  NXP offers one of the broadest selections of
and C input pins of the 74AXP1G57 device small-scale, automotive-grade, RoHS-compliant
NPN transistor PMBT3904 to drive a green/red
4  and Halogen-free logic packages. Our packaging
2.2 V, 20 mA LED, and a current-limiting resistor linecard, which is populated with actual packages,
Rotary switch for selecting one of seven
4  is a quick reference to compare all our TSSOP,
functions with output connected to status LED PicoGate, QFN, MicroPak, Diamond, and CSP
Mini-USB socket or battery holder to supply 4.5
4  options. It provides an at-a-glance comparison
or 5 V DC power to the board of size, and lists order number, SOT number, and
footprint for each package type.

NXP Logic selection guide 2016 153

 Competitive cross reference

This cross reference allows you to match a competitor’s part number to an NXP part number. Once
you have the equivalent part number, check the NXP website www.nxp.com/logic to confirm that the
particular configuration is released.

Texas instruments logic Fairchild semiconductor tiny logic

SN74 LVC 1G 08 DCK NC7 S Z 157 P6

Prefix Logic Family Gate count Package Prefix Gate count Logic Family Package
TI NXP TI NXP TI NXP Function TI NXP Function
FSC NXP FSC NXP FSC NXP FSC NXP
- - ABT ABT - - E P NC7 74 S 1G - HC P5 GW
SN74 74 AHC(T) AHC(T) nG nG M T W 2G B LVC M5 GV
SN54 74 ALVC ALVC nT nT D D N 3G P AUP P6 GW
ALVT ALVT PW PW, TT T HCT K8 DC
AUP AUP DB DB V AUP L6 GM
AVC AVC DL DL Z LVC L8 GM
CBT CBT DGG DGG
CBTLV CBTLV DGV DGV
CD HEF GKE EV
F F ZKE EC
HC(T) HC(T) DCK GW
LV
LVC
LV
LVC
DBV
DCU
GV
DC 74 LVC 1G 157 GW
LVT LVT DCT DP
TPIC6C NPIC6C DRY GM
YZP GM

74 LVC 1G 08 GW
On semiconductors logic

MC74 VHC 1GT 08 DTT

Fairchild semiconductor standard logic
Prefix Logic Family Gate count Package
ON NXP ON NXP ON NXP Function ON NXP
- - HC HC(T) - - N, C N, P
MC74 74 LCX LVC nG nG D D
LVX LV nGT* nG DT PW
MC1 HEF * Indicates TTL DFT GW
VCX ALVC variant of the family DTT GV
VHC AHC(T) US DC
QZ DS
MN BQ
AMX GM
CMX GS

74 AHCT 1G 08 GW

Toshiba standard logic On semiconductor low pin count logic

TC74 LCX 125 FT NL 1 7 SZ 08 DFT

Prefix Logic Family Package Prefix Gate count Logic Family Package
Tosh NXP Tosh NXP Function Tosh NXP Function
ON NXP ON NXP ON NXP ON NXP
— — HC(T) HC(T) P N
NLn7 74 n nG SV AUP DFT GW
TC74 74 LCX LVC FW D
LVX LV FN D SZ LVC DTT GV
TC HEF FT PW WZ LVC US DC
VCX ALVC FS DB WB LVC AMX GM
VHC(T) VHC(T) CMX GS

74 LVC 125 PW 74 LVC 1G 08 GW

154 NXP Logic selection guide 2016

Toshiba one gate IDT logic

TC7 S Z 157 FU 74 FCT 244 PY

Prefix Logic Family Package

Function
Prefix Gate count Logic Family Package IDT NXP IDT NXP IDT NXP
Tosh NXP Tosh NXP Tosh NXP Function Tosh NXP 74 74 ALVC ALVC BF EC
54 74 CBTLV CBTLV CD N
TC7 74 S 1G - HC FK GV FCT ABT DC, PS D
W 1,2 or 3G A LVC FU GW, DP LVC LVC DJ, PF DGV
P 1 or 2G G AUP QS CBT PA DGG
T HCT PC DS, DK
H AHC PG PW
PV DL
ET AHCT
PY DB
Z LVC

74 ABT 244 DB
74 LVC 1G 157 GW

Renesas logic

Diodes Inc. logic

HD74 HC 1G 08 CM
74 LVC 1G 08 FW4
Prefix Logic Family Gate count Package
Ren . NXP Ren . NXP Ren . NXP Function Ren . NXP
HD74 74 ALVC ALVC - - CM GW
Prefix Logic Family Gate count Package BC, LS ABT nG nG FP DC
Diodes NXP Diodes NXP Diodes NXP Function Diodes NXP CBT CBT P N
HC(T) HC(T) T PW
74 74 AHC(T) AHC(T) - - T14 PW
LV LV US DC
LVC LVC nG nG S14 D
LVC LVC
SE GW
LVT LVT
DW GW
W5 GV
FZ4 GM
FW4 GF
74 HC 1G 08 GW

74 LVC 1G 08 GW

NXP Logic selection guide 2016 155

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© 2016 NXP Semiconductors N.V.

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Date of release: March 2016

Published in the USA