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MIPS Pipeline PDF

The MIPS architecture uses a 5-stage pipeline with registers to transfer instructions and data between stages. The 5 stages are: 1) Instruction Fetch, 2) Instruction Decode, 3) Instruction Execute, 4) Memory access, and 5) Writeback. In the Execute stage, one of three operations occurs - ALU instruction, load/store instruction, or branch instruction. The ALU performs operations and stores results, load/store calculates addresses and reads/writes memory, and branches compute new program counters. Registers copy data between stages and the final stage writes results to registers.

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137 views2 pages

MIPS Pipeline PDF

The MIPS architecture uses a 5-stage pipeline with registers to transfer instructions and data between stages. The 5 stages are: 1) Instruction Fetch, 2) Instruction Decode, 3) Instruction Execute, 4) Memory access, and 5) Writeback. In the Execute stage, one of three operations occurs - ALU instruction, load/store instruction, or branch instruction. The ALU performs operations and stores results, load/store calculates addresses and reads/writes memory, and branches compute new program counters. Registers copy data between stages and the final stage writes results to registers.

Uploaded by

Phil DN
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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MIPS

(​M​icroprocessor without​ I​nterlocked​ P​ipeline​ S​tages)


v. 2018

Registros: IR,NPC IR,NPC,A,B,IMM IR,B,ALUO IR,ALUO,LMD

Formatos de instrucción:
I-type (Load/Store, Cond branch, Jump register):
Opcode[6] | rs[5] | rt[5] | immediate[16] 
R-type (ALU ops, moves, and shifts):  
Opcode[6] | rs[5] | rt[5] | rd[5] | shift[5] | func[6] 
J-type (Jump, Jump and link, trap and return exception):  
Opcode[6] | offset_to_PC[26]
STAGE-1: Instruction Fetch

IF/ID.IR <- IM[PC] 


IF/ID.NPC <- PC + 4  
PC <- PC + 4 o EX/ME.ALUO # Proxima instr o salida de la ALU (branch address) 
# Depende de ‘cond’ (ver 3.3)
STAGE-2: Instruction Decode

ID/EX.A <- Reg[IF/ID.IR[rs]] # Copiar el primer argumento al buffer A 


ID/EX.B <- Reg[IF/ID.IR[rt]] # Copiar el segundo argumento al buffer B 
ID/EX.NPC <- IF/ID.NPC # Copiar el PC into the ID/EX buffer 
ID/EX.IR <- IF/ID.IR; # Copy the IR into the ID/EX buffer 
ID/EX.IMM <- sign-extend(IF/ID.IR[imm field]) # Sign extend the immediate field to a 
# 32-bit number and copy it into  
# the ID/EX buffer
STAGE-3: Instruction Execute: ​Una de estas tres opciones

3.1. ALU Instruction


EX/ME.ALUO <- func(ID/EX.A, ID/EX.B) o func(ID/EX.A, ID/EX.IMM) 
# Compute a binary operation and store the result in EX/ME 
EX/ME.IR <- ID/EX.IR # Copy the IR into the EX/ME buffer 

3.2. Load/Store Instruction


EX/ME.ALUO <- ID/EX.A + ID/EX.IMM (address) # Compute and address (through the ALU), 
# and copy it into the EX/ME buffer 
EX/ME.B <- ID/EX.B; (operand) # Copy the operand in the ID/EX.B buffer 
# into the EX/MEM buffer 
EX/ME.IR <- ID/EX.IR # Copy the IR into the EX/ME buffer 

3.3. Branch Instruction


EX/ME.ALUO <- ID/EX.NPC + 4*ID/EX.IMM # Compute the next address (relative to the  
# PC in multiples of 4) and copy it into EX/ME 
EX/ME.cond <- (ID/EX.A == 0) # Check if buffer A that has been copied in the 
# previous cycle is zero to trigger a branch. 
# (Branch instructions end here) 
# Only conditional branches with equality  
# test are handled
STAGE-4: Memory

4.1. ALU Instruction 


ME/WB.ALUO <- EX/ME.ALUO # Copy the EX/ME.ALU buffer into the ME/WB.ALU buffer 
ME/WB.IR <- EX/ME.IR # Copy the IR into the ME/WB buffer 

4.2. Load Instruction


ME/WB.LMD <- DM[EX/ME.ALUO] # Read the operand into the load memory data  
# register (LMD) from the DM. 
ME/WB.IR <- EX/ME.IR # Copy the IR into the ME/WB buffer 

4.3. Store Instruction


DM[ME/WB.ALUO] <- EX/ME.LMD # Write the operand from the load memory data  
# register (LMD) into the DM. 
ME/WB.IR <- EX/ME.IR # Copy the IR into the ME/WB buffer (Store  
# instructions end here) 

STAGE-5: Writeback

5.1. ALU Instruction


Regs[ME/WB.IR[rd]] <- ME/WB.ALUO # Copy the ME/WB.ALUO buffer into the  
# destination register
5.2. Load Instruction
Regs[ME/WB.IR[rd] ] <- ME/WB.LMD # Copy the ME/WB.LMD register into the  
# destination register

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