ASSIGNMENT – 2

Hardware Design Methodology

Submitted By:
Shaily Garg
M.Tech MI
MEC2019010
IIIT Allahabad
Question 1: Design and implement a sequence detector to detect the sequence 1011. Use
behavioural modelling style and translate FSM exactly to its Verilog code. Perform the
same using different state coding schemes such as one hot assignment and binary
assignment (using gates/FF/Mux etc.) and compare results.

Solution 1:
//Verilog code using gates and D FF
module ques1(clk, reset, in, out);
input clk, reset, in;
output out;
wire [0:1] PS, NS;
wire t1, t2;
and D11(t1, ~in, PS[0]);
and D12(t2, in, PS[1], ~PS[0]);
or D1(NS[1], t1, t2);
and D0(NS[0], in, 1'b1);
and a1(out, in, PS[1], PS[0]);
dflop df1(reset, NS[1], PS[1], clk);
dflop df2(reset, NS[0], PS[0], clk);
endmodule

//verilog code for D FF

module dflop(reset, NS, PS, clk);
input clk, reset, NS;
output reg PS;
always @(posedge clk or posedge reset)
begin
if(reset) PS<=0;
else PS<=NS;
end
endmodule

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//Verilog code using behavioural modeling

module mealyover(clk, reset, in, out);

input clk, reset, in;
output reg out;
parameter S0=0, S1=1, S2=2, S3=3;
reg [0:1] PS, NS;
always @(posedge clk, posedge reset)
if(reset)
PS<=S0;
else
PS<=NS;

always @(PS, in)

begin
case(PS)

S0: begin
if(in==1)
NS<=S1;
else
NS<=S0;
end

S1: begin
if(in==0)
NS<=S2;
else
NS<=S1;
end

S2: begin
if(in==1)
NS<=S3;
else
NS<=S0;
end

S3: begin
if(in==1)
NS<=S1;
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 else
NS<=S2;
end

default: NS<=S0;
endcase
end

always @(PS)
begin
case(PS)
S0: out<=0;
S1: out<=0;
S2: out<=0;
S3: out<=1;
default: out<=0;
endcase
end
endmodule

//test bench for sequence detector 1011

module tb_mealyover();
reg clk, reset, in;
wire out;

mealyover Q1(clk, reset, in, out);

//ques1 Q1(clk, reset, in, out);
initial
begin
clk=1'b0;
end
always #5 clk=~clk;
initial
begin
in=0; reset=1;
#10 reset=0; #2 in=1; #10 in=0; #10 in=1;
#10 in=1; #10 in=1; #10 in=1;
#10 in=0; #10 in=1; #10 in=1;
#10 in=0; #10 in=1; #10 in=1;
#10 in=0; #10 in=1; #10 in=1;
#10 $finish;
end
endmodule
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Question 2: Design a machine that can detect three consecutive heads in a sequence of
random trials of tossing a fair coin. Develop a stimulus model for functional
verification.

Solution 2:
//verilog code for three consecutive heads
module head(clk, reset, in, out);
input clk, reset;
input in; //INPUT=HEAD(1) or INPUT=TAIL(0)
output out;
reg [1:0]PS, NS;
parameter S0=0, S1=1, S2=2, S3=3;
parameter HEAD=1, TAIL=0;

always @(posedge clk or posedge reset)

if(reset) PS<=S0;
else PS<=NS;
always @(PS or in)
case(PS)
S0: begin
if(in) NS<=S1;
else NS<=S0;
end
S1: begin
if(in) NS<=S2;
else NS<=S0;
end
S2: begin
if(in) NS<=S3;
else NS<=S0;
end
S3: begin
if(in) NS<=S3;
else NS<=S0;
end
endcase
assign out=(NS==S3);
endmodule

//test bench for verilog code three consecutive heads

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module tb_head();
reg clk, reset, in;
wire out;
head Q2(clk, reset, in, out);

initial
begin
clk=1'b1; reset=1;
end
always #5 clk=~clk;

initial
begin
#1 reset=0;
#2 in=1; #10 in=1;
#10 in=1; #10 in=0;
#10 in=0; #10 in=1; #10 in=1;
#10 in=1; #10 in=0;
end
endmodule

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Question 3: Design a sequence detector if the in sequence “0110” (the leading ‘0’ can’t
use in more than one sequence). Implement the FSM using
1. Logic gates and D FF
2. MUX and D FF

Solution 3:

1. Verilog code Logic gates and D FF

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//verilog code for sequence detector 0110 using Logic gates and D FF
module q3rda(x, clk, reset, y);
input x, clk, reset;
output y;
wire [2:0] PS, NS;
wire t1, t2, t3, t4, t5;

and D2(NS[2], ~x, ~PS[2], PS[1], PS[0]);

and D11(t1, x, ~PS[2], ~PS[1], PS[0]);

and D12(t2, x, ~PS[2], PS[1], ~PS[0]);
or D1(NS[1], t1, t2);

and D01(t3, ~x, ~PS[2], ~PS[1]);

and D02(t4, ~x, ~PS[1], ~PS[0]);
and D03(t5, ~PS[2], PS[1], ~PS[0]);
or D0(NS[0], t3, t4, t5);

and out(y, PS[2], ~PS[1], ~PS[0]);

dflop df1(reset, NS[2], PS[2], clk);

dflop df2(reset, NS[1], PS[1], clk);
dflop df3(reset, NS[0], PS[0], clk);

endmodule

//verilogcode for D FF
module dflop(reset, NS, PS, clk);
input clk, reset, NS;
output reg PS;
always @(posedge clk or posedge reset)
begin
if(reset) PS<=0;
else PS<=NS;
end
endmodule

//verilog code for sequence detector 0110 using behavioral modeling

module q3rda1(x, clk, reset, y);
input x, clk, reset;
output reg y;
reg [0:2] states;
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parameter s0=0, s1=1, s2=2, s3=3, s4=4;
initial
begin
states=s0;
end
always @(posedge clk or posedge reset)
case(states)
s0: begin
if(x) begin
y=0;
states=s0;
end
else begin
y=0;
states=s1;
end
end
s1: begin
if(x) begin
y=0;
states=s2;
end
else begin
y=0;
states=s1;
end
end
s2: begin
if(x) begin
y=0;
states=s3;
end
else begin
y=0;
states=s1;
end
end
s3: begin
if(x) begin
y=0;
states=s0;
end
else begin
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 y=0;
states=s4;
end
end
s4: begin
if(x) begin
y=1;
states=s0;
end
else begin
y=1;
states=s1;
end
end
endcase
endmodule

2. Verilog code using MUX and D FF

// verilog code of sequence detector 0110 using MUX and D FF

module q3rdb(x, clk, reset, y);
input x, clk, reset;
output y;
wire [2:0] PS, NS;
wire t1, t2, t3, t4, t5;

mux2x1 m1(~PS[1], ~PS[0], 1'b1, t1); // Instantiation of mux2x1(sel, in1, in2, out)
mux2x1 m2(~PS[1], 1'b0, ~PS[0], t2);
mux2x1 m3(PS[1], 1'b0, ~PS[0], t3);
mux2x1 m4(PS[1], 1'b0, PS[0], t4);
mux2x1 m5(PS[1], PS[0], ~PS[0], t5);
mux4x1 m6({x,NS[2]}, t1, t2, t3, 1'b0, NS[0]); // Instantiation of mux4x1(sel0, sel1,
in1, in1, in2, in3, out)
mux4x1 m7({x,NS[2]}, 1'b0, 1'b0, t5, 1'b0, NS[1]);
mux4x1 m8({x,NS[2]}, t4, 1'b0, 1'b0, 1'b0, NS[2]);
mux4x1 m9({x,NS[2]}, 1'b0, t2, 1'b0, t2, y);

dflop df1(reset, NS[2], PS[2], clk); // reset, in(D), out(Q), clk

dflop df2(reset, NS[1], PS[1], clk);
dflop df3(reset, NS[0], PS[0], clk);
endmodule

//Verilog code for 2x1 MUX

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module mux2x1(sel, in1, in2, out);
input in1, in2, sel;
output reg out;
always @(in1 or in2 or sel)
begin
if(sel==1)
out=in2;
else
out=in1;
end
endmodule

//Verilog code for 4x1 MUX

module mux4x1(sel0, sel1, in0, in1, in2, in3, out);
input in0, in1, in2, in3;
input sel0, sel1;
output reg out;
wire [1:0]t;
assign t={sel0, sel1};
always @(*)
begin
case(t)
2'b00: out=in0;
2'b01: out=in1;
2'b10: out=in2;
2'b11: out=in3;
default: out=1'b0;
endcase
end
endmodule

//testbench for sequence detector 0110

module tb_q3rda();

reg x, clk, reset;

wire y;
q3rda Q3(x, clk, reset, y);// for using logic gates and D FF
//q3rdb Q3(x, clk, reset, y); //for using multiplexer and D FF

initial
begin
clk=1'b0; reset=1'b1; x=1'b0;

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 #1 reset=1'b0;
#2 x=1'b1; #10 x=1'b0; #10 x=1'b1; #10 x=1'b1;
#10 x=1'b0; #10 x=1'b1; #10 x=1'b1; #10 x=1'b0;
#10 x=1'b1; #10 x=1'b1; #10 x=1'b1; #10 x=1'b0;
#10 x=1'b1; #10 x=1'b1; #10 x=1'b0; #10 x=1'b0;
#10 x=1'b1; #10 x=1'b1; #10 x=1'b0;

end
always #5 clk=~clk;
initial #200 $finish;
endmodule

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Question 4: Design a FSM to detect “10110” sequence, leading “10” can be taken in
more than one sequence. Develop Mealy Machine. Finally implement using D FF and
MUX. Develop a stimulus model for functional verification.

Solution 4:

// Verilog code for sequence detector 10110 using gates and D FF

module ques4(clk, reset, x, y, z, w);
input clk, reset, x;
output y;
output [2:0] z, w;
wire [2:0] NS, PS;
wire t1, t2, t3, t4, t5;
assign z=NS;
assign w=PS;
and a1(NS[1], x, PS[2], ~PS[1], PS[0]);
and a2(t3, ~x, PS[2], ~PS[1], ~PS[0]);
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 and a3(t2, ~PS[2], PS[1], PS[0]);
and a4(t1, ~x, ~PS[2], PS[0]);
or o1(NS[2], t1, t2);
and a5(t4, ~x, ~PS[2], PS[0]);
and a6(t5, x, ~PS[1]);
or o2(NS[0], t4, t5);
dflop d(reset, t3, y, clk);
dflop df1(reset, NS[2], PS[2], clk);
dflop df2(reset, NS[1], PS[1], clk);
dflop df3(reset, NS[0], PS[0], clk);
// dflop df4(reset, w, y, clk);
endmodule

// Verilog code for D FF

module dflop(reset, NS, PS, clk);
input clk, reset, NS;
output reg PS;
always @(posedge clk or posedge reset)
begin
if(reset) PS<=0;
else PS<=NS;
end
endmodule

// test bench for sequence detector 10110

module tb_ques4();
reg x, clk, reset;
wire y;
wire [2:0] z,w;
ques4 Q4(clk, reset, x, y, z, w);

initial
begin
clk=1'b0; reset=1'b1; x=1'b0;

#1 reset=1'b0;
#2 x=1'b1; #10 x=1'b0; #10 x=1'b1; #10 x=1'b1;
#10 x=1'b0; #10 x=1'b0;
#10 x=1'b1; #10 x=1'b1; #10 x=1'b0; #10 x=1'b1;
#10 x=1'b1; #10 x=1'b0; #10 x=1'b1;
#10 x=1'b1;

end
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 always #5 clk=~clk;
initial #400 $finish;

endmodule

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Question 5: Derive a Mealy type FSM that has an input x and an output y. The machine
is a sequence detector that produces y=1 when the previous two values of x were 00 or
11; otherwise y=0. Implement the FSM using the minimum number of gates and FF
(use don’t care). Develop a stimulus model for functional verification.

Solution 5:

// Verilog code for sequence detector 00 or 11 using behavioral modeling

module ques5(in, clk, reset, out);
input in, clk, reset;
output reg out;

parameter S0=0, S1=1, S2=2;

reg [0:1] PS, NS;

always @(posedge clk, posedge reset)

if(reset)
PS<=S0;
else
PS<=NS;

always @(PS, in)

begin
case(PS)

S0: begin
out=0;
if(in==1)
NS<=S2;
else
NS<=S1;

end

S1: begin
out=in?0:1;
if(in==1)
NS<=S2;
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 else
NS<=S1;
end

S2: begin
out=in?1:0;
if(in==1)
NS<=S2;
else
NS<=S1;
end

default: NS<=S0;
endcase
end
endmodule

// Verilog code for sequence detector 00 or 11 using Gates and FF

module ques5b(in, clk, reset, out, qa, qb);
input in, clk, reset;
output reg out;
output qa, qb;
//wire [0:1] PS, NS;
wire w1, w2, t1, inbar;
not (inbar, in);
dflop df1(clk, in, reset, qa); // clk, D, reset, Q
dflop df2(clk, inbar, reset, qb);
and a1(w1, inbar, qb);
and a2(w2, in, qa);
or o1(t1, w1, w2);
always @(posedge clk, posedge reset)
out<=t1;

endmodule

// Verilog code for D FF

module dflop(clk, D, reset, Q);
input clk, reset, D;
output reg Q;
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always @(posedge clk or posedge reset)
begin
if(reset) Q<=0;
else Q<=D;
end
endmodule

// testbench for sequence detector 00 or 11

module tb_ques5();
reg in, clk, reset;
wire out;
wire qa, qb;
//ques5 Q5(in, clk, reset, out);
ques5b Q5(in, clk, reset, out, qa, qb);
initial
begin
clk=1'b0; reset=1'b1; in=1'b0;

#1 reset=1'b0;
#2 in=1;
#10 in=0;
#10 in=1;
#10 in=0;
#10 in=1;
#10 in=0;
#10 in=0;
#10 in=1;
#10 in=0;
#10 in=0;
#10 in=1;
#10 in=1;
#10 in=0;
#10 in=1;
#10 in=1;
#10 $finish;

end
always #5 clk=~clk;
endmodule

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Question 6: A sequence of bits has odd parity if numbers of ‘1’ are odd. Design a circuit
that accepts string of bits and output a ‘1’, if parity thus far is odd; or else output a ‘0’.
Develop the FSM. Use structural level style to implement (MUX and FF). Develop a
stimulus model for functional verification.

Solution 6:

// Verilog code for EVEN or ODD parity

module parity(x, clk, y);
input x, clk;
output reg y;
reg even_odd;
parameter EVEN=0, ODD=1;
always @(posedge clk)
case(even_odd)
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EVEN: begin
if(x==1)
even_odd<=ODD;
else
even_odd<=EVEN;
end
ODD: begin
if(x==1)
even_odd<=EVEN;
else
even_odd<=ODD;
end
default: even_odd<=EVEN;
endcase
always @(even_odd)
begin
case(even_odd)
EVEN: y=0;
ODD: y=1;
endcase
end
endmodule

// Verilog code for EVEN or ODD parity using D FF

module ques6b(clk, reset, x, y, NS, PS);
input clk, reset, x;
output y;
output NS, PS;
wire t1, t2;
and a1(t1, ~x, PS);
and a2(t2, x, ~PS);
or o1(NS, t2, t1);
dflop df1(clk, reset, NS, PS);
assign y=PS;

endmodule

// verilog code for D FF

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module dflop(clk, reset, NS, PS);
input clk, reset, NS;
output reg PS;
always @(posedge clk or posedge reset)
if(reset)
PS<=0;
else
PS<=NS;
endmodule

// testbench for EVEN or ODD parity

module tb_parity();
reg x, clk, reset;
wire y, NS, PS;
parity Q6(x, clk, y);
//ques6b Q6(clk, reset, x, y, NS, PS);
initial
begin
clk=1'b0; //reset=1'b1;
end
always #5 clk=~clk;
initial
begin
x=0; //#1 reset=1'b0;
#2 x=1;
#10 x=1; #10 x=1;
#10 x=0; #10 x=1;
#10 x=1; #10 x=0;
#10 x=0; #10 x=1;
#10 x=1; #10 x=0;
#10 x=1; #10 x=0;
end
endmodule

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Question 7: Let us think about a special shifter circuit, which is capable of shifting by
more bit positions at a time; this circuit rotates the bit of input vector X[3:0] by a
specified number of bit positions, This circuit is known as Barrel shifter. Design a four
bit barrel shifter. Use structural level design style. Develop a stimulus model for
functional verification.

Solution 7:

//Verilog code for Barrel shifter

module shifter(X, reset, lrsh, S0, S1, out);
input [3:0] X;
input reset;
input [1:0] lrsh; //lrsh==0(left shift), lrsh==1(right shift)
input S0, S1;
output reg [3:0] out;
always @(reset or S0 or S1 or X or lrsh)
begin
if(reset==1)
out=4'b0000;
else if(reset==0 && lrsh==0)
begin
if(S0==0 && S1==0)
out<=X;
else if(S1==0 && S0==1)
out<=X<<1;
else if(S1==1 && S0==0)
out<=X<<2;
else if(S1==1 && S0==1)
out<=X<<3;
end
end
always @(reset or S0 or S1 or X or lrsh)
begin
if(reset==1)
out=4'b0000;
else if(reset==0 && lrsh==1)
begin
if(S0==0 && S1==0)
out<=X;
else if(S1==0 && S0==1)
out<=X>>1;
else if(S1==1 && S0==0)
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 out<=X>>2;
else if(S1==1 && S0==1)
out<=X>>3;
end
end
endmodule

//test bench for Barrel Shifter

module tb_shifter();
reg [3:0] X;
reg [1:0] lrsh;
reg reset;
reg S0, S1;
wire [3:0] out;
shifter Q7(X, reset, lrsh, S0, S1, out);
initial
begin
$display($stime, X, lrsh, out, reset, S0, S1);
X=4'b0000; reset=1'b1; S0=0; S1=0; lrsh=0;
#5 X=4'b1001; reset=1'b0;
#5 reset=1'b0; S0=0; S1=0; lrsh=0;
#5 S1=1;
#5 S0=1; S1=0;
#5 S1=1; #5 lrsh=1;
#5 S1=1;
#5 S0=1; S1=0;
#5 S1=1;
end
endmodule

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