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Coa Assignment-4: Akshit Aggarwal CS63 171294

This document contains the answers to three questions about input/output techniques. It discusses programmed I/O, interrupt-driven I/O, and direct memory access (DMA). For each technique, it provides details on how they work, advantages, and disadvantages. It also provides specifics on the Intel 8237A DMA controller and works through examples calculating time spent on bus transfers and processor time handling DMA transfers.

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Rajput Rishav
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121 views7 pages

Coa Assignment-4: Akshit Aggarwal CS63 171294

This document contains the answers to three questions about input/output techniques. It discusses programmed I/O, interrupt-driven I/O, and direct memory access (DMA). For each technique, it provides details on how they work, advantages, and disadvantages. It also provides specifics on the Intel 8237A DMA controller and works through examples calculating time spent on bus transfers and processor time handling DMA transfers.

Uploaded by

Rajput Rishav
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Coa Assignment-4

Akshit Aggarwal
CS63
171294

Ques.1.Explain the following techniques for Input/Output operations with suitable


flow chart , diagrams and step by step working:
1. Programmed I/O
2. Interrupt Driven I/O
3. Direct Memory Access (DMA)
Also compare the above techniques with their advantages and disadvantages

Ans1. Programmed I/O:-Programmed I/O (PIO) refers to data transfers initiated by a CPU
under driver software control to access registers or memory on a device. The CPU issues a
command then waits for I/O operations to be complete. As the CPU is faster than the I/O
module, the problem with programmed I/O is that the CPU has to wait a long time for the I/O
module of concern to be ready for either reception or transmission of data.
The CPU, while waiting, must repeatedly check the status of the I/O module, and this process
is known as Polling. As a result, the level of the performance of the entire system is severely
degraded.
Programmed I/O basically works in these ways:
 CPU requests I/O operation
 I/O module performs operation
 I/O module sets status bits
 CPU checks status bits periodically
 I/O module does not inform CPU directly
 I/O module does not interrupt CPU
 CPU may wait or come back later
Advantages & Disadvantages of Programmed I/O

Advantages - simple to implement

- very little hardware support

Disadvantages - busy waiting

- ties up CPU for long period with no useful work


Interrupt:-The CPU issues commands to the I/O module then proceeds with its normal
work until interrupted by I/O device on completion of its work.
For input, the device interrupts the CPU when new data has arrived and is ready to be
retrieved by the system processor. The actual actions to perform depend on whether the
device uses I/O ports, memory mapping.
For output, the device delivers an interrupt either when it is ready to accept new data or to
acknowledge a successful data transfer. Memory-mapped and DMA-capable devices
usually generate interrupts to tell the system they are done with the buffer.Although
Interrupt relieves the CPU of having to wait for the devices, but it is still inefficient in
data transfer of large amount because the CPU has to transfer the data word by word
between I/O module and
memory.
Below are the basic operations of
Interrupt: -CPU issues read
command -I/O module gets
data from peripheral whilst CPU does other work -I/O module interrupts
CPU -CPU requests
data -I/O
module transfers data
Advantages & Disadvantages of Interrupt Drive I/O

Advantages - fast

- efficient
Disadvantages - can be tricky to write if using a low level language

- can be tough to get various pieces to work well together

- usually done by the hardware manufacturer / OS maker,


e.g. Microsoft

Direct Memory Access (DMA):-Direct Memory Access (DMA) means CPU grants I/O
module authority to read from or write to memory without involvement. DMA module
controls exchange of data between main memory and the I/O device. Because of DMA
device can transfer data directly to and from memory, rather than using the CPU as an
intermediary, and can thus relieve congestion on the bus. CPU is only involved at the
beginning and end of the transfer and interrupted only after entire block has been
transferred.
Direct Memory Access needs a special hardware called DMA controller (DMAC) that
manages the data transfers and arbitrates access to the system bus.
The controllers are programmed with source and destination pointers (where to read/write
the data), counters to track the number of transferred bytes, and settings, which includes
I/O and memory types, interrupts and states for the CPU
cycles.
DMA increases system concurrency by allowing the CPU to perform tasks while the
DMA system transfers data via the system and memory busses. Hardware design is
complicated because the DMA controller must be integrated into the system, and the
system must allow the DMA controller to be a bus master. Cycle stealing may also be
necessary to allow the CPU and DMA controller to share use of the memory bus.
Advantages & Disadvantages of DMA

Advantages - allows a peripheral device to read from/write to memory


without going through the CPU

- allows for faster processing since the processor can be


working on something else while the peripheral can be populating
memory

Disadvantages - requires a DMA controller to carry out the operation, which


increases the cost of the system

- cache coherence problems


Ques.2. Explain the working of Intel 8237A DMA controller with suitable diagram.

•While the 8237A is using the buses to transfer data, the processor is idle. Similarly,
when the processor is using the bus, the DMA is idle.
•The 8237 DMA is known as a fly-by DMA controller. This means that the data being
moved from one location to another does not pass through the DMA chip and is not
stored in the DMA chip.
•Therefore, the DMA can only transfer data between an I/O port and a memory address,
but not between two I/O ports or two memory locations. However, the DMA chip can
perform a memory-to-memory transfer via a register which can temporarily hold the data.
•Phase 1: Initially, when the microprocessor-controlled devices were first introduced the
CPU directly controls a peripheral device.
•Phase 2: Then a controller or I/O module is added to the system configuration in which
the CPU uses programmed I/O without the interrupts.
•Phase 3: Interrupts are employed so that the CPU need not spend time waiting for an I/O
operation to be performed, thus increasing efficiency.
•Phase 4: During this evolutionary phase the I/O module is given direct access to memory
via DMA. The I/O device can now move a block of data to or from memory without
involving the CPU, except at the beginning and end of the transfer.
•Phase 5: Now, the I/O module is enhanced with a specialized instruction set tailored for
I/O operations. It is termed as the I/O channel, which is capable of fetching and executing
the I/O instructions without CPU intervention.
•Phase 6: The I/O module now has a local memory of its own and is, in fact, known as
I/O processor. With this architecture, a large set of I/O devices can be
controlled , with minimal CPU involvement.
Ques.3. a. Consider a system in which a data transfer over a bus
takes 500 ns. Transfer of bus control in either direction, from
processor to I/O device or vice versa, takes 250 ns. One of the
I/O devices has a data transfer rate of 50 KB/s and employs
DMA. Data are transferred one byte at a time. Suppose we
employ DMA in a burst mode. For how long would the device
tie up the bus when transferring a block of 128 bytes?
b.An I/O device transfers 10 MB/s of data into the memory of a
processor over the I/O bus, which has a total data transfer
capacity of 100 MB/s. The 10 MB/s of data is transferred as 2500
independent pages of 4 KB each. If the processor operates at 200
MHz, it takes 1000 cycles to initiate a DMA transaction, and
1500 cycles to respond to the device's interrupt when the DMA
transfer completes, what fraction of the processor's time is spent
handling the data transfer with and without DMA?

Ans.3.a) For the actual transfer, 50Kbytes require 1 sec to be


transferred so the time required to transfer 128Bytes is equal(128
bytes)/(50 KBps) = 2.56ms.
Added to this is the time to transfer bus control at the beginning and
end of the transfer, which is 250 + 250 = 500 ns.
This additional time is negligible, so that the transfer time can be
considered as 2.56 ms.

b.Initiating each DMA and responding to the interrupt at the end of each
transfer. This takes 2500 cycles/transfer, or a total of 6,250,000 cycles
(2500 pages * 2500 cycles/page transfer) spent handling DMAs each
second. Since the processor operates at 200 MHz. this means that 3.125
percent of each second, or 3.125 percent of the processor's time

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