Dept.

of ECE MCQ - Regulations 2017

d) The collector current is always zero and

the base current is always non zero
EC8351
Answer: b
ELECTRONIC

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Explanation: Both collector and emitter
current are zero in cut-off region.
CIRCUITS I

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3. Which of the following is true for a typical
active region of an npn transistor?

ECE - 3rd Semester -

a) The potential difference between the

C
emitter and the collector is less than 0.5 V
b) The potential difference between the
Reg. 2017

T.
emitter and the collector is less than 0.4 V
c) The potential difference between the
emitter and the collector is less than 0.3 V

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d) The potential difference between the
emitter and the collector is less than 0.2 V
UNIT I BIASING OF

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Answer: c
DISCRETE BJT, JFET Explanation: Most commonly used
transistors have Vce less than 0.4 V for the
AND MOSFET active region.
G
TOPIC 1.1 BIPLOLAR 4. Which of the following is true for the
active region of an npn transistor?
LO

JUNCTION TRANSISTOR (BJT) a) The collector current is directly

proportional to the base current
1. Which of the following condition is true b) The potential difference between the
for cut-off mode? emitter and the collector is less than 0.4 V
.B

a) The collector current Is zero c) All of the mentioned

b) The collector current is proportional to the d) None of the mentioned
base current
17

c) The base current is non zero Answer: c

d) All of the mentioned Explanation: The base current and the
collector current are directly proportional to
Answer: a each other and the potential difference
Explanation: The base current as well as the
-R

between the collector and the base is always

collector current are zero in cut-off mode. less than 0.4 V.

2. Which of the following is true for the cut- 5. Which of the following is true for the
SE

off region in an npn transistor? saturation region of BJT transistor?

a) Potential difference between the emitter a) The collector current is inversely
and the base is smaller than 0.5V proportional to the base current
b) Potential difference between the emitter b) The collector current is proportional to the
C

and the base is smaller than 0.4V square root of the collector current
c) The collector current increases with the c) The natural logarithm of the collector
increase in the base current current is directly proportional to the base

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 Dept. of ECE MCQ - Regulations 2017

current than 0.3V, for an npn transistor it is greater

d) None of the mentioned than 0.3V.

Answer: b 9. Which of the following is true for a pnp

Explanation: The collector current is directly transistor in active region?

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proportional to the base current in the a) CB junction is reversed bias and the EB
saturation region of the BJT. junction is forward bias
b) CB junction is forward bias and the EB

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6. Which of the following is true for a npn junction is forward bias
transistor in the saturation region? c) CB junction is forward bias and the EB

C
a) The potential difference between the junction is reverse bias
collector and the base is approximately 0.2V d) CB junction is reversed bias and the EB

T.
b) The potential difference between the junction is reverse bias
collector and the base is approximately 0.3V
c) The potential difference between the Answer: a
collector and the base is approximately 0.4V Explanation: Whether the transistor in npn or

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d) The potential difference between the pnp, for it be in active region the EB junction
collector and the base is approximately 0.5V must be reversed bias the CB junction must

SP
be forward bias.
Answer: d
Explanation: The commonly used npn 10. Which of the following is true for a pnp
transistors have a potential difference of transistor in saturation region?
G
around 0.5V between he collector and the a) CB junction is reversed bias and the EB
base. junction is forward bias
b) CB junction is forward bias and the EB
LO

7. The potential difference between the base junction is forward bias

and the collector Vcb in a pnp transistor in c) CB junction is forward bias and the EB
saturation region is ________ junction is reverse bias
a) -0.2 V d) CB junction is reversed bias and the EB
.B

b) -0.5V junction is reverse bias

c) 0.2 V
d) 0.5 V Answer: b
Explanation: Whether the transistor in npn or
17

Answer: b pnp, for it be in saturation region the EB

Explanation: The value of Vcb is -0.5V for a junction must be forward bias the CB
pnp transistor and 0.5V for an npn transistor. junction must be forward bias.
-R

8. For a pnp transistor in the active region the

value of Vce (potential difference between TOPIC 1.2 NEED FOR BIASING -
the collector and the base) is DC LOAD LINE AND BIAS
a) Less than 0.3V POINT
SE

b) Less than 3V
c) Greater than 0.3V
1. Which of the following depicts the DC
d) Greater than 3V
load line?
C

Answer: a
Explanation: For a pnp transistor Vce is less

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 Dept. of ECE MCQ - Regulations 2017

2. For the circuit shown, find the quiescent

point.

M
O
a)

C
T.
a) (10V, 4mA)
b) (4V, 10mA)

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c) (10V, 3mA)
d) (3mA, 10V)

SP
Answer: c
b) Explanation: We know,
IE=VEE/RE=30/10kΩ=3mA
IC=α IE =IE =3mA
G
VCB=VCC-ICRL=25-15=10V. So, quiescent
point is (10V, 3mA).
LO

3. Which of the following depicts the load

line for the circuit shown below?
c)
.B
17
-R

d)
SE

Answer: a
Explanation: In transistor circuit analysis,
sometimes it is required to know the collector
currents for various collector emitter voltages.
The one way is to draw its load line. We
C

require the cut off and saturation points.

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 Dept. of ECE MCQ - Regulations 2017

VCB=VCC-ICRL=20-15=5V. So, quiescent

point is (5V, 3mA).

4. For the circuit shown, find the quiescent

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point.

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a)

C
T.
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SP
a) (6V, 1mA)
b) (4V, 10mA)
b)
c) (10V, 3mA)
d) (3mA, 10V)
G
Answer: c
LO

Explanation: We know, VCE=12V

(IC)SAT =VCC/RL=12/6K=2mA.
IB=10V/0.5M=20µA. IC= βIB=1mA. I
VCE=VCC-ICRL=12-1*6=6V. So, quiescent
.B

point is (6V, 1mA).

c)
5. Which of the following depicts the load
17

line for the given circuit?

-R
SE

d)

Answer: d
Explanation: We know,
C

IE=VEE/RE=15/5kΩ=3mA
IC=α IE =IE =3mA

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 Dept. of ECE MCQ - Regulations 2017

VCE=VCC-ICRL=10-1*2=8V. So, quiescent

point is (8V, 1mA).

6. The DC equivalent circuit for an NPN

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common base circuit is.

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C
a)

T.
O
b)
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G
LO
.B

c)
17
-R
SE

d)

Answer: d
Explanation: We know, VCE=6V
C

(IC)SAT =VCC/RL=10/2K=5mA.
IB=10V/0.5M=20µA. IC= βIB=1mA. I

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 Dept. of ECE MCQ - Regulations 2017

7. The DC equivalent circuit for an NPN

common emitter circuit is.

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C
T.
O
SP
G
LO
.B
17
-R

Answer: a
Explanation: In the common base circuit, the
emitter diode acts like a forward biased ideal
SE

diode, while collector diode acts as a current

source due to transistor action. Thus an ideal
transistor may be regarded as a rectifier diode
in the emitter and a current source at
C

collector.

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 Dept. of ECE MCQ - Regulations 2017

emitter configuration?

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C
T.
O
SP
G
LO
.B
17
-R

Answer: b
Explanation: In the common emitter circuit,
the ideal transistor may be regarded as a
SE

rectifier diode in the base circuit and a current

source in the collector circuit. In the current
source, the direction of arrow points in
direction of conventional current.
C

8. What is the other representation of the Answer: d

given PNP transistor connected in common Explanation: The emitter junction is forward

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 Dept. of ECE MCQ - Regulations 2017

biased with the help of battery VEE by which, VCB=VCC-ICRL=20-10=10V. So, quiescent
negative of the battery is connected to the point is (10V, 2mA).
emitter while positive is connected to base.
RE is the emitter resistance. The collector
TOPIC 1.3 DC ANALYSIS OF

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junction is reversed biased.
TRANSISTOR CIRCUITS
9. What is the DC characteristic used to prove

O
that the transistor is indeed biased in 1. The feature of an approximate model of a
saturation mode? transistor is
a) IC = βIB a) it helps in quicker analysis

C
b) IC > βIB b) it provides individual analysis for different
configurations

T.
c) IC >> βIB
c) it helps in dc analysis
d) IC < βIB d) ac analysis is not possible

O
Answer: d Answer: a
Explanation: When in a transistor is driven Explanation: The small signal model helps in
into saturation, we use VCE(SAT) as another quicker ac analysis of a transistor. The

SP
linear parameter. In, addition when a approximate model is applicable for all the
transistor is biased in saturation mode, we configurations. The dc analysis is not
have IC < βIB. This characteristic used to obtained by using a small signal model of
prove that the transistor is indeed biased in transistor.
G
saturation mode.
2 A transistor has hfe=100, hie=2kΩ,
LO

10. For the circuit shown, find the quiescent hoe=0.005mmhos, hre=0. Find the output
point. impedance if the lad resistance is 5kΩ.
a) 5kΩ
b) 4kΩ
.B

c) 20kΩ
d) 15kΩ

Answer: b
17

Explanation: RO=I/hoe=1/0.005m
=20kΩ.ROI= RO || RLI=20||5
=4kΩ.
-R

3. A CE amplifier when bypassed with a

a) (10V, 4mA) capacitor at the emitter resistance has
b) (4V, 10mA) a) increased input resistance and increased
SE

c) (10V, 3mA) voltage gain

d) (3mA, 10V) b) increased input resistance and decreased
voltage gain
Answer: c c) decreased input resistance and increased
Explanation: We know,
C

voltage gain
IE=VEE/RE=10/5kΩ=2mA d) decreased input resistance and decreased
IC=α IE =IE =2mA voltage gain

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 Dept. of ECE MCQ - Regulations 2017

Answer: c
Explanation: When a transistor is bypassed
with a capacitor, it short circuits in the small
signal analysis of transistor and the resistor
too shorts. The input resistance becomes

M
RI=hie. The value of the input resistance is
decreased and the gain now will be

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increasing.

4. A transistor has hie =2kΩ, hoe=25µmhos a) 100kΩ

b) 50kΩ

C
and hfe=60 with an unbypassed emitter c) 40kΩ
resistor Re=1kΩ. What will be the input d) 60kΩ

T.
resistance and output resistance?
a) 90kΩ and 50kΩ respectively Answer: b
b) 33kΩ and 45kΩ respectively Explanation: RAB=RO||100Ω

O
c) 6kΩ and 40kΩ respectively
= (RSI+hie/1+hfe)||100
d) 63kΩ and 40kΩ respectively
=9+1/100||100=100||100=50Ω.

SP
Answer: d
Explanation: As the emitter is unbypassed, 7. Which of the following acts as a buffer?
the input resistance Ri=hie+(1+hfe)Re a) CC amplifier
b) CE amplifier
=2+61=63kΩ. The output resistance
G
c) CB amplifier
RO=1/hoe=1/25MΩ=40kΩ.
d) cascaded amplifier
LO

5. A transistor has hie =1KΩ and hfe=60 with Answer: a

an bypassed emitter resistor Re=1kΩ. What Explanation: The voltage gain of a common
will be the input resistance and output collector amplifier is unity. It is then used as a
resistance? buffer. The CC amplifier is also called as an
.B

a) 90kΩ and 50kΩ respectively emitter follower. Though there is no

b) 33kΩ and 45kΩ respectively amplification done, the output will be
c) 6kΩ and 40kΩ respectively stabilised.
17

d) 63kΩ and 40kΩ respectively

8. Which of the following is true?
Answer: d a) CC amplifier has a large current gain
Explanation: As the emitter is bypassed, the b) CE amplifier has a large current gain
c) CB amplifier has low voltage gain
-R

input resistance Ri=hie

=1kΩ. The output resistance RO=1/hoe but d) CC amplifier has low current gain
the value is not given. Answer: b
So, hoe=0 and RO=1/0=∞.
SE

Explanation: The CE amplifier has high

current and voltage gains. The CC amplifier
6. In the given circuit, find the equivalent has unity voltage gain which cannot be
resistance between A and B nodes. regarded as high. The common base amplifier
has a unity current gain and high voltage
C

gain.

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 Dept. of ECE MCQ - Regulations 2017

9. In an NPN silicon transistor, α=0.995, IC = βIB and IE = IC + IB

IE=10mA and leakage current ICBO=0.5µA. Hence, IE = (β + 1) IB.
Determine ICEO.
a) 10µA 2. For best operation of a BJT, which region

M
b) 100µA must the operating point be set at?
c) 90µA a) Active region
d) 500µA b) Cutoff region

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c) Saturation region
Answer: b d) Reverse active region
Explanation: IC=α IE +ICBO

C
=0.995*10mA+0.5µA=9.9505mA. Answer: a
IB=IE-IC=10-9.9505=0.0495mA. β=α/(1- Explanation: Operating point for a BJT must

T.
always be set in the active region to ensure
α)=0.995/(1-0.995)=199
proper functioning. Setting up of Q-point in
ICEO=9.9505-199*0.0495=0.1mA==100µA.
any other region may lead to reduced

O
functionality.
10. In CB configuration, the value of
α=0.98A. A voltage drop of 4.9V is obtained 3. From the given circuit, using a silicon

SP
across the resistor of 5KΩ when connected in transistor, what is the value of IBQ?
collector circuit. Find the base current.
a) 0.01mA
b) 0.07mA
G
c) 0.02mA
d) 0.05mA
LO

Answer: c
Explanation: Here, IC=4.9/5K=0.98mA
α = IC/IE .So,
IE=IC/α=0.98/0.98=1mA.
.B

IB=IE-IC=1-0.98=0.02mA.
a) 47.08 mA
b) 47.08 uA
17

TOPIC 1.4 VARIOUS BIASING c) 50 uA

METHODS OF BJT d) 0 mA

Answer: b
1. Which of the following is the correct
-R

Explanation: Consider the BJT to be in

relationship between base and emitter current saturation. Then IC=12-0.2/2.2k=5.36 mA
of a BJT? And IB=12-0.8/240k=0.047 mA
a) IB = β IE
IBMIN=ICSAT/β=5.09/50=0.1072mA which is
SE

b) IB = IE
greater than above IB.
c) IB = (β + 1) IE
Hence transistor is in the active region.
d) IE = (β + 1) IB Thus IC=βIB.
C

VBE=0.7V
Answer: d
Explanation: For a BJT, the collector current IB=12-0.7/240=47.08μA

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 Dept. of ECE MCQ - Regulations 2017

4. From the given circuit, using a silicon BJT, b) -6.13 V

what is the value of VCEQ? c) 7 V
d) -7 V

Answer: b

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Explanation: Consider the BJT to be in
saturation. Then IC=12-0.2/2.2k=5.36 mA

O
And IB=12-0.8/240k=0.047 mA
IBMIN=ICSAT/β=5.09/50=0.1072mA which is

C
greater than above IB.
Hence transistor is in the active region.

T.
Thus IC=βIB.
a) 7 V VBE=0.7V
b) 0.7 V IB=12-0.7/240=47.08μA
c) 6.83 V

O
IC=50×47.08=2.354 mA
d) 7.17 V
VCE=VCC-ICRC=12-2.354*2.2=12-

SP
Answer: c 5.178=6.83V
Explanation: Consider the BJT to be in Hence VBC = 0.7-6.83 = -6.13V.
saturation. Then IC=12-0.2/2.2k=5.36 mA
And IB=12-0.8/240k=0.047 mA 6. From the given circuit, using silicon BJT,
G
IBMIN=ICSAT/β=5.09/50=0.1072mA which is what is the value of the saturation collector
greater than above IB. current?
LO

Hence transistor is in the active region.

Thus IC=βIB.
VBE=0.7V
IB=12-0.7/240=47.08μA
.B

IC=50×47.08=2.354 mA
VCE=VCC-ICRC=12-2.354*2.2=12-
17

5.178=6.83V.

5. From the given circuit, using a silicon BJT,

what is the value of VBC? a) 5 mA
b) 5.36 mA
-R

c) 5.45 mA
d) 10.9 mA
SE

Answer: b
Explanation: To obtain an approximate
answer, under saturation the BJT is ON and
hence acts like a short circuit. However,
ideally a drop exists for the transistor which is
C

a fixed value. For an exact answer, if the BJT

is a Silicon transistor, then drop VCE = 0.2V
a) 6.13 V and current is 12-0.2/2.2=5.36 mA.

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 Dept. of ECE MCQ - Regulations 2017

7. In the given circuit, what is the value of IC

if the BJT is made of Silicon?

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C
T.
a) 20 V

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b) 15.52 V
a) 2.01 mA c) 14.98 V

SP
b) 2.01 uA d) 13.97 V
c) 10.05 mA
d) 10.05 uA Answer: b
Explanation: Consider the BJT to be in
saturation. Then IC=20-0.2/2k=9.9 mA
G
Answer: a
Explanation: Consider the BJT to be in And IB=20-0.8/430k=0.044 mA
saturation. Then IC=20-0.2/2k=9.9 mA IBMIN=ICSAT/β=5.09/50=0.198mA which is
LO

And IB=20-0.8/430k=0.044 mA greater than above IB.

IBMIN=ICSAT/β=5.09/50=0.198mA which is Hence transistor is in the active region.
greater than above IB. Thus IC=βIB.
.B

Hence transistor is in the active region. VBE=0.7V

Thus IC=βIB. IB=20-0.7/430=44.88μA
VBE=0.7V IC=50×44.88=2.24 mA
17

IB=20-0.7/430=44.88μA VCE=20-2.24*2=15.52V.
IC=50×44.88=2.24 mA.
9. In the given circuit, what is the value of VE
8. In the given circuit, using a silicon BJT, when using a silicon BJT?
-R

what is the value of VCE?

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C

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 Dept. of ECE MCQ - Regulations 2017

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C
T.
a) 2.01 V a) 10 mA

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b) 0.28 V b) 8.77 mA
c) 0 V c) 6.67 mA

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d) 2.28 V d) 5 mA

Answer: d Answer: c
Explanation: Consider the BJT to be in Explanation: To obtain an approximate
saturation. Then IC=20-0.2/2k=9.9 mA answer, under saturation the BJT is ON and
G
And IB=20-0.8/430k=0.044 mA hence acts like a short circuit. However,
ideally a drop exists for the transistor which is
IBMIN=ICSAT/β=5.09/50=0.198mA which is
LO

a fixed value. For an exact answer, if the BJT

greater than above IB. is a Silicon transistor, then drop VCE = 0.2V
Hence transistor is in the active region. and current is 20-0.2/2.2=9.9 mA.
Thus IC=βIB.
.B

VBE=0.7V
TOPIC 1.5 BIAS CIRCUIT
IB=20-0.7/430=44.88μA
DESIGN - THERMAL
IC=50×44.88=2.24 mA
STABILITY - STABILITY
17

VCE=20-2.24*2=15.52V
FACTORS
VE=IERE=(1+β)IBRE=51*44.88*1=2.28V.

10. In the given circuit using a silicon BJT, 1. What is Stability factor?
-R

what is the value of saturation collector a) Ratio of change in collector current to

current? change in a current amplification factor
b) Ratio of change in collector current to
change in base current
SE

c) Current amplification factor

d) Ratio of base current to collector current

Answer: a
C

Explanation: Stability factor is defined as the

rate at which collector current changes when
Base to emitter voltage changes, keeping base

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 Dept. of ECE MCQ - Regulations 2017

current constant. It can also be defined as the change in beta does not affect much on the
ratio of change in collector current to change collector current. When S is high, even if IB
in base current when temperature changes changes by a small value, the IC current will
occur. drastically vary. Hence stability factor must

M
possess lesser value for the proper working of
2. The base current for a BJT remains
a transistor.
constant at 5mA, the collector current
changes from 0.2mA to 0.3 mA and beta was

O
5. What is the value of Stability factor for an
changed from 100 to 110, then calculate the ideal transistor?
value of S.
a) 100

C
a) 0.01m
b) 1000
b) 1m
c) infinite

T.
c) 100m
d) 0
d) 25m
Answer: 0
Answer: a

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Explanation: For a transistor, the ideal value
Explanation: Since the current in the above
of S is 0 which interprets that for a change in
case, remains constant, therefore stability
beta, there should not be changing. In Ideal

SP
factor is 0.01 as it is defined as the ratio of
transistor, the collector current will vary only
change in collector current to change in beta.
if either base or emitter current varies or
S=change in collector current/change in
hence for an ideal transistor the value of S is
beta=0.1mA/10=0.01m.
zero.
G
3. For a n-p-n transistor, the collector current
6. For a fixed bias circuit having Ic = 0.3mA
changed from 0.2mA to 0.22mA resulting a
LO

change of base emitter voltage from 0.8v to and In=0.0003mA, S is______________

0.8005V. What is the value of Stability a) 100
factor? b) 0
a) 0 c) 11
d) 111
.B

b) 0.25
c) 0.04
Answer: c
d) 0.333
Explanation: For fixed bias S=1+beta
17

Answer: c Beta=IC/IB=10
Explanation: Change in Vbe = 0.0005V S=1+10=11.
Change in collector current = 0.02mA
S = 0.02m/0.0005 = 0.04. 7. For a fixed bias circuit having RC=2Kohm
-R

and VCC=60V, IB=0.25mA and S=101, find

4. There are two transistors A and B having Vce.
‘S’ as 25 and 250 respectively, on comparing a) 12V
SE

the value of S, we can say B is more stable b) 10V

than A. c) 5V
a) True d) 2.5V
b) False
C

Answer: b
Answer: b Explanation: S = 1 + beta,
Explanation: More the value of S, lesser the => 100 = IC/IB => Ic = 25mA
stability, since A has lesser S value the

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 Dept. of ECE MCQ - Regulations 2017

Vce = VCC – Ic RC 1. The compensation techniques are used

Vce = 10V. to_________
a) increase stability
8. For an ideal transistor having a fixed bias b) increase the voltage gain
c) improve negative feedback

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configuration, what will be the value of Beta?
a) 0 d) decrease voltage gain
b) 2
Answer: b

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c) -1
d) 1 Explanation: Usually, the negative feedback
is used to produce a stable operating point.

C
Answer: c But it reduces the voltage gain of the circuit.
Explanation: S = 1 + Beta This sometimes is intolerable and should be

T.
S=0 avoided in some applications. So, the biasing
Beta = -1. techniques are used.

2. Compensation techniques refer to the use

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9. The temperature changes do not affect the
Stability. of_________
a) True a) diodes

SP
b) False b) capacitors
c) resistors
Answer: b d) transformers
Explanation: The temperature changes the
G
value of beta which in turn changes the Answer: a
stability of the transition. The temperature Explanation: Compensation techniques refer
changes affect the mobility of the charge to the use of temperature sensitive devices
LO

carries which results in a change of the such as thermistors, diodes, transistors,

current parameters affecting stability. sensistors etc to compensate variation in
currents. Sometimes for excellent bias and
10. Comparing fixed and collector to base thermal stabilization, both stabilization and
.B

bias which of the following statement is true? compensation techniques are used.
a) Fixed bias is more stable
b) Collector to base bias is more stable 3. In a silicon transistor, which of the
following change significantly to the change
17

c) Both are the same in terms of stability

d) Depends on the design in IC?
a) VCE
Answer: b b) IB
Explanation: For fixed bias circuit, S =
-R

c) VBE
1+beta, more the beta, lesser the stability
For collector to base bias S = b) IE
(1+beta)/(1+beta(RC/RC+RB))
SE

Hence collector to base bias is more stable. Answer: c

Explanation: For germanium transistor,
changes in ICO with temperature contribute
TOPIC 1.6 BIAS more serious problem than for silicon
COMPENSATION TECHNIQUES
C

transistor. On the other hand, in a silicon

USING DIODE, THERMISTOR transistor, the changes of VBE with
AND SENSISTOR

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 Dept. of ECE MCQ - Regulations 2017

temperature possesses significantly to the means, its resistance decreases exponentially

changes in IC. with increasing T. The thermistor RT is used
to minimize the increase in collector current.
4. What is the compensation element used for
7. Which of the following has a negative

M
variation in VBE and ICO?
a) diodes temperature coefficient of resistance?
b) capacitors a) capacitor
b) diode

O
c) resistors
d) transformers c) thermistor
d) sensistor

C
Answer: a
Answer: d
Explanation: A diode is used as the

T.
Explanation: The sensistor has a positive
compensation element used variation in VBE
temperature coefficient of resistance. It is a
and ICO. The diode used is of the same temperature sensitive resistor. It is a heavily
material and type as that of transistor. Hence, doped semiconductor. When voltage is

O
the voltage across the diode has same decreased, the net forward emitter voltage
temperature coefficient as VBE of the decreases. As a result the collector current

SP
transistor. decreases.

5. The expression for IC in the compensation 8. Increase in collector emitter voltage from
for instability due to ICO variation_________ 5V to 8V causes increase in collector current
G
from 5mA to 5.3mA. Determine the dynamic
a) βI+βIO+βICO
output resistance.
b) βI+βIO a) 20kΩ
LO

c) βIO+βICO b) 10kΩ
d) βI+βICO c) 50kΩ
d) 60kΩ
Answer: a
.B

Answer: b
Explanation: In this method, diode is used
Explanation: ro=∆VCE/∆IC
for the compensation in variation of ICO. The
=3/0.3m=10kΩ.
diode used is of the same material and type as
17

that of transistor. Hence, the reverse

9. The output resistance of CB transistor is
saturation current IO of the diode will
given by _________
increase with temperature at the same rate as a) ∆VCB/∆IC
the transistor collector saturation current ICO.
-R

b) ∆VBE/∆IB
6. Which of the following has a negative c) ∆VBE/∆IC
temperature coefficient of resistance? d) ∆VEB/∆IE
SE

a) sensistor
b) diode Answer: a
c) thermistor Explanation: The ratio of change in collector
d) capacitor base voltage (∆VCB) to resulting change in
collector current (∆IC) at constant emitter
C

Answer: c
current (IE) is defined as output resistance.
Explanation: The thermistor has a negative
temperature coefficient of resistance. It This is denoted by ro.

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 Dept. of ECE MCQ - Regulations 2017

10. The negative sign in the formula of to VGS, and small changes in VGS cause
amplification factor indicates_________ proportionate changes in IDS, and the device
a) that IE flows into transistor while IC flows can act as an amplifier.
out it

M
b) that IC flows into transistor while IE flows 2. In the given situation for n-channel JFET,
out it we get drain-to-source current is 5mA. What
c) that IB flows into transistor while IC flows is the current when VGS = – 6V?

O
out it
d) that IC flows into transistor while IB flows

C
out it

T.
Answer: a
Explanation: When no signal is applied, the
ratio of collector current to emitter current is
called dc alpha, αdc of a transistor. αdc=-

O
IC/IE. It is the measure of the quality of a
transistor. Higher is the value of α, better is

SP
the transistor in the sense that collector
current approaches the emitter current. a) 5 mA
b) 0.5A
c) 0.125 A
G
TOPIC 1.7 BIASING BJT d) 0.5A
SWITCHING CIRCUITSJFET -
Answer: c
LO

DC LOAD LINE AND BIAS

POINT, VARIOUS BIASING Explanation: IDS = IDSS(1-VGS/VP)2
METHODS OF JFET - JFET When VGS = 0, IDSS = IDS = 5mA
BIAS CIRCUIT DESIGN When VGS = -6V, IDS = 5mA(1 + 4)2
.B

IDS = 5 x 25 = 125 mA.

1. Which of the following statements are
true? 3. Consider the following circuit. Given that
17

P: JFET is biased to operate it in active region VDD = 15V, VP = 2V, and IDS = 3mA, to bias
Q: MOSFET is biased to operate it in the circuit properly, select the proper
saturation region statement.
a) Both P and Q are correct
-R

b) P is correct and Q is incorrect

c) P is incorrect and Q is correct
d) Both P and Q are incorrect
SE

Answer: c
Explanation: While transistors are biased to
work in the active region, to act as amplifiers,
FET devices are instead biased in the
C

saturation region to work as an amplifier,

whether it be a JFET or a MOSFET. In
saturation, current IDS changes with respect

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 Dept. of ECE MCQ - Regulations 2017

M
O
C
T.
O
a) RD < 6kΩ
b) RD > 6kΩ a) -30V

SP
c) RD > 4kΩ b) 30V
c) 33V
d) RD < 4kΩ
d) Any value of voltage less than 12 V
G
Answer: a Answer: c
Explanation: In given circuit, VGS = -5V Explanation: VDS = VDD – IDS(10k + 5k)
VDS = VDD – IDSRD
LO

3 = VDD – 2(15)
To bias properly VDS > |VP| – |VGS| 3 = VDD – 30
VDS > -3 VDD = 33 V.
15 – 3mA*RD > -3
.B

-3mA*RD > -18 5. To bias a e-MOSFET ___________

RD < 6kΩ. a) we can use either gate bias or a voltage
divider bias circuit
17

4. Consider the circuit shown. VDS=3 V. If b) we can use either gate bias or a self bias
circuit
IDS=2mA, find VDD to bias circuit. c) we can use either self bias or a voltage
divider bias circuit
d) we can use any type of bias circuit
-R

Answer: a
Explanation: To bias an e-MOSFET, we
SE

cannot use a self bias circuit because the gate

to source voltage for such a circuit is zero.
Thus, no channel is formed and without the
channel, the MOSFET doesn’t work properly.
If self bias circuit is used, then D-MOSFET
C

can be operated in depletion mode.

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 Dept. of ECE MCQ - Regulations 2017

6. Consider the following circuit. Process

transconductance parameter = 0.50 mA/V2,
W/L=1, Threshold voltage = 3V, VDD = 20V.
Find the operating point of circuit.

M
O
C
T.
a) -3.83V, 0.766mA

O
b) -2.345V, 0.469mA
c) 3.83V, 0.469mA
d) 2.3V, 0.7mA

SP
a) 20V, 25mA Answer: b
b) 13V, 22mA Explanation: When VGS = VP then IDSS =
c) 12.72V, 23.61mA
IDS = 10mA
G
d) 20V, 23.61mA
Also, in above circuit, VGS = -IDSRS = –
Answer: c IDSx5k
LO

Explanation: IDS = [k’W/L(VGS – VT)2]/2 Thus, IDS = IDSS(1-VGS/VP)2

VGS = 20 x 35 / 55 = 12.72 V Solving we get, IDS = 0.766mA, 0.469mA
IDS = 0.25 (9.72)2 Thus we get VGS = -3.83V, -2.345V
.B

IDS = 23.61 mA. However, VGS should lie between 0 and VP.

7. Given VDD = 25V, VP = -3V. When VGS = 8. Consider the following circuit. IDSS =
17

-3V, IDS = 10mA. Find the operating point of 2mA, VDD = 30V. Find R, given that VP = –
the circuit. 2V.
-R
SE
C

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 Dept. of ECE MCQ - Regulations 2017

IDS is stable due to the presence of source

resistance RS in the circuit. The source
resistance helps provide negative feedback to
keep current stable. Capacitor CS is a bypass

M
capacitor to prevent decrease in voltage gain.

10. For a MOSFET, the pinch-off voltage is

O
-3V. Gate to source voltage is 20V. W/L ratio
is 5. Process transconductance parameter is

C
40μA/V2. Find drain to source current in
saturation.

T.
a) 0.10 mA
b) 0.05mA
c) – 0.05mA
d) – 50A

O
a) 10kΩ Answer: c

SP
b) 4kΩ Explanation: ISD = k’W(VSG – |VT|)2/2L
c) 2kΩ ISD = 20*5*(-20-3)2 = 52900μA = 0.05mA.
d) 5kΩ
G
Answer: b TOPIC 1.8 MOSFET BIASING
Explanation: IDSS = 2mA
LO

IDS = (VDD – 15)/50k = 0.3mA 1. Which of the following statements are

VGS = VP [1 – √
IDS
] true?
DSS
P: JFET is biased to operate it in active region
VGS = -2 x (1 – √.15) = – 1.22V Q: MOSFET is biased to operate it in
saturation region
.B

Thus VGS + IDS x (R) = 0

R = 1.22/0.3mA = 4kΩ. a) Both P and Q are correct
b) P is correct and Q is incorrect
9. Which of the following statements are c) P is incorrect and Q is correct
17

true? d) Both P and Q are incorrect

A: In a self bias circuit, the current IDS is not
stable. Answer: c
B: Source capacitance, CS, parallel to RS, Explanation: While transistors are biased to
-R

reduces stability. work in the active region, to act as amplifiers,

a) Both statements are correct and B is the FET devices are instead biased in the
correct reasoning saturation region to work as an amplifier,
whether it be a JFET or a MOSFET. In
SE

b) Both statements are correct but B is not the

correct reason for it saturation, current IDS changes with respect
c) Statement A is correct while statement B is to VGS, and small changes in VGS cause
wrong proportionate changes in IDS, and the device
d) Both statements are incorrect
C

can act as an amplifier.

Answer: d 2. In the given situation for n-channel JFET,
Explanation: In a self bias circuit, the current we get drain-to-source current is 5mA. What

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 Dept. of ECE MCQ - Regulations 2017

is the current when VGS = – 6V? c) RD > 4kΩ

d) RD < 4kΩ

Answer: a

M
Explanation: In given circuit, VGS = -5V
VDS = VDD – IDSRD
To bias properly VDS > |VP| – |VGS|

O
VDS > -3
15 – 3mA*RD > -3

C
-3mA*RD > -18
RD < 6kΩ.

T.
a) 5 mA
b) 0.5A 4. Consider the circuit shown. VDS=3 V. If
c) 0.125 A IDS=2mA, find VDD to bias circuit.

O
d) 0.5A

SP
Answer: c
Explanation: IDS = IDSS(1-VGS/VP)2
When VGS = 0, IDSS = IDS = 5mA
When VGS = -6V, IDS = 5mA(1 + 4)2
G
IDS = 5 x 25 = 125 mA.
LO

3. Consider the following circuit. Given that

VDD = 15V, VP = 2V, and IDS = 3mA, to bias
the circuit properly, select the proper
statement.
.B
17

a) -30V
b) 30V
c) 33V
-R

d) Any value of voltage less than 12 V

Answer: c
Explanation: VDS = VDD – IDS(10k + 5k)
SE

3 = VDD – 2(15)
3 = VDD – 30
VDD = 33 V.
C

a) RD < 6kΩ 5. To bias a e-MOSFET ___________

b) RD > 6kΩ a) we can use either gate bias or a voltage
divider bias circuit

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 Dept. of ECE MCQ - Regulations 2017

b) we can use either gate bias or a self bias 7. Given VDD = 25V, VP = -3V. When VGS =
circuit -3V, IDS = 10mA. Find the operating point of
c) we can use either self bias or a voltage the circuit.
divider bias circuit
d) we can use any type of bias circuit

M
Answer: a
Explanation: To bias an e-MOSFET, we

O
cannot use a self bias circuit because the gate
to source voltage for such a circuit is zero.

C
Thus, no channel is formed and without the
channel, the MOSFET doesn’t work properly.

T.
If self bias circuit is used, then D-MOSFET
can be operated in depletion mode.

6. Consider the following circuit. Process

O
transconductance parameter = 0.50 mA/V2,
W/L=1, Threshold voltage = 3V, VDD = 20V.

SP
a) -3.83V, 0.766mA
Find the operating point of circuit.
b) -2.345V, 0.469mA
c) 3.83V, 0.469mA
d) 2.3V, 0.7mA
G
Answer: b
Explanation: When VGS = VP then IDSS =
LO

IDS = 10mA
Also, in above circuit, VGS = -IDSRS = –
IDSx5k
Thus, IDS = IDSS(1-VGS/VP)2
.B

Solving we get, IDS = 0.766mA, 0.469mA

Thus we get VGS = -3.83V, -2.345V
17

However, VGS should lie between 0 and VP.

a) 20V, 25mA
b) 13V, 22mA 8. Consider the following circuit. IDSS =
c) 12.72V, 23.61mA 2mA, VDD = 30V. Find R, given that VP = –
-R

d) 20V, 23.61mA 2V.

Answer: c
SE

Explanation: IDS = [k’W/L(VGS – VT)2]/2

VGS = 20 x 35 / 55 = 12.72 V
IDS = 0.25 (9.72)2
IDS = 23.61 mA.
C

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 Dept. of ECE MCQ - Regulations 2017

IDS is stable due to the presence of source

resistance RS in the circuit. The source
resistance helps provide negative feedback to
keep current stable. Capacitor CS is a bypass

M
capacitor to prevent decrease in voltage gain.

10. For a MOSFET, the pinch-off voltage is

O
-3V. Gate to source voltage is 20V. W/L ratio
is 5. Process transconductance parameter is

C
40μA/V2. Find drain to source current in
saturation.

T.
a) 0.10 mA
b) 0.05mA
c) – 0.05mA
d) – 50A

O
a) 10kΩ Answer: c

SP
b) 4kΩ Explanation: ISD = k’W(VSG – |VT|)2/2L
c) 2kΩ ISD = 20*5*(-20-3)2 = 52900μA = 0.05mA.
d) 5kΩ
G
Answer: b TOPIC 1.9 BIASING FET
Explanation: IDSS = 2mA SWITCHING CIRCUITS.
LO

IDS = (VDD – 15)/50k = 0.3mA

VGS = VP [1 – √
IDS
] 1. Which of the following relation is true
DSS
about gate current?
VGS = -2 x (1 – √.15) = – 1.22V a) IG=ID+IS
.B

Thus VGS + IDS x (R) = 0 b) ID=IG

R = 1.22/0.3mA = 4kΩ. c) IS= IG
9. Which of the following statements are d) IG=0
17

true?
A: In a self bias circuit, the current IDS is not Answer: d
stable. Explanation: The FET physical structure
B: Source capacitance, CS, parallel to RS, which contains silicon dioxide provides
-R

reduces stability. infinite resistance. Hence no current will flow

a) Both statements are correct and B is the through the gate terminal.
correct reasoning
2. Which of the following equations gives the
SE

b) Both statements are correct but B is not the

correct reason for it relation between ID and Vgs?
c) Statement A is correct while statement B is a) ID=IDSS (1-Vgs/Vp)2
wrong
b) ID=IDSS (1-Vgs/Vp)1
d) Both statements are incorrect
C

c) ID=IDSS (1-Vgs/Vp)3
Answer: d
d) ID=IDSS (1-Vgs/Vp)4
Explanation: In a self bias circuit, the current

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 Dept. of ECE MCQ - Regulations 2017

Answer: a ButVRs+Vgs=0
Explanation: The above equation called as Vgs=-ID Rs.
Shockley’s equation depicts the relation
between ID and Vgs. When Vgs becomes 6. For a self-bias circuit, find drain to source

M
equal toVp, the current will become zero, voltage if VDD=12V, ID=1mA, Rs=RD=1KΩ?
which clearly satisfies the physical nature of a) 1V
FET. b) 2V

O
c) 10V
3. For a fixed bias circuit the drain current d) 5V
was 1mA, what is the value of source

C
current? Answer: c
a) 0mA Explanation: VDS=VDD-ID (RD+Rs)

T.
b) 1mA =>VDS=12-1mA(1KΩ+1KΩ)
c) 2mA
d) 3mA =>VDS=10V.

O
Answer: c 7. Find the gate voltage for voltage divider
Explanation: We know that for an FET same having R1=R2=1KΩ and VDD=5V?

SP
current flows through the gate and source a) 1V
terminal, Hence source current=1mA. b) 5V
c) 3V
4. For a fixed bias circuit the drain current d) 2.5V
G
was 1mA, VDD=12V, determine drain
resistance required if VDS=10V? Answer: d
LO

Explanation: VG = R2×VDD/R1+R2
a) 1KΩ
b) 1.5KΩ =>VG=1×5/2
c) 2KΩ => VG= 2.5V.
d) 4KΩ
.B

8. Find the gate to source voltage for voltage

Answer: c divider having R1=R2=2KΩ and VDD=12V,
Explanation: VDS=VDD-ID RD
ID=1mA and RS=4KΩ?
=>10=12-RD×1mA
17

a) 3V
=>RD=2/1mA=2 KΩ. b) 2V
c) 0V
5. Which of the following equation brings the d) 1V
-R

relation between gate to source voltage and

drain current in Self Bias? Answer: b
a) Vgs=VDD Explanation: VG = R2×VDD/R1+R2
b) Vgs=-ID Rs =>VG=2×12/4
SE

c) Vgs=0 =>VG=6V
d) Vgs=1+ID Rs =>VGS=VG-ID Rs
=>VGS=2V.
C

Answer: b
Explanation: VRs=ID Rs 9. What will happen if values of Rs increase?
a) Vgs Increases

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 Dept. of ECE MCQ - Regulations 2017

b) Vgs Decreases For small a.c. signal, transistor behaves as

c) Vgs Remains the same linear device. Under such circumstances the
d) Vgs=0 a.c. signal operation of a transistor can be
described in terms of h-parameters.

M
Answer: b 2. For what type of signals does a transistor
Explanation: Increasing values of Rs result in behaves as linear device?
lower quiescent values of ID and more a) small signals only

O
negative values of Vgs. b) large signals only
c) both large and small signal

C
10. What is the current flowing through the d) no signal
R1 resistor for voltage divider (R1=R2=1KΩ,

T.
Answer: a
VDD=10V)? Explanation: The small variation in the total
a) 5mA voltage and current due to an application of
b) 3mA signal moves the point up and down just by a

O
c) 1mA bit and that whole up and down dynamics of
d) 2mA the operating point from its DC value point

SP
can be approximated to be along a straight
Answer: a line. Whole analysis can be done with same
Explanation: IR1=IR2 =VDD/R1+R2 assumption of linearity with the limit of
=>IR1 = 10/2KΩ signal being in the same vicinity of the DC
G
=>IR1 = 5mA. operating point.
That’s how we get all those equations for
linear operation and also its small signal
LO

equivalent model using h-parameters.

UNIT II BJT AMPLIFIERS 3. How many h-parameters are there for a

transistor?
.B

a) two
TOPIC 2.1 SMALL SIGNAL b) three
HYBRID π EQUIVALENT c) four
d) five
17

CIRCUIT OF BJT
Answer: c
1. The h-parameters analysis gives correct Explanation: A transistor has four h-
results for __________ parameters –
-R

a) large signals only H11 = V1/i1 (Input Impedance with output

b) small signals only short circuited)
c) both large and small H21 = i2/i1 (Current gain with output short
SE

d) not large nor small signals

circuited)
Answer: b H12 = V1/V2 (Voltage gain with feedback
Explanation: Every linear circuit is ratio with input terminals open)
associated with h –parameters. When this H22 = i2/V2 (Output Admittance with input
C

linear circuit is terminated with load rL, we terminals open).

can find input impedance, current gain,
voltage gain, etc in terms of h-parameters.

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 Dept. of ECE MCQ - Regulations 2017

4. The dimensions of hie parameters are 7. If temperature changes, h parameters of a

_______ transistor _____
a) MHO a) also change
b) OHM b) does not change
c) remains same

M
c) Farad
d) Ampere d) may or may not change

Answer: a

O
Answer: b
Explanation: hie = vBE/ib; common emitter Explanation: It is very difficult to get exact
input impedance values of h parameters for a particular

C
For VCE = 0 i.e. output short circuited transistor. It is because these parameters are
subject to considerable variation unit to unit
Where vBE = Base emitter voltage i.e. input

T.
variation, variation due to change in
voltage temperature and variation due to the operating
ib = Base current i.e. input current point.
We know that V/I = R. Its unit is ohm.

O
8. In CE arrangement, the value of input
5. The hfe parameter is called _______ in CE impedance is approximately equal to _____

SP
arrangement with output short circuited. a) HIE
a) Voltage Gain b) HIB
b) Current gain c) HOE
c) Input impedance d) HRE
G
d) Output impedance
Answer: a
Answer: b
LO

Explanation: hie = vBE/ib; common emitter

Explanation: hfe in CE arrangement is given
input impedance
as
For VCE = 0 i.e. output short circuited
Hfe = Ic/Ib for VCE = 0 short circuited
Where vBE =Base emitter voltage i.e. input
So, this is current gain as it is then output to
.B

input current ratio. voltage

ib = Base current i.e. input current.
6. What happens to the h parameters of a
17

transistor when the operating point of the 9. How many h-parameters of a transistor are
transistor changes? dimensionless?
a) It also changes a) Four
b) Does not change b) Two
-R

c) May or may not change c) Three

d) Nothing happens d) One

Answer: a Answer: b
SE

Explanation: It is very difficult to get exact Explanation: (i) H11 = V1/I1; for V2 = 0
values of h parameters for a particular (output short circuited)
transistor. It is because these parameters are This parameter is input impedance with
subject to considerable variation unit to unit output short.
C

variation, variation due to change in Its unit is ohm.

temperature and variation due to the operating (ii) H21 = i2/i1; for V2 = 0 (output short
point. circuited)

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 Dept. of ECE MCQ - Regulations 2017

This parameter is Current gain ratio with

TOPIC 2.2 EARLY EFFECT -
output short.
It is unit less or dimensionless. ANALYSIS OF CE CC AND CB
(iii) H12 = V1/V2; for i1 = 0 (input open
1. Ignoring early effect, if R1 is the total

M
circuited)
This is voltage gain feedback ratio with resistance connected to the base and R2 is the
terminals open. total resistance connected at the collector,

O
And it is unit less or dimensionless. what could be the approximate input pole of a
(iv) H22 = i2/v2; for i1 = 0 (input open simple C.E. stage?
circuited)

C
a) 1 / [R1 * (Cµ(2+gm*R2) + Cπ)]
This is output admittance with input terminals b) 1 / [R1 * (Cµ(1+2*gm*R2) + Cπ)]
open.

T.
c) 1 / [R1 * (Cµ(1+gm*R2) + Cπ)]
Its unit is ohm-1 or mho.
d) 1 / [R1 * (Cµ(1-gm*R2) + Cπ)]
Thus there are two h-parameters which are
unit less or dimensionless.

O
Answer: c
10. The values of h-parameters of a transistor Explanation: The input pole can be
approximately calculated by observing the

SP
in CE arrangement are ________
arrangement. input node. The input node is the node where
a) same as for CB the base of the B.J.T. is connected to the input
b) same as for CC voltage. The product of total resistance and
c) different from that in CB capacitance connected at that particular node
G
d) similar to no is R1 * Cin and Cin is Cµ(1+gm*R2) + Cπ- the
inverse of this product gives us the input pole.
LO

Answer: c Thus the correct option is 1 / [R1 *

Explanation: The values of h-parameter in (Cµ(1+gm*R2) + Cπ)].
CE arrangement:
Hie = Vbe/Ib; for Vce = 0 (output short 2. Ignoring early effect, if R2 is the total
.B

circuited) resistance at the collector, what could be the

Hfe = ic/ib; for Vce = 0 (output short circuited) approximate output pole of a simple C.E.
Hre = Vbe/Vce; for ib = 0 (input open stage?
17

circuited) a) 1 / [R2 * (Ccs + Cµ*(1 + 2/gm*R2))]

Hoe = ic/vce; for ib = 0 (input open circuited) b) 1 / [R2 * (Ccs – Cµ*(1 + 1/gm*R2))]
c) 1 / [R2 * (Ccs + Cµ*(1 – 1/gm*R2))]
The values of h-parameter in CB
d) 1 / [R2 * (Ccs + Cµ*(1 + 1/gm*R2))]
-R

arrangement:
Hib = Vbe/Ie; for Vbc = 0 (output short
Answer: d
circuited) Explanation: The output pole can be
SE

Hfb = ic/Ie; for Vbc = 0 (output short approximately calculated by observing the
circuited) output node. For a C.E. stage, the output node
Hrb = Vbe/Vbc; for ie = 0 (input open is the node where the Collector of the B.J.T.
circuited) is connected to the output measuring device.
C

Hob = ic/vbe; for ie = 0 (input open circuited). The product of total resistance and
capacitance connected at that particular node
is R2 * Cout and Cout is (Ccs + Cµ*(1 +

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 Dept. of ECE MCQ - Regulations 2017

1/gm*R2). The inverse of this product gives emitter of the B.J.T. is 1/gm. The capacitance
us the output pole. Thus the correct option is connected to the input node is C1 (as
1 / [R2 * (Ccs + Cµ*(1 + 1/gm*R2))]. mentioned). The inverse product of these two
provides us the input pole of the C.B. stage.

M
3. If the load resistance of a C.E. stage
increases by a factor of 2, what happens to the 6. Ignoring early effect, if R1 is the total
high frequency response? resistance connected to the collector; what is

O
a) The 3 db roll off occurs faster the output pole of a simple C.B. stage?
b) The 3 db roll off occurs later a) 1/[R1 * (Ccs + Cµ)]
c) The input pole shifts towards origin

C
b) 1/[R1* (Ccs + 2*Cµ)]
d) The input pole becomes infinite
c) 1/[R1 * (2*Ccs + Cµ)]

T.
Answer: a d) 1/[R1 * 2*(Ccs + Cµ)]
Explanation: If the load resistance increases
by a factor of 2, the output pole decreases Answer: a

O
since it’s inversely proportional to the load Explanation: The output pole is calculated,
resistance. Hence the C.E. stage experiences a approximately, by the inverse product of the
faster roll off due to the pole. total resistance and the capacitance connected

SP
at the output node. We find that the total
4. During high frequency applications of a resistance connected to the output node is R1
B.J.T., which of the following three stages do
while the total capacitance is Ccs + Cµ. In
not get affected by Miller’s approximation?
G
a) C.E. absence of early effect, 1/[R1 * (Ccs + Cµ)]
b) C.B. becomes the output pole.
LO

c) C.C.
d) Follower 7. If early effect is included, and R1 is the
total resistance connected at the collector.
Answer: b What is the output pole of a simple C.B.
Explanation: During the C.B. stage, the stage?
.B

capacitance between the base and the a) 1/[(R1 || ro) * 2(Ccs + Cµ)]
collector doesn’t suffer from Miller b) 1/[(R1 || ro) * (Ccs + Cµ)]
approximation since the input is applied to
c) 1/[(R1 || ro) * (2*Ccs + Cµ)]
17

the emitter of the B.J.T. There are no

capacitors connected between two nodes d) 1/[(R1 || ro) * 2*(Ccs + 2*Cµ)]
having a constant gain. Hence the C.B. stage
doesn’t get affected by miller approximation. Answer: b
-R

Explanation: The output pole is calculated,

5. Ignoring early effect, if C1 is the total approximately, by the inverse product of the
capacitance tied to the emitter, what is the total resistance and the capacitance connected
input pole of a simple C.B. stage? at the output node. We find that the total
SE

a) 1/gm * C1 resistance connected to the output node is R1

b) 2/gm * C1 in parallel with ro, due to early effect, while
the total capacitance is C2 ie Ccs + Cµ. Thus,
c) gm * C1
the correct option is 1/[(R1 || ro) * (Ccs +
C

d) gm * 2C1
Cµ)].
Answer: a
Explanation: The resistance looking into the

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 Dept. of ECE MCQ - Regulations 2017

8. In a simple follower stage, C2 is a parasitic sensed at the collector of the B.J.T. We

capacitance arising due to the depletion observe that the only capacitance connected
region between the collector and the between two nodes- where there is an
substrate. What is the value of C2? amplification unit between the nodes, is Cπ.

M
a) 0 Hence, the correct option is Cπ.
b) Infinite
c) Ccs 11. If 1/h12 = 10 for a C.E. stage- what is the

O
d) 2*Ccs value of the base to collector capacitance,
after Miller multiplication, at the output side?

C
Answer: a a) 1.1Cµ
Explanation: During the high frequency b) 1.2Cµ

T.
response, the capacitor between the collector c) 2.1Cµ
and the substrate gets shorted to A.C. ground
d) 2.2Cµ
at both of its terminals. Hence, C2=0. The
answer would have been Ccs for any other

O
Answer: a
stage of B.J.T. Explanation: At the output side of a C.E.
stage, Cµ gets multiplied by a factor of

SP
9. For a cascode stage, with input applied to (1+1/Av) where Av is the voltage gain. 1/h12
the C.B. stage, the input capacitance gets
multiplied by a factor of ____ is nothing but Av. Hence, the value changes
a) 0 to 1.1Cµ.
G
b) 1
c) 3 12. If 1/h12 = 4, for a C.E. stage- what is the
LO

d) 2 value of the base to collector capacitance,

after Miller multiplication, at the input side?
Answer: d a) 4Cµ
Explanation: The small signal gain, of the
b) 5Cµ
C.B. stage, in a cascode stage is
.B

approximately equal to the ratio of the c) 6Cµ

transconductances of the two B.J.T.’s. Since d) 1.1Cµ
they are roughly same, the gain is 1. Miller
17

multiplication leads to multiplying the Answer: c

capacitance, between base and collector, by a Explanation: The capacitor, Cµ, gets
factor of (1 + small signal gain) which is 2. multiplied by a factor of (1 + Av), at the input
Hence, the correct option is 2.
side of a C.E. stage. 1/h12 is equal to Av since
-R

10. If the B.J.T. is used as a follower, which h12 is the reverse voltage amplification factor.
capacitor experiences Miller multiplication? Hence, the final value becomes 5Cµ.
a) Cπ
SE

b) Cµ 13. The transconductance of a B.J.T.is 5mS

c) Ccs (gm) while a 2KΩ (Rl) load resistance is
d) Cb connected to the C.E. stage. Neglecting Early
effect, what is the Miller multiplication factor
C

Answer: a for the input side?

Explanation: We find that the input is given a) 21
to the base of the B.J.T. while the output is b) 11

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 Dept. of ECE MCQ - Regulations 2017

c) 20 can be approximated to be along a straight

d) 0 line. Whole analysis can be done with same
assumption of linearity with the limit of
Answer: b signal being in the same vicinity of the DC
Explanation: The Miller multiplication factor operating point.

M
for the input side of a C.E. stage is (1+Av). That’s how we get all those equations for
Now, Av is the small signal low frequency linear operation and also its small signal

O
gain of the C.E. stage which is gm*RL=10. equivalent model using h-parameters.
Hence, the Miller multiplication factor is 11.
3. How many h-parameters are there for a

C
transistor?
TOPIC 2.3 AMPLIFIERS USING a) two

T.
HYBRID π EQUIVALENT b) three
CIRCUITS - AC LOAD LINE c) four
d) five
ANALYSIS

O
Answer: c
1. The h-parameters analysis gives correct Explanation: A transistor has four h-

SP
results for __________ parameters –
a) large signals only H11 = V1/i1 (Input Impedance with output
b) small signals only short circuited)
c) both large and small H21 = i2/i1 (Current gain with output short
G
d) not large nor small signals circuited)
H12 = V1/V2 (Voltage gain with feedback
Answer: b
LO

Explanation: Every linear circuit is ratio with input terminals open)

associated with h –parameters. When this H22 = i2/V2 (Output Admittance with input
linear circuit is terminated with load rL, we terminals open).
can find input impedance, current gain,
.B

voltage gain, etc in terms of h-parameters. 4. The dimensions of hie parameters are
For small a.c. signal, transistor behaves as _______
linear device. Under such circumstances the a) MHO
17

a.c. signal operation of a transistor can be b) OHM

described in terms of h-parameters. c) Farad
d) Ampere
2. For what type of signals does a transistor
behaves as linear device? Answer: b
-R

a) small signals only Explanation: hie = vBE/ib; common emitter

b) large signals only input impedance
c) both large and small signal For VCE = 0 i.e. output short circuited
SE

d) no signal Where vBE = Base emitter voltage i.e. input

Answer: a voltage
Explanation: The small variation in the total ib = Base current i.e. input current
We know that V/I = R. Its unit is ohm.
C

voltage and current due to an application of

signal moves the point up and down just by a
bit and that whole up and down dynamics of 5. The hfe parameter is called _______ in CE
the operating point from its DC value point arrangement with output short circuited.

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 Dept. of ECE MCQ - Regulations 2017

a) Voltage Gain b) HIB

b) Current gain c) HOE
c) Input impedance d) HRE
d) Output impedance

M
Answer: b Answer: a
Explanation: hfe in CE arrangement is given Explanation: hie = vBE/ib; common emitter
input impedance

O
as
Hfe = Ic/Ib for VCE = 0 short circuited For VCE = 0 i.e. output short circuited
So, this is current gain as it is then output to Where vBE =Base emitter voltage i.e. input

C
input current ratio. voltage
ib = Base current i.e. input current.

T.
6. What happens to the h parameters of a
transistor when the operating point of the 9. How many h-parameters of a transistor are
transistor changes? dimensionless?

O
a) It also changes a) Four
b) Does not change b) Two
c) May or may not change c) Three

SP
d) Nothing happens d) One

Answer: a Answer: b
Explanation: It is very difficult to get exact Explanation: (i) H11 = V1/I1; for V2 = 0
G
values of h parameters for a particular (output short circuited)
transistor. It is because these parameters are This parameter is input impedance with
LO

subject to considerable variation unit to unit output short.

variation, variation due to change in Its unit is ohm.
temperature and variation due to the operating (ii) H21 = i2/i1; for V2 = 0 (output short
point.
circuited)
.B

7. If temperature changes, h parameters of a This parameter is Current gain ratio with

transistor _____ output short.
a) also change It is unit less or dimensionless.
(iii) H12 = V1/V2; for i1 = 0 (input open
17

b) does not change

c) remains same circuited)
d) may or may not change This is voltage gain feedback ratio with
terminals open.
-R

Answer: a And it is unit less or dimensionless.

Explanation: It is very difficult to get exact (iv) H22 = i2/v2; for i1 = 0 (input open
values of h parameters for a particular circuited)
transistor. It is because these parameters are This is output admittance with input terminals
SE

subject to considerable variation unit to unit open.

variation, variation due to change in
Its unit is ohm-1 or mho.
temperature and variation due to the operating
Thus there are two h-parameters which are
point. unit less or dimensionless.
C

8. In CE arrangement, the value of input

10. The values of h-parameters of a transistor
impedance is approximately equal to _____
in CE arrangement are ________
a) HIE

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 Dept. of ECE MCQ - Regulations 2017

arrangement. 2. Consider the circuit shown below where

a) same as for CB hfe=50
b) same as for CC
c) different from that in CB
d) similar to no

M
Answer: c
Explanation: The values of h-parameter in

O
CE arrangement:
Hie = Vbe/Ib; for Vce = 0 (output short

C
circuited)
Hfe = ic/ib; for Vce = 0 (output short circuited)

T.
Hre = Vbe/Vce; for ib = 0 (input open
circuited)
Hoe = ic/vce; for ib = 0 (input open circuited) Calculate the input resistance of the network.

O
a) 255 kΩ
The values of h-parameter in CB b) 13 MΩ

SP
arrangement: c) 5 MΩ
Hib = Vbe/Ie; for Vbc = 0 (output short d) 250 kΩ
circuited)
Hfb = ic/Ie; for Vbc = 0 (output short Answer: b
G
Explanation: The load for the first transistor
circuited)
in the figure is the input resistance of the
Hrb = Vbe/Vbc; for ie = 0 (input open
second.
LO

circuited) RE1 = (1+hfe)5k = 255kΩ

Hob = ic/vbe; for ie = 0 (input open circuited).
Net input resistance, RI = (1+hfe)RE1=
(1+hfe)25k = 13005k = 13MΩ.
TOPIC 2.4 DARLINGTON
.B

AMPLIFIER - BOOTSTRAP 3. Given the following circuit

TECHNIQUE - CASCADE,
CASCODE CONFIGURATIONS
17

1. Which of these are incorrect about

Darlington amplifier?
-R

a) It has a high input resistance

b) The output resistance is low
c) It has a unity voltage gain
d) It is a current buffer
SE

Answer: d It is given that hfe=55, hie=1kΩ, hoe=25μΩ-1.

Explanation: A Darlington amplifier has a Calculate the net current gain and the voltage
very high input resistance, low output gain of the network.
C

resistance, unity voltage gain and a high a) AI=192.6, Av=220

current gain. It is a voltage buffer, not a b) AI=1, AV=220
current buffer.

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 Dept. of ECE MCQ - Regulations 2017

c) AI=192.6, AV=1 c) To prevent a decrease in the input

d) AI=192.6, AV=55 resistance due to the presence of multiple BJT
amplifiers
Answer: c d) To prevent a decrease in the input
resistance due to the biasing network

M
Explanation: AI=A1xA2
AI = [1+hfe/1+hoehfeRE]x[1+hfe] AI = Answer: b
51×51/(1+25x50x10x10-3) Explanation: A bootstrap biasing network is

O
= 192.6.
a special biasing circuit used in Darlington
4. In a Darlington pair, the overall amplifier to prevent the decrease in input

C
β=15000.β1=100. Calculate the collector resistance due to the biasing network being
current for Q2 given base current for Q1 is 20 used. Capacitors and resistors are added to the

T.
μA. circuit to prevent it from happening.

7. Consider a Darlington amplifier. In the self

bias network, the biasing resistances are

O
220kΩ and 400 kΩ. What can be the correct
value of input resistance if hfe=50 and emitter

SP
resistance = 10kΩ.
a) 141 kΩ
b) 15 MΩ
a) 300 mA
c) 20 MΩ
b) 298 mA
G
d) 200 kΩ
c) 2 mA
d) 200mA Answer: a
LO

Explanation: R’ = 220k||400k = 142 kΩ

Answer: b
Explanation: IB = 20 μA RI = (1+hfe)2RE = 26MΩ
IC = β.IB = 15000 x 20μ = 300 mA RI’ = 26M||142k = 141.22 K.
.B

IC1 = β1.IB = 100.20μ = 2mA

8. What is a cascode amplifier?
IC2 = 300 – 2 = 298mA. a) A cascade of two CE amplifiers
b) A cascade of two CB amplifiers
17

5. Darlington amplifier is an emitter follower. c) A cascade of CE and CB amplifiers

a) True d) A cascade of CB and CC amplifiers
b) False
Answer: c
Answer; a
-R

Explanation: A cascode amplifier is a

Explanation: Darlington pair is an emitter cascade network of CE and CB amplifiers, or
follower circuit, in which a darling pair is CS and CG amplifiers.
used in place of a single It is used as a wide-band amplifier.
SE

transistor. It also provides a large β as per

requirements.

6. What is the need for bootstrap biasing?

C

a) To prevent a decrease in the gain of

network
b) To prevent an increase in the input
resistance due to the biasing network

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 Dept. of ECE MCQ - Regulations 2017

9. Consider the figure shown. a) 30mΩ-1

b) 10mΩ-1
c) 1mΩ-1
d) 20mΩ-1

M
Answer: a
Explanation: For a MOSFET cascode

O
amplifier, the net transconductance in the
above network shown is equal to the

C
transconductance of MOSFET M1 that is
equal to 30mΩ-1.

T.
11. In the given circuit, hfe = 50 and hie =
Given that gm1 = 30mΩ-1 and gm2 =50mΩ-1, 1000Ω, find overall input and output

O
resistance.
α1 = 1.1, α2 = 1.5 what is the
transconductance of the entire network?

SP
a) 80 mΩ-1
b) 75 mΩ-1
c) 33 mΩ-1
d) 55 mΩ-1
G
Answer: d
LO

Explanation: The above circuit is a cascode

pair. For this circuit, the overall
transconductance is
gm = α1gm2
.B

gm = 1.1 gm2 = 55mΩ-1.

a) RI=956Ω, RO=1.6 kΩ
10. Find the transconductance of the network
b) RI=956 kΩ, RO=2 kΩ
17

given below, provided that gm1 = 30mΩ-1. VT

c) RI=956 Ω, RO=2 kΩ
= 25mV, VBias > 4V.
d) RI=900Ω, RO=10 kΩ
-R

Answer: c
Explanation: RO = RC = 2kΩ
Input resistance = hie||50k||40k = 0.956 kΩ.
SE

TOPIC 2.5 DIFFERENTIAL

AMPLIFIER, BASIC BJT
DIFFERENTIAL PAIR
C

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 Dept. of ECE MCQ - Regulations 2017

1. A Differential Amplifier should have Answer: a

collector resistor’s value (RC1 & RC2) as Explanation: When two input signals are
a) 5kΩ, 5kΩ applied to base of transistor, it is said to be
b) 5Ω, 10kΩ Dual Input. When both collectors are at same
c) 5Ω, 5kΩ DC potential with respect to ground, then it is

M
d) 5kΩ, 10kΩ said to be Balance Output.

Answer: a 5. A differential amplifier is capable of

O
Explanation: The values of collector current amplifying
will be equal in differential amplifier a) DC input signal only

C
(RC1=RC2). b) AC input signal only
c) AC & DC input signal

T.
2. A Differential Amplifier amplifies d) None of the Mentioned
a) Input signal with higher voltage
b) Input voltage with smaller voltage Answer: c
c) Sum of the input voltage Explanation: Direct connection between

O
d) None of the Mentioned stages removes the lower cut off frequency
imposed by coupling capacitor; therefore it

SP
Answer: d can amplify both AC and DC signal.
Explanation: The purpose of differential
amplifier is to amplify the difference between 6. In ideal Differential Amplifier, if same
two signals. signal is given to both inputs, then output will
G
be
3. The value of emitter resistance in Emitter a) Same as input
Biased circuit are RE1=25kΩ & RE2=16kΩ. b) Double the input
LO

Find RE c) Not equal to zero

a) 9.756kΩ d) Zero
b) 41kΩ
c) 9.723kΩ Answer: d
.B

d) 10kΩ Explanation: In ideal amplifier, Output

voltage
Answer: a ⇒ Vout = Vin1-Vin2.
Explanation: In emitter biased circuit, RE1
17

& RE2 is connected in parallel combination. 7. Find the Single Input Unbalance Output
⇒ RE = RE1 II RE2 = (RE1× configuration in following circuit diagrams :
RE2)/(RE1+RE2) =
(25kΩ×16kΩ)/(25kΩ+16kΩ) = 9.7561kΩ.
-R

4. If output is measured between two

collectors of transistors, then the Differential
SE

amplifier with two input signal is said to be

configured as
a) Dual Input Balanced Output
b) Dual Input Unbalanced Output
c) Single Input Balanced Output a)
C

d) Dual Input Unbalanced Output

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 Dept. of ECE MCQ - Regulations 2017

⇒ IE = (VEE-VBE)/(2RE) = (20v-
07v)/(2×1.3kΩ) = 7.42mA.

9. Find IC, given VCE=0.77v, VCC=10v,

VBE=0.37v and RC=2.4kΩ in Dual Input

M
Balanced Output differential amplifier
a) 0.4mA

O
b) 0.4A
c) 4mA
b) d) 4A

C
Answer: c

T.
Explanation: Substitute the values in
collector to emitter voltage equation,
VCE= VCC+ VBE-RC IC
⇒IC = (VCC-VCE+VBE)/RC = (10v-

O
0.77v+0.37v)/2.4kΩ = 4mA

SP
10. Find the correct match
c)
Voltage gain and
Configuration
Input resistance
G
1. Single Input i. Ad = Rc/re , Ri1 Ri2
Unbalanced Output = 2βacRE
LO

2. Dual Input ii. Ad= Rc/2re , Ri1 Ri2 =

Balanced Output 2βacRE

3. Single Input iii. Ad= Rc/re , Ri =

.B

Balanced Output 2βacRE

d) iv. Ad = Rc/2re , Ri =
4. Dual Input
Answer: c Unbalanced Output 2βacRE
17

Explanation: Circuit c has only single input

(V1) and output is measure only at one of the a) 1-i , 2-iii, 3-iv, 4-ii
collector with respect to ground. b) 1-iv, 2-ii, 3-iii, 4-i
c) 1-ii, 2-iv, 3-i , 4-iii
-R

8. An emitter bias Dual Input Balanced d) 1-iii, 2-i, 3-ii, 4-iv

Output differential amplifier has VCC=20v,
β=100, VBE=0.7v, RE=1.3kΩ. Find IE Answer: d
a) 7.42mA Explanation: Properties of differential
SE

b) 9.8mA amplifier circuit configuration.

c) 10mA
d) 8.6mA 11. Obtain the collector voltage, for collector
resistor (RC) =5.6kΩ, IE=1.664mA and
C

Answer: a VCC=10v for single input unbalanced output

Explanation: Emitter current can be found differential amplifier
out by substituting the values in the equation, a) 0.987v

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 Dept. of ECE MCQ - Regulations 2017

b) 0.682v c) 38
c) 0.555v d) 61
d) None of the mentioned
Answer: a
Answer: b Explanation: In single Input Balance Output

M
Explanation: Substitute the given values in amplifier,
collector voltage equation, ⇒ IE = (VEE-VBE)/2RE
VC= VCC – RC×IC

O
=(15v-0.7v)/(2×3.9kom)= 1.83mA
⇒ VC= 10v – 5.6kΩ×1.664mA (∵ IC ≅ IE ) (∵VCC=VEE)
⇒ VC= 0.682v. From the equation, VCE = VCC +VBE-

C
RC×IC
12. For the circuit shown below, determine ⇒ RC = (14.3v – 2.4v)/1.83mA = 6.5kΩ

T.
the Output voltage (Assume β=5, differential The voltage gain, Vo
input resistance=12 kΩ) ⇒ Vo = RC/re
= 6.5kΩ/250Ω = 26(no units).

O
TOPIC 2.6 SMALL SIGNAL

SP
ANALYSIS AND CMRR.

1. For the difference amplifier which of the

following is true?
G
a) It responds to the difference between the
two signals and rejects the signal that are
LO

common to both the signal

b) It responds to the signal that are common
a) 4.33v to the two inputs only
b) 2.33v c) It has a low value of input resistance
d) The efficacy of the amplifier is measured
.B

c) 3.33v
d) 1.33v by the degree of its differential signal to the
preference of the common mode signal
Answer: c
17

Explanation: From the circuit dig, Answer: a

RC=10kΩ, Vin1= 1.3v and Vin2=0.5v, Explanation: All the statements are not true
Differential input resistance = 2 βre, except for the fact that it responds only when
⇒ 12kΩ = 2×5×Re there is difference between two signals only.
-R

⇒ Re = 1.2 kΩ
2. If for an amplifier the common mode input
Output voltage Vo = RC/2Re(Vin1-Vin2) signal is vc, the differential signal id vd and
⇒ Vo = 10kΩ/(2 ×1.2kΩ) × (1.3v-0.5v)
Ac and Ad represent common mode gain and
SE

⇒ Vo = 3.33v.
differential gain respectively, then the output
13. In a Single Input Balanced Output voltage v0 is given by
Differential amplifier, given VCC=15v, RE = a) v0 = Ad vd – Ac vc
C

3.9kΩ, VCE=2.4 v and re=250Ω. Determine b) v0 = – Ad vd + Ac vc

Voltage gain c) v0 = Ad vd + Ac vc
a) 26
b) 56 d) v0 = – Ad vd – Ac vc

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 Dept. of ECE MCQ - Regulations 2017

Answer: c
Explanation: It is a standard mathematical
expression.

3. If for an amplifier v1 and v2 are the input

M
signals, vc and vd represent the common
mode and differential signals respectively,

O
then the expression for CMRR (Common
Mode Rejection Ratio) is
a) 20 log (|Ad| / |Ac|)

C
b) -10 log (|Ac| / |Ad|)2

T.
c) 20 log (v2 – v1 / 0.5(v2 + v1)) a) 20 log [K+1/4ε].
d) All of the mentioned b) 20 log [K+1/2ε].
c) 20 log [K+1/ε].

O
Answer: d d) 20 log [2K+2/ε].
Explanation: Note that all the expressions are
identical. Answer: a

SP
Explanation: None.
4. The problem with the single operational
difference amplifier is its 6. For the circuit given below determine the
a) High input resistance input common mode resistance.
G
b) Low input resistance
c) Low output resistance
d) None of the mentioned
LO

Answer: b
Explanation: Due to low input resistance a
large part of the signal is lost to the source’s
.B

internal resistance.

5. For the difference amplifier as shown in

17

the figure show that if each resistor has a

tolerance of ±100 ε % (i.e., for, say, a 5%
resistor, ε = 0.05) then the worst-case CMRR
is given approximately by (given K = R2/R1 a) (R1 + R3) || (R2) || + (R4)
b) (R1 + R4) || (R2 + R3)
-R

= R4/R3)
c) (R1 + R2) || (R3 + R4)
d) (R1 + R3) || (R2 + R4)
SE

Answer: c
Explanation: Parallel combination of series
combination of R1 & R3 with the series
combination of R3 and R4 is the required
C

answer as is visible by the circuit.

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 Dept. of ECE MCQ - Regulations 2017

7. For the circuit shown below express v0 as a 9. Determine Ad and Ac for the given circuit.
function of v1 and v2.

M
O
C
a) Ac = 0 and Ad = 1

T.
a) v0 = v1 + v2
b) v0 = v2 – v1 b) Ac ≠ 0 and Ad = 1
c) v0 = v1 – v2 c) Ac = 0 and Ad ≠ 1

O
d) v0 = -v1 – v2 d) Ac ≠ 0 and Ad ≠ 1

Answer: a

SP
Answer: b
Explanation: Considering the fact that the Explanation: Consider the fact that the
potential at the input terminals are identical potential at the input terminals are identical
and proceeding we obtain the given result. and obtain the values of V1 and V2. Thus
obtain the value of Vd and Vc.
G
8. For the difference amplifier shown below,
let all the resistors be 10kΩ ± x%. The 10. Determine the voltage gain for the given
LO

expression for the worst-case common-mode circuit known that R1 = R3 = 10kΩ abd R2 =
gain is R4 = 100kΩ.
.B
17
-R

a) x / 50
b) x / 100
c) 2x / (100 – x)
d) 2x / (100 + x)
SE

a) 1
Answer: d b) 10
Explanation: None. c) 100
d) 1000
C

Answer: b
Explanation: Voltage gain is 100/10. 

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 Dept. of ECE MCQ - Regulations 2017

3. The slope obtained in VGS vs ID was

0.002. What is the value ofgm?
UNIT III SINGLE STAGE a) 1
b) 2
FET, MOSFET

M
c) 0.002
AMPLIFIERS d) 0

O
Answer: c
TOPIC 3.1 SMALL SIGNAL Explanation: gm = change in drain current/
HYBRID π EQUIVALENT

C
change in gate to source voltage gm = slope
CIRCUIT OF FET AND MOSFET of VGS vs ID gm = 0.002.

T.
1. What is trans-conductance? 4. Which of the following is an expression for
a) Ratio of change in drain current to change gm0?
in collector current

O
a) gm0 = IDSS/Vp
b) Ratio of change in drain current to change b) gm0 = 2IDSS/|Vp|
in gate to source voltage

SP
c) gm0 = IDSS/5Vp
c) Ratio of change in collector current to
change in drain current d) gm0 = IDSS/2Vp
d) Ratio of change in collector current to
change in gate to source voltage Answer: b
G
Explanation: gm0 is the value of gm when
Answer: b VGS=0, we have seen that trans conductance
Explanation: The change in drain current
LO

is the ratio of drain current to change in gate

which is resulted due to change in gate to
to source voltage, but this is an exceptional
source voltage in a FET is measured by trans-
case, here the transistor will be working in cut
conductance. This is termed as trans because
off region.
it provides relationship between input and
.B

output quantity. 5. Find the maximum value of gm for FET

2. For a FET, graph is drawn by taking with IDSS=10mA, Vp=-2V, VGS=5V?
a) 10mS
17

voltage VGS in X axis and drain current in Y

axis, if the value of X changes from 10 to 20 b) 20mS
results in change in value of Y axis from 2 to c) 1mS
3. What is the value of trans conductance? d) 0
-R

a) 1
Answer: a
b) 2
Explanation: gm0=2IDSS/|Vp|
c) 0.1
d) 0.01 gm0=2×10mA/2V gm0=10mS.
SE

Answer: c 6. Find the value of gm for FET with

Explanation: Trans-conductance= change in IDSS=8mA, Vp=4V, VGS=-0.5V?
drain current/ change in gate to source
a) 1mS
C

voltage b) 2mS
trans conductance=3-2/20-10=1/10 c) 3mS
trans conductance=0.1. d) 3.5mS

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 Dept. of ECE MCQ - Regulations 2017

Answer: d Answer: b
Explanation: For FET, the voltage is applied
across the gate and source to control the drain
current, hence while writing small signal
model of an FET, on the output side gm VGS

M
represents a current source which can be
controlled by the input voltage VGS.

O
Explanation:
10. Given yfs = 3.6mS and yos = 0.02mS,
7. A FET has IDSS=4ID and gm0 = 10mS then

C
determine r0?
gm = _________________________
a) 100Kohm
a) 10mS

T.
b) 50Mohm
b) 20mS c) 50Kohm
c) 5mS d) 20Kohm
d) 14mS

O
Answer: c
Answer: c Explanation: r0=1/yos
Explanation:

SP
It is independent of yfs. => r0=1/20mS
r0=50Kohm.
G
TOPIC 3.3 AMPLIFIERS USING
HYBRID π EQUIVALENT
LO

CIRCUITS

1. Which of the following statement is

8. Determine the value of output impedance
incorrect?
for JFET, if the value of gm =1mS?
.B

a) Output of CE amplifier is out of phase with

a) 1Kohm respect to its input
b) 0 b) CC amplifier is a voltage buffer
c) 100Kohm c) CB amplifier is a voltage buffer
17

d) 5Kohm d) CE amplifier is used as an audio (low

frequency) amplifier
Answer: a
Explanation: Output impedance=inverse of Answer: c
-R

trans conductance Explanation: The output of the CE amplifier

Output impedance=1/1mS
has a phase shift of 180o with respect to the
Output impedance=1Kohm.
input. The CC amplifier has AV≅1, thus it is
SE

9. In a small signal equivalent model of an a voltage buffer. However, the CB amplifier

FET, What does gm VGS stand for? has a large voltage gain, and its current gain
a) A pure resistor AI≅1, thus it is a current buffer. CE amplifier
b) Voltage controlled current source has an application has an audio amplifier.
C

c) Current controlled current source

d) Voltage controlled voltage source 2. Consider the following circuit.
__________ provides DC isolation.

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 Dept. of ECE MCQ - Regulations 2017

_____________ prevents a decrease in hoRL’) where RL’ = 2kΩ||4kΩ

voltage gain. _____________ is used to RL’ = 1.33kΩ.
control the bandwidth. Thus AI = – 60 / (1 + 0.0266) = -58.4453.

M
4. Consider the circuit. Given hfe = 50, hie =
1200Ω. Find voltage gain.

O
C
a) C3, C1, C4

T.
b) C4, C1, C2
c) C2, C3, C2
d) C4, C3, C2

O
a) – 278
Answer: b b) -277.9

SP
Explanation: Capacitor C3 and C4, are the c) – 300
blocking capacitor and coupling capacitor d) – 280
respectively, both providing DC isolation to
biasing circuit. Capacitor C1 is the emitter Answer: a
G
bypass capacitor, to prevent decrease in Explanation: Voltage gain = AV = -
voltage gain by avoiding negative feedback.
hfeRL’/hie
Capacitor C2 is the shunt capacitor, used to
LO

control the bandwidth, wherein the bandwidth RL’ = 20k||10k = 6.67kΩ

is inversely proportional to C2. AV = -50 * 6.67k/1.2k = -277.9 ≅ – 278.

3. Given hfe = 60, hie=1000Ω, hoe = 20μ Ω–, 5. Given that IB = 5mA and hfe = 55, find
.B

hre = 2 * 10-4. Find the current gain of the load current.

BJT, correct up to two decimal points.
17
-R

a) 28mA
SE

a) – 58.44 b) 280mA
b) -59.21 c) 2.5A
c) – 60.10 d) 2A
d) – 60.00
C

Answer: b
Answer: a Explanation: In given circuit, which is an
Explanation: Current gain, AI = – hf / (1 + emitter follower, current gain = 1 + hfe

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 Dept. of ECE MCQ - Regulations 2017

IL = IB (1+hfe)
IL = 5mA(56) = 280 mA.

6. Consider the following circuit, where

M
source current = 10mA, hfe = 50, hie =
1100Ω, then for the transistor circuit, find
output resistance RO and input resistance RI.

O
C
a) RI = 20Ω, RO = ∞

T.
b) RI = 20Ω, RO = 2kΩ
c) RI = 59Ω, RO = ∞

O
d) RI = 59Ω, RO = 2kΩ

Answer: c

SP
Explanation: RI = 20k = hie/(1+hfe) = hie/51
a) RO = 0, RI = 21Ω hie =1020 Ω
b) RO = ∞, RI = 0Ω Hence, after adding base resistance, RI’=
G
c) RO = ∞, RI = 21Ω (hie+RB)/(1+hfe) = (1020+2000) / 51 ≅ 59Ω
d) RO = 10, RI = 21Ω There is no change in output resistance or
LO

current gain due to an extra base resistance.

Answer: c RO’ = ∞.
Explanation: Since hoe is not given, we can
consider it to be small; i.e 1/hoe is neglected, 8. Consider its input resistance to be R1.
Now, the bypass capacitor is attached, so that
.B

open circuited. Hence output resistance RO =

the new input resistance is R2. Given that hie
∞.
Input resistance = hie/(1 + hfe) = 1100/51 ≅ = 1000Ω and hfe = 50, find R1-R2.
17

21Ω.

7. For the given circuit, input resistance RI =

20Ω, hfe = 50. Output resistance = ∞. Find
-R

the new values of input and output resistance,

if a base resistance of 2kΩ is added to the
circuit.
SE

a) 112.2Ω
b) 0Ω
c) 110Ω
C

d) 200Ω

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 Dept. of ECE MCQ - Regulations 2017

Answer: a gain with respect to transistor input. However

Explanation: For the circuit, CE amplifier when RS=0 then AVS = AV.
without bypass capacitor, input resistance,
R1=hie + (1+hfe)RE
TOPIC 3.4 BASIC FET

M
R1 = 1000 + 51*2.2 = 1000 + 112.2 =
1112.2Ω DIFFERENTIAL PAIR- BICMOS
With a bypass capacitor attached, input CIRCUITS.

O
resistance, R2 = hie = 1000Ω
Thus R1 – R2 = 112.2Ω. 1. The difference output of the basic

C
differential amplifier is taken at ___________
9. Given that for a transistor, hie = 1100Ω, hfe a) At X and ground
= 50, hre = 2*10-4 and hoe = 2μΩ-1. Find CB b) At Y and ground

T.
c) Difference of the voltages at the gates of
h-parameters.
M1 and M2
a) hfb = 1, hib = 22, hob = 3μΩ-1, hrb = d) Difference of the voltages between X and

O
-1.5×10-4 Y
b) hfb = -0.98, hib = -21.56, hob = 0.03μΩ-1,
Answer: d

SP
hrb = 1.5×10-4 Explanation: None.
c) hfb = -0.98, hib = 21.56, hob = 0.03μΩ-1,
2. The Differential output of the difference
hrb = -1.5×10-4 amplifier is the amplification of __________
G
d) hfb =1, hib = -21.56, hob = 0.03μΩ-1, hrb = a) Difference between the voltages of input
signals
-2×10-4
LO

b) Difference between the output of the each

transistor
Answer: c c) Difference between the supply and the
Explanation: hfb = -hfe/(1+hfe) = -50/51= output of the each transistor
-0.98 d) All of the mentioned
.B

hib = hie/(1+hfe) = 21.56Ω

Answer: a
hob = hoe/(1+hfe) = 0.03 μΩ-1
Explanation: None.
17

hrb = (hiehoe/1+hfe) – hre = -1.5×10-4.

3. The inputs to the differential amplifier are
10. If source resistance in an amplifier circuit applied at __________
is zero, then voltage gain (output to input a) At X and Y
-R

voltage ratio) and source voltage gain (output b) At the gates of M1 and M2
to source voltage ratio) are the same. c) All of the mentioned
a) True d) None of the mentioned
b) False
SE

Answer: b
Answer: a Explanation: None.
Explanation: When a source resistance RS is
4. The Maximum and minimum output of the
present, the voltage gain with respect to
C

Differential amplifiers is defined as:

source becomes
a) Vmax = VDD, Vmin = -VDD
AVS = AVRI’/(RS+RI’), where AV is voltage
b) Vmax = VDD, Vmin = Rd.Iss

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 Dept. of ECE MCQ - Regulations 2017

c) Vmax = VDD, Vmin = VDD – Rd.Iss TOPIC 4.1 AMPLIFIER

d) None of the mentioned
FREQUENCY RESPONSE
Answer: c
Explanation: None. 1. Consider a voltage amplifier having a

M
frequency response of the low-pass STC type
5. In Common Mode Differential Amplifier, with a dc gain of 60 dB and a 3-dB frequency
the outputs Vout1 and Vout2 are related as:

O
of 1000 Hz. Then the gain db at
a) Vout2 is in out of phase with Vout1 with a) f = 10 Hz is 55 db
same amplitude b) f = 10 kHz is 45 db

C
b) Vout2 and Vout1 have same amplitude but c) f = 100 kHz is 25 db
the phase difference is 90 degrees d) f = 1Mhz is 0 db

T.
c) Vout1 and Vout2 have same amplitude and
are in phase with each other and their Answer: d
respective inputs Explanation: Use standard formulas for
d) Vout1 and Vout2 have same amplitude and frequency response and voltage gain.

O
are in phase with each other but out of phase
with their respective inputs 2. STC networks can be classified into two

SP
categories: low-pass (LP) and high-pass (HP).
Answer: d Then which of the following is true?
Explanation: None. a) HP network passes dc and low frequencies
and attenuate high frequency and opposite for
6. In a small signal differential gain vs input
G
LP network
CM level graph, the gain decreases after V2 b) LP network passes dc and low frequencies
due to: and attenuate high frequency and opposite for
LO

a) As the input voltage increases, the output HP network

will be clipped c) HP network passes dc and high frequencies
b) When the input voltage to the transistors and attenuate low frequency and opposite for
are high, the transistor enters saturation LP network
.B

region and increases the current, which inturn d) LP network passes low frequencies only
decreases the output voltage = VDD – Rd.Iss and attenuate high frequency and opposite for
c) When Common Mode voltage is greater HP network
than or equal to V2, the input transistors enter
17

triode region, the gain begins to fall Answer: b

d) Increasing the input voltage beyond V2 Explanation: By definition a LP network
causes the gate oxide to conduct and the gain allows dc current (or low frequency current)
is reduced and an LP network does the opposite, that is,
-R

allows high frequency ac current.

Answer: c
Explanation: None. 3. Single-time-constant (STC) networks are
SE

those networks that are composed of, or can

be reduced to
a) One reactive component (L or C) and a
resistance (R)
UNIT IV FREQUENCY b) Only capacitive component (C) and
C

RESPONSE OF resistance (R)

c) Only inductive component (L) and
AMPLIFIERS resistance (R)

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 Dept. of ECE MCQ - Regulations 2017

d) Reactive components (L, C or both L and

C) and resistance (R)

Answer: a
Explanation: STC has only one reactive

M
component and one resistive component.

4. The signal whose waveform is not effected

O
by a linear circuit is
a) Triangular Waveform signal

C
b) Rectangular waveform signal
c) Sine/Cosine wave signal a) C1R1 = C2R2

T.
d) Sawtooth waveform signal b) C1R2 = C2R1
c) C1C2 = R1R2
Answer: c d) R1 = 0
Explanation: Only sine/cosine wave are not

O
affected by a linear circuit while all other Answer: a
waveforms are affected by a linear circuit. Explanation: Standard condition of a

SP
compensated attenuator. Here is the
5. Which of the following is not a derivation for the same.
classification of amplifiers on the basis of
their frequency response?
a) Capacitively coupled amplifier
G
b) Direct coupled amplifier
c) Bandpass amplifier
LO

d) None of the mentioned

Answer: d
Explanation: None of the options provided
are correct.
.B

6. General representation of the frequency

response curve is called
17

a) Bode Plot
b) Miller Plot
c) Thevenin Plot
d) Bandwidth Plot
-R

Answer: a
Explanation: General representation of
frequency response curves are called Bode
SE

plot. Bode plots are also called semi

logarithmic plots since they have logarithmic
values values on one of the axes. 8. When a circuit is called compensated
attenuator?
C

7. Under what condition can the circuit shown a) Transfer function is directly proportional to
be called a compensated attenuator. the frequency
b) Transfer function is inversely proportional

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 Dept. of ECE MCQ - Regulations 2017

to the frequency b) Ccs

c) Transfer function is independent of the c) Cb
frequency d) Ccs and Cb
d) Natural log of the transfer function is
proportional to the frequency

M
Answer: a
Answer: c Explanation: There are two capacitors which
Explanation: Transfer function does not has arise between bases and emitter. One is Cje

O
frequency in its mathematical formula. due to depletion region associated between
base and emitter. Cb is another capacitor

C
9. Which of the following is true? which arises due to the accumulation of
a) Coupling capacitors causes the gain to fall electrons in the base which further results into

T.
off at high frequencies the concentration gradient within the base of
b) Internal capacitor of a device causes the the transistor.
gain to fall off at low frequencies
c) All of the mentioned 2. During high frequency applications of a

O
d) None of the mentioned B.J.T., which parasitic capacitors arise
between the collector and the emitter?

SP
Answer: d a) No capacitor arises
Explanation: Both the statements are false. b) Ccs
c) Cb
10. Which of the following is true?
a) Monolithic IC amplifiers are directly d) Ccs and Cb
G
coupled or dc amplifiers
b) Televisions and radios use tuned amplifiers Answer: a
LO

c) Audio amplifiers have coupling capacitor Explanation: The emitter and the collector
amplifier are far away from each other when the B.J.T.
d) All of the mentioned is being constructed. Hence, we find that they
don’t share a common junction where charges
Answer: d can accumulate. Thus, no such parasitic
.B

Explanation: These all are practical capacitors appear.

applications of different types of amplifiers.
3. During high frequency applications of a
17

B.J.T, which parasitic capacitors arise

TOPIC 4.2 FREQUENCY between the collector and the base?
RESPONSE OF TRANSISTOR a) Cje and Cb
AMPLIFIERS WITH CIRCUIT b) Ccs
-R

CAPACITORS c) Cπ
d) Cµ
TOPIC 4.3 BJT FREQUENCY
SE

Answer: d
RESPONSE Explanation: Only one capacitor up between
the base and the collector. This is due to the
1. During high frequency applications of a depletion region present between the base and
C

B.J.T., which parasitic capacitors arise the collector region.

between the base and the emitter?
a) Cje and Cb 4. Which parasitic capacitors are present at
the collector terminal of the B.J.T.?

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 Dept. of ECE MCQ - Regulations 2017

a) Cje and Cb a) Ccs

b) Ccs and Cµ b) Ccs and Cb
c) Cb c) Cb
d) Ccs and Cb d) Ccs and Cµ

M
Answer: b Answer: a
Explanation: There are two capacitors Explanation: In the follower stage, the load

O
attached to the collector terminal. The is present at the emitter. The parasitic
collector-base junction provides a depletion capacitors present between the collector and

C
capacitance (Cµ) while the collector substrate the substrate i.e. Cµ gets deactivated. This is
junction provides a certain capacitance (Ccs). observed from the small signal analysis where

T.
both the terminals of this capacitor get
5. Which parasitic capacitors do not affect the shorted to A.C. ground.
frequency response of the C.E. stage, of the
8. If the transconductance of the B.J.T

O
B.J.T.?
a) Cje and Cb increases, the transit frequency ______
b) Ccs and Cµ a) Increases

SP
b) Decreases
c) Cb and Cµ c) Doesn’t get affected
d) No parasitic capacitor gets deactivated d) Doubles
G
Answer: d Answer: a
Explanation: While observing the frequency Explanation: The transit frequency is directly
response of a C.E. stage, we find that all the proportional to the transconductance of the
LO

parasitic capacitances of the B.J.T. end up B.J.T. Hence, the correct option is increases.
slowing the speed of the B.J.T. The frequency Since it hasn’t been mentioned that whether
response of this stage is affected by all the the transconductance has been doubled or not,
parasitic capacitors. we cannot conclude the option “doubles” as
.B

an answer.
6. Which parasitic capacitors don’t affect the
frequency response of the C.B. stage of the 9. If the total capacitance between the base
B.J.T.? and the emitter increases by a factor of 2, the
17

a) None of the parasitic capacitances transit frequency __________

b) All the parasitic capacitances a) reduces by 2
c) Some of the coupling capacitors b) increases by 2
d) Ccs and Cb c) reduces by 4
-R

d) increases by 4
Answer: b
Explanation: All the parasitic capacitors of a Answer: a
SE

B.J.T. affect the C.B. stage. None of the Explanation: The transit frequency is almost
parasitic capacitors gets deactivated and they inversely proportional to the total capacitance
end up behaving as a pole during the between the base and the emitter of the B.J.T.
frequency response of the C.B. stage. Hence, the transit frequency will
approximately reduce by 2 and the correct
C

7. Which parasitic capacitors don’t affect the option becomes reduces by 2.

frequency response of the C.C. stage of the
B.J.T.?

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 Dept. of ECE MCQ - Regulations 2017

10. Which effect plays a critical role in the C.E. stage is gmRl. By the application of
producing changes in the frequency response miller effect, we find that the capacitance
of the B.J.T.? between the base and the collector, looking
a) Thevenin’s effect from the output side, will be increased by a
b) Miller effect

M
factor of 1 + 1/gmRl. Hence, the correct
c) Tellegen’s effect
option is 1 + 1/ gmRl.
d) Norton’s effect

O
Answer: a 13. If a C.E. stage with early effect has a load
Explanation: The miller effect results in a Rl and transconductance gm, what is the

C
change in the capacitance seen between the factor by which the capacitance between the
base and the collector. This is why, it affects base and the collector at the output side, gets

T.
the frequency response of the B.J.T. deeply multiplied?
by changing the poles and affecting the high a) 1 + 2/gm*(Rl || ro)
frequency voltage gain stage. b) 1 – 1/gm*(Rl || ro)

O
c) 1 + 1/gm*(Rl || ro)
11. If a C.E. stage has a load Rl and
d) 1 – 2/gm*(Rl || ro)
transconductance gm, what is the factor by

SP
which the capacitance between the base and Answer: c
the collector at the input side gets multiplied? Explanation: If the early effect is considered,
a) 1 + gmRl the low frequency response of the C.E. stage
b) 1 – gmRl becomes gm*(Rl || ro). Thereby, miller
G
c) 1 + 2*gmRl approximation shows that the capacitance
d) 1 – 2*gmRl between the base and the collector, looking
LO

from the output side, will be increased by a

Answer: a factor of 1 + 1/gm*(Rl || ro). Hence the
Explanation: The low frequency gain of the correct option is 1 + 1/ gm*(Rl || ro).
C.E. stage is gmRl. By the application of
.B

miller effect, we find that the capacitor 14. For a high frequency response of a simple
between the base and the collector, looking C.E. stage with a transconductance of gm,
into the input of the C.E. stage, will be what is Cin?
17

increased by a factor of 1 + gmRl. a) Cµ(1 + gm*R2) – Cπ

b) Cµ(1 + gm*R2) + Cπ
12. If a C.E. stage has a load Rl and
c) Cµ(1 – 2*gm*R2) + Cπ
transconductance gm, what is the factor by
-R

d) Cµ(1 + 2*gm*R2) – Cπ
which the capacitance between the base and
the collector at the output side gets
multiplied? Answer: b
Explanation: The input capacitance is an
SE

a) 1 + 1/gmRl
equivalent of the base to emitter capacitance
b) 1 – 1/gmRl in parallel to the miller approximation of the
c) 1 + 2/gmRl base to collector capacitance. Due to miller
d) 1 – 2/gmRl approximation, the base to collector
C

capacitance becomes Cµ(1+gm*R2) while the

Answer: a base to emitter capacitance is Cπ. Capacitors
Explanation: The low frequency response of

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 Dept. of ECE MCQ - Regulations 2017

get added, when in parallel and thus ignored as. Instead of h-parameter model, we
Cµ(1+gm*R2) + Cπ is correct. use π-model.

15. For a high frequency response of a simple 2. Consider a CE circuit, where trans-
conductance is 50mΩ-1, diffusion capacitance

M
C.E. stage with a transconductance of gm,
what is Cout? is 100 pF, transition capacitance is 3 pF. IB =
a) Ccs – Cµ*(2 + 1/gm*R2) 20μA. Given base emitter dynamic resistance,

O
b) Ccs + Cµ*(1 + 2/gm*R2) rbe = 1000 Ω, input VI is 20*sin(107t). What
c) Ccs – Cµ*(1 + 1/gm*R2) is the short circuit current gain?

C
a) 30
d) Ccs + Cµ*(1 + 1/gm*R2)
b) 35

T.
c) 40
Answer: d
d) 100
Explanation: We have a capacitor from the
collector to substrate, Ccs, which comes in Answer: b

O
parallel to the miller approximation of the Explanation: AI = IL/IB
capacitance from base to collector. The miller IL = -gmVb’e

SP
approximation defines the latter as Cµ*(1 +
Vb’e = Ib rb’e / (1+jωCrb’e)
1/gm*R2). Since capacitors gets added, when
C = CD + CT = 103pF
in parallel, the correct option is Ccs + Cµ*(1+
1/gm*R2). Vb’e = 20μ.1k/(1+j.107.103.10-12.1000)
G
AI = IL/IB = 50m.1k/(1+j.107.103.10-12.1000)
AI = 35 (approx).
TOPIC 4.4 SHORT CIRCUIT
LO

CURRENT GAIN 3. Given that transition capacitance is 5 pico

F and diffusion capacitance is 80 pico F, and
TOPIC 4.5 CUT OFF base emitter dynamic resistance is 1500 Ω,
.B

find the β cut-off frequency.

FREQUENCY - Fα, Fβ AND
a) 7.8 x 106 rad/s
UNITY GAIN BANDWIDTH
b) 8.0 x 106 rad/s
17

c) 49.2 x 106 rad/s

1. We cannot use h-parameter model in high
frequency analysis because ____________ d) 22.7 x 106 rad/s
a) They all can be ignored for high
Answer: a
frequencies
-R

b) Junction capacitances are not included in it Explanation: The frequency in radians is

c) Junction capacitances have to be included calculated by
in it ωβ = 1/C.rbe
SE

d) AC analysis is difficult for high frequency ωβ = 7.8 x 106.

using it
4. For given BJT, β=200. The applied input
Answer: b frequency is 20 Mhz and net internal
Explanation: The effect of smaller capacitors
C

capacitance is 100 pF. What is the CE short

is considerable in high frequency analysis of circuit current gain at β cut-off frequency?
analog circuits, and hence they cannot be a) 200
b) 100

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 Dept. of ECE MCQ - Regulations 2017

c) 141.42 Bandwidth Product of BJT

d) 440.2 c) Gain of BJT decreases at higher
frequencies due to junction capacitances
Answer: c d) β- cut-off frequency is one where the CE
Explanation: The current gain for the CE short circuit current gain becomes β/2

M
β
circuit is A =
√1+(
f

f
β
2
) Answer: d
Explanation: At unity gain frequency the

O
β
At f = fβ, A = √2 current gain is 1 is a correct statement. The
Hence A = 141.42. same frequency is fT = βfβ which is the gain

C
bandwidth product of BJT. Gain of BJT at
5. Given that β=200, input frequency is f= high frequency decreases due to the junction

T.
20Mhz and short circuit current gain is capacitance. However, at β cut-off frequency,
A=100. What is the unity gain frequency?
current gain becomes β .
a) 2300 Mhz √2

b) 2000 Mhz

O
c) 2500 Mhz 8. Given a MOSFET where gate to source
d) 3000 Mhz capacitance is 300 pF and gate to drain

SP
capacitance is 500 pF. Calculate the gain
Answer: a bandwidth product if the transconductance is
Explanation: A =
β
30 mΩ-1.
√ 1+(20M hz/f β)
2

a) 5.98 Mhz
1 + (20/f)2 = 4
G
b) 4.9 Mhz
20/f = 1.732 c) 6.5Mhz
fβ = 11.54 Mhz d) 5.22Mhz
LO

Unity gain frequency = βfβ = 200 x 11.54Mhz

= 2308 Mhz. Answer: a
Explanation: Gain bandwidth product for
6. Gain bandwidth frequency is GBP= 3000 any MOSFET is fT = gm/2π(Cgs+Cgd)
.B

Mhz. The cut-off frequency is f=10Mhz. Thus GBP is approximately 5.9 Mhz.
What is the CE short circuit current gain at
the β cutoff frequency? 9. In an RC coupled CE amplifier, when the
17

a) 212 input frequency increases, which of these are

b) 220 incorrect?
c) 300 a) Reactance CSH decreases
d) 200 b) Voltage gain increases
-R

c) Voltage gain decreases due to shunt

Answer: a capacitance
Explanation: fT = 3000Mhz d) An RC coupled amplifier behaves like a
βfβ = 3000Mhz low pass filter
SE

β = 3000/10 = 300
β Answer: b
A= √2
= 212.13. Explanation: When frequency increases,
shunt reactance decreases. The voltage drop
7. Which of the statement is incorrect?
C

across shunt capacitance decreases and net

a) At unity gain frequency the CE short voltage gain decrease. RC coupled amplifier
circuit current gain becomes 1 acts as a low pass filter at high frequencies.
b) Unity gain frequency is the same as Gain

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 Dept. of ECE MCQ - Regulations 2017

TOPIC 4.6 MILLER EFFECT -

FREQUENCY RESPONSE OF
FET

M
1. In Miller’s theorem, what is the constant
K?

O
a) Total voltage gain
b) Internal voltage gain
c) Internal current gain

C
d) Internal power gain

T.
Answer: b a) 27.68
Explanation: The constant K=V2/V1, which b) -22
c) 30.55
is the internal voltage gain of the network.
d) -27.68

O
Thus resistance RM=R/1-K
RN=R/1-K-1. Answer: d

SP
Explanation: Apply millers theorem to
2. When applying miller’s theorem to resistance between input and output.
resistors, resistance R1 is for node 1 and R2 At input, RM=100k/1-K = RI
for node 2. If R1>R2, then for same circuit, Output, RN=100k/1-K-1 ≈ 100k
G
then for capacitance for which the theorem is
Internal voltage gain , K = -hfeRL’/hie
applied, which will be larger, C1 or C2?
a) C1 K = – 50xRc||100k/1k = – 50x4x100/104= –
LO

b) C2 192
c) Both are equal RI = 100k/1+192 = 0.51kΩ
d) Insufficient data RI’ = RI||hie = 0.51k||1k = 0.51×1/1.51 =
0.337kΩ
.B

Answer: a
Net voltage gain = K.RI’/RS+RI’ = – 192 x
Explanation: Given R1>R2
0.337/2k + 0.337k = -27.68.
R/1-K > R/1-K-1, and so 1-K-1>1-K
17

Thus K2>1, K>1, K<-1 (correct) 4. Given that capacitance w.r.t the input node
Thus, C1=C(1-K) and C2=C(1-K-1) is 2pF and output node is 4pF, find
Hence C1>C2 capacitance between input and output node.
a) 0.67 pF
-R

3. Find net voltage gain, given hfe = 50 and b) 1.34pF

hie = 1kΩ. c) 0.44pF
d) 2.2pF
SE

Answer: a
Explanation: C1=C(1-K), C2=C(1-K-1)
C1=2pF
C2=4pF
C

C1/C2=1/2=1-K/1-K-1
K = -2

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 Dept. of ECE MCQ - Regulations 2017

C1 = C(1+2) = 3C a) 22.73 Hz
C = C1/3 = 2/3pF = 0.67 pF. b) 612 Hz
c) 673Hz
5. Consider an RC coupled amplifier at low d) 317 Hz
frequency. Internal voltage gain is -120. Find

M
the voltage gain magnitude, when given that Answer: b
collector resistance = 1kΩ, load = 9kΩ, Explanation: RC = 2kΩ, RL = 5kΩ, CC =
collector capacitance is 0. is 0.1μF, and input

O
1μF, CB = 10μF, CE = 20μF, RS = 2 kΩ
frequency is 20Hz.
hie = 1kΩ, IC = 2mA
a) 120

C
b) 12 fL1 = 1/2πCC(RC+RL) = 22.73 Hz
c) 15 fL2 = gm/2πCE = IC/2πCEVT = 612 Hz

T.
d) -12 Since fL2 > 4fL1, hence fL2 is the correct
answer.
Answer: c
Explanation: AV = -120

O
8. Consider the circuit shown.
fL = 1/2πCC(RC+RL) = 1/2π*0.001 = 1000/2π
= 159.15Hz

SP
AV’ = |AV |

√1
+ (
fL
)
f
2

AV’ = 120/8.02 ≈ 15.

G
6. Find the 3-dB frequency given that the gain
of RC coupled amplifier is 150, the low
frequency voltage gain is 100 and the input
LO

frequency is 50Hz. hfe = 50, hie = 1000Ω. Find magnitude of

a) 50.8 Hz voltage gain at input frequency 10Hz.
b) 55.9 Hz a) 100
c) 60Hz b) 133
.B

d) 100Hz c) 166
d) 220
Answer: b
Answer: b
17

Explanation: AVM = 150

AVL = 100 Explanation: Net load = 10k||10k = 5kΩ =
RL’
f = 50Hz
AVM = -hfeRL’/hie = -50×5/1 = -250
100 = 150 fL 2
+ ( )
-R

√1 50
fL = 1/2πCC(RC+RL) = 15.9 Hz
1+f2/2500 =1.52
AVL = AV M
+ (
fL 2
) = 133.
f2 = 2500*1.25 = 3125 √1 f

f = 55.90 Hz.
SE

9. What is the phase shift in RC coupled CE

7. Given collector resistance = 2kΩ, load amplifier at lower 3dB frequency?
resistance = 5kΩ, collector capacitance = 1μF, a) 180°
emitter capacitance = 20μF, collector current b) 225°
C

= 2mA, source resistance = 2kΩ. If the effect c) 270°

of blocking capacitor is ignored, find the d) 100°
applicable cut-off frequency.

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 Dept. of ECE MCQ - Regulations 2017

Answer: b 20μA. Given base emitter dynamic resistance,

Explanation: Total phase shift = 180°+ tan- rbe = 1000 Ω, input VI is 20*sin(107t). What
1(f /f) is the short circuit current gain?
L
At 3dB frequency fL/f = 1 a) 30

M
Total phase shift = 180° + 45° = 225°. b) 35
c) 40
10. Consider that the phase shift of an RC d) 100

O
coupled CE amplifier is 260°. Find the low
frequency gain when the voltage gain of the Answer: b
Explanation: AI = IL/IB

C
transistor is -150.
a) 100 IL = -gmVb’e

T.
b) 26 Vb’e = Ib rb’e / (1+jωCrb’e)
c) 40 C = CD + CT = 103pF
d) 55
Vb’e = 20μ.1k/(1+j.107.103.10-12.1000)

O
Answer: b AI = IL/IB = 50m.1k/(1+j.107.103.10-12.1000)
Explanation: 180° + tan-1(fL/f) = 260° AI = 35 (approx).

SP
fL/f = tan(80) = 5.67
A= 150
+ 5.672 = 26.05. 3. Given that transition capacitance is 5 pico
F and diffusion capacitance is 80 pico F, and
√1

base emitter dynamic resistance is 1500 Ω,

G
TOPIC 4.7 HIGH FREQUENCY find the β cut-off frequency.
ANALYSIS OF CE AND MOSFET a) 7.8 x 106 rad/s
LO

CS AMPLIFIER b) 8.0 x 106 rad/s

c) 49.2 x 106 rad/s
1. We cannot use h-parameter model in high d) 22.7 x 106 rad/s
frequency analysis because ____________
.B

a) They all can be ignored for high Answer: a

frequencies Explanation: The frequency in radians is
b) Junction capacitances are not included in it calculated by
17

c) Junction capacitances have to be included ωβ = 1/C.rbe

in it ωβ = 7.8 x 106.
d) AC analysis is difficult for high frequency
using it
4. For given BJT, β=200. The applied input
-R

Answer: b frequency is 20 Mhz and net internal

Explanation: The effect of smaller capacitors capacitance is 100 pF. What is the CE short
is considerable in high frequency analysis of circuit current gain at β cut-off frequency?
SE

analog circuits, and hence they cannot be a) 200

ignored as. Instead of h-parameter model, we b) 100
use π-model. c) 141.42
d) 440.2
C

2. Consider a CE circuit, where trans-

Answer: c
conductance is 50mΩ-1, diffusion capacitance Explanation: The current gain for the CE
is 100 pF, transition capacitance is 3 pF. IB =

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 Dept. of ECE MCQ - Regulations 2017

circuit is A = β Answer: d
√1+(
f

f
β
2
) Explanation: At unity gain frequency the
β current gain is 1 is a correct statement. The
At f = fβ, A = same frequency is fT = βfβ which is the gain
√2

Hence A = 141.42.

M
bandwidth product of BJT. Gain of BJT at
high frequency decreases due to the junction
5. Given that β=200, input frequency is f= capacitance. However, at β cut-off frequency,
20Mhz and short circuit current gain is

O
current gain becomes β .
A=100. What is the unity gain frequency? √2

a) 2300 Mhz

C
b) 2000 Mhz 8. Given a MOSFET where gate to source
c) 2500 Mhz capacitance is 300 pF and gate to drain
capacitance is 500 pF. Calculate the gain

T.
d) 3000 Mhz
bandwidth product if the transconductance is
Answer: a 30 mΩ-1.
β
Explanation: A = a) 5.98 Mhz

O
√ 1+(20M hz/f β)
2

b) 4.9 Mhz
1+ (20/f)2 =4 c) 6.5Mhz

SP
20/f = 1.732 d) 5.22Mhz
fβ = 11.54 Mhz
Unity gain frequency = βfβ = 200 x 11.54Mhz Answer: a
= 2308 Mhz. Explanation: Gain bandwidth product for
G
any MOSFET is fT = gm/2π(Cgs+Cgd)
6. Gain bandwidth frequency is GBP= 3000 Thus GBP is approximately 5.9 Mhz.
LO

Mhz. The cut-off frequency is f=10Mhz.

What is the CE short circuit current gain at 9. In an RC coupled CE amplifier, when the
the β cutoff frequency? input frequency increases, which of these are
a) 212 incorrect?
b) 220 a) Reactance CSH decreases
.B

c) 300 b) Voltage gain increases

d) 200 c) Voltage gain decreases due to shunt
capacitance
17

Answer: a d) An RC coupled amplifier behaves like a

Explanation: fT = 3000Mhz low pass filter
βfβ = 3000Mhz
β = 3000/10 = 300 Answer: b
-R

β Explanation: When frequency increases,

A= √2
= 212.13. shunt reactance decreases. The voltage drop
across shunt capacitance decreases and net
7. Which of the statement is incorrect? voltage gain decrease. RC coupled amplifier
SE

a) At unity gain frequency the CE short acts as a low pass filter at high frequencies.
circuit current gain becomes 1
b) Unity gain frequency is the same as Gain
Bandwidth Product of BJT TOPIC 4.8 TRANSISTOR
SWITCHING TIMES
C

c) Gain of BJT decreases at higher

frequencies due to junction capacitances
d) β- cut-off frequency is one where the CE
short circuit current gain becomes β/2

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 Dept. of ECE MCQ - Regulations 2017

1. The collector current will not reach the 3. The technique used to quickly switch off a
steady state value instantaneously because transistor is by_________
of_________ a) reverse biasing its emitter to collector
a) stray capacitances junction
b) resistances b) reverse biasing its base to collector

M
c) input blocking capacitances junction
d) coupling capacitance c) reverse biasing its base to emitter junction

O
d) reverse biasing any junction
Answer: a
Explanation: When a pulse is given, the Answer: c

C
collector current will not reach the steady Explanation: The technique used to quickly
state value instantaneously because of stray switch off a transistor is by reverse biasing its

T.
capacitances. The charging and discharging base to collector junction. It is demonstrated
of capacitance makes the current to reach a in a high voltage switching circuit. The
steady state value after a given time constant. advantage of this circuit is that it is not
necessary to have high voltage control signal.

O
2. For the BJT, β=∞, VBEon=0.7V
VCEsat=0.7V. The switch is initially closed. 4. The disadvantage of using the method of

SP
reverse biasing base emitter junction
At t=0, it is opened. At which time the BJT
is_________
leaves the active region?
a) high voltage control signal
b) low voltage control signal
G
c) output swing
d) incomplete switching of output
LO

Answer: d
Explanation: This method is used to quickly
switch off a transistor is by reverse biasing its
base to collector junction. It is demonstrated
.B

in a high voltage switching circuit. The

disadvantage of using the method of reverse
biasing base emitter junction is that the output
does not switch completely to GND due to
17

a) 20ms forward voltage drop of the diode.

b) 50ms
c) 60ms 5. Which of the following circuits helps in the
d) 70ms applications of switching times?
-R

Answer: b
Explanation: At t < 0, the BJT is OFF in cut
off region. IB=0 as β=∞, so IC=IE. When t >
SE

0, switch opens and BJT is ON. The voltage

across capacitor increases. From the input
loop, -5-VBE-I(4.3K)+10=0 and gives
C

I=1mA. IC1=1-0.5=0.5mA.
VC1=0.7+4.3+10=-5V. IC1=C1dVC1/dt. From
this equation, we get t=50ms.

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 Dept. of ECE MCQ - Regulations 2017

M
O
C
T.
O
a)
c)

SP
G
LO
.B
17

b) d)
-R

Answer: b
Explanation: This is an inverter, in which the
transistor in the circuit is switched between
SE

cut off and saturation. The load, for example,

can be a motor or a light emitting diode or
any other electrical device.

6. Which of the following helps in reducing

C

the switching time of a transistor?

a) a resistor connected from base to ground
b) a resistor connected from emitter to ground

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 Dept. of ECE MCQ - Regulations 2017

c) a capacitor connected from base to ground c) less than 0.7V

d) a capacitor connected from emitter to d) cannot be predicted
ground
Answer: c
Answer: a Explanation: From the cut off characteristics,

M
Explanation: Connecting a resistor connected the base emitter voltage (VBE) in a cut off
from base of a transistor to ground/negative region is less than 0.7V. The cut off region
voltage helps in reducing the switching the

O
can be considered as ‘off mode’. Here, VBE <
switching time of the transistor. When 0.7 and IC=0. For a PNP transistor, the
transistor saturate, there is stored charge in

C
the base that must be removed before it turns emitter potential must be negative with
off. respect to the base.

T.
7. The time taken for a transistor to turn from 10. Switching speed of P+ junction depends
saturation to cut off is _________ on _________
a) inversely proportional to charge carriers a) Mobility of minority carriers in P junction

O
b) directly proportional to charge carriers b) Life time of minority carriers in P junction
c) charging time of the capacitor c) Mobility of majority carriers in N junction
d) Life time of minority carriers in N junction

SP
d) discharging time of the capacitor

Answer: b Answer: d
Explanation: When sufficient charge carriers Explanation: Switching leads to move holes
in P region to N region as minority carriers.
G
exist, the transistor goes into saturation.
When the switch is turned off, in order to go Removal of this accumulation determines
into cut off, the charge carriers in the base switching speed. P+ regards to a diode in
LO

region need to leave. The longer it takes to which the p type is doped excessively.
leave, the longer it takes for a transistor to
turn from saturation to cut off.
.B

8. The switching of power with a PNP

transistor is called _________ UNIT V POWER
a) sourcing current SUPPLIES AND
b) sinking current
17

c) forward sourcing ELECTRONIC DEVICE

d) reverse sinking TESTING
Answer: a
-R

Explanation: Sometimes DC current gain of TOPIC 5.1 LINEAR MODE

a bipolar transistor is too low to directly POWER SUPPLY
switch the load current or voltage, so multiple
SE

switching transistors is used. The load is

connected to ground and the transistor 1. What is done in switching regulators to
switches the power to it. minimize its power dissipation during
switching?
9. The base emitter voltage in a cut off region a) Uses external transistor
C

is _________ b) Uses 1mH choke

a) greater than 0.7V c) Uses external transistor and 1mH choke
b) equal to 0.7V d) None of the mentioned

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 Dept. of ECE MCQ - Regulations 2017

Answer: c 5. The switching regulators can operate in

Explanation: To minimize power dissipation a) Step up
during switching, the external transistor must b) Step down
be a switching power transistor and a 1mH c) Polarity inverting
choke smooth out the current pulses delivered d) All the mentioned

M
to the load.
Answer: d
2. Fixed voltage regulators and adjustable Explanation: The switching regulators can

O
regulators are often called as operate in any one of the three modes
a) Series dissipative regulators depending on the way in which the

C
b) Shunt dissipative regulators components are connected.
c) Stray dissipative regulators

T.
d) All the mentioned 6. Find the diagrammatic representation of
basic switching regulator?
Answer: a
Explanation: Series dissipative regulators

O
simulate a variable resistance between the
input voltage & the load and hence functions

SP
in a linear mode.

3. Linear series regulators are suited for

application with
G
a) High current
b) Medium current Answer: a
c) Low current Explanation: Basic switching regulators
LO

d) None of the mentioned consist of four major components;

1) Voltage source
Answer: b 2) Switch
Explanation: In series dissipative regulator, 3) Pulse generator
4) Filters as mentioned in the diagram.
.B

conversion efficiency decreases as the input

or output voltage differential increases and
vice versa. So, linear series regulators are 7. What are the conditions to be satisfied by a
suited for medium current application with a voltage source for using it in switching
17

small voltage differential. regulator.

1. It must supply the required output power
4. A series switching regulators and the losses associated with the switching
a) Improves the efficiency of regulators regulator
-R

b) Improves the flexibility of switching 2. It must be large enough to supply sufficient

c) Enhance the response of regulators dynamic range line and load variations
d) All of the mentioned 3. It must be sufficient high to meet the
minimum requirement of the regulator system
SE

Answer: a to be designed
Explanation: A series switching regulators is 4. It may be required to store energy for a
constructed such that, a series pass transistor specified amount of time during power failure
is used as a switch rather than as a variable especially if the system is designed for a
C

resistance in linear mode. computer power supply.

a) 1 and 3
b) 1,2,3 and 4

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 Dept. of ECE MCQ - Regulations 2017

c) 2,3 and 4 11. Which of the following is considered to

d) 1,3 and 4 be the most important components of the
switching regulator?
Answer: b a) RC or RLC filter
Explanation: A voltage source must satisfy b) RL or RLC filter

M
the entire given requirement to be used in c) ORC or RL filter
switching regulator. d) RC, RLC or RL filter

O
8. Which among the following act as a switch Answer: b
in switching regulator? Explanation: RL or RLC filter is the most

C
a) Rectifiers important components of the switching
b) Diode regulator, because there are several areas that

T.
c) Transistors are affected by the choke of inductor
d) Relays including energy storage for the regulators
output ripple, transient, response etc.
Answer: c

O
Explanation: A transistor is connected as 12. Which is the most commonly used low
power switch and is operated in the saturated voltage switching regulators?

SP
mode.Thus, the pulse generator output a) Powdered Permalloy toroids
alternatively turns the switch ON and OFF in b) Fermite EI, U and toroid cores
switching regulator. c) Silicon steel EI butt stacks
d) None of the mentioned
9. What should be the frequency range of
G
pulse generator? Answer: c
a) 250 kHz Explanation: The silicon steel EI butt stack
LO

b) 40 kHz exhibits high permeability high flux density

c) 120 kHz and ease of construction and mounting
d) 20 kHz therefore, it is most commonly used in low
voltage switching regulators.
Answer: d
.B

Explanation: The most effective frequency 13. Find the value of Rsc, L and Co for a
range for pulse generator for optimum µA7840 switching regulator to provide +5 v
efficiency and component size is 20kHz.
17

at 3A, using the following specifications:

toff= 24µs, ripple voltage = 400mA and
10. Filter used in switching regulator’s are
also as called ton=26µs.
a) DC – AC transformers a) Rsc = 55 mΩ , L = 25µH & Co = 750µF
-R

b) AC – DC transformers b) Rsc = 550 mΩ , L = 25µH & Co = 75µF

c) DC transformer c) Rsc = 650 mΩ , L = 25µH & Co = 65µF
d) AC transformer
d) Rsc = 720 mΩ , L = 25µH & Co = 250µF
SE

Answer: c
Explanation: Filter converts the pulse Answer: a
waveform from the output of the switch into a Explanation: Peak current,Ipk= 400mA× 1.5
dc voltage. Since this switching mechanism (since Ipk = 1.5 A for peak current)
C

allows a conversion similar to transformers, ∴ Rsc = 0.33ohm/Ipk = 0.33ohm/6 =

the switching regulators is often referred to as 0.055ohm.
a DC transformer. => L= [(Vo +Vp) / I pk]×toff =[(5+1.25) /6 ]×

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 Dept. of ECE MCQ - Regulations 2017

24×10-6 =25µH. a) 1- iii , 2- i , 3- ii

=> Co = [Ipk (Ton +Toff)]/[8×Vripple] ∵T = b) 1- i , 2- ii , 3- iii
c) 1- iii , 2- ii , 3- i
[ton + toff] = 26µs + 24µs = 50µs
d) 1- iii , 2- ii , 3- i
=> Co = [ (6×50µs)]/(8×50mA) = 7.5×10-4 =

M
750µF. Answer: b
Explanation: Characteristics and design
formula for step up, step down and converting

O
14. Calculate the efficiency of the step down
switching regulator given the input voltage mode of switching regulator.
Vin= 13.5v and output voltage =6v. Assume

C
the saturating Voltage Vs=1.1v and the TOPIC 5.2 RECTIFIERS -
forward voltage drop Vd = 1.257v FILTERS - HALF-WAVE

T.
a) η = 75% RECTIFIER POWER SUPPLY
b) η = 48.5%
c) η = 63.9%

O
1. The diode in a half wave rectifier has a
d) η = 80.5%
forward resistance RF. The voltage is
Vmsinωt and the load resistance is RL. The

SP
Answer: d
Explanation: Efficiency of the step down DC current is given by _________
switching regulator, η = {[(Vin-Vs+Vd)]/ a) Vm/√2RL
[Vin]}×(Vo) / [(Vo+Vd)] = {[(13.5v- b) Vm/(RF+RL)π
G
1.1v+1.257v)/13.5v]} ×[(6/(6 ×1.257)] => c) 2Vm/√π
Efficiency of switching regulator, η = d) Vm/RL
(1.012×0.7955)×100 = 0.8051×100 = 80.5%.
LO

Answer: b
15. Match the characteristics for various Explanation: For a half wave rectifier, the
switching regulators. IDC=IAVG=Im/π
I= Vmsinωt/(RF+RL)=Imsinωt
.B

Switching
Characteristics Im =Vm/ RF+RL So, IDC=Im/π=Vm/(RF+RL).
regulator
(i) [ton / toff ] = [ Vo
2. The below figure arrives to a conclusion
17

1. + Vd] / [Vin -Vs - that _________

Inverting Vd]; Rsc = ( 0.33/
Ipk)
-R

(ii) [ton / toff ] = [

2. step Vo + Vd -Vin] /
down [Vin-Vs] ; Rsc = (
SE

0.33/ Ipk)
(iii) [ton / toff ] = [
Modulus Vo +Vd] / a) for Vi > 0, V0=-(R2/R1)Vi
3. step up
C

(Vin-Vs); Rsc = ( b) for Vi > 0, V0=0

0.33/ Ipk c) Vi < 0, V0=-(R2/R1)Vi
d) Vi < 0, V0=0

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 Dept. of ECE MCQ - Regulations 2017

Answer: b information with this equation, Vm =50.

Explanation: The given op-amp is in
Power=Vm2/RL=50*50/1000=2.5V.
inverting mode and this makes the output
voltage to have a phase shift of 180°. The
output voltage is now negative. So, the diode 5. In a half wave rectifier, the sine wave input

M
is 200sin300t. The average value of output
1 is reverse biased and diode 2 is forward
voltage is?
biased. Then output is clearly zero.
a) 57.876V

O
3. What is the output as a function of the b) 67.453V
input voltage (for positive values) for the c) 63.694V

C
given figure. Assume it’s an ideal op-amp d) 76.987V
with zero forward drop (Di=0)
Answer: c

T.
Explanation: Comparing with the standard
equation, Vm=200V.
Average value is given by, Vavg=Vm/π.

O
So, 200/π=63.694.

SP
6. Efficiency of a half wave rectifier is
a) 50%
b) 60%
c) 40.6%
G
a) 0 d) 46%
b) -Vi
c) Vi Answer: c
LO

Explanation: Efficiency of a rectifier is the

d) 2Vi
effectiveness to convert AC to DC. For half
wave it’s 40.6%. It’s given by, Vout/Vin*100.
Answer: c
Explanation: When the input of the inverted
.B

7. If peak voltage for a half wave rectifier

mode op-amp is positive, the output is
circuit is 5V and diode cut in voltage is 0.7,
negative.
then peak inverse voltage on diode will be?
The diode is reverse biased. The input
17

a) 5V
appears at the output. b) 4.9V
4. In a half wave rectifier, the sine wave input c) 4.3V
d) 6.7V
is 50sin50t. If the load resistance is of 1K,
-R

then average DC power output will be? Answer: c

a) 3.99V Explanation: PIV is the maximum reverse
b) 2.5V
bias voltage that can be appeared across a
c) 5.97V
SE

diode in the given circuit, If the PIV rating is

d) 6.77V
less than this value of breakdown of diode
Answer: b will occur. For a rectifier, PIV=Vm-Vd=5-
Explanation: The standard form of a sine 0.7=4.3V.
C

wave is Vmsinωt. BY comparing the given

8. Transformer utilisation factor of a half
wave rectifier is _________
a) 0.234

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 Dept. of ECE MCQ - Regulations 2017

b) 0.279 1. Efficiency of a centre tapped full wave

c) 0.287 rectifier is _________
d) 0.453 a) 50%
b) 46%
Answer: c c) 70%

M
Explanation: Transformer utilisation factor is d) 81.2%
the ratio of AC power delivered to load to the
DC power rating. This factor indicates Answer: d

O
effectiveness of transformer usage by Explanation: Efficiency of a rectifier is the
rectifier. For a half wave rectifier, it’s low and effectiveness to convert AC to DC. It’s

C
equal to 0.287. obtained by taking ratio of DC power output
to maximum AC power delivered to load. It’s

T.
9. If the input frequency of a half wave usually expressed in percentage. For centre
rectifier is 100Hz, then the ripple frequency tapped full wave rectifier, it’s 81.2%.
will be_________
a) 150Hz 2. A full wave rectifier supplies a load of

O
b) 200Hz 1KΩ. The AC voltage applied to diodes is
c) 100Hz 220V (rms). If diode resistance is neglected,

SP
d) 300Hz what is the ripple voltage?
a) 0.562V
Answer: c b) 0.785V
Explanation: The ripple frequency of the c) 0.954V
G
output and input is same. This is because, one d) 0.344V
half cycle of input is passed and other half
cycle is seized. So, effectively the frequency Answer: c
LO

is the same. Explanation: The ripple voltage is

(Vϒ)RMS=ϒVDC /100.
10. Ripple factor of a half wave rectifier VDC=0.636*VRMS* √2=0.636*220*
is_________(Im is the peak current and RL is
√2=198V and ripple factor ϒ for full wave
.B

load resistance) rectifier is 0.482.

a) 1.414 Hence, (Vϒ)RMS=0.482*198 /100=0.954V.
b) 1.21
17

c) 1.4
3. A full wave rectifier delivers 50W to a load
d) 0.48 of 200Ω. If the ripple factor is 2%, calculate
the AC ripple across the load.
Answer: b
a) 2V
Explanation: The ripple factor of a rectifier
-R

b) 5V
is the measure of disturbances produced in
c) 4V
the output. It’s the effectiveness of a power
d) 1V
supply filter to reduce the ripple voltage. The
SE

ratio of ripple voltage to DC output voltage is Answer: a

ripple factor which is 1.21.
Explanation: We know that, PDC=VDC2/RL.

TOPIC 5.3 FULL-WAVE So, VDC=(PDC*RL)1/2=100001/2=100V.

C

RECTIFIER POWER SUPPLY Here, ϒ=0.02

ϒ=VAC/VDC=VAC/100.So,
VAC=0.02*100=2V.

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 Dept. of ECE MCQ - Regulations 2017

4. A full wave rectifier uses load resistor of 6. If input frequency is 50Hz for a full wave
1500Ω. Assume the diodes have Rf=10Ω, rectifier, the ripple frequency of it would be
Rr=∞. The voltage applied to diode is 30V _________
a) 100Hz
with a frequency of 50Hz. Calculate the AC
b) 50Hz

M
power input.
c) 25Hz
a) 368.98mW
d) 500Hz
b) 275.2mW

O
c) 145.76mW Answer: a
d) 456.78mW Explanation: In the output of the centre

C
tapped rectifier, one of the half cycle is
Answer: b
Explanation: The AC power input repeated. The frequency will be twice as that

T.
of input frequency. So, it’s 100Hz.
PIN=IRMS2(RF+Rr).
IRMS=Im/ 7. Transformer utilization factor of a centre
√2=Vm/(Rf+RL)√2=30/(1500+10)*1.414=13.5mA tapped full wave rectifier is_________

O
So, PIN=(13.5*10-3)2*(1500+10)=275.2mW. a) 0.623
b) 0.678

SP
c) 0.693
5. In a centre tapped full wave rectifier,
d) 0.625
RL=1KΩ and for diode Rf=10Ω. The primary
voltage is 800sinωt with transformer turns Answer: c
ratio=2. The ripple factor will be _________
G
Explanation: Transformer utilisation factor is
the ratio of AC power delivered to load to the
DC power rating. This factor indicates
LO

effectiveness of transformer usage by

rectifier. For a half wave rectifier, it’s low and
equal to 0.693.
.B

8. In the circuits given below, the correct full

wave rectifier is _________
a) 54%
b) 48%
17

c) 26%
d) 81%

Answer: b
-R

Explanation: The ripple factor ϒ=

[(IRMS/IAVG)2 – 1]1/2. IRMS =Im /
√2=Vm/(Rf+RL)√2=200/1.01=198.
SE

(Secondary line to line voltage is 800/2=400.

Due to centre tap Vm=400/2=200)
a)
IRMS=198/√2=140mA, IAVG=2*198/
π=126mA. ϒ=[(140/126)2-1]1/2=0.48. So,
C

ϒ=48%.

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 Dept. of ECE MCQ - Regulations 2017

9. If the peak voltage on a centre tapped full

wave rectifier circuit is 5V and diode cut in
voltage is 0.7. The peak inverse voltage on
diode is_________
a) 4.3V

M
b) 9.3V
c) 5.7V

O
d) 10.7V

Answer: b

C
Explanation: PIV is the maximum reverse
bias voltage that can be appeared across a
b)

T.
diode in the given circuit, if PIV rating is less
than this value of breakdown of diode will
occur. For a rectifier, PIV=2Vm-Vd = 10-0.7

O
= 9.3V.

10. In a centre tapped full wave rectifier, the

SP
input sine wave is 250sin100t. The output
ripple frequency will be _________
a) 50Hz
b) 100Hz
G
c) 25Hz
d) 200Hz
LO

c)
Answer: b
Explanation: The equation of sine wave is in
the form Vmsinωt. So, by comparing we get
ω=100. Frequency, f =ω/2=50Hz. The output
.B

of centre tapped full wave rectifier has double

the frequency of inpu. Hence, fout = 100Hz.
17

TOPIC 5.4 VOLTAGE

REGULATORS: VOLTAGE
REGULATION - LINEAR
-R

SERIES SHUNT AND

d) SWITCHING VOLTAGE
Answer: c REGULATORS
SE

Explanation: When the input is applied, a

full wave rectifier should have a current flow. 1. What is done in switching regulators to
The flow should be in the same direction for minimize its power dissipation during
both positive and negative half cycles. Only switching?
C

the third circuit satisfies the above condition. a) Uses external transistor
b) Uses 1mH choke

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 Dept. of ECE MCQ - Regulations 2017

c) Uses external transistor and 1mH choke is used as a switch rather than as a variable
d) None of the mentioned resistance in linear mode.

Answer: c 5. The switching regulators can operate in

Explanation: To minimize power dissipation a) Step up

M
during switching, the external transistor must b) Step down
be a switching power transistor and a 1mH c) Polarity inverting
choke smooth out the current pulses delivered d) All the mentioned

O
to the load.
Answer: d

C
2. Fixed voltage regulators and adjustable Explanation: The switching regulators can
regulators are often called as operate in any one of the three modes

T.
a) Series dissipative regulators depending on the way in which the
b) Shunt dissipative regulators components are connected.
c) Stray dissipative regulators
d) All the mentioned 6. Find the diagrammatic representation of

O
basic switching regulator?
Answer: a

SP
Explanation: Series dissipative regulators
simulate a variable resistance between the
input voltage & the load and hence functions
in a linear mode.
G
3. Linear series regulators are suited for
application with
LO

a) High current
b) Medium current Answer: a
c) Low current Explanation: Basic switching regulators
d) None of the mentioned consist of four major components;
1) Voltage source
.B

Answer: b 2) Switch
Explanation: In series dissipative regulator, 3) Pulse generator
conversion efficiency decreases as the input 4) Filters as mentioned in the diagram.
17

or output voltage differential increases and

vice versa. So, linear series regulators are 7. What are the conditions to be satisfied by a
suited for medium current application with a voltage source for using it in switching
small voltage differential. regulator.
-R

1. It must supply the required output power

4. A series switching regulators and the losses associated with the switching
a) Improves the efficiency of regulators regulator
b) Improves the flexibility of switching 2. It must be large enough to supply sufficient
SE

c) Enhance the response of regulators dynamic range line and load variations
d) All of the mentioned 3. It must be sufficient high to meet the
minimum requirement of the regulator system
Answer: a to be designed
C

Explanation: A series switching regulators is 4. It may be required to store energy for a

constructed such that, a series pass transistor specified amount of time during power failure
especially if the system is designed for a

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 Dept. of ECE MCQ - Regulations 2017

computer power supply. allows a conversion similar to transformers,

a) 1 and 3 the switching regulators is often referred to as
b) 1,2,3 and 4 a DC transformer.
c) 2,3 and 4
d) 1,3 and 4 11. Which of the following is considered to

M
be the most important components of the
Answer: b switching regulator?
Explanation: A voltage source must satisfy a) RC or RLC filter

O
the entire given requirement to be used in b) RL or RLC filter
switching regulator. c) ORC or RL filter

C
d) RC, RLC or RL filter
8. Which among the following act as a switch

T.
in switching regulator? Answer: b
a) Rectifiers Explanation: RL or RLC filter is the most
b) Diode important components of the switching
c) Transistors regulator, because there are several areas that

O
d) Relays are affected by the choke of inductor
including energy storage for the regulators

SP
Answer: c output ripple, transient, response etc.
Explanation: A transistor is connected as
power switch and is operated in the saturated 12. Which is the most commonly used low
mode.Thus, the pulse generator output voltage switching regulators?
G
alternatively turns the switch ON and OFF in a) Powdered Permalloy toroids
switching regulator. b) Fermite EI, U and toroid cores
c) Silicon steel EI butt stacks
LO

9. What should be the frequency range of d) None of the mentioned

pulse generator?
a) 250 kHz Answer: c
b) 40 kHz Explanation: The silicon steel EI butt stack
.B

c) 120 kHz exhibits high permeability high flux density

d) 20 kHz and ease of construction and mounting
therefore, it is most commonly used in low
Answer: d voltage switching regulators.
17

Explanation: The most effective frequency

range for pulse generator for optimum 13. Find the value of Rsc, L and Co for a
efficiency and component size is 20kHz. µA7840 switching regulator to provide +5 v
at 3A, using the following specifications:
-R

10. Filter used in switching regulator’s are toff= 24µs, ripple voltage = 400mA and
also as called
ton=26µs.
a) DC – AC transformers
b) AC – DC transformers a) Rsc = 55 mΩ , L = 25µH & Co = 750µF
SE

c) DC transformer b) Rsc = 550 mΩ , L = 25µH & Co = 75µF

d) AC transformer c) Rsc = 650 mΩ , L = 25µH & Co = 65µF
Answer: c d) Rsc = 720 mΩ , L = 25µH & Co = 250µF
C

Explanation: Filter converts the pulse

waveform from the output of the switch into a Answer: a
dc voltage. Since this switching mechanism Explanation: Peak current,Ipk= 400mA× 1.5

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 Dept. of ECE MCQ - Regulations 2017

(since Ipk = 1.5 A for peak current) Modulus Vo +Vd] /

∴ Rsc = 0.33ohm/Ipk = 0.33ohm/6 = (Vin-Vs); Rsc = (
0.055ohm. 0.33/ Ipk
=> L= [(Vo +Vp) / I pk]×toff =[(5+1.25) /6 ]×

M
24×10-6 =25µH. a) 1- iii , 2- i , 3- ii
=> Co = [Ipk (Ton +Toff)]/[8×Vripple] ∵T = b) 1- i , 2- ii , 3- iii
c) 1- iii , 2- ii , 3- i

O
[ton + toff] = 26µs + 24µs = 50µs
d) 1- iii , 2- ii , 3- i
=> Co = [ (6×50µs)]/(8×50mA) = 7.5×10-4 =

C
750µF. Answer: b
Explanation: Characteristics and design
14. Calculate the efficiency of the step down formula for step up, step down and converting

T.
switching regulator given the input voltage mode of switching regulator.
Vin= 13.5v and output voltage =6v. Assume
the saturating Voltage Vs=1.1v and the TOPIC 5.5 OVER VOLTAGE

O
forward voltage drop Vd = 1.257v PROTECTION - BJT AND
a) η = 75% MOSFET

SP
b) η = 48.5%
c) η = 63.9%
1. The MOSFET combines the areas of
d) η = 80.5%
_______ & _________
G
Answer: d a) field effect & MOS technology
Explanation: Efficiency of the step down b) semiconductor & TTL
c) mos technology & CMOS technology
LO

switching regulator, η = {[(Vin-Vs+Vd)]/

d) none of the mentioned
[Vin]}×(Vo) / [(Vo+Vd)] = {[(13.5v-
1.1v+1.257v)/13.5v]} ×[(6/(6 ×1.257)] => Answer: a
Efficiency of switching regulator, η = Explanation: It is an enhancement of the
.B

(1.012×0.7955)×100 = 0.8051×100 = 80.5%. FET devices (field effect) using MOS

technology.
15. Match the characteristics for various
switching regulators. 2. Which of the following terminals does not
17

belong to the MOSFET?

Switching a) Drain
Characteristics
regulator b) Gate
(i) [ton / toff ] = [ Vo c) Base
-R

+ Vd] / [Vin -Vs - d) Source

1.
Inverting Vd]; Rsc = ( 0.33/ Answer: c
SE

Ipk) Explanation: MOSFET is a three terminal

(ii) [ton / toff ] = [ device D, G & S.

2. step Vo + Vd -Vin] / 3. Choose the correct statement

down [Vin-Vs] ; Rsc = ( a) MOSFET is a uncontrolled device
C

0.33/ Ipk) b) MOSFET is a voltage controlled device

c) MOSFET is a current controlled device
3. step up (iii) [ton / toff ] = [

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 Dept. of ECE MCQ - Regulations 2017

d) MOSFET is a temperature controlled Answer: b

device Explanation: The arrow is to indicate the
direction of electrons (opposite to the
Answer: b direction of conventional current flow).
Explanation: It is a voltage controlled

M
device. 7. The controlling parameter in MOSFET is
a) Vds
4. Choose the correct statement(s) b) Ig

O
i) The gate circuit impedance of MOSFET is c) Vgs
higher than that of a BJT d) Is

C
ii) The gate circuit impedance of MOSFET is
lower than that of a BJT Answer: b

T.
iii) The MOSFET has higher switching losses Explanation: The gate to source voltage is
than that of a BJT the controlling parameter in a MOSFET.
iv) The MOSFET has lower switching losses
than that of a BJT 8. In the internal structure of a MOSFET, a

O
a) Both i & ii parasitic BJT exists between the
b) Both ii & iv a) source & gate terminals

SP
c) Both i & iv b) source & drain terminals
d) Only ii c) drain & gate terminals
d) there is no parasitic BJT in MOSFET
Answer: c
Answer: b
G
Explanation: MOSFET requires gate signals
with lower amplitude as compared to BJTs & Explanation: Examine the internal structure
has lower switching losses. of a MOSFET, notice the n-p-n structure
LO

between the drain & source. A p-channel

5. Choose the correct statement MOSFET will have a p-n-p structure.
a) MOSFET is a unipolar, voltage controlled,
two terminal device 9. In the transfer characteristics of a
MOSFET, the threshold voltage is the
.B

b) MOSFET is a bipolar, current controlled,

three terminal device measure of the
c) MOSFET is a unipolar, voltage controlled, a) minimum voltage to induce a n-channel/p-
three terminal device channel for conduction
17

d) MOSFET is a bipolar, current controlled, b) minimum voltage till which temperature is

two terminal device constant
c) minimum voltage to turn off the device
Answer: c d) none of the above mentioned is true
-R

Explanation: MOSFET is a three terminal

device, Gate, source & drain. It is voltage Answer: a
controlled unlike the BJT & only electron Explanation: It is the minimum voltage to
induce a n-channel/p-channel which will
SE

current flows.
allow the device to conduct electrically
6. The arrow on the symbol of MOSFET through its length.
indicates
a) that it is a N-channel MOSFET 10.The output characteristics of a MOSFET,
C

b) the direction of electrons is a plot of

c) the direction of conventional current flow a) Id as a function of Vgs with Vds as a
d) that it is a P-channel MOSFET parameter

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 Dept. of ECE MCQ - Regulations 2017

b) Id as a function of Vds with Vgs as a Answer: c

parameter Explanation: SMPS has higher output ripple
c) Ig as a function of Vgs with Vds as a and its regulation is worse.
parameter
d) Ig as a function of Vds with Vgs as a 4. _________ is used for critical loads where

M
parameter temporary power failure can cause a great
deal of inconvenience.
Answer: b a) SMPS

O
Explanation: It is Id vs Vds which are plotted b) UPS
for different values of Vgs (gate to source c) MPS

C
voltage). d) RCCB

T.
Answer: b
TOPIC 5.6 SWITCHED MODE Explanation: Uninterruptible Power Supply
POWER SUPPLY (SMPS) is used where loads where temporary power
failure can cause a great deal of

O
1. SMPS is used for inconvenience.
a) obtaining controlled ac power supply

SP
b) obtaining controlled dc power supply 5. __________ is used in the rotating type
c) storage of dc power UPS system to supply the mains.
d) switch from one source to another a) DC motor
b) Self excited DC generator
G
Answer: b c) Alternator
Explanation: SMPS (Switching mode power d) Battery bank
supply) is used for obtaining controlled dc
LO

power supply. Answer: c

Explanation: When the supply is gone, the
2. SPMS are based on the ________ diesel engine is started, which runs the
principle. alternator and the alternator supplies power to
.B

a) Phase control the mains. Non-rotating type UPS are not

b) Integral control used anymore.
c) Chopper
d) MOSFET 6. Static UPS requires __________
17

a) only rectifier
Answer: c b) only inverter
Explanation: SMPS (Switching mode power c) both inverter and rectifier
supply) are based on the chopper principle. d) none of the mentioned
-R

The output dc voltage is controlled by

varying the duty cycle of the chopper circuit. Answer: c
Explanation: Rectifier to converter the dc
from the battery to ac. Inverter to charge the
SE

3. Choose the incorrect statement.

a) SMPS is less sensitive to input voltage battery from mains.
variations
b) SMPS is smaller as compared to rectifiers 7. No discontinuity is observed in case of
c) SMPS has low input ripple a) short break static UPS configuration
C

d) SMPS is a source of radio interference b) long break static UPS configuration

c) no break static UPS configuration
d) rotating type UPS configuration

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 Dept. of ECE MCQ - Regulations 2017

Answer: c 1. Which of the following can be a source of

Explanation: No dip or discontinuity is supply in dc power supplies?
observed in case of no break static UPS a) Battery
configuration, as the battery inverter set b) Dry cell
immediately takes over the mains. c) Full wave rectifier

M
d) All of the mentioned
8. Usually __________ batteries are used in
the UPS systems. Answer: d

O
a) NC Explanation: Source of supply will be a
b) Li-On battery, dry cell or full wave rectifier etc.

C
c) Lead acid
d) All of the mentioned 2. Which of the application’s filters used for?

T.
a) Reducing ripples
Answer: c b) Increasing ripples
Explanation: Lead acid batteries are cheaper c) Increasing phase change
and have certain advantages over the other d) Increasing amplitude

O
types. NC batteries would however be the
best, but are three to four times more Answer: a

SP
expensive than Lead Acid. Explanation: Ripples are ac components and
filters are used for eliminating ac components
9. HVDC transmission has ___________ as from a signal.
compared to HVAC transmission.
3. Which of the following represent a change
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a) smaller transformer size
b) smaller conductor size of output voltage when load current is
c) higher corona loss increased?
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d) smaller power transfer capabilities a) Line regulation

b) Load regulation
Answer: b c) Current regulation
Explanation: The conductor size is smaller as d) Voltage regulation
.B

there is no sink effect, and the whole

conductor is utilized for transmitting power. Answer: b
Explanation: Load regulation is the process
10. The negative polarity is used in the of fractional change of output voltage when
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monopolar link because it load current is increased from zero to

a) uses less conductor size maximum value.
b) is safer
c) produces less radio interference 4. Which of the following generate output
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d) has less resistance voltage much closer to true value?

a) True generator
Answer: c b) Precision generator
Explanation: The monopolar link uses just a c) Output generator
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single conductor, which is usually negative as d) Accurate generator

it produces less radio interference and corona.
Answer: b
Explanation: Precision generators are one
C

TOPIC 5.8 DESIGN OF which generates output voltage much closer

REGULATED DC POWER to the true value.
SUPPLY

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 Dept. of ECE MCQ - Regulations 2017

5. Why zener diodes are provided in dc 8. For instrumentation system, precision

supply? variable voltage-reference system is
a) For forward conduction necessary.
b) For reverse conduction a) True
c) For reference voltage b) False

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d) For increasing amplitude
Answer: a
Answer: c Explanation: Precision variable voltage

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Explanation: Zener diodes in dc power reference system is used for comparing
supplies are used for providing a reference voltage with a reference voltage and can be

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voltage used for comparison. used in the instrumentation system.

T.
6. Stability of output voltage is entirely 9. Which of the following can be used as a
depended on ______________ comparator?
a) Stability of transformer a) Zener diode
b) Stability of zener diode b) Diode

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c) Quality of wires c) Operational amplifier
d) Capacitor values d) All of the mentioned

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Answer: b Answer: c
Explanation: Stability of zener diodes used is Explanation: Operational amplifier can be
an important factor in determining the used as a comparator circuit.
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stability of output voltage in dc power supply.
10. Which of the following are not the
7. For excellent stability, the zener diode is standard value of Zener diodes?
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kept in temperature controlled casket. a) 5.1 V

a) True b) 5.6 V
b) False c) 5.8V
d) 6.2V
Answer: a
.B

Explanation: Zener diode is kept on Answer: c

temperature controlled casket due to its low Explanation: Standard values of zener
temperature coefficient which may lead to voltages are 5.1V, 5.6V, 6.2V and 9.1V etc.
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less stability.
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