EECE320 - Digital Systems Design Section 1: Homework 2
EECE320 - Digital Systems Design Section 1: Homework 2
Section 1
Homework 2
(Due date: Monday 02 November 2020, by 23:59)
b) (15 pts) For the following Truth table with two outputs:
• Provide the Boolean functions f1 and f2 using the Canonical Sum and
Canonical Product expressions.
• Express f1 and f2 using the Σ and Π notations.
• Sketch the logic circuits corresponding to the Canonical Sum and
Canonical Product.
b) (10 pts) Sketch the resulting logic circuit assuming that the gates you use can have no more than 2
inputs.
Problem 3 (25 pts)
Design a circuit (simplify your circuit) that verifies the logical operation of a 3-input AND gate. f = '1'
(LED ON) if the AND gate works properly. Assumption: when the AND gate is not working, it
generates 1's instead of 0's and vice versa.
c) (7 pts) The following is the timing diagram of a logic circuit with 3 inputs. Sketch the logic circuit
that generates this waveform. Then, complete the VHDL code.