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EEE-4765 Assignment 2

1. The document describes a state machine implementation to introduce a delay of 20 clock cycles to an input signal before assigning it to the output. 2. The state machine has two states: idle and delay_c. It increments a counter from 1 to 20 before assigning the input to the output and returning to the idle state. 3. A testbench is provided to simulate the design and verify the 20 clock cycle delay. Resetting the state machine and changing the timing of the valid_data and data_in signals are also tested.

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Ali Sami Ahmad Faqeeh 160021176
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72 views16 pages

EEE-4765 Assignment 2

1. The document describes a state machine implementation to introduce a delay of 20 clock cycles to an input signal before assigning it to the output. 2. The state machine has two states: idle and delay_c. It increments a counter from 1 to 20 before assigning the input to the output and returning to the idle state. 3. A testbench is provided to simulate the design and verify the 20 clock cycle delay. Resetting the state machine and changing the timing of the valid_data and data_in signals are also tested.

Uploaded by

Ali Sami Ahmad Faqeeh 160021176
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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EEE 4765

Assignment No .2

Name: Ali S. A. Faqeeh


ID: 160021176
Department: EEE
SECTION: A
Introduction:
Here, We will use a counter and state machine to introduce the
delay. We have an input signal, and we want to assign it to the
output only after (say) 20 clock cycles. In the following there is
the state machine.

There are two states in the state machine: idleand delay_c.


when the system is in idle state it waits for a valid input bit at
the port data_in. whenever the data is valid, valid_data will go
high. Upon receiving a valid data, the system moves to delay_c
state where a counter, c is incremented every clock cycle till it
reaches the maximum delay value (here it is 20). Once the max.
count is reached system goes back to idle state and the input
data will be assigned to output data. This process goes on and
on.
Source code
libraryieee;

useieee.std_logic_1164.all;

useieee.numeric_std.all;

entitydelay is

port(

clk:instd_logic;

valid_data:instd_logic;

data_in:instd_logic;

data_out:outstd_logic

);

endentity;

architecturebehavioral ofdelay is

signalc :integer:=0;

constantd:integer:=20;

signaldata_temp:std_logic:='0';

typestate_typeis(idle,delay_c); --listing down the states of FSM

signalnext_s:state_type;--declare the state machine signal

begin

process(clk)

begin

if(rising_edge(clk))then

casenext_sis

whenidle =>

if(valid_data='1')then
next_s<=delay_c;

data_temp<=data_in;

c <=1;

endif;

whendelay_c=>

if(c =d)then

c <=1;

data_out<=data_temp;

next_s<=idle;

else

c <=c +1; --counter increment

endif;

whenothers=>

NULL;

endcase;

endif;

endprocess;

endarchitecturebehavioral;

Testbench
libraryieee;

useieee.std_logic_1164.all;

useieee.numeric_std.all;

entitytb_delayis

endentity;

architecturebehavioral oftb_delayis

componentdelay

port(

clk:instd_logic;

valid_data:instd_logic;

data_in:instd_logic;
data_out:outstd_logic

);

endcomponent;

signalclk:std_logic:='0';

signaltb_valid_data:std_logic:='0';

signaltb_data_in:std_logic:='0';

signaltb_data_out:std_logic:='0';

constantclk_period:time:=4ns;

begin

--Unit Under Test

uut:delay portmap(

clk=>clk,

valid_data=>tb_valid_data,

data_in=>tb_data_in,

data_out=>tb_data_out

);

--clock process definition

clk_proc:process

begin

clk<='0';

waitforclk_period/2;

clk<='1';

waitforclk_period/2;

endprocess;

--Stimulus process

stim_proc:process

begin

Simulation
1.Input at 20ns and synthesizable delay will be
150ns.
Source Code
library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity delay is

port(

clk:in std_logic;

valid_data:in std_logic;

data_in:in std_logic;

data_out:out std_logic

);
end entity;

architecture behavioral of delay is

signal c :integer:=0;

constant d:integer:=20;

signal data_temp:std_logic:='0';

type state_type is(idle,delay_c); --listing down the states of FSM

signal next_s:state_type;--declare the state machine signal

begin

process(clk)

begin

if(rising_edge(clk)) then

case next_s is

when idle =>

if(valid_data='1')then

next_s <= delay_c;

data_temp <= data_in;

c <=1;

end if;

when delay_c=>

if(c =d)then

c <=1;

data_out <= data_temp;

next_s <= idle;

else

c <=c +1; --counter increment

end if;

when others=>

NULL;
end case;

end if;

end process;

end architecture behavioral;

TestBench
library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity tb_delay is

end entity;

architecture behavioral of tb_delay is

component delay

port(

clk:in std_logic;

valid_data:in std_logic;

data_in:in std_logic;

data_out:out std_logic

);

end component;

signal clk:std_logic:='0';

signal tb_valid_data:std_logic:='0';

signal tb_data_in:std_logic:='0';

signal tb_data_out:std_logic:='0';

constant clk_period:time:=4ns;

begin

--Unit Under Test

uut:delay port map(

clk=>clk,

valid_data=>tb_valid_data,
data_in=>tb_data_in,

data_out=>tb_data_out);

--clock process definition

clk_proc:process

begin

clk<='0';

wait for clk_period/2;

clk<='1';

wait for clk_period/2;

end process;

--Stimulus process

stim_proc:process

begin

wait for 20ns;

tb_data_in<='1';

wait for 70ns;

tb_valid_data<='1';

wait;

end process;

end architecture behavioral;

Simulation
2.Transposing valid_data and data_in timing
sequence:
Testbench
library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity tb_delay is

end entity;

architecture behavioral of tb_delay is

component delay

port(

clk:in std_logic;

valid_data:in std_logic;

data_in:in std_logic;

data_out:out std_logic

);

end component;

signal clk:std_logic:='0';

signal tb_valid_data:std_logic:='0';

signal tb_data_in:std_logic:='0';

signal tb_data_out:std_logic:='0';

constant clk_period:time:=4ns;

begin

--Unit Under Test

uut:delay port map(

clk=>clk,

valid_data=>tb_valid_data,

data_in=>tb_data_in,
data_out=>tb_data_out);

--clock process definition

clk_proc:process

begin

clk<='0';

wait for clk_period/2;

clk<='1';

wait for clk_period/2;

end process;

--Stimulus process

stim_proc:process

begin

wait for 70ns;

tb_data_in<='1';

wait for 20ns;

tb_valid_data<='1';

wait;

end process;

end architecture behavioral;

Simulation
Observation:
Here,we have transposed the valid_data and data_in timing
sequence from 20ns and 70ns to 70ns and 20ns
respectively.We can see that the output is found at 170ns for
both cases.The difference is in the synthesizable
delay.Previously it was 150ns,after transposing it is 100ns.
3.Inserting a reset in Source code:
Source code
library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity delay is

port(

clk:in std_logic;

valid_data:in std_logic;

data_in:in std_logic;

data_out:out std_logic;

rst:in std_logic

);

end entity;

architecture behavioral of delay is

signal c :integer:=0;

constant d:integer:=20;

signal data_temp:std_logic:='0';

type state_type is(idle,delay_c); --listing down the states of FSM


signal next_s:state_type;--declare the state machine signal

begin

process(clk)

begin

if(rising_edge(clk)) then

case next_s is

when idle =>

if(rst='0')then

if(valid_data='1')then

next_s <= delay_c;

data_temp <= data_in;

c <=1;

end if;

else

next_s <= idle;

data_out<='0';

end if;

when delay_c=>

if(rst='0')then

if(c =d)then

c <=1;

data_out <= data_temp;

next_s <= idle;

else

c <=c +1; --counter increment

end if;

else

next_s <= idle;

data_out<='0';

end if;

when others=>
NULL;

end case;

end if;

end process;

end architecture behavioral;

Testbench
library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity tb_delay is

end entity;

architecture behavioral of tb_delay is

component delay

port(

clk:in std_logic;

valid_data:in std_logic;

data_in:in std_logic;

data_out:out std_logic;

rst:in std_logic

);

end component;

signal clk:std_logic:='0';

signal tb_valid_data:std_logic:='0';

signal tb_data_in:std_logic:='0';

signal tb_data_out:std_logic:='0';

signal tb_rst:std_logic:='0';

constant clk_period:time:=4ns;

begin

--Unit Under Test

uut:delay port map(


clk=>clk,

valid_data=>tb_valid_data,

data_in=>tb_data_in,

data_out=>tb_data_out,

rst=>tb_rst

);

--clock process definition

clk_proc:process

begin

clk<='0';

wait for clk_period/2;

clk<='1';

wait for clk_period/2;

end process;

--Stimulus process

stim_proc:process

begin

wait for 70ns;

tb_data_in<='1';

wait for 20ns;

tb_valid_data<='1';

wait for 100ns;

tb_rst<='1';

wait;

end process;

end architecture behavioral;

Simulation

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