Alvin J.
Gilay
ECE 538 – Logic Circuits and Logic Theory
Laboratory 3
IV - RESULTS/ VERIFICATION:
Record your observations to the corresponding truth table below.
Table 1
INPUT OUTPUT
A B F
0 0 0
0 1 1
1 0 1
1 1 1
Table 2
INPUT OUTPUT
A B F
0 0 0
0 1 0
1 0 0
1 1 1
Table 3
INPUT OUTPUT
A B F
0 0 0
0 1 0
1 0 0
1 1 1
Simplified Circuit Expression
F = AB
Table 4
INPUT OUTPUT
A B F
0 0 0
0 1 1
1 0 1
1 1 1
Simplified Circuit Expression
F=A+B
V - CONCLUSIONS:
After performing the third laboratory exercise, which is the implementation of the
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NAND and NOR gates, I have learned that various combinations and creativity in
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using logic gates, it can represent another logic gate, it can either be more complex
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or it can shorten the circuit diagram of an expression which originally is long when
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you use the standard gates and not experimenting in using other gates like the NAND
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and the NOR gates.
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Furthermore I have learned that the NAND-NOR gates is an universal gate which can
create and implement any other boolean functions without the need of any other gate
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type like the NOT, OR, AND, XOR, XNOR boolean gates.
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Moreover, in practice the NAND-NOR gates are economical and easier to fabricate
and are the basic gates used in all IC digital logic families, because in a single gate
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like the NOR gate, it contains a NOT-OR gate.
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VI - POST-LABORATORY ASSESSMENT:
1. Implement a NOR gate using NAND gates; then implement a NAND gate using
NOR gates.
2. F = (X + Y + Z')( X + Y' + Z)( X' + Y + Z)( X' + Y' + Z')
Convert the POS expression into its corresponding SOP expression. Implement
the SOP expression using NAND gates only.
F = (X + Y + Z')(X + Y' + Z)(X' + Y + Z)(X' + Y' + Z')
F = (X + XY' + XZ + XY + YZ + XZ' + Y'Z')(X' + Y + Z)(X' + Y' + Z')
F = (X'YZ + X'Y'Z' + XZ + XY + XYZ + YZ + XYZ' + XY'Z)(X' + Y' + Z')
3. F = X' Y' Z' + X ' Y Z + X Y' Z +X Y Z'
Convert the SOP expression into its corresponding POS expression. Implement
the POS expression using NOR gates only.
F = X'Y'Z' + X'YZ + XY'Z + XYZ'
F Y'Z' Y'Z YZ YZ'
X' 1 0 1 0
X 0 1 0 1
F = (X' + Y' + Z')(X' + Y + Z)(X + Y' + Z)(X + Y + Z')
Rubric for Laboratory Report in Logic Circuits and Switching Theory
Name of Student: Alvin J. Gilay Score: ________
Exemplary Proficient Fair Poor
Criteria
The diagrams
The diagrams The diagrams
The diagrams and truth
and truth are and truth
and truth tables are < 40
Analysis and 75 - 94% tables are 40
tables are 95- % correct and
Design (All correct and/or to 74%
100% are poor in
circuit is sub- correct and/or
accurate, and designing &
diagrams & exemplary in is poor in
are very neatly drawing
truth tables.) designing & designing &
designed & quality. Does
(35pts) drawing drawing
drawn not know how
quality. quality.
(30 -35 pts) to design
(25 -30 pts) (15 -25 pts)
(0-15 pts)
80-100% of the
79 -60 % of the Less than 40%
required 59-40% design
design design
Conduct of design elements are
elements are elements are
Experiment elements are obtained
obtained obtained
(25 pts) obtained properly.
properly properly
properly. (10 -20 pts)
(15 -20 pts). (0-10 pts)
(20-25) pts)
75%-
Completed all 40-74% <40%
90-100% 89%completed,
parts of the completed, completed or
Completed without any
laboratory (20 with help (10- not done
(18-20 pts) help
pts) 15 pts) (0-10 pts)
(15- 20 pts)
The results are
The results are
interpreted
interpreted
correctly not in
correctly and The results are Does not know
a complete
Interpretation with not interpreted about the
manner with a
(10 pts) demonstrated correctly. material. (0-
little
understanding (4-6 pts) 3pts)
understanding
of the design.
of the design.
(9-10 pts)
(6-8 pts)
Safety
Safety
Safety instructions Safety
instructions
instructions were carried instructions
were carried
Safety (10 pts) were carried after many were not
after instruction
completely; instructions carried;
from faculty;
(10 pts) from faculty; (0-3 pts)
(7-9pts)
(4-7 pts)
