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This document outlines the contents of a course on ASIC design and verification. The course contains 7 modules that cover hardware description languages like Verilog, functional verification using testbenches and systemverilog, assertion based verification, coverage driven verification, direct programming interfaces, and ASIC prototyping using FPGAs. The modules introduce key concepts and teach tools, methodologies, and best practices for verifying ASIC designs from functional verification to formal verification and validation on FPGA prototypes.

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26 views1 page

Course

This document outlines the contents of a course on ASIC design and verification. The course contains 7 modules that cover hardware description languages like Verilog, functional verification using testbenches and systemverilog, assertion based verification, coverage driven verification, direct programming interfaces, and ASIC prototyping using FPGAs. The modules introduce key concepts and teach tools, methodologies, and best practices for verifying ASIC designs from functional verification to formal verification and validation on FPGA prototypes.

Uploaded by

brk_318
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Course Contents

Module-1:Hardware Description Languages - Verilog


ASIC Design Concepts, ASIC Design Flow-Fronded and backend, EDA tools for
Fronded and backend, Hardware Modeling Overview ,Verilog Language
Concepts,Modules and Ports ,Introduction to Test benches Verilog Operators and
Expressions,Data Flow and behavior Level Modeling ,Verilog Procedural
Statements ,Controlled Operation Statements ,Verilog Tasks and Functions
,Advanced Language Concepts,Finite State Machines, RTL Coding guidelines,
linting.
Module-2: Functional Verification
Introduction to Functional Verification ,Verification Cycle ,Test bench structures
and different types of TBs VerificationFlow,Basic Verification environment ,Ver
ifi cation components, Verification Planning ,Introduction to bus functional
model Verification Planning ,Verification Technologies ,Stimulus and response.
Introduction to Unix commands, vim editor, Perl and Tcl, Basics of Perl scripting,
Array Fundamentals, Hashes Basics, Control structures, Functions, File I/O,
Regular expression, Test automation using script.
Module-3: Advanced Verification Languages - System Verilog
Introduction to functional verification languages, Introduction to System Verilog,
System Verilog data types. System Verilog procedures, Interfaces and modports,
System Verilog routines. Introduction to object oriented programming , Classes
and Objects, Inheritance , Composition, Inheritance v/s composition, Virtual
methods. Parameterized classes, Virtual interface, Using OOP for verification,
System Verilog Verification Constructs
Module- 4: Assertion based verification
Introduction to assertion, Overview of properties and assertion, Basics
ofproperties and sequences, Advanced properties and sequences, Assertions in
design and formal verification, some guidelines in assertion writing
Module-5: Coverage Driven Verification and functional coverage in SV
Coverage Driven Verification, Coverage Metrics, Code Coverage, Introduction to
functional coverage, Functional coverage constructs, Assertion Coverage,
Coverage measurement, Coverage Analysis
Module-6: DPI and Verification Methodology
Basics of PLI of Verilog, Direct Programming Interface,VerificationMethodology
(VMM) , Verification components, OVM Overview
Module-7 ASIC Prototyping
ASIC Prototyping using FPGAs, Importance and advantages of FPGA
prototyping in ASIC Verification and Validation, Challenges in ASIC
Prototyping,Design partitioning of Multimillion Gate ASIC into FPGAs,
Embedded Logic Analyzers-Xilinx Chip Scope and ALTERA Signal Tap.
Debugging in FPGA validation environment.

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