TDA7492P

25 W + 25 W dual BTL class-D audio amplifier

Datasheet - production data

Description
The TDA7492P is a dual BTL class-D audio
amplifier with single power supply, designed for
LCD TVs and monitors.
Thanks to the high efficiency and exposed-pad-
down (EPD) package no heatsink is required.

PowerSSO-36
with exposed pad down

Features
 25 W + 25 W continuous output power at
THD = 10% with VCC = 20 V and RL = 8 
 Wide-range single-supply operation (8 - 26 V)
 High efficiency ( = 90%)
 Four selectable, fixed gain settings of
nominally 21.6 dB, 27.6 dB, 31.1 dB and
33.6 dB
 Differential inputs minimize common-mode
noise
 Standby and mute features
 Short-circuit protection
 Thermal overload protection
 Externally synchronizable
 ECOPACK®, environmentally-friendly package

Table 1. Device summary

Order code Operating temp. range Package Packaging

TDA7492P13TR -40 to 85 °C PowerSSO-36 EPD Tape and reel

February 2014 DocID15068 Rev 6 1/27

This is information on a product in full production. www.st.com
Contents TDA7492P

Contents

1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Characterizations for 6  loads with 18 V . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Characterizations for 8  loads with 20 V . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3 Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.1 Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.2 Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6 Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.7 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/27 DocID15068 Rev 6

TDA7492P List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. How to set up SYNCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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27
List of figures TDA7492P

List of figures

Figure 1. Internal block diagram (showing one channel only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Pin connections (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. THD at 1 kHz vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. THD at 100 Hz vs. output power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. THD at 1 W vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Crosstalk vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. FFT 0 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. FFT -60 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Output power vs supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. THD at 1 kHz vs output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. THD at 100 Hz vs output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 14. THD at 1 W vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 15. Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Crosstalk vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 17. FFT 0 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18. FFT -60 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19. Test board (SZ-LAB-TDA7492P) layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 20. Applications circuit for class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 21. Standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22. Turn-on/off sequence for minimizing speaker “pop” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 23. Device input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 24. Master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. Typical LC filter for a 8  speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 26. Typical LC filter for a 4  speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 27. Behavior of pin DIAG for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 28. PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4/27 DocID15068 Rev 6

TDA7492P Device block diagram

1 Device block diagram

Figure 1 shows the block diagram of one of the two identical channels of the TDA7492P.

Figure 1. Internal block diagram (showing one channel only)

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Pin description TDA7492P

2 Pin description

2.1 Pinout
Figure 2. Pin connections (top view, PCB view)

SUB_GND 1 36 VSS
OUTPB 2 35 SVCC
OUTPB 3 34 VREF
PGNDB 4 33 INNB
PGNDB 5 32 INPB
PVCCB 6 31 GAIN1
PVCCB 7 30 GAIN0
OUTNB 8 29 SVR
OUTNB 9 28 DIAG
OUTNA 10 27 SGND
OUTNA 11 26 VDDS
PVCCA 12 25 SYNCLK
PVCCA 13 24 ROSC
PGNDA 14 Exposed pad down 23 INNA
(Connect to ground)
PGNDA 15 22 INPA
OUTPA 16 21 MUTE
OUTPA 17 20 STBY
PGND 18 19 VDDPW

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TDA7492P Pin description

2.2 Pin list

Table 2. Pin description list
Pin n° Name Type Description

1 SUB_GND PWR Connect to the frame

2,3 OUTPB O Positive PWM for right channel
4,5 PGNDB PWR Power stage ground for right channel
6,7 PVCCB PWR Power supply for right channel
8,9 OUTNB O Negative PWM output for right channel
10,11 OUTNA O Negative PWM output for left channel
12,13 PVCCA PWR Power supply for left channel
14,15 PGNDA PWR Power stage ground for left channel
16,17 OUTPA O Positive PWM output for left channel
18 PGND PWR Power stage ground
19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage
20 STBY I Standby mode control
21 MUTE I Mute mode control
22 INPA I Positive differential input of left channel
23 INNA I Negative differential input of left channel
24 ROSC O Master oscillator frequency-setting pin
25 SYNCLK I/O Clock in/out for external oscillator
3.3-V (nominal) regulator output referred to ground for signal
26 VDDS O
blocks
27 SGND PWR Signal ground
28 DIAG O Open-drain diagnostic output
29 SVR O Supply voltage rejection
30 GAIN0 I Gain setting input 1
31 GAIN1 I Gain setting input 2
32 INPB I Positive differential input of right channel
33 INNB I Negative differential input of right channel
34 VREF O Half VDDS (nominal) referred to ground
35 SVCC PWR Signal power supply
36 VSS O 3.3-V (nominal) regulator output referred to power supply
- EP PWR Exposed pad for connection to ground plane as heatsink

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27
Electrical specifications TDA7492P

3 Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings
Symbol Parameter Value Unit

VCCMAX DC supply voltage for pins PVCCA, PVCCB, SVCC 30 V

Voltage limits for input pins STANDBY, MUTE, INNA, INPA,
VI -0.3 to 3.6 V
INNB, INPB, GAIN0, GAIN1
Top Operating temperature -40 to 85 °C
Tj Junction temperature -40 to 150 °C
Tstg Storage temperature -40 to 150 °C

3.2 Thermal data

Table 4. Thermal data
Symbol Parameter Min Typ Max Unit

Rth j-case Thermal resistance, junction to case - 2 3 °C/W

Rth j-amb (1)
Thermal resistance, junction to ambient - 24 - °C/W
1. FR4 with vias to copper area of 9 cm2

3.3 Electrical specifications

Unless otherwise stated, the results in Table 5 below are given for the conditions:
VCC = 20 V, RL (load) = 8 , ROSC = R3 = 39 k, C8 = 100 nF, f = 1 kHz, GV = 21.6 dB, and
Tamb = 25 °C.

Table 5. Electrical specifications

Symbol Parameter Condition Min Typ Max Unit

Supply voltage for

VCC - 8 - 26 V
pins PVCCA, PVCCB, SVCC
Iq Total quiescent - - 26 35 mA
IqSTBY Quiescent current in standby - - 2.5 5.0 µA
Play mode - - ±100 mV
VOS Output offset voltage
Mute mode - - ±60 mV
IOCP Overcurrent protection threshold RL = 0  3.8 4.2 - A
Junction temperature at thermal
TjSD - - 150 - °C
shutdown
Ri Input resistance Differential input 48 60 - k

8/27 DocID15068 Rev 6

TDA7492P Electrical specifications

Table 5. Electrical specifications (continued)

Symbol Parameter Condition Min Typ Max Unit

VOVP Overvoltage protection threshold - 28 29 - V

Undervoltage protection
VUVP - - - 7 V
threshold
High side - 0.2 -
RdsON Power transistor on resistance 
Low side - 0.2 -
THD = 10% - 25 -
Po Output power W
THD = 1% - 20 -
VCC = 12 V, THD = 10% - 9.5 -
Po Output power W
VCC = 12 V, THD = 1% - 7.2 -
Po = 25 W + 25 W,
PD Power dissipated by device - 5.0 - W
THD = 10%
 Efficiency Po = 10 W + 10 W 80 90 - %
THD Total harmonic distortion Po = 1 W - 0.1 0.4 %
GAIN0 = L, GAIN1 = L 20.6 21.6 22.6
GAIN0 = L, GAIN1 = H 26.6 27.6 28.6
GV Closed-loop gain dB
GAIN0 = H, GAIN1 = L 30.1 31.1 32.1
GAIN0 = H, GAIN1 = H 32.6 33.6 34.6
GV Gain matching - - - ±1 dB
CT Cross talk f = 1 kHz - 50 - dB
A Curve, GV = 20 dB - 20 -
eN Total input noise µV
f = 22 Hz to 22 kHz - 25 35
fr = 100 Hz, Vr = 0.5 V,
SVRR Supply voltage rejection ratio 40 50 - dB
CSVR = 10 µF
Tr, Tf Rise and fall times - - 50 - ns
fSW Switching frequency Internal oscillator 290 310 330 kHz
(1)
Output switching frequency With internal oscillator 250 - 400
fSWR kHz
range With external oscillator (2) 250 - 400
VinH Digital input high (H) 2.3 - -
- V
VinL Digital input low (L) - - 0.8
AMUTE Mute attenuation VMUTE = 1 V 60 80 - dB
1. fSW = 106 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 k, see Figure 20.
2. fSW = fSYNCLK / 2 with the frequency of the external oscillator.

DocID15068 Rev 6 9/27

27
Characterization curves TDA7492P

4 Characterization curves

The following characterizations were made using the SZ-LAB-TDA7492P demo board. The
layout is shown in Figure 19 on page 16. The LC filter for the 6  load used 22 µH and
220 nF components, whilst that for the 8  load used 33 µH and 220 nF.

4.1 Characterizations for 6  loads with 18 V

Figure 3. Output power vs. supply voltage
28
Test conditions: 26

Vcc = 8 to 18 V, 24
THD = 10%
RL = 6 Ω, 22
20
Rosc = 39 kΩ, Cosc = 100 nF,
Output power (W)
18
f = 1 kHz,
16
Gv = 30 dB,
14
Tamb = 25r C
12 THD = 1%
10

Specification limit: 8

Typical: 6

Vcc =18 V, RL = 6 Ω 4

2
Po = 25 W @THD = 10%
0
Po = 20 W @THD = 1% 8 9 10 11 12 13 14 15 16 17 18

Supply voltage (V)

Figure 4. THD at 1 kHz vs. output power

10

Test conditions: 5

Vcc = 18 V, THD (%)

2
RL = 6 Ω,
Rosc = 39 kΩ, Cosc = 100 nF, 1

f = 1 kHz,
0.5
Gv = 30 dB,
Tamb = 25r C 0.2

0.1

0.05
Specification limit:
Typical: 0.02

Po = 25 W @THD = 10%
0.01

0.005
200m 500m 1 2 5 10 20 30

Output power (W)

10/27 DocID15068 Rev 6

TDA7492P Characterization curves

Figure 5. THD at 100 Hz vs. output power

10

Test conditions: 5
THD (%)
Vcc = 18 V,
2
RL = 6 Ω,
Rosc = 39 kΩ, Cosc = 100 nF, 1

f = 100 Hz,
0.5
Gv = 30 dB,
Tamb = 25r C 0.2

0.1

0.05

Specification limit: 0.02

Typical:
0.01
Po = 25 W @THD = 10%
0.005
200m 500m 1 2 5 10 20 30

2XWSXWSRZHU:

Figure 6. THD at 1 W vs. frequency

0.5
Test conditions:
Vcc = 18 V, THD (%)
RL = 6 Ω, 0.2

Rosc = 39 kΩ, Cosc = 100 nF,

f = 1 kHz, 0.1
Gv = 30 dB,
Po = 1 W
0.05
Tamb = 25r C

0.02

Specification limit: 0.01

Typical:
THD < 0.4% 0.005
20 50 100 200 500 1k 2k 5k 10k 20k

Frequency (Hz)

Figure 7. Frequency response

+2
Test conditions:
Vcc = 18 V, +1
RL = 6 Ω, Ampl
Rosc = 39 kΩ, Cosc = 100 nF, (dB)
-0
f = 1 kHz,
Gv = 30 dB,
-1
Po = 1 W
Tamb = 25r C
-2

-3

Specification limit:
Max: -4

+/-3 dB @20 Hz to 20 kHz

-5
10 20 50 100 200 500 1k 2k 5k 10k 30k

Frequency (Hz)

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27
Characterization curves TDA7492P

Figure 8. Crosstalk vs frequency

-60

Test conditions: -65

Vcc = 18 V, Crosstalk
-70
RL = 6 Ω, (dB)
-75
Rosc = 39 kΩ, Cosc = 100 nF,
f = 1 kHz, -80

Gv = 30 dB, -85

Po = 1 W
-90
Tamb = 25r C
-95

-100

-105

Specification limit: -110

Typical:
-115
> 50 dB @f = 1 kHz
-120
20 50 100 200 500 1k 2k 5k 10k 20k

Frequency (Hz)

Figure 9. FFT 0 dB
+10
+0
Test conditions:
FFT -10
Vcc = 18 V,
(dB) -20
RL = 6 Ω,
-30
Rosc = 39 kΩ, Cosc = 100 nF,
-40
f = 1 kHz,
-50
Gv = 30 dB,
-60
Po = 1 W -70
Tamb = 25r C -80

-90

-100

-110
Specification limit: -120
Typical: -130
> 60 dB for the harmonic frequency -140

-150
20 50 100 200 500 1k 2k 5k 10k 20k

Frequency (Hz)

Figure 10. FFT -60 dB

+0

Test conditions: -10

Vcc = 18 V, FFT -20

RL = 6 Ω, (dB) -30

Rosc = 39 kΩ, Cosc = 100 nF, -40

f = 1 kHz, -50

Gv = 30 dB, -60

Po = -60 dB @1 W = 0 dB -70

Tamb = 25r C -80

-90

-100

-110

Specification limit: -120

Typical: -130

> 90dB for the harmonic frequency -140

-150
20 50 100 200 500 1k 2k 5k 10k 20k

Frequency (Hz)

12/27 DocID15068 Rev 6

TDA7492P Characterization curves

4.2 Characterizations for 8  loads with 20 V

Figure 11. Output power vs supply voltage

28
Test conditions:
26
Vcc = 8 to 20 V,
24
RL = 8 Ω,
22

Output power (W)

Rosc = 39 kΩ, Cosc = 100 nF,
20 THD = 10%
f = 1 kHz,
18
Gv = 30 dB, 16
Tamb = 25r C 14

12
THD = 1%
10
Specification limit:
8
Typical:
6
Vs = 20 V, RL = 8 Ω 4
Po = 25 W @THD = 10% 2
Po = 20 W @THD = 1% 8 9 10 11 12 13 14 15 16 17 18 19 20

Supply voltage (V)

Figure 12. THD at 1 kHz vs output power

10

Test conditions: 5

Vcc = 20 V, THD (%)

RL = 8 Ω, 2

Rosc = 39 kΩ, Cosc = 100 nF, 1

f = 1 kHz,
0.5
Gv = 30 dB,
Tamb = 25r C 0.2

0.1

0.05
Specification limit:
Typical: 0.02
Po = 25 W @THD = 10%
0.01

0.005
100m 200m 500m 1 2 5 10 20 30

Output power (W)

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Characterization curves TDA7492P

Figure 13. THD at 100 Hz vs output power

10

Test conditions: 5

Vcc = 20 V, THD (%)

RL = 8 Ω, 2

Rosc = 39 kΩ, Cosc = 100 nF, 1

f = 100 Hz,
0.5
Gv = 30 dB,
Tamb = 25r C
0.2

0.1

0.05

Specification limit:
0.02
Typical:
0.01
Po = 25 W @THD = 10%

0.005
100m 200m 500m 1 2 5 10 20 30

Output power (W)

Figure 14. THD at 1 W vs frequency

0.5

Test conditions:
Vcc = 20 V,
RL = 8 Ω, 0.2

Rosc = 39 kΩ, Cosc = 100 nF, THD (%)

f = 1 kHz, 0.1
Gv = 30 dB,
Po = 1 W
0.05
Tamb = 25r C

0.02

Specification Limit:
0.01
Typical:
THD < 0.4%
0.005
20 50 100 200 500 1k 2k 5k 10k 20k

Frequency (Hz)

Figure 15. Frequency response

+2
Test conditions:
Vcc = 20 V, +1
RL = 8 Ω,
Ampl
Rosc = 39 kΩ, Cosc = 100 nF,
(dB) -0
f = 1 kHz,
Gv = 30 dB,
-1
Po = 1 W
Tamb = 25r C
-2

-3

Specification limit:
-4
Max:
+/-3 dB @20 Hz to 20 kHz
-5
10 20 50 100 200 500 1k 2k 5k 10k 20k 30k

Frequency (Hz)

14/27 DocID15068 Rev 6

TDA7492P Characterization curves

Figure 16. Crosstalk vs frequency

-60
TTTTTTTTTTT TTTT T TTTTT

Test conditions: -65

Vcc = 20 V, Crosstalk
-70
RL = 8 Ω, (dB)
-75
Rosc = 39 kΩ, Cosc = 100 nF,
-80
f = 1 kHz,
Gv = 30 dB, -85

Po = 1 W -90
Tamb = 25r C
-95

-100

-105

Specification limit: -110

Typical:
-115
> 50 dB @f = 1 kHz
-120
20 50 100 200 500 1k 2k 5k 10k 20k

Frequency (Hz)

Figure 17. FFT 0 dB

+10

Test conditions: +0

Vcc = 20 V, FFT -10

RL = 8 Ω (dB)
-20

Rosc = 39 kΩ, Cosc = 100 nF, -30

-40
f = 1 kHz,
-50
Gv = 30 dB,
-60
Po = 1 W
-70
Tamb = 25r C
-80

-90
-100

-110
Specification limit:
-120
Typical:
-130
> 60 dB for the harmonic frequency
-140

-150
20 50 100 200 500 1k 2k 5k 10k 20k

Frequency (Hz)

Figure 18. FFT -60 dB

+0

Test conditions: -10

Vcc = 20 V, -20
FFT
RL = 8 Ω, -30
(dB)
Rosc = 39 kΩ, Cosc = 100 nF, -40

f = 1 kHz, -50

Gv = 30 dB, -60

Po = -60 dB (1 W = 0 dB) -70

Tamb = 25r C -80

-90

-100

-110
Specification limit:
-120
Typical:
-130
> 90 dB for the harmonic frequency
-140

-150
20 50 100 200 500 1k 2k 5k 10k 20k

Frequency (Hz)

DocID15068 Rev 6 15/27

27
Characterization curves TDA7492P

Figure 19. Test board (SZ-LAB-TDA7492P) layout

2. Test Board

16/27 DocID15068 Rev 6

 5 Applications circuit

TDA7492P
Figure 20. Applications circuit for class-D amplifier

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17/27
Applications information TDA7492P

6 Applications information

6.1 Mode selection

The three operating modes of the TDA7492P are set by the two inputs STBY (pin 20) and
MUTE (pin 21).
 Standby mode: all circuits are turned off, very low current consumption.
 Mute mode: inputs are connected to ground and the positive and negative PWM
outputs are at 50% duty cycle.
 Play mode: the amplifiers are active.
The protection functions of the TDA7492P are enabled by pulling down the voltages of the
STBY and MUTE inputs shown in Figure 21. The input current of the corresponding pins
must be limited to 200 µA.

Table 6. Mode settings

Mode selection STBY MUTE

Standby L (1) X (don’t care)

(1)
Mute H L
Play H H
1. Drive levels defined in Table 5: Electrical specifications on page 8

Figure 21. Standby and mute circuits

Standby STBY
3.3 V R2 C7
0V 30 k 2.2 µF TDA7492P

Mute MUTE
3.3 V R4 C15
0V 30 k 2.2 µF

Figure 22. Turn-on/off sequence for minimizing speaker “pop”

VCC
0
t

STBY
0
t

MUTE
0
t
Input
0
t

Output
0 t
Standby Mute Play Mute Standby
Iq

0 t

18/27 DocID15068 Rev 6

TDA7492P Applications information

6.2 Gain setting

The gain of the TDA7492P is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin31).
Internally, the gain is set by changing the feedback resistors of the amplifier.

Table 7. Gain settings

GAIN0 GAIN1 Nominal gain, Gv (dB)

0 0 21.6
0 1 27.6
1 0 31.1
1 1 33.6

6.3 Input resistance and capacitance

The input impedance is set by an internal resistor Ri = 60 k (typical). An input capacitor
(Ci) is required to couple the AC input signal.
The equivalent circuit and frequency response of the input components are shown in
Figure 23. For Ci = 470 nF the high-pass filter cutoff frequency is below 20 Hz:

fc = 1 / (2 *  * Ri * Ci)

Figure 23. Device input circuit and frequency response

Rf

Input
signal Input Ri
Ci
pin

DocID15068 Rev 6 19/27

27
Applications information TDA7492P

6.4 Internal and external clocks

The clock of the class-D amplifier can be generated internally or can be driven by an
external source.
If two or more class-D amplifiers are used in the same system, it is recommended that all
devices operate at the same clock frequency. This can be implemented by using one
TDA7492P as master clock, while the other devices are in slave mode (that is, externally
clocked. The clock interconnect is via pin SYNCLK of each device. As explained below,
SYNCLK is an output in master mode and an input in slave mode.

6.4.1 Master mode (internal clock)

Using the internal oscillator, the output switching frequency, fSW, is controlled by the
resistor, ROSC, connected to pin ROSC:

fSW = 106 / ((16 * ROSC + 182) * 4) kHz

where ROSC is in k.
In master mode, pin SYNCLK is used as a clock output pin, whose frequency is:

fSYNCLK = 2 * fSW
For master mode to operate correctly then resistor ROSC must be less than 60 k as given
below in Table 8.

6.4.2 Slave mode (external clock)

In order to accept an external clock input the pin ROSC must be left open, that is, floating.
This forces pin SYNCLK to be internally configured as an input as given in Table 8.
The output switching frequency of the slave devices is:
fSW = fSYNCLK / 2
s

Table 8. How to set up SYNCLK

Mode ROSC SYNCLK

Master ROSC < 60 k Output

Slave Floating (not connected) Input

Figure 24. Master and slave connection

Master Slave
TDA7492P TDA7492P

ROSC SYNCLK SYNCLK ROSC

Output Input

Cosc Rosc
100 nF 39 k

20/27 DocID15068 Rev 6

TDA7492P Applications information

6.5 Output low-pass filter

To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The
cutoff frequency should be larger than 22 kHz and much lower than the output switching
frequency. It is necessary to choose the L-C component values depending on the loud
speaker impedance. Some typical values, which give a cutoff frequency of 27 kHz, are
shown in Figure 25 and Figure 26 below.

Figure 25. Typical LC filter for a 8  speaker

Figure 26. Typical LC filter for a 4  speaker

DocID15068 Rev 6 21/27

27
Applications information TDA7492P

6.6 Protection functions

The TDA7492P is fully protected against overvoltage, undervoltage, overcurrent and
thermal overloads as explained here.

Overvoltage protection (OVP)

If the supply voltage exceeds the value for VOVP given in Table 5: Electrical specifications
on page 8 the overvoltage protection is activated which forces the outputs to the
high-impedance state. When the supply voltage drops to below the threshold value the
device restarts.

Undervoltage protection (UVP)

If the supply voltage drops below the value for VUVP given in Table 5: Electrical
specifications on page 8 the undervoltage protection is activated which forces the outputs to
the high-impedance state. When the supply voltage recovers the device restarts.

Overcurrent protection (OCP)

If the output current exceeds the value for IOCP given in Table 5: Electrical specifications on
page 8 the overcurrent protection is activated which forces the outputs to the
high-impedance state. Periodically, the device attempts to restart. If the overcurrent
condition is still present then the OCP remains active. The restart time, TOC, is determined
by the R-C components connected to pin STBY.

Thermal protection (OTP)

If the junction temperature, Tj, reaches 145 °C (nominally), the device goes to mute mode
and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction
temperature reaches the value for Tj given in Table 5: Electrical specifications on page 8 the
device shuts down and the output is forced to the high-impedance state. When the device
cools sufficiently the device restarts.

6.7 Diagnostic output

The output pin DIAG is an open-drain transistor. When the protection is activated it is in the
high-impedance state. The pin can be connected to a power supply (<26 V) by a pull-up
resistor whose value is limited by the maximum sinking current (200 µA) of the pin.

Figure 27. Behavior of pin DIAG for various protection conditions

VDD

TDA7492P
R1

DIAG

Protection logic

VDD
Restart Restart

Overcurrent OV, UV, OT

protection protection

22/27 DocID15068 Rev 6

TDA7492P Package mechanical data

7 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
The TDA7492P comes in a 36-pin PowerSSO package with exposed pad down.
Figure 28 below shows the package outline and Table 9 gives the dimensions.

DocID15068 Rev 6 23/27

27
Package mechanical data TDA7492P

Figure 28. PowerSSO-36 EPD outline drawing

h x 45°

24/27 DocID15068 Rev 6

TDA7492P Package mechanical data

Table 9. PowerSSO-36 EPD dimensions

Dimensions in mm Dimensions in inches
Symbol
Min Typ Max Min Typ Max

A 2.15 - 2.45 0.085 - 0.096

A2 2.15 - 2.35 0.085 - 0.093
a1 0 - 0.10 0 - 0.004
b 0.18 - 0.36 0.007 - 0.014
c 0.23 - 0.32 0.009 - 0.013
D 10.10 - 10.50 0.398 - 0.413
E 7.40 - 7.60 0.291 - 0.299
e - 0.5 - - 0.020 -
e3 - 8.5 - - 0.335 -
F - 2.3 - - 0.091 -
G - - 0.10 - - 0.004
H 10.10 - 10.50 0.398 - 0.413
h - - 0.40 - - 0.016
k 0 - 8 degrees 0 - 8 degrees
L 0.60 - 1.00 0.024 - 0.039
M - 4.30 - - 0.169 -
N - - 10 degrees - - 10 degrees
O - 1.20 - - 0.047 -
Q - 0.80 - - 0.031 -
S - 2.90 - - 0.114 -
T - 3.65 - - 0.144 -
U - 1.00 - - 0.039 -
X 4.10 - 4.70 0.161 - 0.185
Y 4.90 - 7.10 0.193 - 0.280

DocID15068 Rev 6 25/27

27
Revision history TDA7492P

8 Revision history

Table 10. Document revision history

Date Revision Changes

30-Sep-2008 1 Initial release.

Updated supply operating range to 8 V - 26 V on page 1
Changed C1 to C8 at beginning of Section 3.3 on page 8
Updated Table 5: Electrical specifications on page 8 for VCC min, VOS
min/max and added new parameter VUV
Updated Figure 20: Applications circuit for class-D amplifier on
page 17
11-May-2009 2
Inserted brackets in equation in Table 5 footnote and in
Section 6.4.1 on page 20
Updated values in UVP and OCP in Section 6.6 on page 22
Updated voltage to “<26 V” in Section 6.7 on page 22
Updated max dimensions for A and A2 in Table 9: PowerSSO-36 EPD
dimensions on page 25.
Updated value for GV at head of Section 3.3 on page 8
02-Sep-2009 3
Updated package Y (Min) dimension in Table 9 on page 25.
Updated operating temperature range
19-Jan-2011 4
Updated datasheet presentation.
12-Sep-2011 5 Updated OUTNA in Table 2: Pin description list
20-Feb-2014 6 Updated order code Table 1 on page 1

26/27 DocID15068 Rev 6

TDA7492P

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