ECE 428 Programmable ASIC Design

Fundamentals of Digital IC Design

Haibo Wang
ECE Department
Southern Illinois University
Carbondale, IL 62901

2-1
 Semiconductor Devices
‰ Bipolar Transistors: c b e

P N
N NPN transistor

‰ Junction Field Effective Transistor (JFET):

S D
P
N-channel FET N
P

‰ Metal-Oxide-Semiconductor (MOS) Devices: G

G
S Metal D
B
P+ N+ N+
NMOS Device P-
2-2
 CMOS Process
‰ Cross-Section Diagram

‰ Layout

Source from http://infopad.eecs.berkeley.edu/~icdesign

For a great tour of IC fabrication process, see
http://www.fullman.com/semiconductors/semiconductors.html

2-3
 Digital Signals and Basic Logic Gates
‰ Digital signal values
True 1 High Voltage (e.g. 5V)12
False 0 Low Voltage (e.g. 0V)

‰ Basic logic gates

X Y
1. Inverter X Y=X
1 0 Truth Table of
0 1 an inverter

X Y Z
2. AND X
Y Z=X•Y 0 0 0
0 1 0 Truth Table of
1 0 0 an AND gate
1 1 1
3. NAND X
Z=X•Y
Y
2-4
 Basic Logic Gates
X Y Z
4. OR X
Y Z=X+Y 0 0 0
0 1 1
1 0 1 Truth Table of
1 1 1 an OR gate
X
5. NOR Y Z=X+Y

X Y Z
4. XOR X
Y Z = X•Y +X•Y 0 0 0
0 1 1
Z=X+Y Truth Table of
1 0 1
1 1 0 an XOR gate
X
5. XNOR Z = X•Y +X•Y
Y
Z=X+Y

2-5
 Basic Logic Gates
‰ Tri-state Buffer
C I O
I O Truth table of a
1 X Z
tri-state buffer
0 0 0
C 0 1 1

I1

O X Y
I2

S C
Mux
2-to-1 multiplexer Bi-direction circuit

2-6
 Gate Delay Definition

Vin Vout

50% 50%

Vin tpHL tpLH

Vout
90%
90%
50% 50%

10% 10%
tf tr
2-7
 Sequential Logic Circuits
‰ D latch
D
D Q
CLK
CLK Q
Q

¾ When CLK=1, Q always reflects the signal value at input D

¾ If CLK=0, Q stores the last D value which appears at D just before CLK falls to 0

‰ D Flip-flop
D
D Q
Q CLK
CLK
Q
¾ D flip-flop will not change its output values unless there is a negative edge event
at CLK input (CLK switches from logic 1 to 0).
¾ When a negative edge appears at CLK input , D Flip-flop updates Q to the current D value
2-8
 Timing Parameters for D Flip-Flops
‰ Clock-Q Delay
D

D Q CLK
CLK
Q
DFF
Clock-Q delay

‰ Setup Time ‰ Hold time

D D

CLK CLK
Setup time Hold time

2-9
 Decoder Circuits
‰ A decoder circuit uniquely selects one of its outputs according to its
input signals

•••
N inputs 2N outputs

•••
Decoder

‰ 2-to-4 decoder implementation

X Z1 (00)
X Y Z1 Z2 Z3 Z4
Z2 (01)
0 0 1 0 0 0
0 1 0 1 0 0 Y Z3 (10)
1 0 0 0 1 0
1 1 0 0 0 1
Z4 (11)

2-10
 Decoder Circuit
‰ 3-to-8 decoder implementation
¾ Assume that we have 2-to-4 decoders available as standard components
¾ When CS is low (0), all the outputs of the decoder are X
low (0)
Y

CS
X X
2-to-4 decoder
Y Y

CS
Z

X
Y

CS

2-11
 Sequential Logic Circuits
‰ Counter
Clk C B A
¾ Basic binary counter

A B C Init. 0 0 0
DFF DFF DFF
D Q Q Q
0 0 1
D D

CLK
Q Q Q 0 1 0
0 1 1
1 0 0
¾ Synchronous counter
1 0 1
A B C
1 1 0
1 1 1
DFF DFF
D Q D Q D Q
Q Q Q

CLK
2-12
 Sequential Logic Circuits
‰ frequency divider
¾ Divide clock frequency by 4

DFF DFF
D Q D Q CLK
Q Q CLK_4
CLK
CLK_4

¾ Divide clock frequency by 3

DFF DFF
D Q D Q CLK
Q Q CLK_3
CLK_3
CLK

2-13
 Sequential Logic Circuits
‰ Register
¾ A row of storage elements (e.g. D flip-flops)
Q3 Q2 Q1 Q0
DFF DFF DFF DFF
Q[3:0]
D Q D Q D Q D Q
Q Q Q Q
Data
CLK

‰ Shift register

Q3 Q2 Q1 Q0 CLK Q3 Q2 Q1 Q0
DFF DFF DFF DFF
0 D Q D Q D Q D Q Init. 1 0 1 0
Q Q Q Q 0 1 0 1
CLK 0 0 1 0
0 0 0 1
0 0 0 0

2-14
 Major Parasitic Effects in Digital ICs
‰ Ideal Circuit
Vin
Vout
Vin Interconnect
Vout

No delay!

‰ Real Circuit

Vin
C
C Vout
Vin
C C Vout
C
C Significant delay!
2-15
 Power Consumption of CMOS Gates
‰ Dynamic Power Consumption

Id
Vin Vout

ISC

PDynamic = 0.5 • C • VDD

2
•f

‰ Short-Circuit Power Consumption

ISC PSC = ∫ I SC (t )Vdt

Vin
‰ Leakage Power Consumption

2-16
 Transistor Sizing

C C
C

Delay Power Silicon

area

Driver Size Driver Size Driver Size

2-17
 Design Constraints for Digital ICs

Vin1
Vin2 Circuit Under Vout1
Vin3
construction Vout2
CLK

‰ Delay (speed) constraints

— For example, the delay from Vin1 to Vout1 should be smaller than 10 ns; the clock
frequency should be greater 100MHz

‰ Power constraints

‰ Area constraints

2-18
How to Find Circuits Complying with Design
Constraints

Full-custom approach Standard-cell based approach

Gate-array approach
FPGA approach

1. It heavily depends on 1. These approaches heavily use

designers’ expertise. design automation techniques
2. Finding a proper circuit to search circuits complying with
implementation can be constraints.
very time consuming. 2. They are time saving approaches.
3. Very creative circuit 3. These approaches require
implementations can be pre-developed technology libraries.
achieved. 4. The quality of the final implementation
depends on algorithms and libraries
used in the search.
2-19
 Example: How to Search a Proper Circuit
Implementation in FPGA Design Flow
‰ FPGA Design Flow

Schematic HDL coding &

Capture Logic Synthesis

netlist

FPGA cell Technology mapping

library Implementation Placement & routing

Fail
Verification Timing verification

Pass
Download
Generate FPGA Bit Stream

FPGA
2-20
 Example: How to Search a Proper Circuit
Implementation in FPGA Design Flow
‰ Given Logic Function
a d
— This circuit is either from
schematic capture or from
b
logic synthesis
e
c

‰ FPGA Library Components

— The library contains five components
— Three inverters at size 1, 3, 5
— Two two-input NAND gates at size 1 and 3

‰ Design Constraints
— The maximum delay between an input and an output should not exceed 5 ns

2-21
 Example: How to Search a Proper Circuit
Implementation in FPGA Design Flow
‰ Step 1: Use the available logic gates to implement the given function.
(Technology Mapping)
INV1 NAND1
a d
b
INV2
e
c NAND2
INV3
‰ Step 2: Select proper size for each gate used in the above circuit.
(Gate Sizing) 1X 3X
— After this step, the circuit can a d
be simulated to verify that it
complies with timing constraints. b 1X 3X
— In the simulation, the parasitic
capacitance and resistance on
e
c
interconnects are estimated 1X 2-22
(Estimated wire load)
 Example: How to Search a Proper Circuit
Implementation in FPGA Design Flow
‰ Step 3: Determine where to place these gates and how to
connect them (Placement & Routing).
— Some algorithms first place the components
and then route the interconnects. INV1 NAND1

NAND2
— Some algorithms perform the placement
and routing simultaneously
INV2 INV3

¾ Steps 1, 2, and 3 are included in the implementation phase of the FPGA design Flow

‰ Step 4: Perform post-layout simulation to verify that the generated

circuit complies with timing constraints
— Since detail information of each interconnect is available, the circuit can be simulated
with accurate wire load.
— The process that writes the accurate wire load into the circuit netlist is called
back annotation 2-23
 What Information Should Be Stored in FPGA
Library
‰ Logic function
‰ Timing (delay) information
‰ Power consumption information
‰ Silicon area
‰ Layout information
‰ Placement & routing constraints
‰ ••••
‰ ••••

2-24
 Example: How to Store Delay Information
‰ Normally, the delay of gate is proportional to the load on its output

Delay

D0

Load

Delay = D0 + K*Load

So, we can store two parameters (D0 and K) for each gate to model its
delay property.

2-25
 Binary Number System

‰ Converting binary numbers to decimal numbers

Binary Decimal
1011 Æ 1*2^3 + 0*2^2 + 1*2^1 + 1*2^0 = 11
0111 Æ 0*2^3 + 1*2^2 + 1*2^1 + 1*2^0 = 7

‰ Converting binary numbers to hexadecimal numbers

1 1 1 1 0 1 0 1 1 0 1 0 0 0 1 1

F 5 A 3

2-26
 Binary Addition

¾ Example ¾ A single-bit full adder

0 1 0 1 A B

+ 1 0 0 1
Full
1 1 1 0 C_in adder C_out
S

¾ 4-bit adder
A[0] B[0] A[1] B[1] A[2] B[2] A[3] B[3]

Full Full Full Full

C_in adder adder adder adder C_out
C_0 C_1 C_2

S[0] S[1] S[2] S[3]

2-27
 Handling Negative numbers
‰ Signed magnitude Signed magnitude Decimal
0 0 0 0
0 0 1 1
¾ The left-most bit is a sign bit
0 1 0 2
0 indicates positive a number and 0 1 1 3
1 indicates negative a number 1 0 0 0
1 0 1 -1
1 1 0 -2
1 1 1 -3

‰ One’s complement 1’s complement Decimal

0 0 0 0
0 0 1 1
¾ For positive number A, it is
0 1 0 2
represented as usual binary number 0 1 1 3
1 1 1 0
¾ For negative number -A, its 1 1 0 -1
representation is obtained by flipping 1 0 1 -2
the bits of the binary representation of A 1 0 0 -3
2-28
 Handling Negative numbers
2’s complement Decimal
‰ Two’s complement
0 0 0 0
¾ For positive number A, it is the 0 0 1 1
same as the one’s complement 0 1 0 2
0 1 1 3
¾ For negative number A, add one 1 1 1 -1
1 1 0 -2
to the one’s complement
1 0 1 -3
representation 1 0 0 -4

‰ By using two’s complement number representation, minus operations

can be performed by adders
3 0 1 1 2 0 1 0
⎯ 1 + 1 1 1 ⎯ 3 + 1 0 1
2 1 0 1 0 -1 1 1 1
Overflow
Ignore 2 -1

2-29