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TPS8804
SLVSF29A – OCTOBER 2019 – REVISED MARCH 2020

TPS8804 Smoke Detector AFE

1 Features 2 Applications
1• Photo Chamber AFE • Smoke and CO detector
– Dual 8-bit programmable current LED drivers
– Temperature compensation of LED current 3 Description
The TPS8804 is a smoke detection ASIC specialized
– Ultra-low offset op-amp for photodiodes for commercial smoke detectors. The TPS8804
– Programmable and bypassable gain stage integrates all of the amplifiers and drivers required for
• Carbon Monoxide Sensor AFE a dual-wave photoelectric smoke detection and
carbon monoxide detection system. Its high flexibility
– Ultra-low offset gain stage
is ideal for smoke detection systems where precision
– Programmable gain and reference and power consumption are critical.
• Power Management
– Programmable LDO for external Device Information(1)
microcontroller PART NUMBER PACKAGE BODY SIZE (NOM)
TPS8804 TSSOP (38) 9.7 mm x 4.4 mm
• SLC interface transmitter and receiver
• Ultra-low power consumption (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• I2C serial interface
• Wide input voltage range
Simplified Application
VLINE
TPS8804
Pre-Regulator
VSLC COO
5V to 15V
VCC
CON
PLDO
COP CO
VINT Sensor

REF0P3

LEDLDO
VMCU

MCUSEL PREF
Photo
Chamber
PDP

VIN ADC AMUX Blue IR

PDN

LEDEN
GPIO PDO
GPIO
DINA

MCU SCL DINB

2
I C
CSA VLINE
SDA

CSEL CSB

GPIO MCU_TX1 SLC_TX1

MCU_RX AGND PGND DGND SLC_RX

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.5 Programming .......................................................... 30
2 Applications ........................................................... 1 8.6 Register Maps ......................................................... 30
3 Description ............................................................. 1 9 Application and Implementation ........................ 39
4 Revision History..................................................... 2 9.1 Application Information............................................ 39
9.2 Typical Application ................................................. 39
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 10 Power Supply Recommendations ..................... 44
6.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 45
6.2 ESD Ratings.............................................................. 5 11.1 Layout Guidelines ................................................. 45
6.3 Recommended Operating Conditions....................... 5 11.2 Layout Example .................................................... 45
6.4 Thermal Information .................................................. 5 12 Device and Documentation Support ................. 48
6.5 Electrical Characteristics........................................... 5 12.1 Receiving Notification of Documentation Updates 48
7 Typical Characteristics........................................ 16 12.2 Community Resources.......................................... 48
12.3 Trademarks ........................................................... 48
8 Detailed Description ............................................ 17
12.4 Electrostatic Discharge Caution ............................ 48
8.1 Overview ................................................................. 17
12.5 Glossary ................................................................ 48
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 19 13 Mechanical, Packaging, and Orderable
8.4 Device Functional Modes........................................ 29
Information ........................................................... 49

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (October 2019) to Revision A Page

• Changed document status from Advanced Information to Production Data .......................................................................... 1

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5 Pin Configuration and Functions

DCP Package
38-Pin TSSOP
Top View

RESERVE D 1 38 REF0P3
RESERVE D 2 37 PREF
RESERVE D 3 36 COP
LEDLDO 4 35 CON
AGND 5 34 COO
PDP 6 33 AMUX
PDN 7 32 DGND
PDO 8 31 LEDEN
CSA 9 30 MCU_TX1
DINA 10 29 CSEL
CSB 11 28 SDA
DINB 12 Thermal 27 SCL
MCUSE L 13 Pad 26 GPIO
SLC_TX1 14 25 MCU_RX
SLC_TX2 15 24 SLC_RX
MCU_TX2 16 23 VMCU
PGND 17 22 VINT
RESERVE D 18 21 PLDO
VSL C 19 20 VCC

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
AGND 5 I Analog ground. Connect to ground plane.
AMUX 33 O Analog multiplexer output.
CON 35 I Negative terminal of CO operational amplifier. Connect to GND if unused.
COO 34 O Output of CO operational amplifier. Connect to GND if unused.
COP 36 I Positive terminal of CO operational amplifier. Connect to GND if unused.
CSA 9 I LED driver A current sense.
CSB 11 I LED driver B current sense. Connect to GND if unused.
Device address select pin for I2C serial interface. Pull to GND for I2C address 0x3F. Pull to
CSEL 29 I
VMCU for I2C address 0x2A. Do not leave floating.
DGND 32 I Digital ground. Connect to AGND.
DINA 10 I LED driver A current sink. Connect to cathode of LED.
DINB 12 I LED driver B current sink. Connect to cathode of LED. Connect to GND if unused.
GPIO 26 I/O Multi-purpose digital input and output.
LEDEN 31 I LED driver enable. Do not leave floating while device is powered.
LEDLDO 4 O LDO output for charging LED supply capacitor. Connect to GND if unused.
MCU_RX 25 O SLC interface output for receiving data from VLINE.
MCU_TX1 30 I Primary SLC interface input for transmitting data to VLINE.
MCU_TX2 16 I Secondary SLC interface input for transmitting data to VLINE.
Default MCULDO voltage selection input. Leave floating for VMCU = 3.3 V. Tie to VINT for
MCUSEL 13 I VMCU = 2.5 V. Tie to GND for VMCU = 1.8 V. Connect to GND with 620-Ω resistor for
VMCU = 1.5 V.
PDN 7 I Photo input amplifier negative input. Connect to cathode of photodiode.
PDO 8 O Photo input amplifier output pin.
PDP 6 I Photo input amplifier positive Input. Connect to anode of photodiode.
PGND 17 I Power ground connection. Connect to AGND.

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Pin Functions (continued)

PIN
I/O DESCRIPTION
NAME NO.
PLDO 21 O Capacitor connection to PLDO regulator.
PREF 37 O Photo reference voltage and output for testing CO sensor connectivity.
REF0P3 38 O 300mV reference. Connect to GND if unused.
RESERVED 1, 2, 3, 18 N/A Connect to GND.
SCL 27 I Clock input for I2C serial interface.
SDA 28 I/O Data line for I2C serial interface.
SLC_RX 24 I SLC interface input for receiving data from VLINE.
SLC_TX1 14 O Primary SLC interface output for transmitting data to VLINE.
SLC_TX2 15 O Secondary SLC interface output for transmitting data to VLINE.
VCC 20 I Input supply pin.
VINT 22 O Capacitor connection to internal supply LDO.
VMCU 23 I/O LDO supply for external microcontroller and internal IO buffers.
VSLC 19 I SLC transmitter supply.
Thermal Pad 39 N/A Metal connection for thermal dissipation. Connect to ground plane.

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER MIN MAX UNIT
Power IO SLC_TX1, SLCTX_2, VCC, VSLC –0.3 16.5 V
Analog IO DINA, DINB, LEDLDO –0.3 12 V
VINT + 0.3 or
Analog
AMUX, CON, COO, COP, PREF, MCUSEL, PDO, REF0P3 –0.3 3.6, whichever V
connections
is lower
PLDO + 0.3 or
LDO outputs VINT, VMCU –0.3 3.6, whichever V
is lower
DINA + 0.3 or
LED current
CSA –0.3 3.6, whichever V
sense
is lower
DINB + 0.3 or
LED current
CSB –0.3 3.6, whichever V
sense
is lower
Photo amplifier
PDN, PDP –0.3 3.6 V
inputs
PLDO voltage PLDO –0.3 7.0 V
SLC receiver SLC_RX –0.3 18 V
VMCU + 0.3 or
Digital IO CSEL, GPIO, LEDEN, MCU_RX, MCU_TX1, MCU_TX2, SCL, SDA –0.3 3.6, whichever V
is lower
Max operating
ambient TA -40 125 °C
temperature
Max operating
junction TJ -40 125 °C
temperature

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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6.2 ESD Ratings

over operating free-air temperature range (unless otherwise noted)
Value UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±3000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1500
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
SLC transmitter
VSLC 4.5 15.6 V
supply
Power supply VCC 2.6 15.6 V
LED driver DINA, DINB 0 11.5 V
SLC receiver SLC_RX 0 17 V
Digital IO CSEL, GPIO, LEDEN, MCU_RX, MCU_TX1, MCU_TX2, SCL, SDA 0 VMCU V
Digital IO
VMCU 1.425 3.6 V
supply
Ambient
TA –40 85 °C
temperature
Junction
TJ –40 85 °C
temperature

6.4 Thermal Information

TPS8804
(1)
THERMAL METRIC DCP UNIT
38 PINS
RθJA Junction-to-ambient thermal resistance 29.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 20.0 °C/W
RθJB Junction-to-board thermal resistance 10.1 °C/W
ΨJT Junction-to-top characterization parameter 0.3 °C/W
ΨJB Junction-to-board characterization parameter 10.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE AND CURRENTS
Power up threshold. Note:
VPWRUP Device enters active state VCC rising 1.2 1.55 2.0 V
when MCU_PG=1.
VPWRDOWN Power down threshold VCC falling 0.932 1.15 2.0 V
VCC power up to power
VPWR, HYS 6.4 400 580 mV
down hysteresis
VCC low warning reset PLDO voltage rising 2.35 2.54 2.7 V
VVCCLOW, RISE threshold Deglitch time 110 141 172 µs
VVCCLOW, VCC low warning assert PLDO voltage falling 2.15 2.42 2.6 V
FALL threshold Deglitch time 110 141 172 µs

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
All blocks that can be
disabled are off, TJ=27C, 3.8 4.4 µA
VCC=3V, VMCU=1.8V
ISTANDBY Standby Supply Current
All blocks that can be
disabled are off, TJ=27C, 7.7 9.1 µA
VCC=9V, VMCU=3.3V
POWER LDO
VCC = 2.0 V, IPLDO = 10 mA 1.93 1.96 1.99 V
VCC = 2.0 V, IPLDO = 30 mA 1.8 1.89 1.95 V
VPLDO Output Voltage VCC = 3.3 V, IPLDO = 30 mA 3.1 3.22 3.3 V
VCC = 9 V, IPLDO = 30 mA 4.1 4.9 6.7 V
VCC = 11.5 V, IPLDO = 30 mA 4.1 5 6.7 V
PLDO capacitor required for
CPLDO 0.7 1 1.3 µF
stability
INTERNAL LDO
IVINT < 10 mA 2.25 2.3 2.35 V
Output Voltage
IVINT < 10 uA, T>80C 2.25 2.3 2.40 V
No external/internal load,
DC Output Voltage Accuacy –2 2 %
VCC = 2.6 V - 11.5 V
VCC = 2.6 V-11.5 V, IOUT =
Line Regulation –2 2 %
10 mA
VINTLDO IVINT = 0 mA - 10 mA, VCC =
Load Regulation –2 2 %
3V
IVINT stepped from 0 mA to
–8 8 %
10 mA in 1us
Transient regulation
IVINT stepped from 10 mA to
–5 5 %
0 mA in 1us
VIN = 3.0 V, IOUT = 10 mA, f =
PSRR 50 dB
60 Hz (200 mVpp)
IINTLDO, OUT Output current range 0 10 mA
IINTLDO, SC Short Circuit Current Limit 30 280 500 mA
From PLDO to VINT, IVINT =
VINTLDO, DO Dropout Voltage 52 66 mV
10 mA, PLDO = 2.2 V
Output Capacitor 0.7 1 1.3 µF
CINTLDO, OUT Ceramic
ESR of Output Capacitor 100 mΩ
MCU LDO

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IMCULDO < 30 mA, VCC > 2.2
V, VMCUSET = 00 (T < 80°C 1.425 1.5 1.575 V
for no load)
IMCULDO < 10 uA, VCC > 2.2
1.425 1.5 1.65 V
V, VMCUSET = 00, T > 80°C
IMCULDO < 30 mA, VCC > 2.6
V, VMCUSET = 01 (T < 1.71 1.8 1.89 V
80°C for no load)
IMCULDO < 10 uA, VCC > 2.6
1.71 1.8 1.98 V
V, VMCUSET = 01, T > 80°C
IMCULDO < 30 mA, VCC > 3.65
Output Voltage (1)
VMCULDO V, VMCUSET = 10 (T < 2.38 2.5 2.63 V
80°C for no load)
IMCULDO < 10 uA, VCC > 3.65
2.38 2.5 2.75 V
V, VMCUSET = 10, T > 80°C
IMCULDO < 10 mA, VCC > 3.65
V, VMCUSET = 11 (T < 3.13 3.3 3.47 V
80°C for no load)
IMCULDO < 10 uA, VCC > 4.5
3.13 3.3 3.60 V
V, VMCUSET = 11, T > 80°C
IMCULDO < 50 mA, VCC > 5.5
3.13 3.3 3.47 V
V, VMCUSET = 11
DC Output Voltage Accuracy T < 80°C –5 5 %
MCULDO power good VMCU rising 75 82 95 %
VMCULDO,PG
threshold VMCU falling 65 78 85 %
VCC > 2.2 V, VMCUSET = 00 0 30 mA
VCC > 2.6 V, VMCUSET = 01 0 30 mA
IMCULDO Output Current Range VCC > 3.65 V, VMCUSET =
0 30 mA
10
VCC > 4.5 V, VMCUSET = 11 0 50 mA
IMCULDO stepped from 0 mA
–7 7 %
to 10 mA in 1us, T < 80°C
IMCULDO stepped from 0 mA
–8 8 %
MCULDO load transient to 10 mA in 1us, T > 80°C
VMCULDO, TR
regulation IMCULDO stepped from 10 mA
–5 5 %
to 0 mA in 1us, T < 80°C
IMCULDO stepped from 10 mA
–8 8 %
to 0 mA in 1us, T > 80°C
IMCULDO, SC Short Circuit current limit 72 162 253 mA
CMCULDO = 1µF, time from
tMCULDO, PWR Power Up Time VMCU=0V to 90% of target 600 1100 µs
voltage
MCULDO power good
TMCULDO, PG 92 125 158 µs
deglitch time
MCULDO low voltage error
mask time. MCULDO_ERR is
TMCULDO, masked for
10 ms
MASK T_MCULDO,MASK after
VMCUSET or MCU_DIS is
changed.
IMCULDO, Q Quiescent Current IMCULDO = 0µA 1.54 3 µA
Output Capacitor 0.7 1 10 µF
CMCULDO Ceramic
ESR of Output Capacitor 100 mΩ

(1) MCU LDO output voltage on power-up is determined by the MCUSEL pin state.
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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Pull-down resistance to set
VMCUSET[1:0]=00 on 558 620 682 Ω
powerup
Pull-down resistance to set
VMCUSET[1:0]=01 on 0 10 Ω
MCUSEL component powerup
RMCUSEL requirements. Not tested in
production Pull-up resistance to VINT to
set VMCUSET[1:0]=10 on 0 10 Ω
powerup
Capacitance to set
VMCUSET[1:0]=11 on 300 1000 pF
powerup
PHOTO CHAMBER INPUT STAGE AMPLIFIER
PAMP_EN=1, Feedback
VPDO Output voltage range 0 0.5 V
network: 1.5M Ω, 10pF
fPDIN, BW Unity Gain Bandwidth 1 5 MHz
VPDIN, OFS Input Offset Voltage -530 240 µV
50mV applied to PDP with
1.5MΩ series resistor. 1.5MΩ
VPDO, OFS Output Offset Voltage resistor connects PDN to -10 10 mV
PDO. Voltage measured
between 50mV and PDO.
fPDIN, CHOP Chop Frequency 2 MHz
Feedback network: 1.5M Ω,
10pF. 1 nA to 10 nA applied
0 30 40 µs
Input amplifier settling time. from PDN to PDP. 0V
Time between stepping the reference
TPDIN, SET current and measuring 90% Feedback network: 1.5MΩ,
of the final value + 10% of 5pF. 1.5MΩ connected from
the initial value at PDO PDP to PREF. 1 nA to 10 nA 0 20 40 µs
applied from PDN to PDP.
PREF_SEL=1
Active current. Current does
IPDIN, ACT not include bias block or 8 175 210 µA
MHz oscillator.
PHOTO CHAMBER GAIN STAGE AMPLIFIER

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] = 4.75 4.9 5.05 V/V
00
Closed Loop Gain
Slope (VAOUT_PH2- VPDO1=10mV, VPDO2=20mV,
VAOUT_PH1)/(VSIG2-VSIG1). PREF_SEL=0, PGAIN[1:0] = 10.67 11 11.33 V/V
Apply VSIG1 from PREF to 01
PDO and measure VPDO1=10mV, VPDO2=20mV,
AOUT_PH. Apply VSIG2 from PREF_SEL=0, PGAIN[1:0] = 19.4 20 20.6 V/V
COTEST to PDO and 10
measure AOUT_PH
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] = 33.95 35 36.05 V/V
11
GPGAIN
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] = 4.61 4.75 4.89 V/V
00
Closed Loop Gain
Slope (VAOUT_PH2- VSIG1=10mV, VSIG2=20mV,
VAOUT_PH1)/(VSIG2-VSIG1). PREF_SEL=1, PGAIN[1:0] = 10.09 10.4 10.71 V/V
Apply VSIG1 from PREF to 01
PDO and measure VSIG1=10mV, VSIG2=20mV,
AOUT_PH. Apply VSIG2 from PREF_SEL=1, PGAIN[1:0] = 17.94 18.5 19.06 V/V
PREF to PDO and measure 10
AOUT_PH
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] = 31.28 32.25 33.22 V/V
11
FPGAIN, BW Unity Gain Bandwidth 1 5 8 MHz
VPGAIN, OFS Input offset Voltage -6 5 mV
Gain amplifier settling time.
Time between stepping the PGAIN[1:0]=00. PDO
TPGAIN, SET voltage and measuring 90% stepped from 3mV to 30mV. 1.8 2.522 µs
of the final value + 10% of PREF_SEL=0
the initial value at AOUT_PH
1.0 V input voltage,
Active current. Current does
IPGAIN, ACT PGAIN[1:0] = 00, PGAIN_EN 40 70 µA
not include bias block.
=1
LED LDO
LEDLDO output voltage
VLEDLDO 7.5 10 V
range
VLEDLDO,ACC LDO output accuracy I_LEDLDO = 0uA to 100uA -5 5 %
VLEDLDO, RES LED LDO output step size 0.5 V
ILEDLDO, OUT LDO output current limit 1 3 6 mA
Quiescent current. Current
ILEDLDO, Q 31 60 µA
does not include bias block.
VLEDLDO,
LED LDO dropout voltage VSLC=7V, ILEDLDO=100uA 565 1000 mV
DROP
LED DRIVER A
NPDACA, RES Resolution 8 Bits

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ = 27°C TEMPCOA[1:0] =
00, PDAC_A = 00, RCSA=1 274 299 323 mV
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
00, PDAC_A = FF, RCSA=1 567 593 619 mV
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
01, PDAC_A = 00, RCSA=1 252 277 301 mV
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
01, PDAC_A = FF, RCSA=1 546 572 597 mV
kOhms, VDINA=3V
VCSA CSA output voltage
TJ = 27°C TEMPCOA[1:0] =
10, PDAC_A = 00, RCSA=1 164 188 213 mV
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
10, PDAC_A = FF, RCSA=1 458 484 510 mV
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
11, PDAC_A = 00, RCSA=1 54 79 104 mV
kOhms, VDINA=3V
TJ = 27°C TEMPCOA[1:0] =
11, PDAC_A = FF, RCSA=1 350 376 403 mV
kOhms, VDINA=3V
DAC step size 1.18 mV
VPDACA, STEP INL -10 10 LSB
DNL -1.5 1.5 LSB
tPDACA, SET Settling Time 1 5 µs
TEMPCOA[1:0] = 00,
PDAC_A[7:0] =
0.174 0.347 0.521 mV/°C
0x00, RCSA=1 kOhms,
VDINA=3V, TJ=0°C, 50°C
TEMPCOA[1:0] = 01,
PDAC_A[7:0] =
0.208 0.416 0.624 mV/°C
0x00, RCSA=1 kOhms,
CSA temperature VDINA=3V, TJ=0°C, 50°C
KPDACA, COMP
compensation coefficient TEMPCOA[1:0] = 10,
PDAC_A[7:0] =
0.346 0.693 1.039 mV/°C
0x00, RCSA=1 kOhms,
VDINA=3V, TJ=0°C, 50°C
TEMPCOA[1:0] = 11,
PDAC_A[7:0] =
0.520 1.040 1.560 mV/°C
0x00, RCSA=1 kOhms,
VDINA=3V, TJ=0°C, 50°C
PLDO=3.6V, RCSA=820mΩ,
TEMPCOA[1:0]=11,
PDAC_A[7:0]=0x28, TJ=27°C 300 mV
(I_LED≈158mA, 0.8% temp
Dropout voltage. Voltage coefficient)
VDINA, DROP required between DINA and
CSA for current regulation. PLDO=3.6V, RCSA=820mΩ,
TEMPCOA[1:0]=01,
PDAC_A[7:0]=0x79, TJ=27°C 500 mV
(I_LED≈507mA, 0.1% temp
coefficient)
IDINA LED current 0 550 mA
LED DRIVER B
NPDACB, RES Resolution 8 Bits

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ = 27°C TEMPCOB[1:0] =
00, PDAC_B = 00, RCSB=1 271 299 327 mV
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
00, PDAC_B = FF, RCSB=1 562 594 626 mV
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
01, PDAC_B = 00, RCSB=1 250 277 305 mV
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
01, PDAC_B = FF, RCSB=1 541 572 604 mV
kOhms, VDINB=3V
VCSB CSB output voltage
TJ = 27°C TEMPCOB[1:0] =
10, PDAC_B = 00, RCSB=1 163 189 216 mV
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
10, PDAC_B = FF, RCSB=1 456 486 516 mV
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
11, PDAC_B = 00, RCSB=1 55 81 108 mV
kOhms, VDINB=3V
TJ = 27°C TEMPCOB[1:0] =
11, PDAC_B = FF, RCSB=1 350 379 408 mV
kOhms, VDINB=3V
DAC step size 1.18 mV
VPDACB, STEP INL -10 10 LSB
DNL -1.5 1.5 LSB
tPDACB, SET Settling time 1 5 µs
TEMPCOB[1:0] = 00,
PDAC[7:0] = 0x00, RCSB=1
0.174 0.347 0.521 mV/°C
kOhms, VDINB=3V, TJ=0°C,
50°C
TEMPCOB[1:0] = 01,
PDAC[7:0] = 0x00, RCSB=1
0.208 0.416 0.624 mV/°C
kOhms, VDINB=3V, TJ=0°C,
CSB temperature 50°C
KPDACB, COMP
compensation coefficient TEMPCOB[1:0] = 10,
PDAC[7:0] = 0x00, RCSB=1
0.346 0.693 1.039 mV/°C
kOhms, VDINB=3V, TJ=0°C,
50°C
TEMPCOB[1:0] = 11,
PDAC[7:0] = 0x00, RCSB=1
0.520 1.040 1.560 mV/°C
kOhms, VDINB=3V, TJ=0°C,
50°C
PLDO=3.6V, RCSA=820mΩ,
TEMPCOB[1:0]=11,
PDAC[7:0]=0x28, TJ=27°C 300 mV
(I_LED≈158mA, 0.8% temp
Dropout voltage. Voltage coefficient)
VDINB, DROP required between DINB and
CSB for current regulation. PLDO=3.6V, RCSA=820mΩ,
TEMPCOB[1:0]=01,
PDAC[7:0]=0x79, TJ=27°C 500 mV
(I_LED≈507mA, 0.1% temp
coefficient)
IDINB LED current 0 550 mA
CO TRANSIMPEDANCE AMPLIFIER
RI, CO CO input resistance COSWRI = 1 0.7 1 1.5 kΩ

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COGAIN[1:0] = 00,
770 1100 1430 kΩ
COSWRG = 1
COGAIN[1:0] = 01,
210 300 390 kΩ
COSWRG = 1
RF, CO CO feedback resistance
COGAIN[1:0] = 10,
350 500 650 kΩ
COSWRG = 1
COGAIN[1:0] = 11,
560 800 1040 kΩ
COSWRG = 1
CO amplifier input voltage
VIN, COP 0 0.6 V
(COP pin)
CO amplifier input voltage
VIN, CON 0 0.6 V
(CON pin)
CO amplifier input offset
VOFFS, CO -130 300 µV
voltage
CO amplifier output voltage
VOUT, COO 0.1 2 V
(COO pin)
CO amplifier quiescent
ICO, Q 1 2.1 µA
current
CO amplifier unity gain
fCO, BW 5 12 20 kHz
bandwidth
fCO, CHOP CO amplifier chop frequency 3.8 4 4.2 kHz
CO amplifier output
RCOO COSWRO = 1 70 95 130 kΩ
resistance
COSWREF=1, COREF[1:0] =
0.89 1.14 1.47
00, TJ = 27°C
COSWREF=1, COREF[1:0] =
0.86 1.14 1.66
00, TJ = -40°C to 85°C
COSWREF=1, COREF[1:0] =
1.75 2.23 2.7
01, TJ = 27°C
COSWREF=1, COREF[1:0] =
1.7 2.23 2.95
CO amplifier reference 01, TJ = -40°C to 85°C
VCOPREF mV
voltage COSWREF=1, COREF[1:0] =
2.6 3.23 4
10, TJ = 27°C
COSWREF=1, COREF[1:0] =
2.55 3.23 4.24
10, TJ = -40°C to 85°C
COSWREF=1, COREF[1:0] =
3.45 4.43 5.38
11, TJ = 27°C
COSWREF=1, COREF[1:0] =
3.4 4.43 5.48
11, TJ = -40°C to 85°C
COTEST pull up FET
RCOTEST, PU 0.36 0.76 1.1 kΩ
resistance
COTEST pull-down FET
RCOTEST, PD 0.25 0.37 0.82 kΩ
resistance
SLC INTERFACE
SLCRX_EN=1,
0 0 0.065
SLCRX_DEG[1:0]=00
SLCRX_EN=1,
0.090 0.125 0.160
SLCRX_DEG[1:0]=01
tSLCRX, DEG SLC receiver deglitch time ms
SLCRX_EN=1,
0.9 1 1.1
SLCRX_DEG[1:0]=10
SLCRX_EN=1,
19.8 20 20.2
SLCRX_DEG[1:0]=11
ISLCRX, Q SLC receiver standby current SLCRX_EN = 1 0.25 0.5 uA

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SLC receiver input high SLCRX_HYS=0 1.3 2.0 2.7 V
VSLCRX,IHI
threshold voltage SLCRX_HYS=1 1.3 2.0 2.7 V
SLC receiver input low SLCRX_HYS=0 0.5 0.8 1.1 V
VSLCRX,ILO
threshold voltage SLCRX_HYS=1 1.2 1.8 2.7 V
SLC receiver input SLCRX_HYS=0 0.7 1.2 1.7 V
VSLCRX,HYS
hysteresis SLCRX_HYS=1 0.01 0.2 0.3 V
SLC receiver input pulldown SLCRX_PD=1 65 107 165 kΩ
RSLCRX,PD
resistance SLCRX_PD=0 3.5 41 56 MΩ
SLC transmitter output high VSLC=11.5V,
VSLCTXx,OH 11.0 11.3 11.5 V
voltage ISLC_TXx=−16mA
SLC transmitter output low
VSLCTXx,OL VSLC=11.5V, ISLC_TXx=16mA 0 0.1 0.5 V
voltage
ANALOG MULTIPLEXER
Multiplexer buffer input signal
VMUX AMUX_BYP=0 0.05 2 V
voltage range
GMUX, GAIN Multiplexer bufffer output gain AMUX_BYP=0 0.99 1 1.01 V/V
Multiplexer buffer offset
VMUX, OFFS AMUX_BYP=0 -8 8 mV
voltage
AMUX_BYP=0, AMUX_SEL
stepped from 000 to 011 with
Multiplexer buffer enable
tMUX, EN PDO=2V, PAMP_EN=0. 0 10 15 us
settling time
Time until AMUX reaches
99% of its final value
AMUX_BYP=0,
AMUX_SEL=011, PDO
Multiplexer buffer input step stepped from 50mV to 2V,
tMUX, STEP 0 10 15 us
settling time PAMP_EN=0. Time until
AMUX reaches 99% of its
final value
fMUX, BW Multiplexer bandwidth AMUX_BYP=0 0.5 1 25 MHz
IMUX, OUT Multiplexer output current AMUX_BYP=0 –10 10 uA
Multiplexer quiescent
IMUX, Q current. Current does not AMUX_BYP=0 8.3 50 uA
include bias block.
Multiplexer buffer output
CMUX AMUX_BYP=0 150 1000 pF
capacitor required for stability
OSCILLATOR, REFERENCE SYSTEM
Oscillator frequency 8 MHz
fOSC8
Frequency accuracy TA = -10°C to 70°C –3 3 %
Low-power Oscillator
32 kHz
fOSC32 frequency
Frequency accuracy TA = -10°C to 70°C –3 3 %
TTIMEOUT Error timeout time 0.9 1 1.1 s
VCC current difference
REF0P3 buffer quiescent
IREF0P3, Q between REF0P3_EN=0 and 0.38 0.76 µA
current
REF0P3=1. IREF0P3=0 µA
REF0P3 output capacitor
CREF0P3 0.7 1 1.5 nF
required for stability
From REF0P3 enabled to
TREF0P3, SET REF0P3 settling time 99% of final output voltage. 1 1.8 ms
CREF0P3=1nF, IREF0P3=0 µA
IREF0P3 = 10 µA 270 300 330 mV
VREF0P3, OUT REF0P3 output voltage
IREF0P3 = -25 µA 270 300 330 mV

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC_LOW monitor quiescent
IVCCLOW,Q 0.9 2 uA
current
IO BUFFERS
LEDEN, CSEL, MCU_TX1,
VIO, ILO IO buffer input low threshold 0.3×VMCU 0.7× VMCU V
MCU_TX2, GPIO
LEDEN, CSEL, MCU_TX1,
VIO, IHI IO buffer input high threshold 0.3×VMCU 0.7× VMCU V
MCU_TX2, GPIO
LEDEN 100 nA
IO buffer input leakage
IIO, LEAK MCU_TX1 100 nA
current
CSEL 100 nA
MCU_RX, GPIO. IIO = 3 mA,
0 0.19 0.6 V
VMCU = 1.8 V
VIO, OL IO buffer output low-level
MCU_RX, GPIO. IIO = 1 mA,
0 0.20 0.6 V
VMCU = 1.5 V
MCU_RX, GPIO. IIO = -3 mA,
IO buffer output high-level. 0 0.30 0.6 V
VMCU = 1.8 V
VIO, OH Spec is the voltage drop from
VMCU (i.e. VMCU - VOH) MCU_RX, GPIO. IIO = -1 mA,
0 0.37 0.6 V
VMCU = 1.5 V
CIN, IO Input capacitance LEDEN, CSEL 2 10 pF
CIN, IO Input capacitance MCU_TX1, MCU_TX2 2 10 pF
CIN, IO Pin capacitance MCU_RX, GPIO 2 10 pF
RIO,PD IO pulldown resistor MCU_RX, GPIO 0.8 10 50 MΩ
THERMAL WARNING
TWARNING Thermal trip point 110 C
THERMAL SHUTDOWN
Thermal trip point 125
TSHTDWN C
Thermal hysteresis 5 15 20
Thermal error mask time.
OTS_ERR is masked for
tOTS,MASK tOTS,MASK after device fully 300 350 us
powers up or OTS_EN set to
1
I2C IO
VI2C,IL Low-level input voltage -0.5 0.3 × VMCU V
VI2C,IH High-level input voltage 0.7 × VMCU V
Hysteresis of Schmitt trigger
VI2C,HYS 0.05 × VMCU V
inputs
3 mA sink current; VMCU
0 0.4 V
>2V
VI2C,OL Low-level output voltage
2 mA sink current; VMCU
0 0.2 × VMCU V
< 2V
VOL = 0.4 V 2.5 mA
II2C,OL Low-level output current
VOL = 0.6 V 4 mA
II2C,IN Input current to each I/O pin 0.1VMCU < VI < 0.9VMCUmax -10 10 µA
CI2C,IN Capacitance for each I/O pin 10 pF
From VIHmin to VILmax,
250 ns
Standard-Mode
tI2C,OF Output fall time
From VIHmin to VILmax, Fast-
250 ns
Mode
Pulse width of spikes that
tI2C,SP must be suppressed by the 0 50 ns
input filter

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I2C BUS LINES
SCL clock frequency,
0 100 kHz
Standard-Mode
fSCL
SCL clock frequency Fast-
0 400 kHz
Mode
hold time (repeated) START After this period, the first
4 µs
condition, Standard-Mode clock pulse is generated.
tHD;STA
hold time (repeated) START After this period, the first
0.6 µs
condition, Fast-Mode clock pulse is generated.
LOW period of the SCL
4.7 µs
clock, Standard-Mode
tSCL,LOW
LOW period of the SCL
1.3 µs
clock, Fast-Mode
HIGH period of the SCL
4 µs
clock, Standard-Mode
tSCL,HIGH
HIGH period of the SCL
0.6 µs
clock, Fast-Mode
set-up time for a repeated
START condition, Standard- 4.7 µs
tSU;STA Mode
set-up time for a repeated
0.6 µs
START condition, Fast-Mode
tHD;DAT data hold time, Standard- CBUS compatible masters 5 µs
tHD;DAT Mode I2C-bus devices 0 µs
tHD;DAT CBUS compatible masters 0 µs
data hold time, Fast-Mode
tHD;DAT I2C-bus devices 0 µs
data set-up time, Standard-
250 ns
tSU;DAT Mode
data set-up time, Fast-Mode 100 ns
rise time of both SDA and
1000 ns
SCL signals, Standard-Mode
tI2C,RISE
rise time of both SDA and
20 300 ns
SCL signals, Fast-Mode
fall time of both SDA and
300 ns
SCL signals, Standard-Mode
tI2C,FALL
fall time of both SDA and 20 × (VMCU /
300 ns
SCL signals, Fast-Mode 5.5 V)
set-up time for STOP
4 µs
condition, Standard-Mode
tSU;STO
set-up time for STOP
0.6 µs
condition, Fast-Mode
bus free time between a
STOP and START condition, 4.7 µs
Standard-Mode
tBUF
bus free time between a
STOP and START condition, 1.3 µs
Fast-Mode
data valid time, Standard-
3.45 µs
tVD;DAT Mode
data valid time, Fast-Mode 0.9 µs
data valid acknowledge time,
3.45 µs
Standard-Mode
tVD;ACK
data valid acknowledge time,
0.9 µs
Fast-Mode

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
capacitive load for each bus
400 pF
line, Standard-Mode
CBUS
capacitive load for each bus
250 pF
line, Fast-Mode
noise margin at the LOW for each connected device
VNL 0.1 × VMCU V
level (including hysteresis)
noise margin at the HIGH for each connected device
VNH 0.2 × VMCU V
level (including hysteresis)

7 Typical Characteristics
TA = 27°C, VCC = 3.65 V

40 35
32
35 30

26
30
25
22
25
20
Counts
Counts

20
16 16 15
15
13
10
10
10
7

5 5 5
5
1 1 1 1 1 1
0 0
60

61

62

63

64

65

66

67
162

164

166

168

170

172

174

176

178

180

182

Current (µA) Current (µA)

µ = 175.41 µA σ = 3.25 µA N = 99 Units µ = 63.44 µA σ = 1.13 µA N = 99 Units

Figure 1. Oscillator Current Figure 2. Bias Block Current

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8 Detailed Description

8.1 Overview
The TPS8804 is a smoke alarm ASIC for photoelectric smoke detection and carbon monoxide (CO) detection.
Designed to be an all-in-one smoke detector solution, the TPS8804 integrates an analog supply LDO, digital
supply LDO, photoelectric chamber analog front end (AFE), carbon monoxide sensor AFE, SLC interface driver,
analog multiplexer, and digital core. The two LED drivers have highly configurable temperature compensation to
support IR and blue LEDs over a wide range of currents. The wide bandwidth of the photo-amplifier saves power
due to reduced LED on-time. The CO amplifier has integrated gain resistors. The SLC interface driver connects
to the two-wire power line, driving it low and sensing when the line has been pulled low. Each block is highly
configurable with the digital core I2C interface, supporting on-the-fly adjustment of amplifier gains, regulator
voltages, and driver currents. Configurable status and interrupt signal registers alert the MCU of fault conditions
such as under-voltage, over-temperature, and SLC power alerts.

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8.2 Functional Block Diagram

VCC VSL C
Power LDO
MCU_TX1
VCCLOW MCU_TX2
PLDO Under-Voltage SLCTX_EN SLC
Monitor Transmitter SLC_TX1

SLC_TX2

VINT Inte rnal LDO To Digi tal Core PGND

2.3V

VMCU MCU LDO LED Dr ive r A DINA

1.5V to 3.3V
Temperature
MCUSE L Compensated +
DAC
±
CSA
SLC_RX PDAC_A
VINT
SLC Re ce iver
MCU_RX

LED Dr ive r B DINB

SCL Temperature
SDA VMCU Compensated +
I2C Interface DAC
CSEL ±
CSB
PDAC_B

GPIO COTEST_EN
VINT Pho to Reference PREF
Digital Cor e PREF_SEL
LEDEN and CO Te st

DGND
Pho to Amplifier

AMUX_SEL

AMUX_BYP
AOUT_PH

AMUX PDO
AMUX
COO ±

+ PDO

± PDN
COO CO Amplifier
+ PDP
CON ±

COP +

VSL C

REF0P3 300mV REF0P3_EN LEDLDO_EN LEDLDO

LED LDO
Reference
AGND

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8.3 Feature Description

8.3.1 System Power-up

VCC<VPWRD OWN
Shu tdo wn Acti ve
All blocks configurab le

VCC>VPWRU P

INTLDO enab led

Wait 6 ms
Registe rs load ed

Wait 2ms
Set VMCUSE T[0:1] based MCU_PG=1
on MCUSE L p in
Ena ble MCU LDO
Wait for MCU_PG=1

Power Up

Figure 3. Power-up State Diagram

The TPS8804 can power-up from a DC power supply above 3.6 V connected to the VCC pin. When the VCC
voltage exceeds the VPWRUP threshold, the TPS8804 initializes for 6 ms. After the initialization, the MCUSEL pin
is sensed for 2 ms to determine the MCULDO voltage and program the VMCUSET register. Table 1 indicates the
VMCU setting for each MCUSEL configuration. The MCULDO is enabled and the system waits for VMCU to
reach its power-good threshold (typically 85% of its target voltage). It is only after VMCU reaches its power-good
threshold that I2C communication is allowed with the TPS8804. This sequence of events is outlined in Figure 3.

Table 1. VMCU Power-up Voltage

MCUSEL Connection VMCU (V)
620-Ω to GND 1.5
Short to GND 1.8
Short to VINT 2.5
330-pF to GND 3.3

8.3.2 LDO Regulators

8.3.2.1 Power LDO Regulator

The power LDO is a voltage clamp that supplies many of the internal blocks in the TPS8804, including the
internal LDO and MCU LDO. Because the power LDO is designed to clamp the VCC voltage, it is not precise
and varies with VCC voltage and load. The power LDO shorts VCC and PLDO when the VCC voltage is below
approximately 5 V, and regulates VCC when VCC is above approximately 5 V. The power LDO has a dropout
voltage of approximately 1 V when it is regulating VCC. When the power LDO transitions from shorting to
regulating, the PLDO voltage drops by approximately 1 V. Connect a 1-µF capacitor to PLDO to stabilize the
PLDO voltage.
The power LDO is designed for use by the TPS8804 device and can be used to supply external circuitry that has
a voltage limit of 7V. The power LDO can also be used to supply the IR or blue LED anode through a diode.

8.3.2.2 Internal LDO Regulator

The internal LDO (INT LDO) regulator powers the TPS8804 amplifiers and digital core with a stable 2.3 V supply.
Connect a 1-µF capacitor to VINT to stabilize the output. The INT LDO is always enabled when the TPS8804 is
powered. The INT LDO can be used to supply external circuitry. It is not recommended to power noisy or
switching loads with INT LDO, as any noise on VINT couples to the internal amplifiers and can generate noise.
The INT LDO can be used in the CO connectivity test circuitry and the photo reference circuitry.
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8.3.2.3 Microcontroller LDO Regulator

The microcontroller LDO (MCU LDO) powers the internal digital input and output buffers (IO buffers) and external
MCU that controls and programs the TPS8804. Connect a 1-µF capacitor to VMCU to stabilize the output. The
MCU LDO can be programmed to output 1.5 V, 1.8 V, 2.5 V, and 3.3 V. The default MCU LDO setting is
determined by the configuration on the MCUSEL pin (see Table 1). After the TPS8804 is powered, the MCU
LDO voltage can be changed using the VMCUSET register. The MCU LDO can also be disabled using the
MCU_DIS register.
The MCU LDO output VMCU powers the IO buffers on SCL, SDA, CSEL, GPIO, LEDEN, MCU_RX, MCU_TX1,
MCU_TX2. The IO buffers level shift signals from the digital core to a level suitable for the microcontroller and
signals from the microcontroller to a level suitable for the digital core. In general, connect VMCU to the
microcontroller supply voltage to guarantee logic level compatibility. If the MCU LDO is disabled, connect an
external supply to VMCU.
The MCU LDO has a power good signal MCU_PG that indicates whether the MCU LDO is above 85% the
regulation voltage. A 125-µs deglitch filter prevents noise from affecting the MCU_PG signal. If MCU_PG is low
after 10 ms of changing the MCU LDO voltage or enabling the MCU LDO, the MCU_ERR flag is set high. If the
MCU_ERR flag is high and MCUERR_DIS is low, the MCU LDO fault state is entered. See MCU LDO Fault
section for more information.

8.3.3 Photo Chamber AFE

PDO
To A MUX

10 pF 1.5 M
PDN
VINT
VINT ±
+ PAMP_EN
+
To A MUX PGA IN_EN PDP
Pho tod iode
±

PGA IN[1:0]
10 pF 1.5 M
Pho to Reference

5mV
1
+
±

Conne ct if
+ PGA IN set to
50mV
0 ± 01, 10, or 11
PREF_SEL
VINT

PGA IN_EN 470 k

PAMP_EN
PREF
To CO Amp
Test

Figure 4. Photo Amplifier Circuit

The TPS8804 photo amplifier connects to a photoelectric chamber photodiode and has two stages—an input
stage and gain stage. When the photoelectric chamber LED is enabled, light scatters off smoke particles in the
chamber into the photodiode, producing a signal proportional to the smoke concentration. The output of each
photo amplifier stage is connected to the AMUX for ADC reading. This configuration provides high bandwidth and
dynamic range for the photodiode signal chain as the gain stage is on-the-fly adjustable.

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8.3.3.1 Photo Input Amplifier

The input stage is a wide-bandwidth, low-offset op-amp designed for amplifying photodiode currents. In Figure 4,
negative feedback causes the photodiode to conduct with zero voltage bias. The photo-current flows through
resistors connected from PDP to a reference (GND or PREF) and PDN to PDO. These two resistors determine
the gain of the input stage. The same value must be used for these two resistors because PDP and PDN
leakage is amplified by these resistors. Capacitors installed in parallel with the resistors compensate the op-amp
feedback loop for optimal response. The optimal compensation capacitance depends on the photodiode's
capacitance. The compensation capacitance should be adjusted to minimize settling time without having
overshoot on the output of the amplifier. Overshoot adds unnecessary noise in the output. The input stage
outputs through the PDO pin, which is internally connected to the integrated photo gain stage and AMUX.
The input stage has the option of being referenced to GND or PREF. PREF is a reference that is normally pulled
to VINT and is set to 50 mV when PREF_SEL = 1 and either PAMP_EN = 1 or PGAIN_EN = 1. The 50 mV
reference keeps the input amplifier in a linear operating region when no signal is applied, improving the speed
and zero-current sensitivity of the amplifier. It is generally recommended to set PREF_SEL=1 and connect the
external gain resistor and compensation capacitor to PREF. Connect a 100-pF filtering capacitor from PREF to
GND to reduce high frequency noise on PREF.
When measuring the photo amplifier output, it is recommended to take multiple ADC samples. Averaging ADC
samples approximately reduces the noise by the square root of the amount of samples. The power consumed in
a photoelectric smoke measurement is dominated by the LED power consumption, which is proportional to the
LED on-time multiplied by the LED current. To maximize the signal-to-noise ratio for a given power level, set the
LED pulse length to approximately twice the photo amplifier rise time and take multiple ADC samples while the
output is stabilized.

8.3.3.2 Photo Gain Amplifier

The high-bandwidth, low noise photo gain amplifier connects to the output of the photo input stage to further
amplify the photodiode signal. The gain amplifier is adjustable on-the-fly using the I2C interface. The gain
amplifier has four settings:
• 5x (4.75x if PREF_SEL=1)
• 11x (10.4x if PREF_SEL=1)
• 20x (18.5x if PREF_SEL=1)
• 35x (32.3x if PREF_SEL=1)
The gain stage has the option of being referenced to GND or PREF with the PREF_SEL bit. When
PREF_SEL=1, a 5 mV reference offset counteracts the gain stage's input offset voltage to keep the gain stage
output above 50 mV. The 5 mV reference offset is amplified by the gain stage, causing the output to change
when the gain is changed, even when there is zero photo-current. It is recommended to connect a 470 kΩ
resistor from PREF to VINT if the gain is set to 11x, 20x, or 35x. This resistor changes the PREF voltage to 70
mV and prevents the output from dropping below 50 mV in worst-case conditions. Referencing the gain stage to
PREF causes the 50 mV reference to change with signal level due to the finite impedance of the reference.
Because the reference is changing with the signal level, the gain is slightly less with PREF_SEL=1.

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8.3.4 LED Driver

VSL C

LEDLDO VCC<11.5V VCC>11.5V

LEDLDO_EN
VCC LEDLDO
LED LDO

LEDLDO[0:2]
1k

DINA

PLDO Blue/IR
TEMPCOA[1:0] LED
LED
+
PDAC_A[7:0] DAC 100 F
±
GPIO[0:2] CSA

To MCU GPIO GPIO PGND

Log ic
VCC<11.5V VCC>11.5V

To MCU LEDEN VCC LEDLDO

LEDPIN_EN
LEDSE L=0 1k

DINB

PLDO Blue/IR
TEMPCOB[1:0] LED
LED
+
PDAC_B[7:0] DAC 100 F
±
CSB

PGND

Figure 5. LED Driver Circuit

8.3.4.1 LED Current Sink

The two LED drivers are current regulated, temperature compensated, and adjustable with an 8-bit DAC. When
the LED driver is enabled, the CSA voltage is regulated, and the current through the CSA resistor also flows
through the LED and the DINA pin. A current sense resistor connects to the CSA pin. The LED driver is enabled
with the LEDEN pin and LEDPIN_EN bit. Both the pin and bit must be high for the LED driver to operate. The
LEDSEL bit switches which driver the LEDEN signal connects to. The GPIO pin can be configured to enable
either LED driver.
The LED driver is temperature compensated to account for reduced LED intensity with increasing temperature.
Four temperature compensation settings are available to support a variety of IR and blue LEDs. Temperature
compensation is implemented by varying the CSA regulated voltage with temperature, thus the temperature
compensation also depends on the CSA resistor. Each temperature compensation setting has a different DAC
output at room temperature. To achieve a specific temperature compensation and current, the PDAC, TEMPCO,
and CSA resistor must all be adjusted according to the LED Driver Component Selection procedure.

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The two LED drivers are interchangeable and support both IR and blue LEDs. The only difference between the
two LED drivers is a code CSA_BIN available to improve the LED A driver current accuracy for IR LEDs.
CSA_BIN in register 0x00 categorizes CSA voltage for each unit as close to the minimum, below average, above
average, or close to the maximum (see Register Maps). Use CSA_BIN to adjust the DAC and compensate for
the variation on the LED A driver's current. After adjusting the DAC, the effective variation is reduced by a factor
of 4 for the TEMPCOA = 11, PDAC_A = 00 setting. IR LEDs typically require the TEMPCOA = 11 temperature
compensation setting. Therefore, use the LED driver A for powering IR LEDs. If better accuracy is required,
calibrate the LED driver current by connecting the CSA or CSB pin to the microcontroller ADC port, measuring
the CSA or CSB voltage, and adjusting PDAC_A or PDAC_B until the required current is achieved.

Ensure that the LED current remains below 550 mA, the pulse width remains below 1 ms, and the duty cycle
remains below 1%. There is no protection to prevent operation outside these conditions. Ensure the PDAC and
TEMPCO registers are programmed before enabling the LED driver.

8.3.4.2 LED Voltage Supply

Enough voltage must be provided to the LED such that the DINA voltage is at least the dropout voltage
(VDINA,DROP) above the CSA voltage while the LED driver is enabled. Ensure the DINA voltage does not exceed
11.5 V. Because of the high LED drive currents, a large capacitor connected to the LED anode is required to
provide pulsed power to the LED. Any of the internal regulators (PLDO, LEDLDO) or external supply (VDC)
meeting the voltage requirements can be used to charge the LED capacitor. Connect the LED anode to LEDLDO
when VCC > 11.5 V.
The LED LDO clamps the VSLC voltage and blocks reverse current with an integrated diode. It is current limited
to prevent inrush current caused by charging the large capacitor. The regulation voltage is adjustable in the
LEDLDO register. The LED LDO may be operated with VSLC below the regulation voltage. In this case, the
LEDLDO voltage stabilizes to VSLC minus a diode voltage drop.
The LED driver current and rise time can vary by a few millivolts and microseconds across the LED anode supply
and VCC voltages. It is recommended to use a consistent LED anode voltage whenever the LED driver is
enabled.

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8.3.5 Carbon Monoxide Sensor AFE

To A MUX
COSWRO=1

RO=100 k COO
CO Co nnectivity Test
COGAIN[1:0] 0.22 …F
COSWRI=1 VINT
COSWRG=1

100 k
VINT
RI=1 k CON
±
COAMP_EN Working
+ COP
CO 10 k ±
100 k
REF0P3_EN REF0P3 Sen sor 100 k To MCU G PIO
Counter
COSWREF=1
+ +
COREF[1:0] 300 mV
± ±

PREF
To P hoto A mp Reference
To P hoto
For CO Conne ctivity Te st Amp
Use in pla ce of p ull-up resistor an d VINT
pull-down FET if P RE F_SEL=0 200 k

COTEST_EN

COTEST_DIR

Figure 6. Carbon Monoxide Detection Circuit Referenced to GND

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To A MUX
COSWRO=1

RO=100 k COO
CO Co nnectivity Test
COGAIN[1:0] 0.22 …F
COSWRI=1 VINT
COSWRG=1

100 k
VINT
RI=1 k CON
±
COAMP_EN Working
+ COP
CO 10 k ±
100 k
REF0P3_EN REF0P3 Sen sor 100 k To MCU G PIO
Counter
COSWREF=0
+ +
COREF[1:0] 300 mV
± ± 1 nF

PREF
To P hoto A mp Reference
To P hoto
For CO Conne ctivity Te st Amp
Use in pla ce of p ull-up resistor an d VINT
pull-down FET if P RE F_SEL=0 200 k

COTEST_EN

COTEST_DIR

Figure 7. Carbon Monoxide Detection Circuit Referenced to 300mV

The TPS8804 CO AFE connects to an electrochemical CO sensor. The amplifier converts the microamps of
sensor current into a voltage readable by an ADC. This is achieved with a low-offset, low-power op-amp with
configurable input, gain, and output resistors.

8.3.5.1 CO Transimpedance Amplifier

The CO transimpedance amplifier is a low-offset, low-power op-amp with integrated input, gain, and output
resistors. Each of these resistors can be disconnected using the COSW register bits if using external resistors.
The input resistor limits amplifier current during a CO sensor connectivity test. The gain resistor amplifies the CO
sensor signal. Adjust the gain resistor by changing the COGAIN register bits. Use the output resistor with an
external capacitor to filter the CO amplifier output signal.
The CO amplifier has two integrated references. A programmable 1.25-mV to 5-mV reference COREF is
internally connected to the op-amp positive terminal. A 300-mV reference is connected to the REF0P3 pin. When
the millivolt reference is used, the CO sensor must be connected to GND. The millivolt reference is amplified to
offset the amplifier output above GND. When the 300 mV reference is used, the reference offsets the CO
amplifier output by 300 mV. In general, either reference can be used. The 300-mV reference offers better DC
accuracy at the cost of extra power consumption. The 300 mV reference is generated with a reference and op-
amp buffer for high precision. The REF0P3 pin must connect to a 1 nF capacitor for stability if it is enabled. The
buffer is designed to source and sink small currents as required by the CO amplifier. The 300 mV reference and
the 1.25 mV to 5mV reference cannot be enabled simultaneously.

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A resistor connected in parallel with the CO sensor prevents charge from accumulating across its terminals. The
output of the CO amplifier is connected to the COO pin for continuous monitoring and the AMUX for periodic
sampling.

8.3.5.2 CO Connectivity Test

The built-in CO connectivity test function connects to the PREF pin and is available when the photo amplifier is
not referenced to PREF. The COTEST_EN and COTEST_DIR register bits program a pull-up and pull-down
switch on PREF. A 200 kΩ pull-up resistor charges the 1 µF capacitor when the CO test is not in use. When
PREF is pulled low, charge is injected into the amplifier and the output pulse shape can be used to determine if
the sensor is connected. An external MOSFET and pull-up resistor achieves the same function as the internal
COTEST circuitry.

8.3.6 SLC Interface Transmitter and Receiver

VLINE
SLCRX_HYS
SLCRX_DEG

SLC_RX
+
SLCRX_EN

100 k
100pF

35 M
±
+
MCU_RX SLCRX_PD
To ±
MCU

Inte rrupt
STATUS_MCURX

VLINE
VSL C

From MCU_TX1 SLC_TX1 4.7 k

MCU

VLINE
SLCTX_EN VSL C

From MCU_TX2 SLC_TX2

MCU

470
External component selection depends on SLC
protocol. Example configuration is shown

External component selection depends on SLC protocol. Example configuration is shown

Figure 8. SLC Interface Circuit

In smoke detection systems where the power line carries communication signals between smoke detectors and
central fire panels, the SLC interface connects to the power line to transmit and receive data from the MCU. The
interface isolates the high voltage power line from the microcontroller, mitigating risk of damage and reducing
external component count.

8.3.6.1 SLC Transmitter

Signals are transmitted to the power line by pulling the line low with a controlled current sink. When the driver is
enabled, the microcontroller controls the SLC_TX1 and SLC_TX2 outputs by driving MCU_TX1 and MCU_TX2
high. In Figure 8, the SLC_TX2 output driver connects to an external transistor and current-limiting resistor. The
current drawn from the power line is shown in Equation 1. The SLC_TX1 output driver is able to pull the line
completely low. This configuration allows for multi-level communication.
VSLC F VBE
ISINK =
RE
(1)

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8.3.6.2 SLC Receiver

The SLC receiver transmits signals from the power line to the microcontroller. A reverse biased Zener diode level
shifts the power line. The Zener diode is selected to drop the voltage such that when VLINE is high, the SLCRX
pin is above 3 V and when VLINE is low, the SLCRX pin is below 0.5 V. The 100-pF capacitor filters voltage
spikes that may occur on VLINE. The hysteretic and deglitched comparator filters spurious noise on VLINE. The
comparator output is synchronized with the 32 kHz clock before being deglitched. The hysteresis voltage and
deglitch time are programmable with the SLCRX_HYS and SLCRX_DEG register bits. An internal pulldown
resistor biases the Zener diode to maintain the SLC_RX voltage below 17 V, the recommended maximum.

8.3.7 AMUX

AMUX_BYP
AMUX_SEL[1:0]•0

VINT Hi-Z
0
To MCU 10 k AMUX COO
ADC 1
AMUX AOUT_PH
2
1 nF PDO
3

AMUX_BYP AMUX_SEL[1:0]

Figure 9. Analog Multiplexer Circuit

The AMUX switch and buffer are used to connect the various TPS8804 amplifier outputs to a single ADC. The
unity-gain amplifier improves the drive strength and fidelity of the analog signals when connected to an ADC. A
330 pF to 1 nF capacitor must be connected to the AMUX pin to stabilize its output. The 10-kΩ resistor filters
high-frequency noise in the analog signal. Using a 10 kΩ resistor and 1 nF capacitor reduces noise levels in the
photo amplifier signal. The buffer has the option of being bypassed to remove the added offset introduced by the
unity-gain amplifier. Because the AMUX requires the bias block (see Analog Bias Block and 8 MHz Oscillator
section), bypassing the buffer does not eliminate the AMUX current consumption.

8.3.8 Analog Bias Block and 8 MHz Oscillator

A central analog bias block connects to many of the amplifiers, drivers, and regulators. This block is enabled
when any of its connected blocks are enabled. Similarly, an internal 8-MHz oscillator is enabled when the photo
input amplifier is enabled. Table 2 lists the conditions when the bias block and 8-MHz oscillator are enabled. The
bias block and 8-MHz oscillator consume current in addition to the connecting blocks whenever they are enabled.
Because the specified current consumption of each block does not include the bias block or the 8-MHz oscillator,
add the bias block and 8-MHz oscillator currents when calculating system power consumption. Typical values of
the bias block and 8-MHz oscillator current are shown in Typical Characteristics.

Table 2. Conditions for Enabling the Bias Block and 8 MHz Oscillator
BLOCK CONDITION BIAS ENABLED? 8-MHZ OSC ENABLED?
Photo input amplifier PAMP_EN = 1 Yes Yes
AMUX buffer AMUX_SEL[0:2] ≠ 000 Yes No
LED LDO LEDLDO_EN = 1 Yes No
Photo gain amplifier PGAIN_EN = 1 Yes No
LED driver LEDEN = VMCU and
Yes No
LEDPIN_EN = 1
Temperature monitor OTS_EN = 1 Yes No
SLC transmitter SLCTX_EN = 1 Yes No

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8.3.9 Interrupt Signal Alerts

VCCLOW
VCCLOWM

MCULDO_ERR
MCULDO_ERRM Inte rrupt To G PIO L ogic
Sign al

To S LC Receiver
OTS_ERR
OTS_ERRM

OTS_WRN
OTS_WRNM

Figure 10. Interrupt Signal Alert Logic

Configurable interrupt signals notify the MCU when a system anomaly occurs. The interrupt signal indicates the
STATUS1 register, which has bits that latch high when reaching various condition limits such as temperature or
voltage. Each of the bits in the STATUS1 register can be independently configured to send an interrupt signal by
setting the MASK register bit corresponding to each STATUS1 bit. The GPIO bits must be set to 0x2 to output
interrupt signals through the GPIO pin, and the STATUS_MCURX bit must be set to 1 to output interrupt signals
through the MCU_RX pin. By connecting the GPIO or MCU_RX pin to the microcontroller, the MCU can be
immediately notified when a STATUS1 bit changes instead of having to repeatedly read the STATUS1 register.
After the device sends the interrupt signal, the signal remains high until the STATUS1 register is read, at which
point the fault clears if the error condition is removed.

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8.4 Device Functional Modes

8.4.1 Fault States

Active

MCUERR_DIS=1
MCU_PG=0 afte r 10 ms
TJ>125°C afte r 300 µs
of e nabling MCU LDO or
of e nabling O TS_EN
changi ng V MCUSET

Set OTS_ERR=1 Set MCULDO_ERR=1

MCUERR_DIS=0

Ena ble tempe ratu re mo nito r

Ena ble tempe ratu re mo nito r
Disa ble amplifiers, drivers, and
Disa ble amplifiers an d d rive rs
MCU LDO

Read STATUS1 regi ster wh ile MCU_PG=1

TJ>125°C
Read STATUS1 regi ster wh ile TJ<110°C

Start 1-second timer Start 1-second timer

TJ>110°C Timeout MCU_PG=0 Timeout

Check TJ Check MCU_PG

TJ<110°C MCU_PG=1

Ena ble blocks if previou sly Ena ble blocks if previou sly
ena bled ena bled

No Was O TS entere d from MCU Yes

LDO fa ult state?

Ove r-Temperature Shutdow n MCU LDO Fault

Figure 11. Fault States Diagram

The TPS8804 has several monitors to alert the MCU when system irregularities occur. In addition to alerting the
MCU, two monitors cause the TPS8804 to enter protective fault states:
• MCULDO under-voltage
• system over-temperature
The fault states reduce risk of damage and brown-outs to the system in the event of short circuits or other power
errors.

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Device Functional Modes (continued)

8.4.1.1 MCU LDO Fault
The MCU LDO has an undervoltage monitor to notify the MCU if the LDO falls out of regulation. This monitor is
enabled any time the MCU LDO is enabled and its status is in the MCU_PG register bit. A 125-μs deglitch time
rejects load and line transient spikes that may briefly drop the MCU LDO voltage below the under-voltage
threshold. If MCU_PG is low while the MCU LDO is enabled and it has been more than 10 ms since the LDO
was enabled or changed voltage, the MCU_ERR register bit latches high. When the MCU_ERR bit is set high
and the MCUERR_DIS bit is low, the MCU LDO fault state is entered.
When the MCU LDO fault state is entered, all amplifiers and drivers are disabled. The MCU LDO remains
enabled to attempt to recover the system. The device enables the over-temperature monitor (OTS_EN) to
prevent a VMCU short circuit from overheating the TPS8804 device. If a VMCU short circuit causes the
temperature of the TPS8804 to rise, an over-temperature shutdown occurs and the MCU LDO shuts off.
There are two methods to exit the fault state. Every second in the fault state, the MCU_PG register bit is
automatically read. If high, the fault state is exited. The MCU_ERR bit remains high until the STATUS1 register is
read. Alternatively, if the STATUS1 register is read and MCU_PG is high, the fault state is exited. When the
device exits the MCU_ERR fault state, the device re-enables all blocks that were enabled before the fault state
occurred.
If an over-temperature fault occurs while in the MCU LDO fault state, the device enters the over-temperature fault
state. The over-temperature fault state disables the MCU LDO in addition to the blocks that are disabled by the
MCU LDO fault state. After the device exits the over-temperature fault state, it immediately re-enters the MCU
LDO fault state to confirm the MCU LDO status.

8.4.1.2 Over-Temperature Fault

An over-temperature shutdown (OTS) fault occurs if OTS_EN = 1 and the die temperature exceeds 125°C. The
fault is masked for 300 μs after setting OTS_EN = 1. OTS_EN must be enabled for at least 300 μs in order to
determine if the die has overheated. After the device detects an over-temperature condition, it disables all
drivers, amplifiers, and regulators and sets OTS_ERR to 1. This action prevents additional temperature stress
caused by a short circuit.
Similar to the MCU LDO fault, the device exits the OTS fault state with two methods:
• The device checks the die temperature once every second. If the temperature is below 110°C, the device
exits the fault state.
• Reading the STATUS1 register with the die temperature below 110°C exits the fault state.
When the device exits the OTS fault state, it re-enables all blocks that were enabled before the OTS fault
occurred.

8.5 Programming
The TPS8804 serial interface follows the I2C industry standard. The TPS8804 supports both standard and fast
mode, and it supports auto-increment for fast reading and writing of sequential registers. A 33 kΩ pullup resistor
connecting the SDA and SCL pins to VMCU is recommended for fast mode operation. The VMCU voltage
determines the logic level for I2C communication. The CSEL pin selects the device address. When CSEL is
pulled to GND, the device address is 0x3F. When CSEL is pulled to VMCU, the device address is 0x2A.

8.6 Register Maps

Table 3 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in
Table 3 should be considered as reserved locations and the register contents should not be modified.

Table 3. Device Registers

Offset Acronym Register Name Section
0h REVID Device Information Go
1h STATUS1 Status 1 Go
2h STATUS2 Status 2 Go

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Table 3. Device Registers (continued)

Offset Acronym Register Name Section
3h MASK Interrupt Mask Go
4h CONFIG1 Config 1 Go
5h CONFIG2 Config 2 Go
6h ENABLE1 Enable 1 Go
7h ENABLE2 Enable 2 Go
8h CONTROL Control Go
Bh GPIO_AMUX GPIO and AMUX Go
Ch COSW CO Switch Go
Dh CO CO Amplifier Go
Fh LEDLDO LED LDO Go
10h PH_CTRL Photo Amplifier Go
11h LED_DAC_A LED DAC A Go
12h LED_DAC_B LED DAC B Go

Complex bit access types are encoded to fit into small table cells. Table 4 shows the codes that are used for
access types in this section.

Table 4. Device Access Type Codes

Access Type Code Description
Read Type
R R Read
RC R Read
C to Clear
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value

8.6.1 REVID Register (Offset = 0h) [reset = 0h]

REVID is shown in Table 5.
Return to Summary Table.

Table 5. REVID Register Field Descriptions

Bit Field Type Reset Description
7-6 CSA_BIN R 0h CSA voltage bin for TEMPCOA=11, PDAC_A=00 setting
0h = CSA voltage between specified minimum and typical, closer to
minimum
1h = CSA voltage between specified minimum and typical, closer to
typical
2h = CSA voltage between specified maximum and typical, closer to
typical
3h = CSA voltage between specified maximum and typical, closer to
maximum
5-0 RESERVED R 0h Reserved

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8.6.2 STATUS1 Register (Offset = 1h) [reset = 0h]

STATUS1 is shown in Table 6.
Return to Summary Table.

Table 6. STATUS1 Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R 0h Reserved
6 VCCLOW RC 0h VCC low warning
0h = no VCCLOW error has occurred
1h = VCC below V_VCCLOW,FALL threshold and VCCLOW_DIS=1
for VCCLOW deglitch time
5 MCULDO_ERR RC 0h MCU LDO power good error
0h = no MCULDO error has occurred
1h = MCU_PG=0 and MCU_EN=1 for TMCULDO,PG.
MCULDO_ERR is masked for TMCULDO,MASK after VMCUSET or
MCU_DIS has changed
4 OTS_ERR RC 0h Thermal shutdown error
0h = no thermal shutdown error has occurred
1h = junction temperature has exceeded T_SHUTDOWN
3 OTS_WRN RC 0h Thermal warning flag
0h = no thermal warning has occurred
1h = junction temperature has exceeded T_WARNING
2-1 RESERVED R 0h Reserved
0 SLC_RX RC 0h SLC_RX status
0h = deglitched SLC_RX is low or SLCRX_EN=0
1h = deglitched SLC_RX is high and SLCRX_EN=1

8.6.3 STATUS2 Register (Offset = 2h) [reset = 0h]

STATUS2 is shown in Table 7.
Return to Summary Table.

Table 7. STATUS2 Register Field Descriptions

Bit Field Type Reset Description
7-2 RESERVED R 0h Reserved
1 MCU_PG R 0h MCU LDO power good indicator
0h = MCU LDO is below power good threshold or MCU_DIS=1
1h = MCU LDO is above power good threshold and MCU_DIS=0
0 RESERVED R 0h Reserved

8.6.4 MASK Register (Offset = 3h) [reset = 0h]

MASK is shown in Table 8.
Return to Summary Table.

Table 8. MASK Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R 0h Reserved
6 VCCLOWM R/W 0h VCC low warning interrupt mask
0h = interrupt on VCC low
1h = no interrupt on VCC low

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Table 8. MASK Register Field Descriptions (continued)

Bit Field Type Reset Description
5 MCULDO_ERRM R/W 0h MCU LDO power good error interrupt mask
0h = interrupt on MCULDO power good error
1h = no interrupt on MCULDO power good error
4 OTS_ERRM R/W 0h Thermal shutdown error interrupt mask
0h = interrupt on thermal shutdown error
1h = no interrupt on thermal shutdown error
3 OTS_WRNM R/W 0h Thermal warning flag interrupt mask
0h = interrupt on thermal warning
1h = no interrupt on thermal warning
2-1 RESERVED R 0h Reserved
0 STATUS_MCURX R/W 0h Status interrupt on the MCU_RX pin
0h = disable
1h = MCU_RX outputs high if any unmasked STATUS1 flags

8.6.5 CONFIG1 Register (Offset = 4h) [reset = 20h]

CONFIG1 is shown in Table 9.
Return to Summary Table.

Table 9. CONFIG1 Register Field Descriptions

Bit Field Type Reset Description
7-6 SLCRX_DEG R/W 0h SLC_RX deglitch control
0h = none
1h = 125us
2h = 1ms
3h = 20ms
5 SLCRX_PD R/W 1h SLC_RX pulldown resistor enable
0h = >1MOhm pulldown resistor on SLC_RX
1h = 100k pulldown resistor on SLC_RX
4-3 VMCUSET R/W 0h MCU LDO voltage. Default value is set by MCUSEL on power-up.
0h = 1.5V
1h = 1.8V
2h = 2.5V
3h = 3.3V
2-0 RESERVED R 0h Reserved

8.6.6 CONFIG2 Register (Offset = 5h) [reset = 0h]

CONFIG2 is shown in Table 10.
Return to Summary Table.

Table 10. CONFIG2 Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R 0h Reserved
5 SLCRX_HYS R/W 0h SLC receiver comparator hysteresis
0h = 1.2V hysteresis
1h = 0.1V hysteresis
4-0 RESERVED R 0h Reserved

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8.6.7 ENABLE1 Register (Offset = 6h) [reset = 0h]

ENABLE1 is shown in Table 11.
Return to Summary Table.

Table 11. ENABLE1 Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R 0h Reserved
5 SLCRX_EN R/W 0h Control of SLC receiver
0h = disable
1h = enable
4 RESERVED R 0h Reserved
3 PAMP_EN R/W 0h Photo input amplifier control
0h = amplifier disabled
1h = amplifier enabled
2 PGAIN_EN R/W 0h Photo Gain amplifier control
0h = amplifier disabled
1h = amplifier enabled
1 RESERVED R 0h Reserved
0 LEDLDO_EN R/W 0h LED LDO control
0h = disabled
1h = enabled

8.6.8 ENABLE2 Register (Offset = 7h) [reset = 0h]

ENABLE2 is shown in Table 12.
Return to Summary Table.

Table 12. ENABLE2 Register Field Descriptions

Bit Field Type Reset Description
7 LEDSEL R/W 0h LED input select
0h = LEDENA
1h = LEDENB
6-3 RESERVED R 0h Reserved
2 LEDPIN_EN R/W 0h LEDEN pin enable
0h = LEDEN pin does not enable LED block
1h = LEDEN pin enables LED block
1 SLCTX_EN R/W 0h SLC transmitter enable
0h = SLC transmitter disabled
1h = SLC transmitter enabled
0 RESERVED R 0h Reserved

8.6.9 CONTROL Register (Offset = 8h) [reset = 0h]

CONTROL is shown in Table 13.
Return to Summary Table.

Table 13. CONTROL Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R 0h Reserved
5 MCU_DIS R/W 0h MCU LDO disable
0h = MCU LDO enabled
1h = MCU LDO disabled

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Table 13. CONTROL Register Field Descriptions (continued)

Bit Field Type Reset Description
4 VCCLOW_DIS R/W 0h VCCLOW brown-out monitor disable
0h = VCCLOW monitor is enabled
1h = VCCLOW monitor is disabled
3 MCUERR_DIS R/W 0h MCULDO error mode disable
0h = in case of MCULDO error, FAULT mode is entered
1h = disable entering FAULT mode in case of MCULDO error
2 OTS_EN R/W 0h Over-temperature shutdown mode disable
0h = disable entering over-temperature FAULT mode.
1h = in case of over-temperature, FAULT mode is entered and
OTS_ERR flag is raised.
1 SOFTRESET R/W 0h Set registers to the default value
0h = do not reset registers
1h = reset all registers. SOFTRESET is reset. VMCUSET bits and
STATUS1 register is unchanged.
0 RESERVED R 0h Reserved

8.6.10 GPIO_AMUX Register (Offset = Bh) [reset = 0h]

GPIO_AMUX is shown in Table 14.
Return to Summary Table.

Table 14. GPIO_AMUX Register Field Descriptions

Bit Field Type Reset Description
7 AMUX_BYP R/W 0h Analog multiplexer bypass
0h = analog multiplexer buffer is enabled when AMUX_SEL[1:0] !=
0h
1h = analog multiplexer buffer is bypassed with a low-resistance
switch
6 RESERVED R 0h Reserved
5-4 AMUX_SEL R/W 0h Analog multiplexer input select
0h = AMUX off
1h = COO
2h = AOUT_PH
3h = PDO
3 RESERVED R 0h Reserved
2-0 GPIO_2:0 R/W 0h Multi-purpose digital input and output
0h = Hi-Z
1h = TI Reserved
2h = output low if no status errors, high if any unmasked errors
3h = TI Reserved
4h = GPIO or LEDENA enables LED A
5h = GPIO or LEDENB enables LED B
6h = TI Reserved
7h = TI Reserved

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8.6.11 COSW Register (Offset = Ch) [reset = 0h]

COSW is shown in Table 15.
Return to Summary Table.

Table 15. COSW Register Field Descriptions

Bit Field Type Reset Description
7 COSWRO R/W 0h CO amplifier output resistor (output of amplifier to COO pin) enable
0h = 0 Ohms
1h = 100 kOhms
6 COSWRG R/W 0h CO gain resistor (output of amplifier to inverting input of amplifier)
enable
0h = Hi-Z
1h = Resistance set by COGAIN register
5 COSWRI R/W 0h CO input resistor (inverting input of amplifier to CON pin) enable
0h = 0 Ohms
1h = 1 kOhms
4 COSWREF R/W 0h CO reference switch enable
0h = positive input of amplifier connected to COP
1h = positive input of amplifier connected to 1mV to 5mV COREF
3-0 RESERVED R 0h Reserved

8.6.12 CO Register (Offset = Dh) [reset = 0h]

CO is shown in Table 16.
Return to Summary Table.

Table 16. CO Register Field Descriptions

Bit Field Type Reset Description
7 REF0P3_EN R/W 0h 300mV reference enable
0h = Buffer disabled
1h = Buffer enabled
6-5 COREF R/W 0h Reference voltage for CO amplifier
0h = 1.25mV
1h = 2.5mV
2h = 3.75mV
3h = 5mV
4-3 COGAIN R/W 0h CO amplifier feedback resistance
0h = 1100 kOhm
1h = 300 kOhm
2h = 500 kOhm
3h = 800 kOhm
2 COTEST_DIR R/W 0h CO test output direction
0h = pull-down
1h = pull-up
1 COTEST_EN R/W 0h Enable COTEST output on PREF
0h = disabled
1h = enabled
0 COAMP_EN R/W 0h CO amplifier control
0h = disabled
1h = enabled

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8.6.13 LEDLDO Register (Offset = Fh) [reset = 0h]

LEDLDO is shown in Table 17.
Return to Summary Table.

Table 17. LEDLDO Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R 0h Reserved
3-1 LEDLDO R/W 0h LED LDO settings
0h = 7.5V
1h = 8.0V
2h = 8.5V
3h = 9.0V
4h = 9.5V
5h = 10V
6h = Reserved
7h = Reserved
0 RESERVED R 0h Reserved

8.6.14 PH_CTRL Register (Offset = 10h) [reset = 0h]

PH_CTRL is shown in Table 18.
Return to Summary Table.

Table 18. PH_CTRL Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R 0h Reserved
6-5 TEMPCOB R/W 0h LED B Temperature Coefficient Setting
0h = 0.347 mV/C
1h = 0.416 mV/C
2h = 0.693 mV/C
3h = 1.040 mV/C
4-3 TEMPCOA R/W 0h LED A Temperature Coefficient Setting
0h = 0.347 mV/C
1h = 0.416 mV/C
2h = 0.693 mV/C
3h = 1.040 mV/C
2 PREF_SEL R/W 0h Photo Reference setting
0h = Photo gain amplifier referenced to 0mV
1h = Photo gain amplifier and PREF pin connected to 50mV internal
reference
1-0 PGAIN R/W 0h Photo Gain setting
0h = 5
1h = 11
2h = 20
3h = 35

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8.6.15 LED_DAC_A Register (Offset = 11h) [reset = 0h]

LED_DAC_A is shown in Table 19.
Return to Summary Table.

Table 19. LED_DAC_A Register Field Descriptions

Bit Field Type Reset Description
7-0 PDAC_A R/W 0h LED DAC A setting
00h to FFh = 0mV to 300mV

8.6.16 LED_DAC_B Register (Offset = 12h) [reset = 0h]

LED_DAC_B is shown in Table 20.
Return to Summary Table.

Table 20. LED_DAC_B Register Field Descriptions

Bit Field Type Reset Description
7-0 PDAC_B R/W 0h LED DAC B setting
00h to FFh = 0mV to 300mV

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS8804 supports a variety of smoke alarm platforms, including single-wave or dual-wave photoelectric
smoke and CO detection.

9.2 Typical Application

VSL C Pre-Regula tor

VCC 0.1 …F 5V to 15V
4.7 …F VLINE

GND
PLDO PGND
1 …F
VLINE

VINT
1 …F
SLC_RX

VLINE VLINE 100pF

To MCU VMCU
1 …F SLC_TX1

MCUSE L
SLC_TX2

To MCU G PIO MCU_RX

470 470
To MCU G PIO MCU_TX1

To MCU G PIO MCU_TX2 DINA

VMCU IR LED
47 …F
33 k

33 k

0.92
CSA

To MCU I²C SCL

To MCU I²C SDA
CSEL
DINB

Blue LE D
To MCU G PIO GPIO 47 …F

6.8
To MCU G PIO LEDEN CSB

To MCU DGND
LEDLDO

10 k
To MCU A DC Port AMUX

PDO
1 nF
10 pF
1.5 M

VINT
COO PDN
100 k
CON

COP PDP Pho tod iode

100 k
100 k

To MCU CO
GPIO Sen sor 10 pF
1.5 M

VINT
REF0P3
PREF 470 k

Thermal Pad AGND RESERVE D

Figure 12. Dual-Wave Photoelectric Smoke and CO Detector

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Typical Application (continued)

9.2.1 Design Requirements
In this example, a smoke alarm requires the following:
• 100 MΩ photoamplifier transconductance with sub-nanoamp detection
• 100mA IR LED current with 1mA/°C temperature compensation
• 50mA blue LED current with 0.1mA/°C temperature compensation

9.2.2 Detailed Design Procedure

9.2.2.1 Photo Amplifier Component Selection

To meet the 100-MΩ photoamplifier transconductance requirement, set the gain stage to 35x with PGAIN = 11.
Because the application requires sub-nanoamp current detection, reference the photo amplifier to PREF and set
PREF_SEL = 1. This reference offsets the input stage output by 50 mV and offsets the gain stage output by 225
mV. Because the application uses PREF, the gain stage amplification reduces to 32.25x. Divide 100 MΩ by
32.25x to get 3.1 MΩ. The gain is distributed across two resistors, therefore use a resistor with a value of
approximately 1.55 MΩ. A 1.5-MΩ resistor is selected. The achieved transconductance is 96.8 MΩ. Use 10-pF of
compensation capacitance in parallel with the 1.5-MΩ resistors. Use an oscilloscope with averaging to verify the
photo amplifier is quickly settling but not overshooting. If the photo amplifier has overshoot, increase the
compensation capacitance. If the photo amplifier is settling slowly, decrease the compensation capacitance.

9.2.2.2 LED Driver Component Selection

The LED current depends on the TEMPCO bits, PDAC register and CSA and CSB resistors. Changing any of
these values affects the LED current and temperature compensation. The following method selects the
TEMPCO, PDAC, and CSA resistor value based on the required LED current and temperature compensation.
The 100-mA LED current and 1 mA/°C temperature compensation is used as an example for LED A. Repeat the
process for LED B.
1. Determine the room temperature current and temperature compensation required by the application.
– 100mA and 1mA/°C is required by the design.
2. Calculate the compensation in percentage per degree by dividing the compensation coefficient by the current
and multiplying by 100.
– 1mA/°C divided by 100mA is 1%/°C.
3. Use Table 21 or Table 22 to select a TEMPCO setting which contains the required compensation. If the
required compensation is in two ranges, use the range with a higher TEMPCO setting. If the required
temperature coefficient is not in any of the ranges, choose the TEMPCO and PDAC setting closest to the
required temperature coefficient, then go to step 5.
– 1%/°C is between the mimumum and maximum for TEMPCO = 11.
4. Calculate the target CSA voltage. Divide the driver temperature coefficient [mV/°C] by the desired
temperature coefficient [%/°C] and multiply by 100.
– 1.040 mV/°C divided by 1 %/°C is 104 mV.
5. Calculate the CSA resistor by dividing the target CSA voltage by the required current and subtracting 0.1 Ω
for internal resistance.
– 104mV divided by 100mA is 1.04 Ω. Subtract 0.1 Ω to get 0.94 Ω.
6. Select the closest available resistor and calculate the final CSA voltage by multiplying the required current by
the total resistance (external and internal).
– Use a 0.92 Ω resistor. Multiply 100 mA and 1.02 Ω to get 102mV CSA voltage.
7. Calculate the PDAC value by subtracting the final CSA voltage by the specified CSA voltage at PDAC =
0x00 and dividing the result by 1.176 mV (the DAC LSB, equal to 300 mV divided by 255).
– 102 mV minus 79 mV is 23mV, divided by 1.176 mV is 20. Write 0x14 to the PDAC register.
8. Calibrate the PDAC value. If using the LED A driver, read the CSA_BIN register bits and add 0x11 if
CSA_BIN=00b, add 0x06 if CSA_BIN=01b, subtract 0x06 if CSA_BIN=10b, or subtract 0x11 if
CSA_BIN=11b. The CSA_BIN value varies from unit to unit and must be read on each unit calibrated using
this method. Alternatively, measure the CSA or CSB voltage using the MCU ADC and adjust PDAC
accordingly.
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Typical Application (continued)

– The microcontroller reads that a unit has CSA_BIN=01b. 0x20 is written to PDAC_A.

Table 21. Temperature Coefficients for Each TEMPCOA and DAC_A Setting
CSA Voltage [mV], T = Temperature Coefficient Temperature Coefficient
Register Setting Coefficient Information
27°C [mV/°C] [%/°C]
TEMPCOA[1:0] = 11, 79 1.040 1.316% Max for TEMPCO = 11b
PDAC_A = 0x00
TEMPCOA[1:0] = 11, 376 1.040 0.277% Min for TEMPCO = 11b
PDAC_A = 0xFF
TEMPCOA[1:0] = 10, 188 0.693 0.369% Max for TEMPCO = 10b
PDAC_A = 0x00
TEMPCOA[1:0] = 10, 484 0.693 0.143% Min for TEMPCO = 10b
PDAC_A = 0xFF
TEMPCOA[1:0] = 01, 277 0.416 0.150% Max for TEMPCO = 01b
PDAC_A = 0x00
TEMPCOA[1:0] = 01, 572 0.416 0.073% Min for TEMPCO = 01b
PDAC_A = 0xFF
TEMPCOA[1:0] = 00, 299 0.347 0.116% Max for TEMPCO = 00b
PDAC_A = 0x00
TEMPCOA[1:0] = 00, 593 0.347 0.059% Min for TEMPCO = 00b
PDAC_A = 0xFF

Table 22. Temperature Coefficients for Each TEMPCOB and DAC_B Setting
CSB Voltage [mV], T = Temperature Coefficient Temperature Coefficient
Register Setting Coefficient Information
27°C [mV/°C] [%/°C]
TEMPCOB[1:0] = 11, 81 1.040 1.284% Max for TEMPCO = 11b
PDAC_B = 0x00
TEMPCOB[1:0] = 11, 379 1.040 0.272% Min for TEMPCO = 11b
PDAC_B = 0xFF
TEMPCOB[1:0] = 10, 189 0.693 0.369% Max for TEMPCO = 10b
PDAC_B = 0x00
TEMPCOB[1:0] = 10, 486 0.693 0.143% Min for TEMPCO = 10b
PDAC_B = 0xFF
TEMPCOB[1:0] = 01, 277 0.416 0.150% Max for TEMPCO = 01b
PDAC_B = 0x00
TEMPCOB[1:0] = 01, 572 0.416 0.073% Min for TEMPCO = 01b
PDAC_B = 0xFF
TEMPCOB[1:0] = 00, 299 0.347 0.116% Max for TEMPCO = 00b
PDAC_B = 0x00
TEMPCOB[1:0] = 00, 594 0.347 0.059% Min for TEMPCO = 00b
PDAC_B = 0xFF

Use the same procedure for the blue LED, requiring 50 mA and 0.1mA/°C, to calculate TEMPCOB = 10, RCSB =
6.8 Ω, VCSB = 345 mV, PDAC_B = 0x85 (before calibration).
The two drivers are identical, except for the CSA_BIN code to improve the accuracy of the LED_A driver for IR
LEDs. Connect the IR LED to the LED A driver and the blue LED to the LED B driver in multi-wave systems.

9.2.2.3 LED Voltage Supply Selection

Each of the LED anodes must have enough voltage to forward bias the LED, regulate the CSA and CSB voltage,
and exceed the driver dropout voltage requirement from DINA to CSA and DINB to CSB. A typical IR LED at 100
mA has 1.5 V forward voltage. The LED driver dropout voltage at 100 mA is 300 mV. With the CSA voltage set to
100 mV, the dropout voltage of 300 mV, and forward voltage of 1.5 V, at least 1.9 V must be applied to the IR
LED anode for current regulation. Connect the IR LED anode to LEDLDO and set LEDLDO_EN = 1 to charge
the IR LED anode capacitor.

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A typical blue LED at 50 mA has 4 V forward voltage. For the blue LED, the CSB voltage is 340 mV, the dropout
voltage is 300 mV, and the forward voltage is 4 V. Supply over 4.64 V to the anode for the duration of the LED
pulse. With a 47 µF capacitor derated to 30 µF, 100 µs LED pulse, the anode voltage drops by 170 mV. Thus,
the capacitor must be charged to 4.81 V. If the VCC voltage is between 5 V and 6 V, connect the blue LED
anode to VCC through a 1-kΩ resistor. If VCC is between 6 V and 15 V, connect the blue LED anode to
LEDLDO and set LEDLDO_EN = 1 to charge the blue LED anode capacitor. The LED LDO has a diode voltage
drop between the VSLC voltage and LEDLDO voltage. The LEDLDO prevents the DINA pin from exceeding its
recommended operating limit of 11.5 V.

9.2.2.4 Regulator Component Selection

To stabilize the output voltage on each regulator, install 1-µF capacitors on VINT, VMCU, and PLDO. Connect
the MCUSEL pin to GND to set the MCU LDO voltage to 1.8 V. The MCU LDO can be set to other voltages by
changing the MCUSEL pin connection. Connect MCUSEL to a 330-pF capacitor to set the MCU LDO to 3.3 V.
Connect MCUSEL to VINT to set the MCU LDO to 2.5 V. Connect MCUSEL to GND with a 620-Ω resistor to set
the MCU LDO to 1.5 V.

9.2.3 Application Curves

All curves use the schematics shown in Figure 12. The photo amplifier curves do not have the 470 kΩ PREF
resistor installed.

Figure 13. LED Driver and Photo Amplifier Waveforms Figure 14. LED Driver and Photo Amplifier Waveforms with
128 Averages

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Figure 15. Carbon Monoxide Amplifier Waveforms with Calibration Gas

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10 Power Supply Recommendations

A 4.5-V to 15-V power supply is recommended on VCC and VSLC. If a blue LED is used with the LED driver,
higher voltage may be required. Ensure the power supply can tolerate transient currents caused by the LED
driver. A supply capable of 5 mA average current is generally sufficient. Ensure the power supply's rise time is
less than 100 ms.

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11 Layout

11.1 Layout Guidelines

These blocks require careful layout placement:
• Photo amplifier
• CO amplifier
• Ground plane and traces

11.1.1 Photo Amplifier Layout

The photo amplifier is a very sensitive analog block in the TPS8804 device. Minimal trace lengths must be used
to connect the photodiode and relevant external components to PDP, PDN, PDO, PREF and AGND. It is
recommended to shield the PDP, PDN, PDO, and PREF traces with the AGND plane.

11.1.2 CO Amplifier Layout

Similar to the photo amplifier, the CO amplifier is very sensitive to noise. Connect the CO electrochemical sensor
close to the TPS8804 device and shield the COP, CON, and COO traces with the AGND plane.

11.1.3 Ground Plane Layout

Connect AGND and DGND to the ground plane. Ensure there is a short path from AGND to DGND. Route PGND
and its associated blocks (LED driver, SLC transmitter) separately from the ground plane. Connect PGND to
AGND at a single point near the IC.

11.2 Layout Example

Figure 16. Photo Amplifier Layout

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Layout Example (continued)

Figure 17. CO Amplifier Layout

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Layout Example (continued)

AGND

DGND

AGND Plane

PGND

PGND PGND

PGND PGND

PGND Pla ne

Figure 18. Ground Layout

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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www.ti.com 27-Mar-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TPS8804DCPR ACTIVE HTSSOP DCP 38 2000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 TPS8804DCP
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 27-Mar-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS8804DCPR HTSSOP DCP 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
TPS8804DCPR HTSSOP DCP 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 27-Mar-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS8804DCPR HTSSOP DCP 38 2000 367.0 367.0 38.0
TPS8804DCPR HTSSOP DCP 38 2000 367.0 367.0 38.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
DCP 38 PowerPAD TSSOP - 1.2 mm max height
4.4 x 9.7, 0.22 mm pitch SMALL OUTLINE PACKAGE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224560/A

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 PACKAGE OUTLINE
DCP0038A SCALE 2.000
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

6.6 C
TYP
A 6.2
PIN 1 INDEX 0.1 C SEATING
AREA 36X 0.5 PLANE
38
1

2X
9.8
9
9.6
NOTE 3

19
20
0.27
38X
4.5 0.17
B
4.3 0.08 C A B

SEE DETAIL A
(0.15) TYP

2X 0.95 MAX
NOTE 5
19 20
2X 0.95 MAX
NOTE 5

0.25
GAGE PLANE 1.2 MAX
4.70 39
3.94
THERMAL
PAD 0.15
0.75
0 -8 0.50 0.05
DETAIL A
A 20

TYPICAL

1 38

2.90
2.43
4218816/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.

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 EXAMPLE BOARD LAYOUT
DCP0038A TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(3.4)
NOTE 9
METAL COVERED
(2.9) BY SOLDER MASK
SYMM
38X (1.5) SEE DETAILS
38X (0.3)
1
38

(R0.05) TYP

36X (0.5)

3X (1.2)

SYMM
39
(4.7) (9.7)
NOTE 9
(0.6) TYP
SOLDER MASK
DEFINED PAD

( 0.2) TYP
VIA

19 20

(1.2)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
15.000

4218816/A 10/2018
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.

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 EXAMPLE STENCIL DESIGN
DCP0038A TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(2.9)
BASED ON
0.125 THICK
38X (1.5) STENCIL
METAL COVERED
38X (0.3) BY SOLDER MASK
1
38

(R0.05) TYP

36X (0.5)

(4.7)
SYMM 39 BASED ON
0.125 THICK
STENCIL

19 20

SYMM SEE TABLE FOR

DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.8) THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 8X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.24 X 5.25
0.125 2.90 X 4.70 (SHOWN)
0.15 2.65 X 4.29
0.175 2.45 X 3.97

4218816/A 10/2018
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

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