Introduction to VHDL

Krzysztof Kuchcinski
[email protected]

Department of Computer Science

Lund Institute of Technology
Sweden

February 17, 2005

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 1 / 44

Outline

1 Basic Aspects

2 An Example

3 The VHDL Simulation Mechanism

4 Signal Assignment and Delay Mechanisms

5 VHDL for System Synthesis

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 2 / 44

VHDL History

The name: VHSIC Hardware Description Language

Important dates:
1983: development started with support from US government.
1987: adopted by IEEE as a standard (IEEE Std. 1076 - 1987).
1993: VHDL’92 adopted as a standard after revision of the initial
version (IEEE Std. 1076 - 1993).

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Main Features

Supports the whole design process:

system level
RT level
logic level
circuit level (to some extent)
Suitable for specification in
behavioral domain
structural domain
Precise simulation semantics is associated with the language
constructs

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 4 / 44

Basic Constructs

The basic building block of a VHDL model is the entity

An entity is described as a set of design units:
entity declaration
architecture body
package declaration
package body
configuration declaration

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 5 / 44

An Example

Example
A four bit parity generator

V EVEN

entity PARITY is
port(V:in BIT_VECTOR(3 downto 0);
EVEN:out BIT);
end PARITY;

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 6 / 44

Architecture body for parity generator – behavioral

architecture PARITY_BEHAVIORAL of PARITY is

begin
process(V)
variable NR_1: NATURAL;
begin
NR_1:=0;
for I in 3 downto 0 loop
if V(I)=’1’ then
NR_1:=NR_1+1;
end if;
end loop;
if NR_1 mod 2 = 0 then
EVEN <= ’1’ after 2.5 ns;
else
EVEN <= ’0’ after 2.5 ns;
end if;
end process;
end PARITY_BEHAVIORAL;

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 7 / 44

A Model of Behavior

Inputs Discrete Outputs

System

Process Process
P1 P2
signal
(directed data
pathway)

a process can be view as a sequential program,

a process can call subprogram (procedures and functions),
processes are run in parallel,
the process can be suspended (wait statement) and reactivated
by receiving a signal or timing condition.

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 8 / 44

A Model of Behavior (cont’d)

entity declaration

declarations

architecture declaration
declarations
port
architecture declaration
declarations

architecture declaration
port
declarations

process
port

process port

process

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 9 / 44

A Model of Behavior (cont’d)
entity Xor is
port (In1, In2: BIT; Out1: out Bit);
end Xor;

In1

Out1
Out1<= In1
xor In2

In2

architecture Behavior1 of Xor is architecture Behavior1a of Xor is

constant Delay : Time := 5 ns; constant Delay : Time := 5 ns;
begin begin
process (In1, In2) process
begin begin
Out1 <=In1 xor In2 after Delay; Out1 <=In1 xor In2 after Delay;
end process; wait on In1, In2;
end Behavior1; end process;
end Behavior1a;

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 11 / 44

A Model of Behavior (cont’d)

architecture Behavior2 of Xor is

In1 Internal1 <= constant Delay : Time := 5 ns;

Internal1
In1 and In2 signal Internal1, Internal2: Bit;
Out1<= Out1
not(Internal1
or Internal2) begin
In2 Internal2 <= process (In1, In2)
not(In1) and
not(In2) Internal2 begin
Internal1 <=In1 and In2 after Delay;
end process;

process (In1, In2)

begin
Internal2 <= not(In1) and not(In2) after Delay;
end process;

process (Internal1, Internal2)

begin
Out1 <= not (Internal1 or Internal2) after Delay;
end process;

end Behavior2;

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 13 / 44

A Model of Time

Start Simulation

Update signals Execute Processes

End Simulation

Transaction
value
time
Transactions queue

collection of transactions is called a signal driver,

two-stage model of time – a component reacts to activity on its
inputs respond through its output connections,
delta delay is used to change a simulation cycle without updating
the simulation time.

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 14 / 44

A Model of Structure

entity declaration

declarations

architecture declaration

port declarations

component

port

component

port

port
component

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Parity Generator – Structural

V(0)
T1
V(1)

EVEN
T3
V(2)
T2
V(3)

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 16 / 44

Example (cont’d)

use WORK.all;
architecture PARITY_STRUCTURAL of PARITY is
component XOR_GATE
port(X,Y: in BIT; Z: out BIT);
end component;

component INV
generic(DEL: TIME);
port(X: in BIT; Z: out BIT);
end component;

signal T1, T2, T3: BIT;

begin
XOR1: XOR_GATE port map (V(0), V(1), T1);
XOR2: XOR_GATE port map (V(2), V(3), T2);
XOR3: XOR_GATE port map (T1, T2, T3);
INV1: INV
generic map (0.5 ns)
port map (T3, EVEN);
end PARITY_STRUCTURAL;

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 17 / 44

Example – testbench

entity BENCH is
end BENCH;

use WORK.all;
architecture ARCH_BENCH of BENCH is
component PARITY
port(V: in BIT_VECTOR (3 downto 0); EVEN: out BIT);
end component;
for PARITY_GENERATOR:PARITY use
entity PARITY(PARITY_STRUCTURAL);
signal VECTOR: BIT_VECTOR (3 downto 0);
signal E: bit;
begin
VECTOR <= ‘0010’,
‘0000’ after 3 ns,
‘1001’ after 5.8 ns,
. . .
‘0111’ after 44.5 ns,
‘1101’ after 50 ns;
PARITY_GENERATOR:PARITY port map(VECTOR, E);
end ARCH_BENCH;

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 18 / 44

Model of Structure

Stage1 Stage2
In1 Out1 <= Internal1
In1 and In2

Out1<= Out1
not(In1 or In2)
In2
Out2 <=
not(In1) and
not(In2) Internal2

architecture Structure of Xor is

signal Internal1, Internal2: Bit;

component Stage1
port (I1, I2: Bit; O1, O2: out Bit);
end component;
component Stage2
port (I1, I2: Bit; O1: out Bit);
end component;

begin
U0: Stage1 port map (In1, In2,Internal1,Internal2);
U1: Stage2 port map (I1=>Internal1, I2=>Internal2, O1=>Out);
end structure;

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 19 / 44

Mixed Descriptions

entity declaration

declarations

architecture declaration

port declarations

process
component

port

component

port
process

port
component

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 20 / 44

Block Structuring in VHDL

entity declaration

declarations

architecture declaration

port declarations

component
process

port
block
declarations
component

port

block
declarations port
process

component

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 21 / 44

The wait statement

A process may suspend itself by executing a wait statement:

wait on A,B,C until A<2*B for 100 ns;

Sensitivity clause
Condition clause
Time-out clause

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The VHDL Simulation Mechanism

After elaboration of a VHDL model results a set of processes

connected through signals.
The VHDL model is simulated under control of an event driven
simulation kernel (the VHDL simulator).
Simulation is a cyclic process; each simulation cycle consists of a
signal update and a process execution phase.
A global clock holds the current simulation time; as part of the
simulation cycle this clock is incremented with discrete values.

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 23 / 44

The VHDL Simulation Mechanism (cont’d)

current signal values are only updated by the simulator at

certain moments during simulation!
. . .
X<=1;
if X=1 then
statement_sequence_1
else
statement_sequence_2
end if;
. . .

A signal assignment statement only schedules a new value to be

placed on the signal at some later time which is specified by the
designer as part of the signal assignment
S<=1 after 20 ns,15 after 35 ns;

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 24 / 44

The VHDL Simulation Mechanism (cont’d)

signal driver contains the projected output waveform of a signal

projected output waveform is a set of transactions
transaction: pair consisting of a value and a time

Signal assignment
A signal assignment only affects the projected output waveform, by
placing one or more transactions into the driver corresponding to the
signal and possibly by deleting other transactions.

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 25 / 44

Signal Assignment

Process P4

. . . . .
X:=S1+S2+S3;

Current
5 S1 150 S2 f(10,1) S3 signal values

ction
n fun
lutio
Reso
5 10ns
100 35ns 1 20ns
0 100ns 10 15ns 0 40ns
10 110ns 150 20ns 0 50ns 0 60ns
55 130ns 88 100ns
Dr_S1 P1 Dr_S3 P3
Dr_S2P2 Dr_S3 P2

. . . . . . . . . .
. . . . .
S1 <= ... S2 <= ...
S3 <= ...
. . . . . . . . . .
. . . . .
S1 <= ... S3 <= ...

Process P1 Process P2 Process P3

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 26 / 44

The VHDL Simulation Cycle

The current time Tc is set to Tn

Each active signal is updated; as result of signal updates events
are generated
Each process that was suspended waiting on signal events that
occurred in this simulation cycle resumes; processes also resume
which were waiting for a certain, completed, time to elapse
Each resumed process executes until it suspends
The time Tn of the next simulation cycle is determined as the
earliest of the following three time values:
1 TIME’HIGH
2 The next time at which a driver becomes active
3 The next time at which a process resumes

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 27 / 44

Delta Delay and Delta Cycle

X
S
Z
Y

entity DELTA_DELAY_EXAMPLE is
port(X, Y:in BIT; Z: out BIT);
end DELTA_DELAY_EXAMPLE;

architecture DELTA of DELTA_DELAY_EXAMPLE is

signal S: BIT;
begin
AND_GATE: process(X,Y)
begin
S <= X and Y;
end process;
INVERTER: process(S)
begin
Z <= not S;
end process;
end DELTA;

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 28 / 44

Delta Delay

If no delay time is specified, a delta delay is assumed for any

signal assignment.
Delta delay represents an infinitesimal delay, less than any
measurable time (i.e., femtoseconds), but still larger than zero.

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 29 / 44

Delta Delay Example

QB <= R nand Q; R
QB
Q <= S nand QB;

S Q

R <= ’0’ after 5ns, ’1’ after 10ns;

S <= ’0’ after 15ns, ’1’ after 20ns;

QB

5 10 15 20

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 31 / 44

Signal Assignment Statement

The projected output waveform stored in the driver of a signal can be

modified by a signal assignment statement.
signal_assignment_statement ::=
target <= [transport | inertial] waveform;

waveform ::= waveform_element {, waveform_element}

waveform_element ::= value_expression [after time_expression]

S <= transport 100 after 20 ns, 15 after 35 ns;

S <= 1 after 20 ns,15 after 35 ns;

The concrete way a driver is updated as result of a signal assignment

depends on the delay mechanism.

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 33 / 44

Transport Delay

Transport delay models devices that exhibit nearly infinite

frequency response: any pulse is transmitted, no matter how short
its duration.
Update rule:
1 All old transactions scheduled to occur at the same time or after the
first new transaction are deleted from the projected waveform.
2 The new transactions are appended to the end of the driver.

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 35 / 44

Transport Delay – Example

Consider the following assignments executed at simulation time 100 ns

(the projected waveform consists of a single transaction with value 0):
S <= transport 100 after 20 ns, 15 after 35 ns;
S <= transport 10 after 40 ns;
S <= transport 25 after 38 ns;

Driver for S after first two assignments:

0 100 15 10
100 ns 120 ns 135 ns 140 ns

Driver for S after last assignment:

0 100 15 25
100 ns 120 ns 135 ns 138 ns

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 37 / 44

Transport Delay – Example

X
10 20 30 50 70 75 85 90

X Z
Z <= transport X after 15 ns

Z
25 35 45 65 85 90 100 105
t=0 ns

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 38 / 44

Inertial Delay

Inertial delay models the timing behaviour of current switching

circuits: an input value must be stable for a duration before the
value propagates to the output.
Additional update rule (after operations have been performed like
for transport delay):
all old transactions scheduled to occur before the first new
transaction are deleted from the projected waveform
accepted are those transactions which are immediately preceding
the first new transaction and have the same value with it

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 39 / 44

Inertial Delay – Example

Consider the following assignments executed at simulation time 100 ns

(the projected waveform consists of a single transaction with value 0):
S <= 1 after 20 ns, 15 after 35 ns;
S <= 8 after 40 ns, 2 after 60 ns,
5 after 80 ns, 10 after 100 ns;
S <= inertial 5 after 90 ns;

0 1 15
1st assignment:
100 ns 120 ns 135 ns
0 8 2 5 10
2nd assignment:
100 ns 140 ns 160 ns 180 ns 200 ns
0 5 5
3rd assignment:
100 ns 180 ns 190 ns

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 41 / 44

Inertial Delay – Example

X
10 20 30 50 70 75 85 90

X Z
Z <= inertial X after 15 ns

Z
45 65

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VHDL For System Synthesis

Semantic of VHDL is simulation based

VHDL widely used for synthesis
Problems:
1 VHDL has the rich capabilities of a modern programming language
⇒ some facilities are not relevant for hardware synthesis.
2 Some features are semantically explained in terms of simulation
(process interaction, timing model).
Solutions:
1 subsetting
2 modeling guidelines

Kris Kuchcinski (LTH) Introduction to VHDL February 17, 2005 43 / 44

VHDL For System Synthesis (cont’d)

VHDL synthesis tools at logic and RT level are commonly

available today.
Industrial use of high-level synthesis with VHDL is at the
beginning.

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