Academic Session 2020/2021

Semester 1

EMT 475/3
Computer Organization
& Architecture
Chapter 2: Computer Function &
Interconnection

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Outline
• Computer Component
• Computer Function
• Interconnection Structures
• Bus Interconnection

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Computer Component
van Neumann architecture
• THREE(3) key concepts
1) Data & instruction : stored in a single read-write
memory
2) The contents of this memory : addressable by location
3) Execution: occurs in sequential fashion from one
instruction to the next
• Unless explicitly modified is necessary
• Thus, the process of connecting the various components in
the desired configuration is called “program”
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Computer Component
Program concept
• Connection in the form hardware
called “hardwired program”
• This systems are inflexible

• General purpose hardware can

do different tasks, given correct
control signals
• Instead of re-wiring, supply
a new set of control signals
or “software”
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Computer Component
What is a program?
• A sequence of steps
• For each step, an arithmetic /logical operation is done
• For each operation, a different set of control signals is
needed

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Computer Component
Control unit
• For each operation a unique code is provided
―e.g. ADD, MOVE
• A hardware segment accepts the code & issues the
control signals

We have a computer!

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Computer Component
Components
• Instruction interpreter & general purpose Arithmetic &
Logic Unit (ALU)  Central Processing Unit (CPU)
• To yield functioning computer
―Input/output (I/O) component
• Providing module for input data & instructions
before processing into the system & module for
output result obtained from the system
―Main memory
• Temporary storage of data & instructions due to
non-sequential program
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Computer Component
• Illustration of
top-level components

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Computer Function
Instruction cycle
1. Fetch
2. Execute

1 2

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Computer Function
Fetch Cycle
• Processor fetches instruction from memory location pointed by
Program Counter (PC)
• Program Counter (PC) holds address of next instruction to be
fetched
• Increment PC
―Unless told otherwise
• Instruction loaded into Instruction Register (IR)
• Processor interprets instruction & performs required actions

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Computer Function
Execute Cycle
• Processor-memory
―data transfer between CPU & main memory
• Processor I/O
―Data transfer between CPU & I/O module
• Data processing
―Some arithmetic or logical operation on data
• Control
―Alteration of sequence of operations, e.g. JUMP
• Combination of above

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 Opcode:
0001 = LOAD AC from memory
Computer Function 0010 = STORE AC to memory
0101 = ADD to AC from memory

Example:
Consist of fetch cycle and execute cycle.
1. Fetch the instruction from memory location
A, PC = 300, value = 1940 (hex) & load into
IR.
2. Execute LOAD operation of value in address
940 into AC.
3. Fetch the instruction from memory location
B, PC = 301, value = 5941 (hex) & load into
IR.
4. Execute ADD operation of two values in 940
& 941. Load into AC.
5. Fetch the instruction from memory location
B, PC = 302, value = 5941 (hex) & load into
IR.
6. Execute STORE operation by storing value
AC into memory location B (941).

Note: Contents of memory & registers in

hexadecimal
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Computer Function
• Instruction Cycle State Diagram
2 5 7

3 4 6

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Computer Function
Interrupt Concept
• a signal/an event used to request the CPU to suspend the
current program execution.
• Occurs when an event inside a computer system requiring
some urgent action by the CPU.
• CPU suspends the current program execution & branches in
to an Interrupt Service Routine (ISR).
―ISR - program that service the interrupt by taking
appropriate actions.
• Before taking up ISR, CPU stores the next instruction
address (contents of Program Counter (PC)) at the time of
branching to ISR.
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Computer Function
• After execution of ISR, the CPU returns back to the
interrupted program.
• The CPU resumes the interrupted program.
―Interrupts - provided as a way to improve processing
efficiency.
• Most external devices - much slower than the processor.
e.g. processor transferring data to a printer using the
instruction cycles.
• After each WRITE operation, the processor must pause &
remain idle  wasteful use of the processor.
• With interrupts, the processor can be engaged in executing
other instructions while an I/O operation is in progress. 15
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Computer Function
Mechanism by which other modules may interrupt normal
sequence of processing
Classes of interrupts
Module Description
Program e.g. overflow, division by zero
Generated by internal processor timer
Timer
Used in pre-emptive multi-tasking
I/O Generated by I/O controller
Hardware e.g. power failure, memory parity
failure error
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Computer Function
Instruction Cycle with Interrupts Refer Pg. 9
1 2 3

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Computer Function
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
―Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If yes (interrupt pending):
―Suspend execution of current program
―Save context
―Set PC to start address of interrupt handler routine
―Process interrupt
―Restore context & continue interrupted program

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 START

• Interrupt Cycle Add to

Instruction cycle

Check
YES for NO
interrupt
Suspend execution Fetch next
of current program instruction
Save context

Set PC to start
address of interrupt
handler routine

Restore context &

continue interrupt

END
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Computer Function
Normal: Program Flow Program Timing

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Computer Function
Short I/O wait: Program Flow Program Timing

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Computer Function
Long I/O wait : Program Flow Program Timing

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Computer Function
Comparison

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Computer Function
Transfer of Control via Interrupts

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Computer Function
Instruction Cycle (with Interrupts) - State Diagram

Refer Pg. 13

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Computer Function
Multiple Interrupts
• Not only single but multiple interrupts at a time
e.g. A program receiving data from communications
line & printing results
• TWO(2) approaches to deal with multiple interrupts:-
―Disable interrupts
―Define priorities

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Computer Function
• Disable interrupts
― Processor will ignore further interrupts whilst
processing one interrupt
― Interrupts remain pending & are checked after first
interrupt has been processed
―Interrupts handled in sequence as they occurred
• Define priorities
― Low priority interrupts can be interrupted by higher
priority interrupts
― When higher priority interrupt has been processed,
processor returns to previous interrupt
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Computer Function
Multiple Interrupts - Sequential

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Computer Function
Multiple Interrupts - Nested

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 Computer Function
Example: Time Sequence of Multiple Interrupts
Priority:
Communication 5
Disk 4
Printer 2

Refer Pg. 29
Faculty of Electronic Engineering Technology Refer Pg. 28 30
ISR – Interrupt Service Routine Universiti Malaysia Perlis
Interconnection Structures
• All the units must be connected
• Different types of connection for different types of unit
―Memory
―Input/Output (I/O)
―CPU

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Interconnection Structures
Refer Chp.01 - Pg. 44

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Interconnection Structures
Memory connection
• Receives & sends data
• Receives addresses (of locations)
• Receives control signals Computer Peripheral/
Computer
―READ
―WRITE
―Timing

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Interconnection Structures
I/O connection
• Similar to memory from computer’s viewpoint
• Output
―Receive data from computer Computer
Peripheral
―Send data to peripheral
• Input
―Receive data from peripheral
―Send data to computer

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Interconnection Structures
• Receive control signals from computer
• Send control signals to peripherals
―e.g. spin disk
• Receive addresses from computer Computer
Peripheral
―e.g. port number to identify
peripheral
• Send interrupt signals (control)

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Interconnection Structures
CPU connection
• Reads instruction & data
• Writes out data (after processing)
• Sends control signals to other units Memory/
Memory/
• Receives (& acts on) interrupts Peripheral Peripheral

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Bus Interconnection
• Top level: Computer consists of CPU, main memory & I/O.
Refer Chp.01 - Pg. 14

• Connecting paths - necessary inside a computer between the

subsystems (CPU, main memory & I/O)
e.g. Instruction from memory to CPU & Data from memory
to CPU & vice versa.
• Consists of multiple comm. pathways, or lines.
• Each line capable of transmitting signals representing binary
1 & binary 0.
• Single & multiple BUS structures - most common
e.g. Control/Address/Data bus (PC), Unibus (DEC-PDP)

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Bus Interconnection
What is a Bus?
• A communication pathway connecting two/more devices
• Carrying information between the subsystems (CPU,
memory & I/O)
• Usually broadcast
• Often grouped
―A number of channels in one bus
―e.g. 32 bit data bus :32 separate single bit channels
• PC consists of 3 different buses : data, address &
control

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 Bus Interconnection
Data Bus
• Carries data : Provide a path for moving data between
system modules.
• May consists of from 32 to hundreds of separate lines,
number of lines refer to bus width & determines how
many bits can be transferred at a time.
• Width - key determinant of performance
―8, 16, 32, 64 bit
―Advanced Microprocessor Bus Architecture (AMBA)
• 256 bit (32 bit address bus)(APB,AHB etc)
ASB: Advanced System Bus
APB: Advanced Peripheral Bus
AHB: Advanced High-Performance Bus
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 https://en.wikipedia.org/wiki/Advanced_Microcontroller
ARM Product _Bus_Architecture#AMBA_protocol_specifications

• Advanced Microcontroller Bus Architecture (AMBA)

Version Specification No. of bus Version ARM product
1 • Advanced System Bus (ASB)
• Advanced Peripheral Bus (APB) 2
2 • Advanced Peripheral Bus (APB) ARM7, ARM9 & ARM
• Advanced System Bus (ASB) 3 AHB, ASB, APB2@APB
• Advanced High-Performance Bus (AHB) Cortex-M based design
3 • Advanced Peripheral Bus (APB) AXI3/AXIv1.0,
• Advanced High-Performance Bus (AHB) ARM Cortex-A including
Advanced Trace Bus (ATB) 4 AHB-Lite v1.0
• Cortex-A9
• Advanced Extensible Interface (AXI) APB3 v1.0, ATB v1.0
4 • Advanced Peripheral Bus (APB)
ACE, ACE-Lite
• Advanced Trace Bus (ATB) AXI4, AXI4-Lite ARM Cortex-A (Cortex-
• Advanced Extensible Interface (AXI) AXI4-Stream v1.0 A7 & Cortex-A15)
• AXI Coherency Extensions (ACE)
ATB v1.1, APB4 v2.0
5 • Advanced High-Performance Bus (AHB)
• Advanced Extensible Interface (AXI) AXI5, AXI5-Lite, ACE5
• AXI Coherency Extensions (ACE)
• Coherent Hub Interface (CHI) AHB5, AHB-Lite
• Distributed Translation Interface (DTI) CHI, DTI, GFB
• Generic Flash Bus (GFB)
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Bus Interconnection
Address Bus
• Identify the source/destination of data
• e.g. CPU needs to read an instruction (data) from a given
location in memory
• Bus width determines maximum memory capacity of
system
―e.g. 8080 has 16 bit address bus giving 64k address
space

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Bus Interconnection
Control Bus
• Transmit both command & timing information between
system modules.
• Timing signal indicate the validity of data & address
information.
• Command signal specify operations to be performed.
• e.g.
―Memory , IO read/write signal
―Interrupt request
―Clock signals, reset
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Bus Interconnection
Bus Interconnection Scheme

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Bus Interconnection
Big & Yellow?
• What do buses look like?
―Parallel lines on circuit boards
―Ribbon cables
―Strip connectors on mother boards
• e.g. PCI
―Sets of wires

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Bus Interconnection
Physical Realization of Bus Architecture

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Bus Interconnection
Single Bus Problems
• Lots of devices on one bus leads to:
―Propagation delays
• Long data paths mean that co-ordination of bus use
can adversely affect performance
• If aggregate data transfer approaches bus capacity
• Most systems use multiple buses to overcome this
problem

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Bus Interconnection
Small Computer System Interface (SCSI)
- A set of standards for physically connecting
& transferring data between computers &
peripheral devices.

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Bus Interconnection
Multiple bus computer
• The communication inside computer system occurs over
different types of bus
―Local bus
―System bus
―I/O bus
―Mezzanine bus
• Mezzanine architecture – high speed bus closely
integrated with the rest of the system, requiring only a
bridge between processor’s bus & high speed bus.
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Bus Interconnection
• Re

Refer Pg. 46

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Bus Interconnection
Bus types
• Dedicated
―Separate data & address lines
• Multiplexed
―Shared lines
―Address valid/data valid control line
―Advantage - fewer lines
―Disadvantages
• More complex control
• Ultimate performance

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 Bus Interconnection
Bus Arbitration
• More than one module controlling the bus
e.g. CPU & DMA controller
• Only one module may control bus at one time
• Arbitration may be centralised/distributed

DMA – Direct Memory Access

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Bus Interconnection
Centralised/Distributed Arbitration
• Centralised
―Single hardware device controlling bus access
• Bus Controller
• Arbiter
―May be part of CPU or separate
• Distributed
―Each module may claim the bus
―Control logic on all modules

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Bus Interconnection
Timing
• Co-ordination of events on bus
• Synchronous
―Events determined by clock signals
―Control Bus includes clock line
―A single 1-0 is a bus cycle
―All devices can read clock line
―Usually sync on leading edge
―Usually a single cycle for an event

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Bus Interconnection
Synchronous Timing
Diagram

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Bus Interconnection
• Asynchronous Timing
– Read Diagram

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Bus Interconnection
• Asynchronous Timing
– Write Diagram

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Bus Interconnection
PCI Bus
• Peripheral Component Interconnection.
• Acting as an intermediate bus between the
system bus & the I/O bus.
• High speed bus
• Isolates slow speed I/O subsystems from the
processor.
• Brings I/O controller closer to the memory.
• Develop in 1990 for Pentium-based system &
released all patents to the public domain.
• PCI may be configured as a 32/64 bit
• 49 mandatory signal lines.
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PCI https://en.wikipedia.org/wiki/Conventional_PCI

Physical

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Bus Interconnection
Why PCI?
• High bandwidth
• Processor independent bus
• Peripheral bus
• Better system performance for high speed I/O systems
• Economically I/O requirements
• A few chips to implement & support other buses
attached to it.

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Bus Interconnection
• Typical Desktop System

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Bus Interconnection
• Typical Server System

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 Bus Interconnection
PCI Bus Line
• Systems lines : include clock & reset pins
• Address & Data :
―include 32 lines - time multiplexed for address & data.
The other lines in this group are used to interpret &
validate the signal lines that carry the address & data.
• Interface Control : control the timing of transactions &
provide coordination among initiators & targets
• Arbitration : - not shared lines & each PCI master has its
own pair of arbitration lines that connect it directly to the
PCI bus arbiter.
• Error lines : used to report parity & error
PCI – Peripheral Component Interconnect
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Bus Interconnection
PCI – Mandatory signal lines
• System pins - CLK, RST#
• Address & Data Pins - AD[31::0], C/BE[3::0]#, PAR
• Interface control lines
• FRAME#, IRDY#, TRDY#,STOP#, IDSEL,DEVSEL
• Arbitration Pins - REQ#,GNT#
• Error reporting pins - PERR#, SERR#

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Bus Interconnection
PCI Bus Lines (Optional)
• Interrupt pins : provide for PCI devices that must generate
requests for service. Each PCI device has its own interrupt line or
lines to an interrupt controller.
• Cache support pin : these pins are needed to support a memory on
PCI that can be cached in the processor or another device.
• 64-bit bus extension pin : include 32 lines - time multiplexed for
address/data & that are combined with the mandatory
address/data lines to form a 64-bit address/data bus. Other lines in
this group are used to interpret & validate the signal lines that
carry the address/data. There are two lines that enable two PCI
devices to agree to use 64 bit capability.
• JTAG/boundary scan pins : These signal lines support testing
procedures define in IEEE 1149.1.
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Bus Interconnection
PCI Commands
• Transaction between initiator (master) & target
• Master claims bus
• Determine type of transaction
―e.g. I/O read/write
• Address phase
• One/more data phases

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Bus Interconnection
• PCI Read
Timing Diagram

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Bus Interconnection
Bus Arbitration
• Process of determining the bus master which has the
bus control at a given time when there is a request for
bus mastership from one/more bus masters.
• When more than one bus master simultaneously needs
the bus, only one of them gains control of the bus and
become active bus master.
• The other would wait for their turn.
• The ‘bus arbiter’ decides who would become current
bus master
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Bus Interconnection
• PCI Bus Arbiter

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Bus Interconnection
• PCI Bus Arbitration
- Timing diagram

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Foreground Reading
• Stallings, chapter 3 (all of it)
- www.pcguide.com/ref/mbsys/buses/

• In fact, read the whole site!

- www.pcguide.com/

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 Finish!
Q&A

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