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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

A Method for Improving Power Grid Resilience to

Electromigration-Caused via Failures
Di-An Li, Malgorzata Marek-Sadowska, Fellow, IEEE, and Sani R. Nassif, Fellow, IEEE

Abstract— Electromigration (EM) has become a major power lifetime. For example, MTTF of a wire is a decreasing function
grid reliability problem in VLSI. In this paper, we first demon- of its current density. Power grid interconnections suffer most
strate that EM reliability analysis of a power grid can be from EM due to large current densities carried by them.
converted to analyzing EM reliability of the grid vias. We develop
a model for calculating EM lifetime of via-arrays and observe In dual-damascene copper metallization, special attention
that making power grid EM-immortal carries a huge metal area must be paid to vias, because they are where the maximum
overhead and possibly makes routing of both power and signal atomic flux divergence (AFD) occurs. According to [4], AFD
networks too difficult to complete. We propose a method for is directly associated with EM lifetime. In this paper, we
trading off power grid integrity and reliability to minimize the demonstrate that power grid EM analysis can be converted
total metal area overhead needed to achieve the desired grid
life time under power integrity constraints. Experimental results to analyzing EM reliability of the power grid vias.
show that using our method, both EM reliability and power The need for low resistance power grid leads to implemen-
integrity can be met, while the additional metal area used is tations with wide wires and multivias (via-arrays). Single large
significantly reduced. vias is not used due to via aspect ratio limit. Current density
Index Terms— Electromigration (EM), power integrity, of an individual via is reduced due to the presence of multiple
via-array. vias in an array. However, current is not evenly distributed
into vias of an array, and such vias fail at different rates due
I. I NTRODUCTION to EM. Also, when one via fails, the current redistributes into
remaining vias, which again changes the via failing rate. In this

E LECTROMIGRATION (EM) is the transport of material

caused by the gradual movement of the metal atoms in a
conductor due to the momentum transfer between conducting
paper, we develop a compact model to calculate via-array EM
lifetime and apply it to several power grid benchmarks. Our
results indicate that a huge additional metal area is required to
electrons and diffusing metal atoms [1]. If a wire undergoes eliminate all EM problems in a power grid, which may prevent
EM stress for a period of time, a void or an extrusion successful signal routing. We define the cost of improving
may be formed, which may eventually damage the wire. For power grid EM reliability as the additional metal area used in
wires manufactured in dual damascene process, void formation the improvement process.
occurs much faster than extrusion growth. To overcome the problem of a huge cost, we investigate the
EM has become a major reliability concern in modern natural redundancy of a power grid, and propose a scheme for
high-performance designs due to shrinking interconnect sizes tradeoff between power integrity and EM reliability. Using
and increasing current densities according to ITRS report on our method, both EM reliability and power integrity can be
interconnects [2]. Black’s equation [3] given by (1) estimates met, while the cost of improving power grid EM reliability is
the mean-time-to-failure (MTTF) trend for wires significantly reduced.
 
−n
Ea In Section II, we discuss EM analysis in power grid vias;
MTTF = A j e kT
. (1)
in Section III, we discuss the compact EM lifetime model
In (1), A is an experimental constant, j is the current density, for via-array; in Section IV, we discuss the tradeoff between
n is the current exponent, E a is the activation energy, k is EM reliability and power integrity; in Section V, we present
the Boltzmann constant, and T is the absolute temperature. our experimental results; finally, conclusions are drawn in
In reality, Black’s equation only indicates the dependency of Section VI.
MTTF on several factors, rather than gives the detailed wire
Manuscript received June 13, 2013; revised October 18, 2013; accepted II. V IA EM A NALYSIS
December 29, 2013. This work was supported in part by SRC under Grant
2178.001 through IBM Corporation and in part by NSF under Grant CCF- In this section, we briefly introduce the dual-damascene
115663. metallization process and describe EM mechanism in wires
D.-A. Li and M. Marek-Sadowska are with the Department of Electrical and manufactured in such a technology.
Computer Engineering, University of California, Santa Barbara, CA 93106
USA (e-mail: [email protected]; [email protected]). In a dual-damascene structure, only a single metal deposi-
S. R. Nassif is with the Austin Research Laboratory, IBM, Austin, TX tion step is used to simultaneously form the main metal line
78758 USA (e-mail: [email protected]). and the via beneath it. After the via and trench recesses are
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. etched, the via is filled in the same metal deposition step that
Digital Object Identifier 10.1109/TVLSI.2014.2301458 fills the trench. Therefore, vias are always in the same copper
1063-8210 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 2. Effective jL extraction.

test results [9] also suggest that vias are the EM critical spots,
Fig. 1. EM effect in dual-damascene copper metallization. (a) Electron therefore, in this paper, we ignore the minor diffusion paths
moving upward. (b) Electron moving downward. and focus on the dominant EM problem at via sites. At the
TABLE I anode, copper atoms are accumulated and compressed causing
C OPPER D IFFUSION PATHS AND THE A CTIVATION E NERGY a back-stress, which resists EM-induced void nucleation [10].
In extreme cases, when the compressive stress of copper atoms
at the anode exceeds a certain value, an extrusion may occur.
However, in dual-damascene Cu metallization, this would
imply that barrier layer is destroyed and copper atoms diffuse
into the dielectric layer. This is very unlikely to occur, thus in
dual-damascene copper metallization voids are considered the
main EM-caused failures [11].
(Cu) body as the upper level metal, but are separated from the Whether or not a wire is affected by EM depends not only
lower level metal by a barrier layer, which prevents copper on its current density, but also on its length. This is known
diffusion into the dielectric, as shown in Fig. 1. Typical barrier as Blech length effect [10], and any wire shorter than Blech
layer materials are Ta, TaN, TiN, and TiW. length is considered EM-immortal. Blech length effect can be
According to the basic EM theory, Cu atoms will gradually briefly described as follows: copper atoms are forced to move
move when moving electrons collide with them. In Cu metal- toward anode but cannot pass through the barrier layer, so they
lization, there are several potential atom diffusion paths. They accumulate there and create a compressive stress at the anode.
are listed in Table I [5], [6] and indicated in the bottom metal This compressive back-stress compensates the stress caused by
in Fig. 1(a). electron flow. Mathematical description of Blech length effect
From Table I, we can see that the surface and interface is given by
σmax 
are the dominant diffusion paths in copper metallization. It ( j · L)critical = ∗ (2)
has been observed that the EM defect locations are related Z eρ
to those dominant diffusion paths. In [7], EM test results where j is the current density, L is the wire length, σ max is the
show that regions around via locations are the most EM-weak. maximum back-stress that can be generated (the upper bound),
In [8], finite-element method (FEM) simulation is performed  is the atomic volume, Z ∗ is the effective valence, e is the
to investigate the nature of the asymmetries, and to identify electron’s charge, and ρ is the resistivity. When maximum
the likely failure locations in the via structures at different back-stress is generated on a wire, the corresponding jL
test conditions. Using the site with maximum AFD as the product is called the critical jL product. It is considered a
void location site, a good correlation between the model constant for a given technology. Given a current density j on a
predictions and experimental observations is obtained. Here, wire, if the wire length l < (jL)critical /j , the wire is considered
we briefly summarize the correlation between EM defect spot EM-immortal. Blech length of a wire is a decreasing function
and diffusion paths. In the wire body, due to high activation of its current density [10] rather than a constant, so a better
energy of grain boundary and bulk, the resulting AFD is much way to interpret Blech length effect is to take the jL product
smaller, which can be mathematically described as AFD = value of a wire and compare it to (jL)critical value to determine
d N/dt ≈ 0, where N is the atomic concentration and t is its EM immorality.
time. Therefore, the wire body is usually not the EM defect The above analyzes were all developed for a simple point-
site. Most of the voids nucleate near vias, since via regions are to-point wire. For a complex network topology, in which
mainly associated with surface and interface diffusion paths at least one node has a degree larger than two (a via con-
with small activation energy. Thus, near vias the nonzero tributes 1°), such as a power grid, it is nontrivial to extract
AFDs are created. In Fig. 1(a), the via acts as cathode for the the proper jL product. The problem of complex topology EM
upper layer metal. This scenario is also referred to as upstream analysis has been addressed in [12]. We briefly explain how
electron flow. For this case, a void is nucleated above the via to apply their results.
bottom barrier layer. In Fig. 1(b), the via acts as cathode for the Fig. 2 shows an example of a general complex topology.
lower layer metal. This is a downstream electron flow scenario. The nodes labeled X denote vias, the edges indicate metal
A void is nucleated below the via bottom barrier layer. In wire segments; all wires are on the same layer. Arrows denote
an extreme case, when a void spans the whole via width, the direction of electron flow. It is a complex topology since at
an open circuit is created. In practice, a typical EM failure least one node has a degree greater than two, e.g., node B, has
criterion is set to 10% of wire resistance increase. Real EM degree 4 due to incident edges AB, BC, EB, and via B. In [12],
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LI et al.: METHOD FOR IMPROVING POWER GRID RESILIENCE 3

hydrostatic stress caused by electron flow. In [12], the EM

lifetime formula (5) is developed for a wire segment. The
expression has two parts; one captures the void nucleation
time tnucleate and the other the void growth time tgrow . This
formula is used to compute EM lifetime in this paper
tlife,k = tnulceate + tgrow
 
σvoid  2 πkT 1 L c kT 1
= · · 2 + ·
ρeZ ∗ 4BD  ρeZ ∗ D ji
ji i
Fig. 3. T -shape interconnect structure. i
(5)
the effective jL product in a complex topology is given by
  where tlife,k is the EM lifetime of a wire segment k, σ void is
( j L)eff = max jk L k (3) the critical stress required to nucleate a void, ji is the current
k density of each wire segment i (including the wire segment k
where jk is the current density and L k is the length of itself) that is connected to the cathode via of wire segment k,
an individual wire segment in a complex topology. The B is the effective modulus of the materials surrounding the
sum is taken over all possible paths, with (jL)eff being the metal, L c is the critical void length, and T is the temperature.
maximum of them. The effective jL product matches well D is the effective diffusivity, computed using (6), where w is
the experimental results in [13]. In a complex topology, such the wire width and h is its height
as a power grid, the approach to extract the effective jL can Ea W
be described as follows: for any power wire segment, find D = D0 · e− kT · . (6)
h
the longest consistent current path that contains it, originates 
and terminates at a via or terminal location, and compute the
It should be noted that the term i ji = j1 + j2 − j3
(considering the current direction) equals to the current density
sum of individual jL products of all wire segments along the
through the cathode via, denoted by jvia,cathode. It can be
path. For example, assume in Fig. 2, jAB L AB > jEB L EB and
observed that void nucleation time is inversely proportional
jCD L CD > jCF L CF , following the above approach, we have (4).
to jvia,cathode2 and void growth time is inversely proportional
A consistent current path does not extend through vias due
to jvia,cathode. Therefore, (5) can be rewritten as
to the sealing property of the barrier layer at the via bottom
1 1
j L AB,eff = j L BC,eff tlife,k = α · 2
+β ·
jvia,cathode jvia,cathode
= j L CD,eff
where
= j L pathABCD  2
σvoid  πkT
= jAB L AB + jBC L BC + jCD L CD α= ·
ρeZ ∗ 4BD
j L EB,eff = j L pathEBCD
L c kT
= jEB L EB + jBC L BC + jCD L CD β = . (7)
ρeZ ∗ D
j L CF,eff = j L pathABCF It is clearly shown in (7) that EM reliability analysis of
= jAB L AB + jBC L BC + jCF L CF . (4) a wire segment is related to the current density through
Assume jLpathABCD > jL critical , jLpathABCF < jL critical , and its cathode via, therefore power grid EM analysis can be
jLpathEBCF < jL critical; we can conclude that wire segments converted to, or is equivalent to analyzing EM reliability of
AB, BC, and CD are EM-mortal, while EB and CF are the vias in the power grid.
EM-immortal. This can be further translated to the statement It should be noted that (7) only considers a single via.
that vias A, B, and C are EM-mortal for wire segments AB, In practice, power grid wires on adjacent layers are mostly
BC, and CD, respectively, and via E is EM-immortal for connected through via-arrays. Experimental results in [15]
wire segment EB since EM lifetime of a wire segment is show that via-array EM behavior is quite different from a
actually associated with its cathode via (the status of vias single via, therefore it is important to develop a model for
D and F need to be determined by wire segments on other computing EM lifetime of a via-array.
layers, since they are not cathode vias of segments CD or
CF). We will briefly explain this point below. III. C OMPACT VIA -A RRAY EM L IFETIME M ODEL
The via-guided EM analysis is validated in both EM behavior of a via-array differs from that of a single via
[12] and [14]. Consider a T shape interconnect structure with a due to nonuniform current distribution within the array. This
via in the center, as shown in Fig. 3. Arrows denote the current causes individual vias to fail at different rates. Lin et al. [15]
flow direction. Assume the via is EM-mortal. We will focus and Raghavan and Tan [16] have shown this effect. In this
EM analysis on that via. The AFD inside the wire segment paper, we perform several FEM-based simulations to observe
is assumed to be zero everywhere except at the via location. the current flow in a via-array and develop a quantitative
At the via location, a void will nucleate and grow due to method to determine via-array current distribution.
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 6. Equivalent circuit for computing forward gradient.

each via, given the wire dimensions, applied voltage and via
resistance Rvia .
Using superposition property of a resistive circuit, we solve
the system each time with only one voltage source present and
all others shorted to ground. Due to symmetry of the system,
when only Va is applied, I1_a_via = I13_a_via , I2_a_via =
I14_a_via , and so on, where Ii_a_via denotes the current flowing
through via i when Va is applied. The currents I1_a_via ,
I2_a_via , I3_a_via , and I4_a_via are different due to the voltage
gradient between left and right end of the horizontal wire. We
define this as the forward voltage gradient of Va , denoted by
f = V1a /V2a , where Via is defined as voltage of via i  ’s top
surface when Va is applied. The currents I1_a_via , I5_a_via , are
Fig. 4. Even/uneven current distribution in a via-array. (a) 3-D orthogonal
wire structure with 4 × 4 via-array. (b) Even distribution. (c) Uneven
different due to the voltage gradient between the left end of
distribution. (d) Extreme uneven. a horizontal wire and the bottom end of a vertical wire. This
is defined as the lateral voltage gradient of Va , denoted by
l = V1a /V5a .
We compute f using resistance divider shown in Fig. 6.
Rvia + R is the equivalent resistance from a via to ground and
R = R B //RT . We have
V1a 3r + R R I1_a_via
f = = = . (8)
V2a 2r + R R I2_a_via
The lateral voltage gradient l is computed using resistances
Fig. 5. 4 × 4 via-array. (a) Grid model. (b) Shortest paths.
approximated by the shortest paths shown in Fig. 5(b).
There are two shortest length paths: path_5 and path_1, and
A 3-D orthogonal wire structure with 4 × 4 via-array is only one of them pass through via 5. Thus, the resistance
built, as shown in Fig. 4(a). We change the currents flowing difference between path_5 and path_1 is r /2. We have
in each wire segment, and record the current densities through V1a Rtotal_path RL + RB
the horizontal cross-sectional plane of multiple vias, as shown l= = = . (9)
V5a Rtotal_path − r/2 R L + R B − r/2
in Fig. 4(b)–(d). It can be observed that when all wire currents
are identical as in Fig. 4(b), current distribution into the vias is Based on this analysis, we can express all via currents first
uniform. Greater differences among the wire segment currents in terms of I1_a_via and the value of I1_a_via can be derived
cause the current split into the vias to be more nonuniform. using the forward and lateral voltage gradients.
This effect can be explained by the differences among path Experimental results indicate that the maximal inaccuracy
resistances through different vias. A pure resistive mesh is is <1% of the total current value. This error is contributed
created in SPICE, and the simulation results validate this mostly by the inaccuracy of forward gradient computation.
observation. Based on the resistive mesh model, a fast current Our method can be easily extended to M × N via-array by
distribution into each via can be determined. A detailed modifying the equivalent circuit and shortest paths.
description can be found in [17]. We briefly summarize the There is also a local current crowding effect even in a single
approach below. via. Tan et al. [18] investigate this phenomenon, and observe
Consider two orthogonal wires on Metal 1 and Metal 2 that the effect is due to the much larger average current density
connected through a 4 × 4 via-array composed of equal size along the interface between the liner and via. This behavior
vias uniformly spaced in horizontal and vertical directions, affects the EM defect location around the via region.
connected through a via-array, as shown in Fig. 5(a). The Due to the variation of the microstructure inside each
lengths of wires extending from the intersection area are L T , interconnect, same current density may result in different
L B , L L , and L R (assume L T = L B and L L = L R ) and their EM lifetimes, therefore the overall EM lifetime of a via-
resistances are RT , R B , R L , and R R . The unit length of mesh array is not uniquely determined, even with known current
gird is d and its unit resistance is r . Voltages Va , Vb , Vc , and distribution. To account for this variation, a large number
Vd are applied at the wire ends. Vd is set to be the reference of simulations are required to obtain the overall via-array
(Vd = 0). Our objective is to compute current flowing through EM lifetime distribution. A complete via-array EM lifetime
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LI et al.: METHOD FOR IMPROVING POWER GRID RESILIENCE 5

Fig. 7. Timeline for via p EM failure. (a) No void before t p−1. (b) Void
nucleates at t ∗ .

distribution model is given in [17], and is verified against

real measurement results in [9], but is highly computationally
expensive to obtain. Current density can still be used as a
criterion at a system level to predict the average or most prob-
able EM lifetime. Therefore, for quick full-chip EM analysis
purpose, we propose a simple model based on the worst-
current fail-first assumption. It assumes that a via in an array
with largest current density will fail first based on the fact that
at a system level, current density can be used to represent the
average EM lifetime as in Black’s equation (1) or the physics-
based formula (7). This assumption ignores the probability
distribution of EM lifetime, but only focuses on the most
Fig. 8. Via-array failure computation procedure.
probable EM lifetime. Before we proceed, we define several
useful terms: describes the condition of no void nucleating before t p−1 is
t p : the failure time of pth via given in (11)
t f p : the time increment between ( p−1)th and pth via ⎧ L c kT
⎪
⎨ A1 = β = ρeZ ∗ D
failure, t f q = t p − t p−1  2

p−1 
p−1 (10)
t ∗ : the void nucleation time. ⎪ A = α − t f j 2 = σvoid  πkT
· 4BD − t f q jq2
⎩ 2 q q ρeZ ∗
The first via will fail after tf1 . Then, current redistributes q=1 q=1
into the remaining vias. Both the initial current distribution and 
p−1  2
σvoid  πkT
all later redistributions can be obtained using the fast current t f q jq2 < · . (11)
ρeZ ∗ 4BD
distribution model. However, because those later failing vias q=1
have already been stressed by currents flowing through them Referring to Fig. 7(b), assume the void nucleates at t ∗ (tk−1 <
previously, therefore (5) cannot be simply applied to compute t ∗ < tk ), then the remaining atomic flux amount A2 propor-
their lifetimes. We provide a translated lifetime computation tional to quadratic current density stress and A1 proportional
given in (14) to account for any previous stress that has to linear current density stress are given in (12). Since at t ∗ ,
been exerted on a via. We briefly explain it in the following. a void just nucleates, so we have (13). Overall the expected
Suppose that the pth via is now to fail. The timeline in Fig. 7 failure time t p is given in (14)
shows the sequence of events leading to the failure of via p: ⎧
ti are the failure times of a sequence of vias up to the pth via ⎪
⎨  L c kT ∗

p−1
A1 = ρeZ ∗ D − (tk − t ) · jk − t f q jq
(i = 1 to p), tfi = ti − ti−1 is the time increment between (12)
⎪
⎩ A = 0
q=k+1
(i −1)th and i th via failure, ji is the current density through 2
the pth via during the time increment tfi –its value is changed

k−1  
each time a new via fails. Fig. 7(a) shows the situation when ∗ σvoid  2 πkT
t f q jq + (t − tk−1 ) jk =
2 2
· (13)
up to time t p−1 , a void has not nucleated yet; Fig. 7(b) shows ρeZ ∗ 4BD
q=1
the case when a void has nucleated before t p−1 . 
Referring to (7), let α and β be the atomic flux amounts that A2 · 1
j p2
+ A1 · jp ,
1
if (8)
will be consumed at a rate of j 2 and j , respectively. In the tp = (14)
A1 · j p , else.
1
case shown in Fig. 7(a), up to t p−1 , via p is experiencing
a stress proportional to the square of current density. The The flowchart in Fig. 8 shows how the via-array failure and
remaining atomic flux amount A2 that will be consumed at lifetime computation works.
a rate proportional to the square of current density and the We use the compact EM lifetime model to analyze the via-
atomic flux amount A1 that will experience linear current array EM reliability in power grids. We observe that our model
density stress are given in (10). The mathematical term that predicts more via-arrays with potential EM problems than the
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6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 9. Counter-intuitive via-array EM reliability. (a) Even current distribu-

tion. (b) Uneven current distribution.

Fig. 11. C4 bump locality effect on via-array current.

lifetime model described in Section III for this purpose is

possible, but is computationally expensive. In this section,
we provide a fast search technique for potentially mortal via-
arrays to speed up the analysis.
We first briefly explain the circuit-level model of the power
grid used in this paper. We assume that power is delivered
Fig. 10. Lifetime for a single via, via-array with even current distribution
and via-array with uneven current distribution.
through a controlled collapse chip connection (C4) package.
Wires and vias are modeled as resistors, the external voltage
model based on even current split into vias assumption. This is supplies are modeled as ideal voltage sources, and switching
because a via-array with a smaller total current density but transistors are modeled as current sources. Nassif [19] provides
unevenly split may have worse EM reliability than a via-array more details of this model. We also assume EM to be a
with greater current and uniform current distribution. This long-term degradation effect; therefore, we use the worst case
counter-intuitive conclusion is demonstrated using the example dc current in our analysis. Note that with increasing current
shown in Fig. 9. density and decreasing wire dimensions, it is possible that
In Fig. 9, the total currents through the via-arrays are 32 mA transient current behavior will have greater effect on EM
in case (a) and 25.6 mA in case (b). In Fig. 9(b), the total reliability. In such cases, more detailed information of current
current splits very unevenly into individual vias; therefore, waveforms is required for EM analysis and discussion on this
although its total value is less than the threshold value, it still topic is beyond the scope of this paper. In this paper, we
cannot meet the EM reliability requirement. On the other hand, consider only the case of a uniform temperature on the power
in Fig. 9(a), although the total current density is greater than grid. In practice, temperatures across the whole power grid can
in the case of Fig. 9(b), the current splits evenly into the vias, be nonuniform. In such a case, the complete thermal profile
resulting in a better EM reliability. The via-array structures of power grid is required to account for temperature effects
are simulated using the compact via-array EM lifetime model on EM reliability. Also, the power grid current distribution
with the worst-via-fails-first assumption discussed above. varies according to circuit working mode or transistor activity
In Fig. 10, we show the simulated EM lifetime for a factors, and the power grid EM behavior will be very different.
single via with I = Ith , even current distribution via-array In practice, some averaged or effective current for each power
with Itotal = Ith [corresponding to the example in Fig. 9(a)] grid segment should be used to evaluate the overall EM
and uneven current distribution via-array with Itotal < Ith reliability. Li and Marek-Sadowska [20] propose a method to
[corresponding to the example in Fig. 9(b)]. On the vertical obtain such effective current. In this paper, we assume that the
axis is the EM lifetime in arbitrary units, which is a typical effective current is already given.
denotation for comparing EM lifetime. It can be observed We develop a fast via-array search approach by taking
that single via and the via-array with even current distribution advantage of the C4 package. According to [21], C4 package
have similar EM lifetimes, whereas the via-array with uneven provides a strong spatial locality. A C4 bump acts as a low
current distribution, although carries a smaller total current, impedance path for local die currents to flow off-chip and
has much worse EM lifetime. therefore, currents are naturally attracted to the nearest bump.
This effect is verified on the industrial C4 package design.
IV. FAST VIA -A RRAY S EARCH In Fig. 11, we show a similar result from one of the IBM
Now, we discuss the full-chip power grid via-array EM power grid benchmarks. The solid nodes denote C4 bumps, the
analysis. Direct application of the compact via-array EM contour lines denote via-array currents, and the arrows denote
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LI et al.: METHOD FOR IMPROVING POWER GRID RESILIENCE 7

satisfy EM requirement, we have

2 jvia_av < jth0 ⇒ jvia_av < 0.5 jth0. (15)
On the via layer, we start from vias beneath C4 bumps, since
they carry the greatest currents as shown in Fig. 11. The fast
search based on step expansion as in Fig. 12 will terminate if
the comparison results in jvia_av < 0.5 jth0 for all vias in the
same search step. Note that we will skip all via-arrays that
are labeled EM-immortal during Blech length effect check.
We collect via-arrays for which jvia_av > 0.5 jth0 and check
if they are actually EM-weak by using compact via-array EM
lifetime model with worst-case-fail-first assumption. We later
Fig. 12. Fast via-array search. provide experimental results of the quick search in Table II,
Section VI.

V. P OWER I NTEGRITY V ERSUS EM R ELIABILITY

Power grid must satisfy the integrity and reliability require-
ments. For power integrity, typically we need to guarantee
that the maximum voltage drop on a current load is below
a threshold value, i.e., Vmax ≤ Vth . Note that using
uniform threshold voltage across the entire chip may be a too
strong criterion. For some nontiming critical components, their
supply voltage can drop more than others. This gives designers
an opportunity for nonuniform threshold voltage optimization.
However, in this paper, due to lack of timing information, this
idea is not explored. For EM reliability, typically all power
grid interconnections are guaranteed to have an EM lifetime
Fig. 13. Extreme triangular distribution and half-biased distribution. larger than a required value (e.g., ten years), i.e., tlife ≥ treq .
With current density increasing, both power integrity and EM
the current change trend, pointing to the current decreasing reliability become more difficult to achieve. However, due
direction. The contour maps of via currents show similar to the near quadratic dependency of EM on current density
behavior on all metal layers. It can be seen that via-arrays compared with linear dependency on voltage drop, EM is
directly beneath C4 bumps carry largest currents and those expected to be a dominant constraint or bottleneck concern for
further away from C4 bumps carry progressively less currents. power grid design. For example, to eliminate all EM problems
Instead of performing a full search of all via-arrays in the in power grid benchmark IBM PG 2, the total metal area
power grid, we propose a quick search that will start from overhead can be as large as 16.94% and the subsequent signal
those directly beneath C4 bumps, and then expand one step network routing could be difficult to complete. EM failures
at a time to the neighboring via-arrays as shown in Fig. 12. may lead to open connections, which will cause an increase of
In Fig. 12, the search will expand as ➀→➁→➂. . . At each the power grid voltage drop. However, not all EM failures will
search step, we check the via-array average current densities cause power grid integrity violations. Due to grid redundancy,
jvia_av . Assume jth0 is the EM threshold current density for it is unnecessary to guarantee all power interconnections to
a single via; if jvia_av < 0.5 jth0, via-array is considered EM- have EM lifetime longer than treq . We illustrate this point using
safe. The validity of this filter is shown in Fig. 13. the example in Fig. 14.
In Fig. 13, we show three line segments ➀➁➂ of current In Fig. 14, we record voltage changes for nodes A through E
distributions, with the same amount of total current, i.e., the when the dashed resistor is removed. If our target is to
area below each segment is that same. Due to resistive effect, maintain the grid voltage at or above the 0.9 V level, then
the uneven current distribution in a via-array is linear. The the grid still satisfies the integrity constraints after the dashed
segment ➀ shows a general uneven current distribution where resistor failed. The result indicates that the redundancy of
some vias carry less current, but other carry more. In the a power grid helps to retain the node voltages above the
extreme case, vias at one end carry zero current density, and threshold value even if EM failures occur on some of the
on the other end, vias carry current the density of 2 jvia_av , as power interconnects.
shown by segment ➁ (gray triangular distribution) in Fig. 13. This example clearly shows that eliminating all EM prob-
To further bias this distribution, we consider ideally only half lems on power interconnect segments are not necessary.
of the vias carry current, and each of them carries uniform This observation inspires us to make tradeoff between power
current of density 2 jvia_av as shown by segment ➂ (the dotted integrity and EM reliability. Such tradeoff space has not been
half-biased distribution) in Fig. 13. The half-biased distribution explored before, but is theoretically feasible and is beneficial
therefore should yield worse EM lifetime than the triangular to designers since it saves metal area and routing resources.
distribution. Since half of the vias uniformly carry 2 jvia_av , to Therefore, we explore this tradeoff on several power grid
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

TABLE II
EM A NALYSIS R ESULTS AND C OMPARISONS

Fig. 16. Multiple strengthening on upsized track.

integrity is achieved. Merged adjoint network approach [22]

is used to calculate the via-array voltage drop sensitivities. It
is briefly explained below.
First, we remove all EM-weak via-arrays from the original
power grid and simulate this residual network. In this paper,
power grid simulations are done using the fast power grid
solver SEVA [23]. All nodes with V > Vth are marked
as target nodes. An empty set of target nodes means that the
Fig. 14. Power grid redundancy. power grid is robust even when all EM-weak via-arrays fail
and there is no need to strengthen any of them. Otherwise a
merged adjoint network is created based on several modifica-
tions to the original network. The modifications are: 1) all
voltage and current sources are set to zero and 2) current
sources of 1 A are attached to all target nodes. Merged adjoint
network is simulated and the merged voltage drop sensitivity
of via-array i that connects node A and node B is calculated
using the following formula:
Fig. 15. Power grid redundancy. (a) Original circuit. (b) Strengthen ∂ Si
via-array 1. (c) Strengthen via-array 2. = (V A − V B )(V A − V B )
∂gi

benchmarks, and compare our results to those without such S= V j . (16)
a tradeoff.
j ∈ target
A naïve way is to improve the interconnect segments with
the shortest EM lifetimes. However, this method can be where Si is the summation of voltage changes on all target
inefficient. For example, in Fig. 15(a), via-array 1 has lifetime nodes if the conductance of via-array i changes, (∂ Si /∂gi ) is
of five years and via-array 2 has lifetime of seven years. Both the merged voltage drop sensitivity of via-array i , gi is the
of them are EM-weak, if we assume required EM lifetime is conductance of via-array i , V and V  are the node voltages of
ten years. A naïve way would be to strengthen via-array 1 in the original and merged adjoint networks, respectively. Later,
Fig. 15(b) such that it could last for ten years. However, when in this paper, merged voltage drop sensitivity is abbreviated to
via-array 1 fails after seven years, the power grid still fails sensitivity, if not specified otherwise.
because load B does not have enough power supply voltage. To strengthen a via-array, we need to upsize uniformly the
On the other hand, realizing the fact that via-array 2 is critical entire track that the via-array is on, in such a way that more
to load B whose supply voltage is originally lower then load A, vias can be inserted. The via insertion does not change the
one would prefer to strengthen via-array 2 to last at least ten uneven current distribution, but it alleviates current density
years as in Fig. 15(c). In this case, even when via-array 1 fails through each via, thus still improves the EM reliability. In this
after five years, the overall power integrity is retained and the paper, we follow the track-based upsizing approach [24] for
grid can last for ten years as required. via-array strengthening. In general, when a wire is upsized, its
We formalize this observation and define via-array sen- dominant EM driving force may change [25]. However, in this
sitivity measured as the total amount of additional voltage paper, we assume that the track width upsizing is kept within a
drop caused by the via-array removal. Obviously, a better certain range such that the dominant EM driving force remains
choice would be to sort EM-weak via-arrays in descending the same. Since each time we strengthen a via-array, we upsize
order of their voltage drop sensitivities not in the order of the entire track, it is possible that more than one EM-weak
EM-weaknesses and strengthen them in that order until power via-array can be strengthened as in Fig. 16. Therefore, we will
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

LI et al.: METHOD FOR IMPROVING POWER GRID RESILIENCE 9

Fig. 18. Thevinen equivalent circuit.

Fig. 17. Observations of the current flow behavior on the grid. (a) Via KCL. According to Kirchhoff’s current law (KCL), the current
(b) Current change trend. (c) Top-down view.
flowing into a network equals to the current flowing out of
the network. In Fig. 17(a), the dashed boxes can be viewed
first translate the via-array sensitivity list to track sensitivity as networks, therefore Iloads = I12 = I23 = · · · . In Fig. 17(b),
list by collecting all sensitivities of EM-weak via-arrays on the upsized via provides a less resistive path between the
the track, and choosing the track for upsizing based on the two metal layers, therefore it carries more current (denoted
track sensitivity. by a + sign). However, the current density through the
The objective of retaining power integrity within the upsized via is decreased. This can be proved using Thevenin’s
required lifetime while minimizing the cost of extra metal area theorem [26].
can be stated as Consider Fig. 18, a power grid in our case is a linear electri-
 cal network with voltage and current sources and resistances.
min A = wi · li It can be replaced at terminals A-B by an equivalent voltage
i ∈ {upsized tracks} source Ueq in series connected to an equivalent resistance
 Req . The resistor connecting A-B is the via-array that is to
s. t.∀i ∈ {power grid nodes} : Vi ≤ Vth
be upsized.
∀ j, k ∈ {power tracks} ∧ j//k : d jk ≥ dmin (17) Assume that the horizontal cross-sectional area of the via-
where A is the total extra metal area; wi is the width array is upsized to α (α > 1) times the original area. The
 resistance of the via-array will be 1/α of the original value.
increase of track i ; li is the length of track i ; Vi is the
voltage drop on node i after all EM failures occur within the This is mathematically stated in (18). In (18), Iv and Iv
required lifetime; Vth is the threshold voltage drop, defined are the via-array currents before and after upsizing, jv and
as Vth = 10%Vdd in our case; djk is the distance between jv are the via-array current densities before and after upsiz-
track j and track k; and dmin is the minimum allowed distance ing, A is the via-array horizontal cross-sectional area before
between two tracks by the process technology. A first thought upsizing
to obtain a solution would be using greedy algorithm that by ⎧
⎨ Iv = Ueq1 > Iv = R U+R eq
iterations of selecting and upsizing each time a track with the Req + α Rv eq v
(18)
⎩ jv = Ueq1 · 1 = Ueq Ueq
greatest sensitivity until power integrity is achieved. In this αA
Req + α Rv A·(α Req +Rv ) < jv = A·(Req +Rv ) .
way, in each iteration, we obtain the local optimal solution
for the current condition; and it is expected to achieve a near Since the total amount of current between two adjacent
optimal solution at the end. However, two concerns would layers is constant, and the upsized via will carry more current,
arise during each iteration step. First, after each step the sensi- so other vias will carry less current (denoted by − sign),
tivity of remaining via-arrays would change; second, the global the amount of current decrease will gradually diminish as the
current distribution of power grid interconnects would change, distance between the other vias and the upsized via increases,
which may create new EM violations or eliminate some since the via that is the nearest to the upsized via will be
of the existing ones. So the true greedy algorithm requires affected the most. Fig. 17(c) shows the top view of a power
updating of track sensitivity list and power grid global current grid. When a track and the vias beneath it is upsized, it
distribution by simulating the upsized power grid at each decreases the current flowing through their first immediate
iteration step. The huge computation time prohibits us from neighboring vias; the effect on other vias on the same layer
taking this path. Instead, we apply a heuristic approach based is negligible. In Fig. 17(b), currents flowing through vias
on the following observations: 1) the total current flowing on different via layers may increase (denoted by ? mark),
through all vias between any two adjacent metal layers is equal especially those beneath and above the upsized via. This may
to the total amount of current drawn by all current loads; 2) the potentially create new EM violations. However, at this point,
current flowing through the via-arrays upsized at the present we will put this problem aside, and later provide a simulation-
iteration step increases, but the current density decreases; and based check to resolve it.
3) the current flowing through all other via-arrays that are Based on these observations, our heuristic greedy upsizing
on the same via layer as the upsized ones decreases with the Algorithm 1 is summarized below followed by brief expla-
largest current decrease on the first immediate neighboring nations. In the algorithm, SS is the track sensitivity list; we
track. We justify these observations below. first translate via-array sensitivity into track sensitivity. Then,
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Algorithm 1 Heuristic Greedy Track Upsizing

we sort the track sensitivity list and upsize the track with the VI. E XPERIMENTAL R ESULT
greatest sensitivity. The test criterion in step 2 is a necessary We first perform EM analysis on several IBM power grid
condition since if the total amount of voltage drop increase benchmarks. The analysis includes jL filter, fast via search,
on the target nodes is not satisfied, there is at least one power and via-array EM lifetime check. The results are summarized
integrity violation among the target nodes. We continue the in Table II. The column labeled #v gives the total number of
track upsizing until the criterion is reached to avoid the time via-arrays in the benchmark; the column labeled #jL lists the
consuming power grid simulation. In step 8, we provide a sim- number of via-arrays that are EM-mortal due to Blech length
ple track sensitivity updating approach. First, the upsized via- violation; the column labeled #fast provides the number of
array lies on both horizontal and vertical tracks; if one track is potentially EM-weak via-arrays among EM-mortal ones that
upsized, the via-array sensitivity contribution to the other track were found during the fast via search; the column labeled
is subtracted. Second, according to the heuristic observation, #EM-weak gives the number of via-arrays that are finally
the current through the first immediate neighboring via-array identified as EM-weak during the via-array EM lifetime check;
to the upsized track will be significantly reduced and will the column labeled #EM-weak-even lists the EM-weak via-
be considered EM-safe, so its sensitivity contribution is sub- arrays found assuming current is evenly distributed into a via-
tracted. This heuristic step may introduce new EM-violations, array; columns labeled t_fast and t_full are runtimes with fast
therefore to guarantee the robustness of the algorithm, in via search and with direct full via search (jL filter time is
steps 10 and 11, power grid is simulated to capture the possible not included); the column labeled t_improve is the runtime
newly created EM-violations and verify power integrity. Even- improvement with and without fast via search. We make sev-
tually the algorithm will either fail if after all possible power eral observations. First, the jL filter is very effective in quickly
track upsizing, power integrity is still not achieved, or other- sifting out EM-immortal wires. On the benchmarks we have
wise succeed in finding a suboptimal solution for minimizing tried, the filtering rate reaches up to 99.96% (IBMPGNEW2)
extra metal area used to achieve power integrity and EM in the best case, and in worst case is still 78.63% (IBMPG2).
reliability. Second, the fast via search, in general, is useful for further
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

LI et al.: METHOD FOR IMPROVING POWER GRID RESILIENCE 11

TABLE III
P OWER G RID T RACK U PSIZING R ESULTS AND C OMPARISONS

Fig. 19. Visualized track upsizing results. (a) Upsizing for IBMPG2 layer 4–5. (b) Upsizing for IBMPG3 layer 2–3. (c) Upsizing for IBMPG4 layer 3–4.
(d) Upsizing for IBMPGNEW2 layer 1–2.

fast filtering out of non-EM-weak via-arrays, however, for a respectively; the column labeled A_improve is the area
specific case (IBMPG4) it does not help, since all EM-mortal improvement of greedy upsizing compared to full or optimal
via-arrays are eventually identified as EM-weak. Third, assum- upsizing; the column labeled t_greedy and t_opt are runtimes
ing even current split into individual vias in the array, much of greedy and optimal upsizing, respectively; the column
fewer via-arrays are identified as EM-weak, which indicates labeled t_improve is the runtime improvement of greedy
that assuming the even current distribution model misses many upsizing compared to optimal upsizing.
EM-weak via-arrays; the miss rate in the worst case reaches We make several observations. The number of via-arrays
up to 76.98%. Forth, the runtime improvement is significant that are upsized using greedy algorithm is much smaller than
for those cases when fast via search filtering rate is not zero; when full upsizing is evoked, but a little greater than in the
the improvement can reach up to 83.05% in the best case. case of optimal upsizing. The corresponding area comparisons
Next, we perform power track upsizing on the IBM power are also provided. For greedy algorithm, the area improvement
grid benchmarks. The results are summarized in Table III. We compared with full upsizing is significant, and in the best case
compare the results for full upsizing, greedy upsizing, and reaches up to 95%. As expected, in area improvement, the
optimal upsizing. Full upsizing strengthens all EM-weak via- optimal exceeds the greedy upsizing, but with a very small
arrays; greedy upsizing applies our heuristic greedy algorithm; advantage. In the worst case, the results of greedy upsizing
optimal upsizing is based on greedy algorithm, but it includes are only 6% worse than the optimal.
a power grid simulation to update sensitivity list and possibly The greedy upsizing algorithm’s runtime is almost an order
adds new EM-weak via-arrays each time a power track is of magnitude faster than that of the optimal algorithm. In
upsized. In Table III, the column labeled target is the number Fig. 19, we show several visualized power track upsizing
of target nodes found in the benchmark; the column labeled results comparing the greedy and full upsizing. X marks
v_greedy is the number of via-arrays that are strengthened denote those EM-weak via-arrays that are critical to power
using heuristic greedy algorithm; the column labeled #v_opt integrity; O marks denote those that are not.
is the number of via-arrays that are strengthened using Finally, we provide a comparison between our via-centric
true optimal upsizing; the columns labeled A_total, A_full, and a traditional wire segment-centric EM analysis. The tradi-
A_greedy, and A_opt are total metal area of the power grid and tional wire segment-centric EM analysis ignores the fact that
extra metal area used for full, greedy, and optimal upsizing, vias are the locations where AFD occurs, which eventually
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

12 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

TABLE IV [6] J. Lienig, “An introduction to electromigration-aware physical design,”

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helpful discussions.

R EFERENCES Di-An Li received the bachelor’s degree from Zhe-

jiang University, Hangzhou, China, and master’s and
[1] [Online]. Available: http://en.wikipedia.org/wiki/Electromigration Ph.D. degrees from the University of California,
[2] [Online]. Available: http://www.itrs.net/reports.html Santa Barbara, CA, USA.
[3] J. R. Black, “Electromigration—A brief survey and some recent results,” He was a Research Assistant with VLSI CAD
IEEE Trans. Electron Devices, vol. 16, no. 4, pp. 338–347, Apr. 1969. Lab, University of California, Santa Barbara, from
[4] D. Dalleau, “3-D time-depending simulation of void formation in met- 2008 to 2013. In 2013, he joined Qualcomm ASIC
allization structures,” Doctoral thesis, Dept. Electr. Eng. Inf. Technol., Design Automation Department, San Diego, CA,
Univ. Hannover, Hannover, Germany, 2003. USA. His current research interests include on-chip
[5] B. Li, “Introduction to electromigration in advanced interconnects,” interconnect electromigration reliability and power
in Proc. Int. Rel. Phys. Symp., 2009. grid analysis.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

LI et al.: METHOD FOR IMPROVING POWER GRID RESILIENCE 13

Malgorzata Marek-Sadowska (F’97) received the Sani R. Nassif (F’08) received the bachelor’s degree
M.S. and Ph.D. degrees from the Technical Univer- from the American University of Beirut, Beirut,
sity of Warsaw, Warsaw, Poland. Lebanon, and the master’s and Ph.D. degrees from
She was an Assistant Professor with the Tech- Carnegie-Mellon University, Pittsburgh, PA, USA, in
nical University of Warsaw, from 1976 to 1982. 1980, 1981 and 1985 respectively.
From 1982 to 1990, she was a Research Engineer He was with Bell Laboratories, Berkeley Heights,
with the Electronics Research Laboratory, University NJ, USA, until 1996 and the IBM Austin Research
of California, Berkeley, CA, USA. In 1990, she Laboratory, Austin, TX, USA, until 2013. He is now
was a Professor with the Department of Electrical a CEO of Radyalis, a firm focused on applying EDA
and Computer Engineering, University of California, techniques in the area of Cancer radiation therapy.
Santa Barbara, CA, USA. He has authored numerous conference and journal
She was an Associate Editor from 1991 to 1993, and Editor-In-Chief of publications, received five Best Paper awards (IEEE Trans. CAD, ICCAD,
IEEE T RANSACTIONS ON CAD from 1993 to 1995. She is currently an DAC, ISQED and ICCD), and given Keynotes at conferences like ASPDAC,
Associate Editor of IEEE T RANSACTIONS ON VLSI. ESSCIRC, BMAS, SISPAD, SEMICON, PATMOS, SELSE and VLSI-SOC.
He is the president of the IEEE Council on EDA, a member of the ACM and
the AAAS, and an IBM Master Inventor with more than 75 patents.