AN2606

Application note
STM32 microcontroller system memory boot mode

Introduction
The bootloader is stored in the internal boot ROM (system memory) of STM32 devices, and is
programmed by ST during production. Its main task is to download the application program to the
internal Flash memory through one of the available serial peripherals (such as USART, CAN,
USB, I2C, SPI). A communication protocol is defined for each serial interface, with a compatible
command set and sequence.
This document applies to the products listed in Table 1, referred to as STM32 throughout the
document. It describes the supported peripherals and hardware requirements to consider when
using the bootloader of STM32 devices. The specifications of the low-level communication
protocol for each supported serial peripheral are detailed in separate documents (see Section 2).

Table 1. Applicable products

Type Part number or product series
STM32F0 Series: STM32F03xxx, STM32F04xxx, STM32F05xxx, STM32F07xxx, STM32F09xxx
STM32F1 Series
STM32F2 Series
STM32F3 Series: STM32F301xx, STM32F302xx, STM32F303xx, STM32F318xx, STM32F328xx,
STM32F334xx, STM32F358xx, STM32F373xx, STM32F378xx, STM32F398xx
STM32F4 Series: STM32F401xx, STM32F405xx, STM32F407xx, STM32F410xx, STM32F411xx,
STM32F412xx, STM32F413xx, STM32F415xx, STM32F417xx, STM32F423xx,
STM32F427xx, STM32F429xx, STM32F437xx, STM32F439xx, STM32F446xx,
STM32F469xx, STM32F479xx
STM32F7 Series: STM32F722xx, STM32F723xx, STM32F732xx, STM32F733xx, STM32F745xx,
STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx, STM32F769xx,
STM32F777xx, STM32F779xx
STM32G0 Series: STM32G030xx, STM32G031xx, STM32G041xx, STM32G07xxx, STM32G08xxx
STM32G4 Series: STM32G431xx, STM32G441xx, STM32G47xxx, STM32G48xxx
STM32H7 Series: STM32H72xxx, STM32H73xxx, STM32H74xxx, STM32H75xxx, STM32H7A3xx,
Microcontrollers STM32H7B3xx
STM32L0 Series
STM32L1 Series: STM32L100xx, STM32L151xx, STM32L152xx, STM32L162xx
STM32L4 Series: STM32L431xx, STM32L432xx, STM32L433xx, STM32L442xx, STM32L443xx,
STM32L451xx, STM32L452xx, STM32L462xx, STM32L471xx, STM32L475xx,
STM32L476xx, STM32L486xx, STM32L496xx, STM32L4A6xx, STM32L4R5xx,
STM32L4R7xx, STM32L4R9xx, STM32L4S5xx, STM32L4S7xx, STM32L4S9xx,
STM32L412xx, STM32L422xx, STM32L4P5xx, STM32L4Q5xx, STM32L431xx,
STM32L432xx, STM32L433xx, STM32L442xx, STM32L443xx, STM32L451xx,
STM32L452xx, STM32L462xx, STM32L471xx, STM32L475xx, STM32L476xx,
STM32L486xx, STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx,
STM32L4R9xx, STM32L4S5xx, STM32L4S7xx, STM32L4S9xx, STM32L412xx,
STM32L422xx, STM32L4P5xx, STM32L4Q5xx
STM32L5 Series: STM32L552xx, STM32L562xx
STM32WB Series: STM32WB50xx, STM32WB55xx
STM32WL Series: STM32WLE5xx

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Contents AN2606

Contents

1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2 Related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 General bootloader description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1 Bootloader activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Bootloader identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 Hardware connection requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4 Bootloader memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.5 Bootloader UART baudrate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.6 Programming constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.7 ExitSecureMemory feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5 STM32F03xx4/6 devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6 STM32F030xC devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7 STM32F05xxx and STM32F030x8 devices bootloader . . . . . . . . . . . . . 46

7.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8 STM32F04xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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8.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9 STM32F070x6 devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

10 STM32F070xB devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

11 STM32F071xx/072xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . 60

11.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

12 STM32F09xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

12.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

13 STM32F10xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

13.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

14 STM32F105xx/107xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . 68

14.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
14.3.1 How to identify STM32F105xx/107xx bootloader versions . . . . . . . . . . 71
14.3.2 Bootloader unavailability on STM32F105xx/STM32F107xx devices
with date code lower than 937 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.3.3 USART bootloader Get-Version command returns 0x20
instead of 0x22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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14.3.4 PA9 excessive power consumption when USB cable is plugged

in bootloader V2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

15 STM32F10xxx XL-density devices bootloader . . . . . . . . . . . . . . . . . . . 74

15.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
15.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
15.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

16 STM32F2xxxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

16.1 Bootloader V2.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
16.1.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
16.1.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
16.1.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
16.2 Bootloader V3.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
16.2.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
16.2.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
16.2.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

17 STM32F301xx/302x4(6/8) devices bootloader . . . . . . . . . . . . . . . . . . . 84

17.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
17.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
17.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

18 STM32F302xB(C)/303xB(C) devices bootloader . . . . . . . . . . . . . . . . . . 87

18.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
18.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
18.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

19 STM32F302xD(E)/303xD(E) devices bootloader . . . . . . . . . . . . . . . . . . 90

19.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
19.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
19.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

20 STM32F303x4(6/8)/334xx/328xx devices bootloader . . . . . . . . . . . . . . 94

20.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
20.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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20.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

21 STM32F318xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

21.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
21.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
21.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

22 STM32F358xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

22.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
22.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
22.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

23 STM32F373xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

23.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
23.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
23.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

24 STM32F378xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

24.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
24.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
24.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

25 STM32F398xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

25.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
25.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
25.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

26 STM32F40xxx/41xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 108

26.1 Bootloader V3.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
26.1.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
26.1.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
26.1.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
26.2 Bootloader V9.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
26.2.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
26.2.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
26.2.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

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27 STM32F401xB(C) devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . 118

27.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
27.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
27.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

28 STM32F401xD(E) devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . 124

28.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
28.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
28.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

29 STM32F410xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

29.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
29.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
29.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

30 STM32F411xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

30.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
30.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
30.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

31 STM32F412xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

31.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
31.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
31.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

32 STM32F413xx/423xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 146

32.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
32.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
32.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

33 STM32F42xxx/43xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 153

33.1 Bootloader V7.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
33.1.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
33.1.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
33.1.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

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33.2 Bootloader V9.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

33.2.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
33.2.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
33.2.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

34 STM32F446xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

34.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
34.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
34.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

35 STM32F469xx/479xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 171

35.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
35.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
35.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

36 STM32F72xxx/73xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 178

36.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
36.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
36.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

37 STM32F74xxx/75xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 184

37.1 Bootloader V7.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
37.1.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
37.1.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
37.1.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
37.2 Bootloader V9.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
37.2.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
37.2.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
37.2.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

38 STM32F76xxx/77xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 196

38.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
38.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
38.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

39 STM32G03xxx/ STM32G04xxx devices bootloader . . . . . . . . . . . . . . 203

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39.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

39.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
39.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

40 STM32G07xxx/08xxx device bootloader . . . . . . . . . . . . . . . . . . . . . . . 206

40.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
40.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
40.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

41 STM32G431xx/441xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 209

41.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
41.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
41.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

42 STM32G47xxx/48xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 214

42.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
42.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
42.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

43 STM32H72xxx/73xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 219

43.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
43.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
43.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

44 STM32H74xxx/75xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 224

44.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
44.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
44.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

45 STM32H7A3xx/B3xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 230

45.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
45.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
45.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

46 STM32L01xxx/02xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 236

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46.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

46.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
46.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

47 STM32L031xx/041xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 240

47.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
47.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
47.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

48 STM32L05xxx/06xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 243

48.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
48.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
48.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

49 STM32L07xxx/08xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 246

49.1 Bootloader V4.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
49.1.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
49.1.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
49.1.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
49.2 Bootloader V11.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
49.2.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
49.2.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
49.2.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

50 STM32L1xxx6(8/B)A devices bootloader . . . . . . . . . . . . . . . . . . . . . . 255

50.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
50.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
50.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

51 STM32L1xxx6(8/B) devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . 257

51.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
51.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
51.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

52 STM32L1xxxC devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

52.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

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52.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

52.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

53 STM32L1xxxD devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

53.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
53.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
53.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

54 STM32L1xxxE devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

54.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
54.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
54.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

55 STM32L412xx/422xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 270

55.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
55.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
55.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

56 STM32L43xxx/44xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 276

56.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
56.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
56.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

57 STM32L45xxx/46xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 283

57.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
57.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
57.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

58 STM32L47xxx/48xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 290

58.1 Bootloader V10.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
58.1.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
58.1.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
58.1.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
58.2 Bootloader V9.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
58.2.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
58.2.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

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58.2.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

59 STM32L496xx/4A6xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 302

59.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
59.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
59.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

60 STM32L4P5xx/4Q5xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 309

60.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
60.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
60.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

61 STM32L4Rxxx/4Sxxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 316

61.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
61.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
61.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

62 STM32L552xx/STM32L562xx devices bootloader . . . . . . . . . . . . . . . 323

62.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
62.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
62.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

63 STM32WB50xx/55xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 329

63.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
63.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
63.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

64 STM32WLE5xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

64.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
64.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
64.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

65 Device-dependent bootloader parameters . . . . . . . . . . . . . . . . . . . . . 337

66 Bootloader timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

66.1 Bootloader startup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

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66.2 USART connection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

66.3 USB connection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
66.4 I2C connection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
66.5 SPI connection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

Appendix A Example of function to use the “ExitSecureMemory” function . 354

67 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

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List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Bootloader activation patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3. Embedded bootloaders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 4. STM32 F2, F4 and F7 voltage range configuration using bootloader. . . . . . . . . . . . . . . . . 37
Table 5. Supported memory area by Write, Read, Erase and Go commands . . . . . . . . . . . . . . . . . 37
Table 6. Jitter software calculation on bootloader USART detection . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 7. Flash memory alignment constraints on STM32 products . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 8. ExitSecureMemory entry address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 9. STM32F03xx4/6 configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . 42
Table 10. STM32F03xx4/6 bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 11. STM32F030xC configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . 44
Table 12. STM32F030xC bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 13. STM32F05xxx and STM32F030x8 devices configuration in system memory boot mode . 46
Table 14. STM32F05xxx and STM32F030x8 devices bootloader versions . . . . . . . . . . . . . . . . . . . . 47
Table 15. STM32F04xxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 16. STM32F04xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 17. STM32F070x6 configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . . 52
Table 18. STM32F070x6 bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 19. STM32F070xB configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . 56
Table 20. STM32F070xB bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 21. STM32F071xx/072xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . 60
Table 22. STM32F071xx/072xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 23. STM32F09xxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 24. STM32F09xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 25. STM32F10xxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 26. STM32F10xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 27. STM32F105xx/107xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . 68
Table 28. STM32F105xx/107xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 29. STM32F10xxx XL-density configuration in system memory boot mode . . . . . . . . . . . . . . . 74
Table 30. STM32F10xxx XL-density bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 31. STM32F2xxxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 32. STM32F2xxxx bootloader V2.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 33. STM32F2xxxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 34. STM32F2xxxx bootloader V3.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 35. STM32F301xx/302x4(6/8) configuration in system memory boot mode. . . . . . . . . . . . . . . 84
Table 36. STM32F301xx/302x4(6/8) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 37. STM32F302xB(C)/303xB(C) configuration in system memory boot mode . . . . . . . . . . . . . 87
Table 38. STM32F302xB(C)/303xB(C) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 39. STM32F302xD(E)/303xD(E) configuration in system memory boot mode . . . . . . . . . . . . . 90
Table 40. STM32F302xD(E)/303xD(E) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 41. STM32F303x4(6/8)/334xx/328xx configuration in system memory boot mode . . . . . . . . . 94
Table 42. STM32F303x4(6/8)/334xx/328xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 43. STM32F318xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . . 96
Table 44. STM32F318xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 45. STM32F358xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . . 99
Table 46. STM32F358xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 47. STM32F373xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 101
Table 48. STM32F373xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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List of tables AN2606

Table 49. STM32F378xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 104

Table 50. STM32F378xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 51. STM32F398xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 106
Table 52. STM32F398xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 53. STM32F40xxx/41xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 108
Table 54. STM32F40xxx/41xxx bootloader V3.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 55. STM32F40xxx/41xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 112
Table 56. STM32F40xxx/41xxx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 57. STM32F401xB(C) configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . 118
Table 58. STM32F401xB(C) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 59. STM32F401xD(E) configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . 124
Table 60. STM32F401xD(E) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 61. STM32F410xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 129
Table 62. STM32F410xx bootloader V11.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 63. STM32F411xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 134
Table 64. STM32F411xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 65. STM32F412xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 140
Table 66. STM32F412xx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 67. STM32F413xx/423xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 146
Table 68. STM32F413xx/423xx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 69. STM32F42xxx/43xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 153
Table 70. STM32F42xxx/43xxx bootloader V7.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 71. STM32F42xxx/43xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 158
Table 72. STM32F42xxx/43xxx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 73. STM32F446xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 165
Table 74. STM32F446xx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 75. STM32F469xx/479xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 171
Table 76. STM32F469xx/479xx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 77. STM32F72xxx/73xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 178
Table 78. STM32F72xxx/73xxx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 79. STM32F74xxx/75xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 185
Table 80. STM32F74xxx/75xxx bootloader V7.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 81. STM32F74xxx/75xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 190
Table 82. STM32F74xxx/75xxx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 83. STM32F76xxx/77xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 196
Table 84. STM32F76xxx/77xxx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 85. STM32G03xxx/G04xxx configuration in system memory boot mode . . . . . . . . . . . . . . . . 203
Table 86. STM32G03xx/04xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 87. STM32G07xxx/8xxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . 206
Table 88. STM32G07xx/08xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 89. STM32G431xx/441xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 209
Table 90. STM32G431xx/441xx bootloader version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 91. STM32G47xxx/48xxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 214
Table 92. STM32G47xxx/48xxx bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 93. STM32H72xxx/73xxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 219
Table 94. STM32H72xxx/73xxx bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 95. STM32H74xxx/75xxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 224
Table 96. STM32H74xxx/75xxx bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 97. STM32H7A3xx/7B3xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 230
Table 98. STM32H7A3xx/7B3xx bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 99. STM32L01xxx/02xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 236
Table 100. STM32L01xxx/02xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

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Table 101. STM32L031xx/041xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 240

Table 102. STM32L031xx/041xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 103. STM32L05xxx/06xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 243
Table 104. STM32L05xxx/06xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 105. STM32L07xxx/08xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 246
Table 106. STM32L07xxx/08xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 107. STM32L07xxx/08xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 250
Table 108. STM32L07xxx/08xxx bootloader V11.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 109. STM32L1xxx6(8/B)A configuration in system memory boot mode . . . . . . . . . . . . . . . . . . 255
Table 110. STM32L1xxx6(8/B)A bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 111. STM32L1xxx6(8/B) configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . 257
Table 112. STM32L1xxx6(8/B) bootloader versions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 113. STM32L1xxxC configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 259
Table 114. STM32L1xxxC bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 115. STM32L1xxxD configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 262
Table 116. STM32L1xxxD bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 117. STM32L1xxxE configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 266
Table 118. STM32L1xxxE bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 119. STM32L412xx/422xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 270
Table 120. STM32L412xx/422xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 121. STM32L43xxx/44xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 276
Table 122. STM32L43xxx/44xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 123. STM32L45xxx/46xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 283
Table 124. STM32L45xxx/46xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 125. STM32L47xxx/48xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 290
Table 126. STM32L47xxx/48xxx bootloader V10.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 127. STM32L47xxx/48xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 296
Table 128. STM32L47xxx/48xxx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 129. STM32L496xx/4A6xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 302
Table 130. STM32L496xx/4A6xx bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Table 131. STM32L4P5xx/4Q5xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 309
Table 132. STM32L4P5xx/4Q5xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Table 133. STM32L4Rxxx/4Sxxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 316
Table 134. STM32L4Rxx/4Sxx bootloader versions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Table 135. STM32L552xx/562xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 323
Table 136. STM32L552xx/562xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Table 137. STM32WB50xx/55xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 329
Table 138. STM32WB50xx/55xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Table 139. STM32WLE5xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . 334
Table 140. STM32WLE5xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Table 141. Bootloader device-dependent parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Table 142. Bootloader startup timings (ms) for STM32 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Table 143. USART bootloader minimum timings (ms) for STM32 devices. . . . . . . . . . . . . . . . . . . . . 345
Table 144. USB bootloader minimum timings (ms) for STM32 devices . . . . . . . . . . . . . . . . . . . . . . . 348
Table 145. I2C bootloader minimum timings (ms) for STM32 devices . . . . . . . . . . . . . . . . . . . . . . . . 350
Table 146. SPI bootloader minimum timings (ms) for STM32 devices . . . . . . . . . . . . . . . . . . . . . . . . 353
Table 147. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

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List of figures AN2606

List of figures

Figure 1. USART connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 2. USB connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 3. I2C connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 4. SPI connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 5. CAN connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 6. ExitSecureMemory function usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 7. Access to securable memory area from the bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 8. Bootloader selection for STM32F03xx4/6 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 9. Bootloader selection for STM32F030xC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 10. Bootloader selection for STM32F05xxx and STM32F030x8 devices . . . . . . . . . . . . . . . . . 47
Figure 11. Bootloader selection for STM32F04xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 12. Bootloader selection for STM32F070x6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 13. Bootloader selection for STM32F070xB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 14. Bootloader selection for STM32F071xx/072xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 15. Bootloader selection for STM32F09xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 16. Bootloader selection for STM32F10xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 17. Bootloader selection for STM32F105xx/107xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 18. Bootloader selection for STM32F10xxx XL-density devices. . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 19. Bootloader V2.x selection for STM32F2xxxx devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 20. Bootloader V3.x selection for STM32F2xxxx devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 21. Bootloader selection for STM32F301xx/302x4(6/8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 22. Bootloader selection for STM32F302xB(C)/303xB(C) devices. . . . . . . . . . . . . . . . . . . . . . 89
Figure 23. Bootloader selection for STM32F302xD(E)/303xD(E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 24. Bootloader selection for STM32F303x4(6/8)/334xx/328xx . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 25. Bootloader selection for STM32F318xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 26. Bootloader selection for STM32F358xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 27. Bootloader selection for STM32F373xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 28. Bootloader selection for STM32F378xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 29. Bootloader selection for STM32F398xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 30. Bootloader V3.x selection for STM32F40xxx/41xxx devices . . . . . . . . . . . . . . . . . . . . . . 110
Figure 31. Bootloader V9.x selection for STM32F40xxx/41xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 32. Bootloader selection for STM32F401xB(C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 33. Bootloader selection for STM32F401xD(E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 34. Bootloader V11.x selection for STM32F410xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 35. Bootloader selection for STM32F411xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 36. Bootloader V9.x selection for STM32F412xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 37. Bootloader V9.x selection for STM32F413xx/423xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 38. Dual bank boot implementation for STM32F42xxx/43xxx Bootloader V7.x . . . . . . . . . . . 155
Figure 39. Bootloader V7.x selection for STM32F42xxx/43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 40. Dual bank boot implementation for STM32F42xxx/43xxx bootloader V9.x . . . . . . . . . . . 162
Figure 41. Bootloader V9.x selection for STM32F42xxx/43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 42. Bootloader V9.x selection for STM32F446xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 43. Dual bank boot implementation for STM32F469xx/479xx Bootloader V9.x . . . . . . . . . . . 175
Figure 44. Bootloader V9.x selection for STM32F469xx/479xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 45. Bootloader V9.x selection for STM32F72xxx/73xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 46. Bootloader V7.x selection for STM32F74xxx/75xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 47. Bootloader V9.x selection for STM32F74xxx/75xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 48. Dual bank boot implementation for STM32F76xxx/77xxx Bootloader V9.x . . . . . . . . . . . 200

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Figure 49. Bootloader V9.x selection for STM32F76xxx/77xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 50. Bootloader V5.x selection for STM32G03xxx/G04xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 51. Bootloader V11.0 selection for STM32G07xxx/G08xxx . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 52. Bootloader selection for STM32G431xx/441xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 53. Bootloader selection for STM32G47xxx/48xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 54. Dual bank boot implementation for STM32G47xxx/48xxx bootloader V13.x . . . . . . . . . . 218
Figure 55. Bootloader V9.0 selection for STM32H72xxx/73xxx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 56. Bootloader V9.x selection for STM32H74xxx/75xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 57. Bootloader V9.x selection for STM32H7A3xx/7B3xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 58. Bootloader selection for STM32L01xxx/02xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 59. Bootloader selection for STM32L031xx/041xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 60. Bootloader selection for STM32L05xxx/06xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 61. Dual bank boot implementation for STM32L07xxx/08xxx bootloader V4.x. . . . . . . . . . . . 248
Figure 62. Bootloader V4.x selection for STM32L07xxx/08xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 63. Dual bank boot implementation for STM32L07xxx/08xxx bootloader V11.x. . . . . . . . . . . 252
Figure 64. Bootloader V11.x selection for STM32L07xxx/08xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 65. Bootloader selection for STM32L1xxx6(8/B)A devices. . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 66. Bootloader selection for STM32L1xxx6(8/B) devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 67. Bootloader selection for STM32L1xxxC devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 68. Bootloader selection for STM32L1xxxD devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 69. Bootloader selection for STM32L1xxxE devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 70. Dual bank boot Implementation for STM32L412xx/422xx bootloader V9.x . . . . . . . . . . . 273
Figure 71. Bootloader V13.x selection for STM32L412xx/422xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 72. Dual bank boot Implementation for STM32L3x2xx/44xxx bootloader V9.x . . . . . . . . . . . 280
Figure 73. Bootloader V9.x selection for STM32L43xxx/44xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Figure 74. Dual bank boot Implementation for STM32L45xxx/46xxx bootloader V9.x . . . . . . . . . . . 287
Figure 75. Bootloader V9.x selection for STM32L45xxx/46xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 76. Dual bank boot implementation for STM32L47xxx/48xxx bootloader V10.x. . . . . . . . . . . 293
Figure 77. Bootloader V10.x selection for STM32L47xxx/48xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Figure 78. Dual bank boot implementation for STM32L47xxx/48xxx bootloader V9.x. . . . . . . . . . . . 299
Figure 79. Bootloader V9.x selection for STM32L47xxx/48xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Figure 80. Dual bank boot Implementation for STM32L496xx/4A6xx bootloader V9.x . . . . . . . . . . . 306
Figure 81. Bootloader V9.x selection for STM32L496xx/4A6xx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 82. Dual bank boot implementation for STM32L4P5xx/4Q5xx bootloader V9.x . . . . . . . . . . . 313
Figure 83. Bootloader V9.x selection for STM32L4P5xx/4Q5xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 84. Dual bank boot implementation for STM32L4Rxxx/STM32L4Sxxx bootloader V9.x . . . . 320
Figure 85. Bootloader V9.x selection for STM32L4Rxx/4Sxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 86. Bootloader V9.x selection for STM32L552xx/562xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Figure 87. Bootloader V13.0 selection for STM32WB50xx/55xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 88. Bootloader V12.x selection for STM32WLE5xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Figure 89. Bootloader Startup timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 90. USART connection timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 91. USB connection timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Figure 92. I2C connection timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 93. SPI connection timing description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

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17
General information AN2606

1 General information

This document applies to Arm®(a)-based devices.

2 Related documents

For each supported product (listed in Table 1) refer to the following documents available
from www.st.com:
 Datasheet or databrief
 Reference manual
 Application notes
– AN3154: CAN protocol used in the STM32 bootloader
– AN3155: USART protocol used in the STM32 bootloader
– AN3156: USB DFU protocol used in the STM32 bootloader
– AN4221: I2C protocol used in the STM32 bootloader
– AN4286: SPI protocol used in the STM32 bootloader
– AN5405: FDCAN protocol used in the STM32 bootloader

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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AN2606 Glossary

3 Glossary

F0 Series:
STM32F03xxx is used to refer to STM32F030x4, STM32F030x6, STM32F038x6,
STM32F030xC, STM32F031x4 and STM32F031x6 devices.
STM32F04xxx is used to refer to STM32F042x4 and STM32F042x6 devices.
STM32F05xxx and STM32F030x8 devices is used to refer to STM32F051x4,
STM32F051x6, STM32F051x8, STM32F058x8 and STM32F030x8 devices.
STM32F07xxx is used to refer to STM32F070x6, STM32F070xB, STM32F071xB
STM32F072x8 and STM32F072xB devices.
STM32F09xxx is used to refer to STM32F091xx and STM32F098xx devices.
F1 Series:
STM32F10xxx is used to refer to Low-density, Medium-density, High-density, Low-
density value line, Medium-density value line and High-density value line devices:
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and
32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and
128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers
where the Flash memory density ranges between 256 and 512 Kbytes.
Low-density value line devices are STM32F100xx microcontrollers where the
Flash memory density ranges between 16 and 32 Kbytes.
Medium-density value line devices are STM32F100xx microcontrollers where
the Flash memory density ranges between 64 and 128 Kbytes.
High-density value line devices are STM32F100xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
STM32F105xx/107xx is used to refer to STM32F105xx and STM32F107xx devices.
STM32F10xxx XL-density is used to refer to STM32F101xx and STM32F103xx
devices where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
F2 Series:
STM32F2xxxx is used to refer to STM32F215xx, STM32F205xx, STM32F207xx and
SMT32F217xx devices.

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F3 Series:
STM32F301xx/302x4(6/8) is used to refer to STM32F301x4, STM32F301x6,
STM32F301x8, STM32F302x4, STM32F302x6 and STM32F302x8 devices.
STM32F302xB(C)/303xB(C) is used to refer to STM32F302xB, STM32F302xC,
STM32F303xB and STM32F303xC devices.
STM32F302xD(E)/303xD(E) is used to refer to STM32F302xD, STM32F302xE,
STM32F303xD and STM32F303xE devices.
STM32F303x4(6/8)/334xx/328xx is used to refer to STM32F303x4, STM32F303x6,
STM32F303x8, STM32F334x4, STM32F334x6, STM32F334x8, and STM32F328x8
devices.
STM32F318xx is used to refer to STM32F318x8 devices.
STM32F358xx is used to refer to STM32F358xC devices.
STM32F373xx is used to refer to STM32F373x8, STM32F373xB and STM32F373xC
devices.
STM32F378xx is used to refer to STM32F378xC devices.
STM32F398xx is used to refer to STM32F398xE devices.
F4 Series:
STM32F40xxx/41xxx is used to refer to STM32F405xx, STM32F407xx,
STM32F415xx and SMT32F417xx devices.
STM32F401xB(C) is used to refer to STM32F401xB and STM32F401xC devices.
STM32F401xD(E) is used to refer to STM32F401xD and STM32F401xE devices.
STM32F410xx is used to refer to STM32F410x8 and STM32F410xB devices.
STM32F411xx is used to refer to STM32F411xD and STM32F411xE devices.
STM32F412xx is used to refer to STM32F412Cx, STM32F412Rx, STM32F412Vx and
STM32F412Zx devices.
STM32F413xx/423xx is used to refer to STM32F413xG, STM32F413xH and
STM32F423xH devices.
STM32F42xxx/43xxx is used to refer to STM32F427xx, STM32F429xx,
STM32F437xx and STM32F439xx devices.
STM32F446xx is used to refer to STM32F446xE and STM32F446xC devices.
STM32F469xx/479xx is used to refer to STM32F469xE, STM32F469xG,
STM32F469xI, STM32F479xG and STM32F479xI devices.
F7 Series:
STM32F72xxx/73xxx is used to refer to STM32F722xx, STM32F723xx,
STM32F732xx and STM32F733xx devices.
STM32F74xxx/75xxx is used to refer to STM32F745xx, STM32F746xx and
STM32F756xx devices.
STM32F76xxx/77xxx is used to refer to STM32F765xx, STM32F767xx,
STM32F769xx, STM32F777xx and STM32F779xx devices.
G0 Series:
STM32G03xxx/04xxx is used to refer to STM32G03xxx and STM32G04xxx devices.
STM32G07xxx/08xxx is used to refer to STM32G07xxx and STM32G08xxx devices.

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G4 Series:
STM32G431xx is used to refer to STM32G431xx devices.
STM32G441xx is used to refer to STM32G441xx devices.
STM32G47xxx is used to refer to STM32G471xx, STM32G473xx and STM32G474xx
devices.
STM32G48xxx is used to refer to STM32G483xx and STM32G484xx devices.
H7 Series:
STM32H72xxx/73xxx is used to refer to STM32H72xxx and STM32H73xxx devices.
STM32H74xxx/75xxx is used to refer to STM32H74xxx and STM32H75xxx devices.
STM32H7A3xx/7B3xx is used to refer to STM32H7A3xx/ STM32H7B3xx devices.
L0 Series:
STM32L01xxx/02xxx is used to refer to STM32L011xx and STM32L021xx devices.
STM32L031xx/041xx is used to refer to STM32L031xx and STM32L041xx devices.
STM32L05xxx/06xxx is used to refer to STM32L051xx, STM32L052xx,
STM32L053xx, STM32L062xx and STM32L063xx ultralow power devices.
STM32L07xxx/08xxx is used to refer to STM32L071xx, STM32L072xx,
STM32L073xx, STM32L081xx, STM32L082xx and STM32L083xx devices
L1 Series:
STM32L1xxx6(8/B) is used to refer to STM32L1xxV6T6, STM32L1xxV6H6,
STM32L1xxR6T6, STM32L1xxR6H6, STM32L1xxC6T6, STM32L1xxC6H6,
STM32L1xxV8T6, STM32L1xxV8H6, STM32L1xxR8T6, STM32L1xxR8H6,
STM32L1xxC8T6, STM32L1xxC8H6, STM32L1xxVBT6, STM32L1xxVBH6,
STM32L1xxRBT6, STM32L1xxRBH6, STM32L1xxCBT6 and STM32L1xxCBH6
ultralow power devices.
STM32L1xxx6(8/B)A is used to refer to STM32L1xxV6T6-A, STM32L1xxV6H6-A,
STM32L1xxR6T6-A, STM32L1xxR6H6-A, STM32L1xxC6T6-A, STM32L1xxC6H6-A,
STM32L1xxV8T6-A, STM32L1xxV8H6-A, STM32L1xxR8T6-A, STM32L1xxR8H6-A,
STM32L1xxC8T6-A, STM32L1xxC8H6-A, STM32L1xxVBT6-A, STM32L1xxVBH6-A,
STM32L1xxRBT6-A, STM32L1xxRBH6-A, STM32L1xxCBT6-A and
STM32L1xxCBH6-A ultralow power devices.
STM32L1xxxC is used to refer to STM32L1xxVCT6, STM32L1xxVCH6 ,
STM32L1xxRCT6, STM32L1xxUCY6, STM32L1xxCCT6 and STM32L1xxCCU6
ultralow power devices.
STM32L1xxxD is used to refer to STM32L1xxZDT6, STM32L1xxQDH6,
STM32L1xxVDT6, STM32L1xxRDY6, STM32L1xxRDT6, STM32L1xxZCT6,
STM32L1xxQCH6, STM32L1xxRCY6, STM32L1xxVCT6-A and STM32L1xxRCT6-A
ultralow power devices.
STM32L1xxxE is used to refer to STM32L1xxZET6, STM32L1xxQEH6,
STM32L1xxVET6, STM32L1xxVEY6, and STM32L1xxRET6 ultralow power devices.

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L4 Series:
STM32L412xx/422xx is used to refer to STM32L412xB, STM32L412x8,
STM32L422xB devices.
STM32L43xxx/44xxx is used to refer to STM32L431xx, STM32L432xx, STM32L433xx
and STM32L442xx and STM32L443xx devices.
STM32L45xxx/46xxx is used to refer to STM32L451xx, STM32L452xx and
STM32L462xx devices.
STM32L47xxx/48xxx is used to refer to STM32L471xx, STM32L475xx, STM32L476xx
and STM32L486xx devices.
STM32L496xx/4A6xx is used to refer to STM32L496xE, STM32L496xG and
STM32L4A6xG devices.
STM32L4Rxxx/4Sxxx is used to refer to STM32L4R5xx, STM32L4R7xx,
STM32L4R9xx, STM32L4S5xx, STM32L4S7xx and STM32L4S9xx devices.
STM32L4P5xx/4Q5xx is used to refer to STM32L4P5xx/STM32L4Q5xx devices.
L5 Series:
STM32L552xx is used to refer to STM32L552xx devices.
STM32L562xx is used to refer to STM32L562xx devices.
WB Series:
STM32WB50xx is used to refer to STM32WB50xx devices.
STM32WB55xx is used to refer to STM32WB55Cx, STM32WB55Rx and
STM32WB55Vx devices.
WL Series:
STM32WLE5xx is used to refer to STM32WLE5JC, STM32WLE5JB and
STM32WLE5J8 devices.
Note: BL_USART_Loop refers to the USART bootloader execution loop.
BL_CAN_Loop refers to the CAN bootloader execution loop.
BL_I2C_Loop refers to the I2C bootloader execution loop.
BL_SPI_Loop refers to the SPI bootloader execution loop.

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4 General bootloader description

4.1 Bootloader activation

The bootloader is activated by applying one of the patterns described in Table 2.
If Boot from Bank2 option is activated (for products supporting this feature), bootloader
executes Dual Boot mechanism as described in figures “Dual bank boot implementation for
STM32xxxx” where STM32xxxx is the relative STM32 product (example: Figure 8),
otherwise bootloader selection protocol is executed as described in figures “Bootloader VY.x
selection for STM32xxxx” where STM32xxxx is the relative STM32 product (example:
Figure 19).
When readout protection Level2 is activated, STM32 does not boot on system memory in
any case and bootloader cannot be executed (unless jumping to it from Flash user code, all
commands are not accessible except Get, GetID, and GetVersion).

Table 2. Bootloader activation patterns

Pattern Condition

Pattern 1 Boot0(pin) = 1 and Boot1(pin) = 0

Pattern 2 Boot0(pin) = 1 and nBoot1(bit) = 1
Boot0(pin) = 1, Boot1(pin) = 0 and BFB2(bit) = 1
Pattern 3 Boot0(pin) = 0, BFB2(bit) = 0 and both banks do not contain valid code
Boot0(pin) = 1, Boot1(pin) = 0, BFB2(bit) = 0 and both banks do not contain valid code
Boot0(pin) = 1, Boot1(pin) = 0 and BFB2(bit) = 1
Pattern 4 Boot0(pin) = 0, BFB2(bit) = 0 and both banks do not contain valid code
Boot0(pin) = 1, Boot1(pin) = 0 and BFB2(bit) = 0
Boot0(pin) = 1, Boot1(pin) = 0 and BFB2(bit) = 0
Pattern 5 Boot0(pin) = 0, BFB2(bit) = 1 and both banks do not contain valid code
Boot0(pin) = 1, Boot1(pin) = 0 and BFB2 (bit) = 1
Boot0(pin) = 1, nBoot1(bit) = 1 and nBoot0_SW(bit) = 1
nBoot0(bit) = 0, nBoot1(bit) = 1 and nBoot0_SW(bit) = 0
Pattern 6
Boot0(pin) = 0, nBoot0_SW(bit) = 1 and main Flash memory empty
nBoot0(bit) = 1, nBoot0_SW(bit)=0 and main Flash memory empty
Boot0(pin) = 1, nBoot1(bit) = 1 and BFB2(bit) = 0
Pattern 7 Boot0(pin) = 0, BFB2(bit) = 1 and both banks do not contain valid code
Boot0(pin) = 1, nBoot1(bit) = 1 and BFB2(bit) = 1
Boot(pin) = 0 and BOOT_ADD0(optionbyte) = 0x0040
Pattern 8
Boot(pin) = 1 and BOOT_ADD1(optionbyte) = 0x0040

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Table 2. Bootloader activation patterns (continued)

Pattern Condition

nDBANK(bit) = 1, Boot(pin) = 0 and BOOT_ADD0(optionbyte) = 0x0040

nDBANK(bit) = 1, Boot(pin) = 1 and BOOT_ADD1(optionbyte) = 0x0040
nDBANK(bit) = 0, nDBOOT(bit) = 1, Boot(pin) = 0 and BOOT_ADD0(optionbyte) =
0x0040

Pattern 9 nDBANK(bit) = 0, nDBOOT(bit) = 1, Boot(pin) = 1 and BOOT_ADD1(optionbyte) =

0x0040
nDBANK(bit) = 0, nDBOOT(bit) = 0, BOOT_ADDx(optionbyte) out of memory range or in
ICP memory range
nDBANK(bit) = 0, nDBOOT(bit) = 0, BOOT_ADDx(optionbyte) in Flash memory range
and both banks do not contain valid code
Boot(pin) = 0 and BOOT_ADD0(optionbyte) = 0x1FF0
Pattern 10
Boot(pin) = 1 and BOOT_ADD1(optionbyte) = 0x1FF0
nBoot0(bit) = 0, nBoot1(bit) = 1, nBOOT0_SEL(bit) = 1 and BOOT_LOCK(bit) = 0
Boot0(pin) = 1, nBoot1(bit) = 1 and nBOOT0_SEL (bit) = 1
nBoot0(bit) = 1, nBOOT0_SEL(bit) = 1, BOOT_LOCK(bit) = 0 and main Flash memory
Pattern 11 empty
Boot0(pin) = 0, nBOOT0_SEL(bit) = 0, BOOT_LOCK(bit) = 0 and main Flash memory
empty
BOOT_LOCK(bit) = 1 and main Flash memory empty
TZen = 0, Boot0(pin) = 0, nSWBoot0(bit) = 1 and NSBOOTADD0 [24:0] = 0x017F200
TZen = 0, Boot0(pin) = 1, nSWBoot0(bit) = 1 and NSBOOTADD1 [24:0] = 0x017F200
TZen = 0, nBoot0(bit) = 0, nSWBoot0(bit) = 0 and NSBOOTADD1 [24:0] = 0x017F200
TZen = 0, nBoot0(bit) = 1, nSWBoot0(bit) = 0 and NSBOOTADD0 [24:0] = 0x017F200
TZen = 1, Boot0(pin) = 0, nSWBoot0(bit) = 1 and SECBOOTADD0 [24:0] = 0x01FF000 &
RSSCMD = 0
TZen = 1, Boot0(pin) = 1, nSWBoot0 (bit) = 1 & RSSCMD = 0, BOOT_LOCK=0 or
Pattern 12
(BOOT_LOCK = 1 and SECBOOTADD0 [24:0] = 0x01FF000)
TZen = 1, nBoot0(bit) = 1, nSWBoot0 (bit) = 0 and SECBOOTADD0 [24:0] = 0x01FF000
& RSSCMD = 0, BOOT_LOCK=0 or (BOOT_LOCK = 1 and SECBOOTADD0 [24:0] =
0x01FF000)
TZen = 1, nBoot0(bit) = 0, nSWBoot0 (bit) = 0 & RSSCMD = 0, BOOT_LOCK=0 or
BOOT_LOCK = 1 and SECBOOTADD1 [24:0] = 0x01FF000
TZen = 1, RSSCMD = 0x1C0, BOOT_LOCK=0 or (BOOT_LOCK = 1 and
SECBOOTADD0 [24:0] = 0x01FF000)
nBoot0(bit) = 0, nBoot1(bit) = 1 and nSWBoot0(bit) = 0
nBoot0(bit) = 1, nBoot1(bit) = 1, nSWBoot0(bit) = 0 and user Flash empty
Pattern 13
nBoot1(bit) = 1, nSWBoot0(bit) = 1 and Boot0(pin) = 1
nBoot1(bit) = 1, nSWBoot0(bit) = 1, Boot0(pin) = 0 and user Flash empty

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Table 2. Bootloader activation patterns (continued)

Pattern Condition

BOOT_LOCK(bit) = 0, nBoot1(bit) = 1, Boot0(pin) = 1 and nSWBoot0(bit) = 1

BOOT_LOCK(bit) = 0, nBoot1(bit) = 1, nBoot0(bit) 0 and nSWBoot0(bit) = 0

Pattern 14 BOOT_LOCK(bit) = 0, Boot0(pin) = 0, nSWBoot0(bit) = 1, BFB2(bit)=1 and both banks

do not contain valid code
BOOT_LOCK(bit) = 0, nBoot0(bit), nSWBoot0(bit) = 0, BFB2(bit)=1 and both banks do
not contain valid code
BOOT_LOCK(bit)=0, Boot0(pin) = 1, nBoot1(bit) = 1 and nBoot0_SW(bit) = 1
Pattern 15
BOOT_LOCK(bit)=0, nBoot0(bit) = 0, nBoot1(bit) = 1 and nBoot0_SW(bit) = 0
Boot0(pin) = 1, nBoot1(bit) = 1 and nBoot0_SW(bit) = 1
Pattern 16 nBoot0(bit) = 0, nBoot1(bit) = 1 and nBoot0_SW(bit) = 0
Boot0(pin) = 0, nBoot0_SW(bit) = 1 and main Flash memory empty

In addition to patterns described above, user can execute bootloader by performing a jump
to system memory from user code. Before jumping to bootloader user must:
 Disable all peripheral clocks
 Disable used PLL
 Disable interrupts
 Clear pending interrupts
System memory boot mode can be exited by getting out from bootloader activation
condition and generating hardware reset or using Go command to execute user code.
Note: When executing the Go command, the peripheral registers used by the bootloader are not
initialized to their default reset values before jumping to the user application. They must be
reconfigured in the user application if they are used. So, if the IWDG is being used in the
application, the IWDG prescaler value has to be adapted to meet the requirements of the
application (since the prescaler was set to its maximum value). For some products, not all
reset values are set. For more information refer to the known limitations detailed for each
product bootloader versions.
Note: For STM32 devices having the Dual Bank Boot feature, to jump to system memory from
user code the user has first to remap the System Memory bootloader at address
0x00000000 using SYSCFG register (except for STM32F7 Series), then jump to bootloader.
For STM32F7 Series, the user has to disable nDBOOT and/or nDBANK features (in option
bytes), then jump to bootloader.
Note: For STM32 devices embedding bootloader using the DFU/CAN interface in which the
external clock source (HSE) is required for DFU/CAN operations, the detection of the HSE
value is done dynamically by the bootloader firmware and is based on the internal oscillator
clock (HSI, MSI). When (because of temperature variations or other conditions) the internal
oscillator precision is altered above the tolerance band (1% around the theoretical value),
the bootloader might calculate a wrong HSE frequency value. In this case, the bootloader
DFU/CAN interfaces might malfunction or not work at all.

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4.2 Bootloader identification

Depending on the STM32 device used, the bootloader may support one or more embedded
serial peripherals used to download the code to the internal Flash memory. The bootloader
identifier (ID) provides information about the supported serial peripherals.
For a given STM32 device, the bootloader is identified by means of the:
1. Bootloader (protocol) version: version of the serial peripheral (e.g. USART, CAN,
USB) communication protocol used in the bootloader. This version can be retrieved
using the bootloader Get Version command.
2. Bootloader identifier (ID): version of the STM32 device bootloader, coded on one
byte in the 0xXY format, where:
– X specifies the embedded serial peripheral(s) used by the device bootloader:
X = 1: one USART is used
X = 2: two USARTs are used
X = 3: USART, CAN and DFU are used
X = 4: USART and DFU are used
X = 5: USART and I2C are used
X = 6: I2C is used 
X = 7: USART, CAN, DFU and I2C are used 
X = 8: I2C and SPI are used 
X = 9: USART, CAN (or FDCAN), DFU, I2C and SPI are used 
X = 10: USART, DFU and I2C are used 
X = 11: USART, I2C and SPI are used 
X = 12: USART and SPI are used 
X = 13: USART, DFU, I2C and SPI are used
– Y specifies the device bootloader version
Let us take the example of a bootloader ID equal to 0x10. This means that it is the
first version of the device bootloader that uses only one USART.
The bootloader ID is programmed in the last byte address - 1 of the device system
memory and can be read by using the bootloader “Read memory” command or by
direct access to the system memory via JTAG/SWD.
Note: The bootloader ID format is applied to all STM32 devices families except the STM32F1xx
family. The bootloader version for the STM32F1xx applies only to the embedded device
bootloader version and not to its supported protocols.

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Table 3 provides identification information of the bootloaders embedded in STM32 devices.

Table 3. Embedded bootloaders

Bootloader ID Bootloader
STM32
Series

Device Supported serial peripherals Memory (protocol)

ID version
location
STM32F05xxx/STM32F030x8 USART1/USART2 0x21 0x1FFFF7A6 USART (V3.1)
STM32F03xx4/6 USART1 0x10 0x1FFFF7A6 USART (V3.1)
USART1/ USART (V3.1)
STM32F030xC 0x52 0x1FFFF796
I2C1 I2C1(V1.0)
F0 USART1/USART2/  USART (V3.1)
STM32F04xxx DFU (USB device FS)/ 0xA1 0x1FFFF6A6 DFU (V2.2)
I2C1 I2C (V1.0)
USART (V3.1)
USART1/USART2/ I2C1/ 
STM32F071xx/072xx 0xA1 0x1FFFF6A6 DFU (V2.2)
DFU (USB device FS)
I2C (V1.0)
USART1/USART2 USART (V3.1)
STM32F070x6 / DFU (USB device FS) 0xA2 0x1FFFF6A6 DFU (V2.2)
/I2C1 I2C (V1.0)
USART (V3.1)
F0 USART1/USART2/ 
STM32F070xB 0xA3 0x1FFFF6A6 DFU (V2.2)
DFU (USB device FS)/I2C1
I2C (V1.0)
USART1/USART2/  USART (V3.1)
STM32F09xxx 0x50 0x1FFFF796
I2C1 I2C (V1.0)
Low-density USART1 NA NA USART (V2.2)
Medium-density USART1 NA NA USART (V2.2)
High-density USART1 NA NA USART (V2.2)
STM32F10xxx
Medium-density
USART1 0x10 0x1FFFF7D6 USART (V2.2)
value line
F1
High-density
USART1 0x10 0x1FFFF7D6 USART (V2.2)
value line
USART1/USART2 (remapped)  USART (V2.2(1))
STM32F105xx/107xx / CAN2 (remapped)  NA NA CAN (V2.0)
/ DFU (USB Device) DFU(V2.2)
STM32F10xxx XL-density USART1/USART2 (remapped) 0x21 0x1FFFF7D6 USART (V3.0)
USART1/USART3 0x20 0x1FFF77DE USART (V3.0)
F2 STM32F2xxxx USART1/USART3/  USART (V3.1)
CAN2/  0x33 0x1FFF77DE CAN (V2.0)
DFU (USB device FS) DFU (V2.2)

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Table 3. Embedded bootloaders (continued)

Bootloader ID Bootloader
STM32
Series

Device Supported serial peripherals Memory (protocol)

ID version
location
USART1/USART2/  USART (V3.1)
STM32F373xx 0x41 0x1FFFF7A6
DFU (USB device FS) DFU (V2.2)
USART (V3.1)
STM32F378xx USART1/USART2/ I2C1 0x50 0x1FFFF7A6
I2C (V1.0)
USART1/USART2/  USART (V3.1)
STM32F302xB(C)/303xB(C) 0x41 0x1FFFF796
DFU (USB device FS) DFU (V2.2)
USART1/USART2/  USART (V3.1)
STM32F358xx 0x50 0x1FFFF796
I2C1 I2C (V1.0)
USART1/USART2/  USART (V3.1)
F3 STM32F301xx/302x4(6/8) 0x40 0x1FFFF796
DFU (USB device FS) DFU (V2.2)
USART1/USART2/  USART (V3.1)
STM32F318xx 0x50 0x1FFFF796
I2C1/ I2C3 I2C (V1.0)
USART1/USART2/ USART (V3.1)
STM32F302xD(E)/303xD(E) 0x40 0x1FFFF796
DFU (USB device FS) DFU (V2.2)
USART1/USART2/  USART (V3.1)
STM32F303x4(6/8)/334xx/328xx 0x50 0x1FFFF796
I2C1 I2C (V1.0)
USART1/USART2/ USART (V3.1)
STM32F398xx 0x50 0x1FFFF796
I2C1/I2C3 I2C (V1.0)

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Table 3. Embedded bootloaders (continued)

Bootloader ID Bootloader
STM32
Series

Device Supported serial peripherals Memory (protocol)

ID version
location
USART1/USART3/  USART (V3.1)
CAN2/  0x31 0x1FFF77DE CAN (V2.0)
DFU (USB device FS) DFU (V2.2)
STM32F40xxx/41xxx USART1/USART3/  USART (V3.1)
CAN2 /  CAN (V2.0)
DFU (USB device FS) 0x90 0x1FFF77DE DFU (V2.2)
/I2C1/I2C2/I2C3/ SPI(V1.1)
SPI1/SPI2 I2C (V1.0)
USART1/USART3/  USART (V3.1)
CAN2 / CAN (V2.0)
0x70 0x1FFF76DE
DFU (USB device FS) /  DFU (V2.2)
I2C1 I2C (V1.0)
STM32F42xxx/43xxx USART1/USART3/  USART (V3.1)
CAN2 /  CAN (V2.0)
DFU (USB device FS) /  0x91 0x1FFF76DE DFU (V2.2)
SPI1/ SPI2/ SPI4 SPI(V1.1)
I2C1/I2C2/I2C3/ I2C (V1.0)
USART (V3.1)
USART1/USART2/ DFU (USB
DFU (V2.2)
STM32F401xB(C) device FS)/ I2C1/I2C2/I2C3/ 0xD1 0x1FFF76DE
SPI(V1.1)
SPI1/SPI2/ SPI3
I2C (V1.0)
USART (V3.1)
USART1/USART2/ DFU (USB
DFU (V2.2)
STM32F401xD(E) device FS)/ I2C1/I2C2/I2C3/ 0xD1 0x1FFF76DE
SPI(V1.1)
SPI1/SPI2/ SPI3
I2C (V1.1)
USART1/USART2/ USART (V3.1)
F4
STM32F410xx I2C1/I2C2/I2C4 0xB1 0x1FFF76DE I2C (V1.2)
SPI1/SPI2 SPI (V1.1)
USART1/USART2/  USART (V3.1)
DFU (USB device FS)/ DFU (V2.2)
STM32F411xx 0xD0 0x1FFF76DE
SPI1/SPI2/ SPI3 SPI(V1.1) 
I2C1/I2C2/I2C3 I2C (V1.1)
USART1/USART2/ USART (V3.1)
USART3/CAN2/ CAN (V2.0)
STM32F412xx DFU (USB device FS)/ 0x91 0x1FFF76DE DFU (V2.2)
I2C1/I2C2/I2C3/I2C4/ SPI (V1.1)
SPI1/SPI3/SPI4 I2C (V1.2)
USART1/USART2/ USART (V3.1)
USART3/CAN2/ CAN (V2.0)
STM32F413xx/423xx DFU (USB device FS)/ 0x90 0x1FFF76DE DFU (V2.2)
I2C1/I2C2/I2C3/I2C4/ I2C (V1.2)
SPI1/SPI3/SPI4 SPI (V1.1)
USART (V3.1)
USART1/USART3/ CAN2 /
CAN (V2.0)
DFU (USB device FS) /
STM32F446xx 0x90 0x1FFF76DE DFU (V2.2)
I2C1/I2C2/I2C3/SPI1/ SPI2/
SPI(V1.1)
SPI4
I2C (V1.2)
USART1/USART3/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
STM32F469xx/479xx CAN2/ 0x90 0x1FFF76DE CAN (V2.0)
DFU (USB device FS)/  DFU (V2.2)
SPI1/ SPI2/ SPI4 SPI (V1.1)

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Table 3. Embedded bootloaders (continued)

Bootloader ID Bootloader
STM32
Series

Device Supported serial peripherals Memory (protocol)

ID version
location
USART1/USART3/ USART (V3.1)
CAN1/ CAN (V2.0)
STM32F72xxx/73xxx DFU (USB device FS)/ 0x90 0x1FF0EDBE DFU (V2.2)
I2C1/I2C2/I2C3/ I2C (V1.2)
SPI1/SPI2/SPI4 SPI (V1.2)
USART1/USART3/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
0x70 0x1FF0EDBE
CAN2/ CAN (V2.0)
DFU (USB device FS) DFU (V2.2)
F7 STM32F74xxx/75xxx USART1/USART3/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
CAN2/ 0x90 0x1FF0EDBE CAN (V2.0)
DFU (USB device FS)/  DFU (V2.2)
SPI1/SPI2/SPI4 SPI (V1.2)
USART1/USART3/ USART (V3.1)
CAN2/ CAN (V2.0)
STM32F76xxx/77xxx DFU (USB device FS)/ 0x93 0x1FF0EDBE DFU (V2.2)
I2C1/I2C2/I2C3/ I2C (V1.2)
SPI1/SPI2/SPI4 SPI (V1.2)
USART1/USART2/ USART (V3.1)
STM32G07xxx/08xxx USART3/I2C1/I2C2/ 0xB2 0x1FFF6FFE I2C (V1.2) 
G0 SPI1/SPI2 SPI (V1.1)
USART1/USART2/ USART (V3.1)
STM32G03xxx/04xxx 0x53 0x1FFF1FFE
I2C1\I2C2 I2C (V1.2)
USART1/USART2/USART3 USART (V3.1)
I2C2/I2C3 I2C (V1.2)
STM32G431xx/441xx 0xD3 0x1FFF6FFE
SPI1/SPI2 SPI (V1.1)
DFU (USB device FS) DFU (V2.2)
G4
USART1/USART2/USART3 USART (V3.1)
I2C2/I2C3/I2C4 I2C (V1.2)
STM32G47xxx/48xxx 0xD4 0x1FFF6FFE
SPI1/SPI2 SPI (V1.1)
DFU (USB device FS) DFU (V2.2)
USART1/USART2/USART3 USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
STM32H72xxx/73xxx DFU (USB device FS)/ 0x92 0x1FF1E7FE DFU (V2.2)
SPI1/SPI2/SPI3/SPI4/ SPI (V1.1)
FDCAN1 FDCAN (V1.0)
USART1/USART2/USART3 USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.1)
H7 STM32H74xxx/75xxx DFU (USB device FS)/ 0x90 0x1FF1E7FE DFU (V2.2)
SPI1/SPI2/SPI3/SPI4/ SPI (V1.2)
FDCAN1 FDCAN (V1.0)
USART1/USART2/USART3 USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.1)
STM32H7A3xx/B3xx DFU (USB device FS)/ 0x91 0x1FF13FFE DFU (V2.2)
SPI1/SPI2/SPI3/SPI4/ SPI (V1.2)
FDCAN1 FDCAN (V1.0)

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Table 3. Embedded bootloaders (continued)

Bootloader ID Bootloader
STM32
Series

Device Supported serial peripherals Memory (protocol)

ID version
location
USART (V3.1)
STM32L01xxx/02xxx USART2/SPI1 0xC3 0x1FF00FFE
SPI (V1.1)
USART (V3.1)
STM32L031xx/041xx USART2/SPI1 0xC0 0x1FF00FFE
SPI (V1.1)
USART1/USART2/ USART (V3.1)
STM32L05xxx/06xxx 0xC0 0x1FF00FFE
L0 SPI1/ SPI2 SPI (V1.1)
USART1/USART2/ USART (V3.1)
0x41 0x1FF01FFE
DFU (USB device FS) DFU (V2.2)
STM32L07xxx/08xxx USART (V3.1)
USART1/USART2/ SPI1/SPI2/
0xB2 0x1FF01FFE SPI (V1.1)
I2C1/I2C2
I2C (V1.2)
STM32L1xxx6(8/B) USART1/USART2 0x20 0x1FF00FFE USART (V3.0)
STM32L1xxx6(8/B)A USART1/USART2 0x20 0x1FF00FFE USART (V3.1)
USART1/USART2/ DFU (USB USART (V3.1)
STM32L1xxxC 0x40 0x1FF01FFE
device FS) DFU (V2.2)
L1
USART1/USART2/ DFU (USB USART (V3.1)
STM32L1xxxD 0x45 0x1FF01FFE
device FS) DFU (V2.2)
USART1/USART2/ DFU (USB USART (V3.1)
STM32L1xxxE 0x40 0x1FF01FFE
device FS) DFU (V2.2)

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Table 3. Embedded bootloaders (continued)

Bootloader ID Bootloader
STM32
Series

Device Supported serial peripherals Memory (protocol)

ID version
location

USART1/USART2/USART3 USART (V3.1)

I2C1/I2C2/I2C3/ I2C (V1.2)
STM32L412xx/422xx 0xD1 0x1FFF6FFE
DFU (USB device FS)/ DFU (V2.2)
SPI1/SPI2 SPI (V1.1)
USART1/USART2/USART3/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
STM32L43xxx/44xxx CAN1/ 0x91 0x1FFF6FFE CAN (V2.0)
DFU (USB device FS)/ DFU (V2.2)
SPI1/SPI2 SPI (V1.1)
USART1/USART2/USART3/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
STM32L45xxx/46xxx CAN1/ 0x92 0x1FFF6FFE CAN (V2.0)
DFU (USB device FS)/ DFU (V2.2)
SPI1/SPI2 SPI (V1.1)
USART1/USART2/ USART3/ USART (V3.1)
I2C1/I2C2/I2C3/ 0xA3 0x1FFF6FFE I2C (V1.2)
DFU (USB device FS) DFU (V2.2)
STM32L47xxx/48xxx USART1/USART2/ USART3/ USART (V3.1)
L4 I2C/I2C2/I2C3/ I2C (V1.2)
SPI1/SPI2/ 0x92 0x1FFF6FFE SPI (V1.1)
CAN1/ CAN(V2.0)
DFU (USB device FS) DFU(V2.2)
USART1/USART2/USART3/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
STM32L496xx/4A6xx CAN1/ 0x93 0x1FFF6FFE CAN (V2.0)
DFU (USB device FS)/ DFU (V2.2)
SPI1/SPI2 SPI (V1.1)
USART1/USART2/USART3/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
STM32L4Rxxx/STM32L4Sxxx CAN1/ 0x95 0x1FFF6FFE CAN (V2.0)
DFU (USB device FS)/ DFU (V2.2)
SPI1/SPI2 SPI (V1.1)
USART1/USART2/USART3 USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
STM32L4P5xx /Q5xx CAN1/ 0x90 0x1FFF6FFE CAN (V2.0)
DFU (USB device FS)/ DFU (V2.2)
SPI1/SPI2 SPI (V1.1)
USART1/USART2/USART3 USART (V3.1)
I2C1/I2C2/I2C3 I2C (V1.2)
L5 STM32L552xx/562xx SPI1/SPI2/SPI3 0x92 0x0BF97FFE SPI (V1.1)
DFU (USB device FS) DFU (V2.2)
FDCAN1 FDCAN (V1.0)

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Table 3. Embedded bootloaders (continued)

Bootloader ID Bootloader
STM32
Series

Device Supported serial peripherals Memory (protocol)

ID version
location
USART1/ USART (V3.2)
I2C1/I2C3 I2C (V1.2)
WB STM32WB50xx/55xx 0xD5 0x1FFF6FFE
SPI1/SPI2 SPI (V1.1)
DFU (USB device FS) DFU (V2.2)
USART1/USART2 USART (V3.1)
WL STM32WLE5xx 0xC2 0x1FF36EFE
SPI1/SPI2 SPI (V1.1)
1. For connectivity line devices, the USART bootloader returns V2.0 instead of V2.2 for the protocol version. For more details
refer to the “STM32F105xx and STM32F107xx revision Z” errata sheet available from www.st.com.

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4.3 Hardware connection requirements

To use the USART bootloader, the host must be connected to the RX and TX pins of the
desired USARTx interface via a serial cable.

Figure 1. USART connection

+V 1

R
RX 2 TX
RS232
Transceiver
STM32
UART Host TX RX Microcontroller
GND GND

MSv35098V1

1. A pull-up resistor must be added, if pull-up resistor are not connected in host side.
2. An RS232 transceiver must be connected to adapt voltage level (3.3 to 12 V) between STM32 device and
host.
Note: +V typically is 3.3 V and R typically 100 KΩ.These values depend upon the application and
the used hardware.
To use the DFU, connect the microcontroller USB interface to a USB host (i.e. a PC).

Figure 2. USB connection

1
+V
10K
36K

1.5K

VBus
DP DP
STM32
USB Host
DM DM Microcontroller
GND GND

MS35037V1

1. This additional circuit permits to connect a pull-up resistor to DP pin using VBus when needed. Refer to
product section (table describing STM32 configuration in system memory boot mode) to know if an external
pull-up resistor must be connected to DP pin.
Note: +V typically is 3.3 V. This value depends upon the application and the used hardware.
To use the I2C bootloader, connect the host (master) and the desired I2Cx interface (slave)
together via the data (SDA) and clock (SCL) pins. A 1.8 KΩ pull-up resistor has to be
connected to both SDA and SCL lines.

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Figure 3. I2C connection

+V

1.8K

1.8K
SCL SCL
STM32
I2C Host
SDA SDA Microcontroller
GND GND

MS35038V1

Note: +V is typically 3.3 V. This value depends upon the application and the used hardware.
To use the SPI bootloader, connect the host (master) and the desired SPIx interface (slave)
together via the MOSI, MISO and SCK pins. The NSS pin must be connected to GND. A
pull-down resistor must be connected to the SCK line.

Figure 4. SPI connection

NSS
MOSI MOSI
STM32
MISO MISO
SPI Host Microcontroller
SCK SCK
R

GND GND

MS35039V1

Note: R is typically 10 KΩ. This value depends on the application and the used hardware.
To use the CAN interface, the host has to be connected to the RX and TX pins of the desired
CANx interface via CAN transceiver and a serial cable. A 120 Ω resistor must be added as
terminating resistor.

Figure 5. CAN connection

RX CAN_H TX
CAN CAN STM32
CAN Host
120

120

Transceiv Transceiv
TX er er RX Microcontroller
CAN_L
GND GND

MS35040V1

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Note: When a bootloader firmware supports DFU, it is mandatory that no USB Host is connected
to the USB peripheral during the selection phase of the other interfaces. After selection
phase, the user can plug a USB cable without impacting the selected bootloader execution
except commands which generate a system reset.
It is recommended to keep the RX pins of unused bootloader interfaces (USART_RX,
SPI_MOSI, CAN_RX and USB D+/D- lines if present) at a known (low or high) level at the
startup of the bootloader (detection phase). Leaving these pins floating during the detection
phase might lead to activating unused interfaces.

4.4 Bootloader memory management

All write operations using bootloader commands must only be Word-aligned (the address
must be a multiple of 4). The number of data to be written must also be a multiple of 4 
(non-aligned half page write addresses are accepted).
Some Products embed bootloader that has some specific features:
 Some products do not support Mass erase operation. To perform a mass erase
operation using bootloader, two options are available:
– Erase all sectors one by one using the Erase command
– Set protection level to Level 1. Then, set it to Level 0 (using the Read protect
command and then the Read Unprotect command). This operation results in a
mass erase of the internal Flash memory.
 Bootloader firmware of STM32 L1 and L0 series supports Data Memory in addition to
standard memories (internal Flash, internal SRAM, option bytes and System memory).
The start address and the size of this area depends on product, refer to product
reference manual for more information. Data memory can be read and written but
cannot be erased using the Erase Command. When writing in a Data memory location,
the bootloader firmware manages the erase operation of this location before any write.
A write to Data memory must be Word-aligned (address to be written must be a
multiple of 4) and the number of data must also be a multiple of 4. To erase a Data
memory location, write zeros at this location.
 Bootloader firmware of STM32 F2, F4, F7 and L4 series supports OTP memory in
addition to standard memories (internal Flash, internal SRAM, option bytes and System
memory). The start address and the size of this area depends on product, refer to
product reference manual for more information. OTP memory can be read and written
but cannot be erased using Erase command. When writing in an OTP memory location,
make sure that the relative protection bit is not reset.
 For STM32 F2, F4 and F7 series the internal Flash memory write operation format
depends on voltage Range. By default write operation are allowed by one byte format
(Half-Word, Word and Double-Word operations are not allowed). to increase the speed
of write operation, the user must apply the adequate voltage range that allows write
operation by Half-Word, Word or Double-Word and update this configuration on the fly
by the bootloader software through a virtual memory location. This memory location is
not physical but can be read and written using usual bootloader read/write operations
according to the protocol in use. This memory location contains 4 bytes described in
Table 4. It can be accessed by 1, 2, 3 or 4 bytes. However, reserved bytes must remain
at their default values (0xFF), otherwise the request is NACKed.

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Table 4. STM32 F2, F4 and F7 voltage range configuration using bootloader

Address Size Description

This byte controls the current value of the voltage range.

0x00: voltage range [1.8 V, 2.1 V]
0x01: voltage range [2.1 V, 2.4 V]
0x02: voltage range [2.4 V, 2.7 V]
0xFFFF0000 1 byte 0x03: voltage range [2.7 V, 3.6 V]
0x04: voltage range [2.7 V, 3.6 V] and double word write/erase
operation is used. In this case it is mandatory to supply 9 V
through the VPP pin (refer to the product reference manual for
more details about the double-word write procedure).
Other: all other values are not supported and are NACKed.
Reserved.
0xFFFF0001 1 byte 0xFF: default value.
Other: all other values are not supported and are NACKed.
Reserved.
0xFFFF0002 1 byte 0xFF: default value.
Other: all other values are not supported and is NACKed.
Reserved.
0xFFFF0003 1 byte 0xFF: default value.
Other: all other values are not supported and are NACKed.

The table below lists the valid memory areas, depending upon the bootloader commands.

Table 5. Supported memory area by Write, Read, Erase and Go commands

Memory area Write command Read command Erase command Go command

Flash Supported Supported Supported Supported

RAM Supported Supported Not supported Supported
System memory Not supported Supported Not supported Not supported
Data memory Supported Supported Not supported Not supported
OTP memory Supported Supported Not supported Not supported

4.5 Bootloader UART baudrate detection

For the UART interface baudrate detection, there are two types of mechanisms
implemented on different STM32 devices:
 Software baudrate detection using internal HSI and timer (use GPIO as input, detect
falling edge and rising edge as explained in AN3155).
The devices using this mechanism are subject to software jitter (variable error of
baudrate calculation) that can reach up to ±5%.
So, in that case, the host connecting to the STM32 bootloader UART interface shall
support a deviation in baudrate equivalent to ±5%.
The software jitter value is variable and is different at each retry, so it is possible to use
multiple retry connections in order to overcome the software jitter (connect and check
for correct bootloader answer, if answer is not correct, reset the device and retry

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connection until the correct answer is received. Once correct answer is received the
rest of the communication is not impacted by software jitter).
It is also possible to reduce software jitter by reducing baudrate value (i.e. use
56000 bps instead of 115200).
Table 6 provides the maximum software jitter value for the baudrate 115200 bps.
The lower the baudrate the lower the software jitter.
 Baudrate detection using UART auto-baudrate feature.The devices using this
mechanism do not present any software jitter.

Table 6. Jitter software calculation on bootloader USART detection

Maximum software jitter
Series Baudrate detection method
for 115200 bps

STM32F0 Software baudrate detection -1%

STM32F1 Software baudrate detection -3%
STM32F2 Software baudrate detection -5%
STM32F3 Software baudrate detection -2%
STM32F4 Software baudrate detection -6%
STM32F7 Software baudrate detection -6%
STM32L0 Software baudrate detection -2%
STM32L1 Software baudrate detection -3%
STM32L4 Software baudrate detection -5%
STM32G07x/8x UART3
Software baudrate detection -4%
STM32G03x/4x UART2
STM32G07x/8x UART1/UART2
Auto-baudrate N/A
STM32G03x/4x UART1
STM32G4 Auto-baudrate N/A
STM32H7 Auto-baudrate N/A
STM32WB Auto-baudrate N/A
STM32WL Auto-baudrate N/A

4.6 Programming constraints

When using bootloader interface to write in the Flash memory, alignment on the
programmed address must be respected according to Table 7.
If the address to which the write operation is not aligned, then it fails and all following
program operations fail as well.

Table 7. Flash memory alignment constraints on STM32 products

Series Alignment

STM32F0 4 bytes
STM32F1 4 bytes

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Table 7. Flash memory alignment constraints on STM32 products (continued)

Series Alignment

STM32F2 4 bytes
STM32F3 4 bytes
STM32F4 4 bytes
STM32F7 8 bytes
STM32L0 8 bytes
STM32L1 8 bytes
STM32L4 8 bytes
STM32G0 4 bytes
STM32G4 4 bytes
STM32H7 8 bytes
STM32WB 8 bytes
STM32WL 8 bytes

Example of alignment:
 4 bytes: 0x08000014 is aligned and passes, 0x08000012 is not aligned and fails
 8 bytes: 0x08000010 is aligned and passes, 0x08000014 is not aligned and fails
Note: On some products (STM32F4 and STM32F7) it is possible to change the alignment
constraint by writing in the device feature space.

4.7 ExitSecureMemory feature

The securable memory area is used to isolate secure boot code/data, which handle
sensitive information (secrets), from application code:
 Access is controlled by a securable memory bit SEC_PROT (write once), in the
FLASH_CR register
 Executed once at boot then locked by writing the securable memory bit
– The code protected: in the securable memory area is hidden until the next reset
that unlocks the SEC_PROT bit
 Width (number of Flash memory pages) is defined through an option byte, SEC_SIZE,
in the Flash memory FLASH_SEC_R register
The ExitSecureMemory is a software developed and hosted on the system memory. When
the user boot code jump to it, the software allows setting the SEC_PROT bit to “1” and then
jumping to the application code. The SEC_SIZE must be set to the needed value before
jumping to the ExitSecureMemory function.
As shown in Figure 6, two jump methods can be used by the customer:

Jump to the secure memory function without parameter

In this case the application must be loaded just after the secure memory defined.

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Jump to the secure memory function using two parameters

1. Magic number
 0x08192A3C
– Used to secure boot code/data in Flash and jump in case of a single bank product
– Used to secure boot code/data in Bank1 and jump in case of a dual bank product
 0x08192A3D
– Used to secure boot code/data and jump to application in Bank2 in case of a dual
bank product
2. User address = Application address
 In this case the application can be loaded to any desired address (as per user address
defined)

Figure 6. ExitSecureMemory function usage

System memory User Flash memory

Boot code/data SEC_SIZE Boot code/data

1
Bootloader (to protect) (hidden)

Application Application
ExitSecureMemory
3
2

Jump to the secure memory area without parameter

System memory User Flash memory

1 Boot code/data SEC_SIZE Boot code/data

Bootloader (to protect) (hidden)

ExitSecureMemory 3
2
Application Application

Jump to the secure memory area with parameter

(Magic number + Application address)
MS53655V1

Note: For more information regarding the option bytes configuration refer to the reference manual.
Note: An example of a function that can be used to call the “ExitSecureMemory” is in Appendix A.

Table 8. ExitSecureMemory entry address

MCU ExitSecureMemory address

STM32G07xxx/08xxx 0x1FFF6800
STM32G0
STM32G03xxx/04xxx 0x1FFF1E00
STM32G47xxx/48xxx 0x1FFF6800
STM32G4
STM32G431xx/441xx 0x1FFF6800

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For more details refer to Figure 7.

Figure 7. Access to securable memory area from the bootloader

Jump to secure
memory address

R1=Magic number
No and
R2=User address

Yes
Flash dual bank

Check link register to know from Jump to ExitSecArea() Single bank Dual bank
which bank happening the jump function

Valid magic bank1 Valid magic

Set bank’s securable number for which bank2
number
memory bit bank

Set securable Set securable

memory bit for memory bit for
Jump just after securable Set securable bank1 bank2
memory area memory bit

Jump to user Jump to user

address address
Jump to user
address

MS51971V1

1. The Bootloader does not check the integrity of the user address, it is up to the user to ensure the validity of the address to
jump to.

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5 STM32F03xx4/6 devices bootloader

5.1 Bootloader configuration

The STM32F03xx4/6 bootloader is activated by applying Pattern 2 (see Table 2: Bootloader
activation patterns). Table 9 shows the hardware resources used by this bootloader.

Table 9. STM32F03xx4/6 configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

RCC HSI enabled (using PLL clocked by HSI).
1 Flash Wait State.
2 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
Common to all 3 Kbyte starting from address 0x1FFFEC00
bootloaders System memory -
contain the bootloader firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
IWDG - value. It is periodically refreshed to prevent
watchdog reset in case the hardware IWDG
option was previously enabled by the user.
Once initialized, the USART1 configuration
USART1 Enabled
is 8 bits, even parity and 1 Stop bit.
USART1 bootloader
(on PA10/PA9) USART1_RX pin Input PA10 pin: USART1 in reception mode.
USART1_TX pin Output PA9 pin: USART1 in transmission mode.
Once initialized, the USART1 configuration
USART1 Enabled
is 8 bits, even parity and 1 Stop bit.
USART1 bootloader
(on PA14/PA15) USART1_RX pin Input PA15 pin: USART1 in reception mode.
USART1_TX pin Output PA14 pin: USART1 in transmission mode.
Used to automatically detect the serial baud
USART1 bootloaders SysTick timer Enabled
rate from the host.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.
Note: After the STM32F03xx4/6 devices has booted in bootloader mode, serial wire debug (SWD)
communication is no longer possible until the system is reset. This is because the SWD
uses the PA14 pin (SWCLK) which is already used by the bootloader (USART1_TX).

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5.2 Bootloader selection

Figure 8 shows the bootloader selection mechanism.

Figure 8. Bootloader selection for STM32F03xx4/6 devices

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

0x7F received on
USARTx

no
yes

Disable all
interrupt sources

Configure
USARTx

Execute
BL_USART_Loop
for USARTx
MS35015V1

5.3 Bootloader version

The following table lists the STM32F03xx4/6 devices bootloader versions.

Table 10. STM32F03xx4/6 bootloader versions

Bootloader
version Description Known limitations
number

For the USART interface, two consecutive

NACKs instead of 1 NACK are sent when a
V1.0 Initial bootloader version
Read Memory or Write Memory command is
sent and the RDP level is active.

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6 STM32F030xC devices bootloader

6.1 Bootloader configuration

The STM32F030xC bootloader is activated by applying Pattern 2 (see Table 2: Bootloader
activation patterns). Table 11 shows the hardware resources used by this bootloader.

Table 11. STM32F030xC configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 48 MHz with

RCC HSI enabled
HSI 8 MHz as clock source.
6 Kbyte starting from address 0x20000000
Common to all RAM -
are used by the bootloader firmware
bootloaders
8 Kbyte starting from address
System memory - 0x1FFFD800, contain the bootloader
firmware.
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA15 pin: USART2 in reception mode
USART2_TX pin Output PA14 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000001x 
(where x = 0 for write and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

Note: After the STM32F030xC devices have booted in bootloader mode using USART2, the serial
wire debug (SWD) communication is no more possible until the system is reset, because
SWD uses PA14 pin (SWCLK) which is already used by the bootloader (USART2_RX).
The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

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6.2 Bootloader selection

Figure 9 shows the bootloader selection mechanism.

Figure 9.Bootloader selection for STM32F030xC

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure I2Cx

yes

0x7F received on Disable all interrupt

USARTx sources and other
yes interfaces clock’s
no
Disable all interrupt
Configure
sources and other
USARTx
I2Cx Address interfaces clock’s
Detected
no Execute
Execute
BL_I2C_Loop for BL_USART_Loop
I2Cx for USARTx

MSv36789V1

6.3 Bootloader version

Table 12 lists the STM32F030xC devices bootloader versions.

Table 12. STM32F030xC bootloader versions

Bootloader
version Description Known limitations
number

V5.2 Initial bootloader version None

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7 STM32F05xxx and STM32F030x8 devices bootloader

7.1 Bootloader configuration

The STM32F05xxx and STM32F030x8 devices bootloader is activated by applying
Pattern 2 (described in Table 2: Bootloader activation patterns). Table 13 shows the
hardware resources used by this bootloader.

Table 13. STM32F05xxx and STM32F030x8 devices configuration in system memory boot mode
Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

RCC HSI Enabled (using PLL clocked by HSI).
1 Flash Wait State.
2 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.

Common to all 3 Kbyte starting from address

bootloaders System memory - 0x1FFFEC00, contain the bootloader
firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
IWDG - value. It is periodically refreshed to prevent
watchdog reset in case the hardware IWDG
option was previously enabled by the user.
Once initialized, the USART1 configuration
USART1 Enabled
is 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode.
USART1_TX pin Output PA9 pin: USART1 in transmission mode.
Once initialized, the USART2 configuration
USART2 Enabled
is 8 bits, even parity and 1 Stop bit.
USART2 bootloader
USART2_RX pin Input PA15 pin: USART2 in reception mode.
USART2_TX pin Output PA14 pin: USART2 in transmission mode.
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.
Note: After the STM32F05xxx and STM32F030x8 devices have booted in bootloader mode, the
serial wire debug (SWD) communication is no more possible until the system is reset,
because SWD uses PA14 pin (SWCLK), already used by the bootloader (USART2_TX).

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7.2 Bootloader selection

Figure 10 shows the bootloader selection mechanism.

Figure 10. Bootloader selection for STM32F05xxx and STM32F030x8 devices

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

0x7F received on
USARTx

no
yes

Disable all
interrupt sources

Configure
USARTx

Execute
BL_USART_Loop
for USARTx
MS35014V1

7.3 Bootloader version

Table 14 lists the STM32F05xxx and STM32F030x8 devices bootloader versions.

Table 14. STM32F05xxx and STM32F030x8 devices bootloader versions

Bootloader
version Description Known limitations
number

– At bootloader startup, the HSITRIM value is set

to 0 (in HSITRIM bits on RCC_CR register)
instead of default value (16), as a consequence
a deviation is generated in crystal
measurement. For better results, use the
V2.1 Initial bootloader version smallest supported crystal value (i.e. 4 MHz).
– For the USART interface, two consecutive
NACKs instead of 1 NACK are sent when a
Read Memory or Write Memory command is
sent and the RDP level is active.

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8 STM32F04xxx devices bootloader

8.1 Bootloader configuration

The STM32F04xxx bootloader is activated by applying Pattern 6 (described in Table 2:
Bootloader activation patterns). Table 15 shows the hardware resources used by this
bootloader.

Table 15. STM32F04xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 48 MHz with

HSI enabled
HSI48 48 MHz as clock source.
RCC The clock recovery system (CRS) is
- enabled for the DFU bootloader to allow
USB to be clocked by HSI48 48 MHz.
6 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
Common to all
13 Kbyte starting from address
bootloaders
System memory - 0x1FFFC400, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA15 pin: USART2 in reception mode
USART2_TX pin Output PA14 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111110x (where x = 0 for write
and x = 1 for read).
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

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Table 15. STM32F04xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB Enabled USB used in FS mode

USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required.

Note: After the STM32F04xxx devices have booted in bootloader mode using USART2, the serial
wire debug (SWD) communication is no more possible until the system is reset, because
SWD uses PA14 pin (SWCLK) which is already used by the bootloader (USART2_RX).
The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.
Note: Due to empty check mechanism present on this product, it is not possible to jump from user
code to system bootloader. Such jump results in a jump back to user Flash memory space.
But if the first 4 bytes of User Flash (at 0x0800 0000) are empty at the moment of jump (i.e.
erase first sector before jump or execute code from SRAM while Flash is empty), then
system bootloader is executed when jumped to.

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8.2 Bootloader selection

Figure 11 shows the bootloader selection mechanism.

Figure 11. Bootloader selection for STM32F04xxx

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure I2Cx

Configure USB FS device

0x7F received
yes
on USARTx
yes
no
Disable all interrupt
Disable all interrupt
sources and other
sources and other
I2Cx Address
Detected yes interfaces clock’s interfaces clock’s

Disable other
no interfaces clock’s Execute Configure
no BL_I2C_Loop for USARTx
I2Cx
USB
Detected Execute DFU
bootloader using USB Execute
interrupts BL_USART_Loop
for USARTx

MS35025V1

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8.3 Bootloader version

The following table lists the STM32F04xxx devices bootloader versions:

Table 16. STM32F04xxx bootloader versions

Bootloader
version Description Known limitations
number

V10.0 Initial bootloader version At bootloader startup, the HSITRIM value is set to 0 (in
HSITRIM bits on RCC_CR register) instead of default
Add dynamic support of value (16), as a consequence a deviation is generated
USART/USB interfaces on in crystal measurement.
V10.1
PA11/12 IOs for small For better results, use the smallest supported crystal
packages. value (i.e. 4 MHz).

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9 STM32F070x6 devices bootloader

9.1 Bootloader configuration

The STM32F070x6 bootloader is activated by applying Pattern 6 (described in Table 2:
Bootloader activation patterns). Table 17 shows the hardware resources used by this
bootloader.

Table 17. STM32F070x6 configuration in system memory boot mode

Feature/Periphe
Bootloader State Comment
ral
At startup, the system clock frequency is configured
HSI enabled to 48 MHz using the HSI. If an external clock (HSE) is
not present, the system is kept clocked from the HSI.
The external clock can be used for all bootloader
interfaces and must have one of the following values
RCC HSE enabled
[24, 18, 16, 12, 8, 6, 4] MHz. The PLL is used to
Common to all generate 48 MHz for USB and system clock.
bootloaders The Clock Security System (CSS) interrupt is enabled
- for HSE. Any failure (or removal) of the external clock
generates system reset.
6 Kbyte starting from address 0x20000000 are used
RAM -
by the bootloader firmware
13 Kbyte starting from address 0x1FFFC400, contain
System memory -
the bootloader firmware.
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bit,
USART2 Enabled
even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA15 pin: USART2 in reception mode
USART2_TX pin Output PA14 pin: USART2 in transmission mode
Used to automatically detect the serial baud rate from
USARTx bootloaders SysTick timer Enabled
the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
I2C1 bootloader Slave 7-bit address: 0b0111110x where x = 0 for write
and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.

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Table 17. STM32F070x6 configuration in system memory boot mode (continued)

Feature/Periphe
Bootloader State Comment
ral
USB FS configured in forced device mode. USB FS
USB Enabled interrupt vector is enabled and used for USB DFU
communications.
DFU bootloader
USB_DM pin PA11 pin: USB FS DM line
Input/Output PA12 pin: USB FS DP line.
USB_DP pin
No external pull-up resistor is required.

Note: If HSI deviation exceeds 1% the bootloader might not function correctly.
Note: After the STM32F070x6 devices have booted in bootloader mode using USART2, the serial
wire debug (SWD) communication is no more possible until the system is reset, because
SWD uses PA14 pin (SWCLK) which is already used by the bootloader (USART2_RX).
The bootloader has two cases of operation depending on the presence of the external clock
(HSE) at bootloader startup:
 If HSE is present and has a value of 24, 18, 16, 12, 8, 6, 4 MHz, the system clock is
configured to 48 MHz with HSE as clock source. The DFU interface, USART1,
USART2 and I2C1 are functional and can be used to communicate with the bootloader
device.
 If HSE is not present, the HSI is kept as default clock source and only USART1,
USART2 and I2C1 are functional.
The external clock (HSE) must be kept if it is connected at bootloader startup because it is
used as system clock source.
Note: Due to empty check mechanism present on this product, it is not possible to jump from user
code to system bootloader. Such jump results in a jump back to user Flash space, but if the
first 4 bytes of User Flash (at 0x0800 0000) are empty at the moment of jump (i.e. erase first
sector before jump or execute code from SRAM while Flash is empty), then system
bootloader is executed when jumped to.

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9.2 Bootloader selection

Figure 12 shows the bootloader selection mechanism.

Figure 12. Bootloader selection for STM32F070x6

System Reset

Configure System clock to

48 MHz using HSI

HSE= 24, 18, 16, no

12, 8, 6, 4 MHz ?

yes

Reconfigure System clock to

48 MHz using HSE

System Init (Clock, GPIOs,

System Init (Clock, GPIOs, IWDG, SysTick)
IWDG, SysTick)

Configure USB

Configure I2Cx

0x7F received
yes
on USARTx

yes
no
Disable all interrupt
sources and other
interfaces clock’s
I2Cx Address
Detected yes
Disable all interrupt
Disable other sources and other Configure
interfaces clock’s interfaces clock’s USARTx
no
no

Execute DFU Execute Execute

USB cable
bootloader using USB BL_I2C_Loop for BL_USART_Loop
Detected & USB
interrupts I2Cx for USARTx
configured

MSv36794V1

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9.3 Bootloader version

Table 18 lists the STM32F070x6 devices bootloader versions.

Table 18. STM32F070x6 bootloader versions

Bootloader
version Description Known limitations
number

V10.2 Initial bootloader version At bootloader startup, the HSITRIM value is set to
0 (in HSITRIM bits on RCC_CR register) instead
of default value (16), as a consequence a
Clock configuration fixed deviation is generated in crystal measurement.
V10.3
to HSI 8 MHz For better results, use the smallest supported
crystal value (i.e. 4 MHz).

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10 STM32F070xB devices bootloader

10.1 Bootloader configuration

The STM32F070xB bootloader is activated by applying Pattern 2 (described in Table 2:
Bootloader activation patterns). Table 19 shows the hardware resources used by this
bootloader.

Table 19. STM32F070xB configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
At startup, the system clock frequency is
configured to 48 MHz using the HSI. If an
HSI enabled
external clock (HSE) is not present, the
system is kept clocked from the HSI.
The external clock can be used for all
bootloader interfaces and must have one of
RCC HSE enabled the following values [24, 18, 16, 12, 8, 6, 4]
MHz. The PLL is used to generate 48 MHz
Common to all for USB and system clock.
bootloaders The Clock Security System (CSS) interrupt
is enabled for HSE. Any failure (or removal)
-
of the external clock generates system
reset.
6 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
12 Kbyte starting from address
System memory - 0x1FFFC800, contain the bootloader
firmware.
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA15 pin: USART2 in reception mode
USART2_TX pin Output PA14 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b0111011x
I2C1 bootloader (where x = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

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Table 19. STM32F070xB configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
USB FS configured in forced device mode.
USB Enabled USB FS interrupt vector is enabled and
used for USB DFU communications.
DFU bootloader USB_DM pin PA11 pin: USB FS DM line
Input/Output PA12 pin: USB FS DP line.
USB_DP pin
No external pull-up resistor is required.

Note: If HSI deviation exceeds 1% the bootloader might not function correctly.
Note: After the STM32F070xB devices have booted in bootloader mode using USART2, the serial
wire debug (SWD) communication is no more possible until the system is reset, because
SWD uses PA14 pin (SWCLK) which is already used by the bootloader (USART2_RX).
The bootloader has two cases of operation depending on the presence of the external clock
(HSE) at bootloader startup:
 If HSE is present and has a value of 24, 18, 16, 12, 8, 6, 4 MHz, the system clock is
configured to 48 MHz with HSE as clock source. The DFU interface, USART1,
USART2 and I2C1 are functional and can be used to communicate with the bootloader
device.
 If HSE is not present, the HSI is kept as default clock source and only USART1,
USART2 and I2C1 are functional.
The external clock (HSE) must be kept if it is connected at bootloader startup because it is
used as system clock source.

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10.2 Bootloader selection

Figure 13 shows the bootloader selection mechanism.

Figure 13.Bootloader selection for STM32F070xB

System Reset

Configure System clock to

48 MHz using HSI

HSE= 24, 18, 16, 12, 8, no

6, 4 MHz ?

yes

Reconfigure System clock to

48 MHz using HSE

System Init (Clock, GPIOs,

System Init (Clock, GPIOs, IWDG, SysTick)
IWDG, SysTick)

Configure USB

Configure I2Cx

0x7F received
yes
on USARTx

yes
no
Disable all interrupt
sources and other
interfaces clock’s
I2Cx Address
Detected yes
Disable all interrupt
Disable other sources and other Configure
interfaces clock’s interfaces clock’s USARTx
no
no

Execute DFU Execute Execute

USB cable
bootloader using USB BL_I2C_Loop for BL_USART_Loop
Detected & USB
interrupts I2Cx for USARTx
configured

MSv36795V1

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10.3 Bootloader version

Table 20 lists the STM32F070xB devices bootloader versions.

Table 20. STM32F070xB bootloader versions

Bootloader
version Description Known limitations
number

V10.2 Initial bootloader version At bootloader startup, the HSITRIM value is set to
(0) (in HSITRIM bits on RCC_CR register) instead
of default value (16), as a consequence a
Clock configuration fixed deviation is generated in crystal measurement.
V10.3
to HSI 8 MHz For better results, use the smallest supported
crystal value (i.e. 4 MHz).

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11 STM32F071xx/072xx devices bootloader

11.1 Bootloader configuration

The STM32F071xx/072xx bootloader is activated by applying Pattern 2 (described in
Table 2: Bootloader activation patterns). Table 21 shows the hardware resources used by
this bootloader.

Table 21. STM32F071xx/072xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 48 MHz with

HSI enabled
HSI48 48 MHz as clock source.
RCC The clock recovery system (CRS) is
- enabled for the DFU bootloader to allow
USB to be clocked by HSI48 48 MHz.
6 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
Common to all
12 Kbyte starting from address
bootloaders
System memory - 0x1FFFC800, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA15 pin: USART2 in reception mode
USART2_TX pin Output PA14 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111011x (where x = 0 for write
and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

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Table 21. STM32F071xx/072xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB Enabled USB used in FS mode

USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required.

Note: After the STM32F071xx/072xx devices have booted in bootloader mode using USART2, the
serial wire debug (SWD) communication is no more possible until the system is reset,
because SWD uses PA14 pin (SWCLK) which is already used by the bootloader
(USART2_RX).
The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

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11.2 Bootloader selection

Figure 14 shows the bootloader selection mechanism.

Figure 14. Bootloader selection for STM32F071xx/072xx

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure I2Cx

Configure USB FS device

0x7F received on
yes
USARTx
yes
no
Disable all interrupt
Disable all interrupt
sources and other
sources and other
I2Cx Address
Detected yes interfaces clock’s interfaces clock’s

Disable other
no interfaces clock’s Execute Configure
no BL_I2C_Loop for USARTx
I2Cx
USB
Detected Execute DFU
bootloader using USB Execute
interrupts BL_USART_Loop
for USARTx

MS35026V1

11.3 Bootloader version

Table 22 lists the STM32F071xx/072xx devices bootloader versions.

Table 22. STM32F071xx/072xx bootloader versions

Bootloader
version Description Known limitations
number

At bootloader startup, the HSITRIM value is set to

(0) (in HSITRIM bits on RCC_CR register) instead
of default value (16), as a consequence a deviation
V10.1 Initial bootloader version
is generated in crystal measurement. For better
results, use the smallest supported crystal value
(i.e. 4 MHz).

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AN2606 STM32F09xxx devices bootloader

12 STM32F09xxx devices bootloader

12.1 Bootloader configuration

The STM32F09xxx bootloader is activated by applying Pattern 6 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 23. STM32F09xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 48 MHz with

RCC HSI enabled
HSI48 48 MHz as clock source.
6 Kbyte starting from address 0x20000000
Common to all RAM -
are used by the bootloader firmware
bootloaders
8 Kbyte starting from address
System memory - 0x1FFFD800, contain the bootloader
firmware.
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
PA3 pin: USART2 in reception mode
USART2 bootloader USART2_RX pin Input
PA15 pin: USART2 in reception mode
PA2 pin: USART2 in transmission mode
USART2_TX pin Output
PA14 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000001x 
(where x = 0 for write and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

Note: After the STM32F09xxx devices have booted in bootloader mode using USART2, the serial
wire debug (SWD) communication is no more possible until the system is reset, because
SWD uses PA14 pin (SWCLK) which is already used by the bootloader (USART2_RX).
The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

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12.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 15. Bootloader selection for STM32F09xxx

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure I2Cx

yes

0x7F received on Disable all interrupt

USARTx sources and other
yes interfaces clock’s
no
Disable all interrupt
Configure
sources and other
USARTx
I2Cx Address interfaces clock’s
Detected
no Execute
Execute
BL_I2C_Loop for BL_USART_Loop
I2Cx for USARTx

MSv36789V1

12.3 Bootloader version

The following table lists the STM32F09xxx devices bootloader versions.

Table 24. STM32F09xxx bootloader versions

Bootloader
version Description Known limitations
number

At bootloader startup, the HSITRIM value is set to

(0) (in HSITRIM bits on RCC_CR register) instead
of default value (16), as a consequence a deviation
V5.0 Initial bootloader version
is generated in crystal measurement. For better
results, use the smallest supported crystal value
(i.e. 4 MHz).

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13 STM32F10xxx devices bootloader

13.1 Bootloader configuration

The STM32F10xxx bootloader is activated by applying Pattern 1 (described in Table 2:
Bootloader activation patterns). Table 25 shows the hardware resources used by this
bootloader.

Table 25. STM32F10xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

RCC HSI enabled
using the PLL.
512 byte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
2 Kbyte starting from address 0x1FFFF000
System memory -
contain the bootloader firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
USART1 bootloader IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output push-pull PA9 pin: USART1 in transmission mode
Used to automatically detect the serial baud
SysTick timer Enabled
rate from the host.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

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13.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 16. Bootloader selection for STM32F10xxx

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

0x7F received on
USARTx

No
Yes

Disable all
interrupt sources

Configure
USARTx

Execute
BL_USART_Loop
for USARTx
MS35004V1

13.3 Bootloader version

Table 26 lists the STM32F10xxx devices bootloader versions:

Table 26. STM32F10xxx bootloader versions

Bootloader version number Description

V2.0 Initial bootloader version

– Updated Go Command to initialize the main stack pointer
– Updated Go command to return NACK when jump address is in
V2.1 the Option byte area or System memory area
– Updated Get ID command to return the device ID on two bytes
– Update the bootloader version to V2.1
– Updated Read Memory, Write Memory and Go commands to
deny access with a NACK response to the first 0x200 bytes of
V2.2 RAM memory used by the bootloader
– Updated Readout Unprotect command to initialize the whole
RAM content to 0x0 before ROP disable operation

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Note: The bootloader ID format is applied to all STM32 devices families except the STM32F1xx
family. The bootloader version for the STM32F1xx applies only to the embedded device’s
bootloader version and not to its supported protocols.

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14 STM32F105xx/107xx devices bootloader

14.1 Bootloader configuration

The STM32F105xx/107xx bootloader is activated by applying Pattern 1 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 27. STM32F105xx/107xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

using the PLL. This is used only for
USARTx bootloaders and during CAN2,
HSI enabled USB detection for CAN and DFU
bootloaders (once CAN or DFU bootloader
is selected, the clock source is derived from
the external crystal).
The external clock is mandatory only for
DFU and CAN bootloaders and it must
provide one of the following frequencies: 8
RCC MHz, 14.7456 MHz or 25 MHz.
For CAN bootloader, the PLL is used only
HSE enabled
to generate 48 MHz when 14.7456 MHz is
used as HSE.
For DFU bootloader, the PLL is used to
generate a 48 MHz system clock from all
Common to all supported external clock frequencies.
bootloaders
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
external clock will generate system reset.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
18 Kbyte starting from address
System memory - 0x1FFFB000 contain the bootloader
firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output push-pull PA9 pin: USART1 in transmission mode

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Table 27. STM32F105xx/107xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized, the USART2 configuration

USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 receive (remapped pin)
USART2_TX pin Output push-pull PD5 pin: USART2 transmit (remapped pin)
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.
Once initialized, the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during the CAN
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 receives (remapped pin).
CAN2_TX pin Output push-pull PB6 pin: CAN2 transmits (remapped pin).
USB OTG FS configured in forced device
USB Enabled
mode
USB_VBUS pin Input PA9: Power supply voltage line
DFU bootloader
USB_DM pin PA11 pin: USB_DM line
Input/Output PA12 pin: USB_DP line.
USB_DP pin
No external pull-up resistor is required

The system clock is derived from the embedded internal high-speed RC for USARTx
bootloader. This internal clock is used also for DFU and CAN bootloaders but only for the
selection phase. An external clock (8 MHz, 14.7456 MHz or 25 MHz) is required for DFU
and CAN bootloader execution after the selection phase.

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14.2 Bootloader selection

Figure 17 shows the bootloader selection mechanism.

Figure 17. Bootloader selection for STM32F105xx/107xx devices

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB

USB cable
yes
Detected

no yes
Disable all
interrupt sources HSE= 8MHz,
no 0x7F received on
USARTx 14.7456MHz or
Configure 25 MHz
USARTx
no
yes
Frame detected on Execute
CANx BL_USART_Loop
Reconfigure System
for USARTx
clock to 48MHz and
yes USB clock to 48 MHz

HSE= 8MHz, Execute DFU

no bootloader using USB
14.7456MHz or no
25 MHz interrupts

Generate System
yes
reset
Reconfigure System
clock to 48MHz

Disable all
interrupt sources

Configure CAN

Execute
BL_CAN_Loop for
CANx
MS35005V1

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14.3 Bootloader version

The following table lists the STM32F105xx/107xx devices bootloader versions:

Table 28. STM32F105xx/107xx bootloader versions

Bootloader version
Description
number

V1.0 Initial bootloader version

– Bootloader detection mechanism updated to fix the issue when GPIOs of
unused peripherals in this bootloader are connected to low level or left
floating during the detection phase.
For more details refer to Section 14.3.2.
– Vector table set to 0x1FFFB000 instead of 0x00000000
– Go command updated (for all bootloaders): USART1, USART2, CAN2,
V2.0
GPIOA, GPIOB, GPIOD and SysTick peripheral registers are set to their
default reset values
– DFU bootloader: USB pending interrupt cleared before executing the Leave
DFU command
– DFU subprotocol version changed from V1.0 to V1.2
– Bootloader version updated to V2.0
– Fixed PA9 excessive consumption described in Section 14.3.4.
– Get-Version command (defined in AN3155) corrected. It returns 0x22
V2.1
instead of 0x20 in bootloader V2.0. Refer to Section 14.3.3 for more details.
– Bootloader version updated to V2.1
– Fixed DFU option bytes descriptor (set to ‘e’ instead of ‘g’ because it is
read/write and not erasable).
V2.2 – Fixed DFU polling timings for Flash Read/Write/Erase operations.
– Robustness enhancements for DFU bootloader interface.
– Updated bootloader version to V2.2.

Note: The bootloader ID format is applied to all STM32 devices families except the STM32F1xx
family. The bootloader version for the STM32F1xx applies only to the embedded device’s
bootloader version and not to its supported protocols.

14.3.1 How to identify STM32F105xx/107xx bootloader versions

Bootloader V1.0 is implemented on devices whose date code is lower than 937 (refer to
STM32F105xx and STM32F107xx datasheet to find the date code on the device marking).
Bootloader V2.0 and V2.1 are implemented on devices with a date code higher than or
equal to 937.
Bootloader V2.2 is implemented on devices with a date code higher than or equal to 227.
There are two ways to distinguish between bootloader versions:
 When using the USART bootloader, the Get-Version command defined in AN2606 and
AN3155 has been corrected in V2.1 version. It returns 0x22 instead of 0x20 as in
bootloader V2.0.

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 The values of the vector table at the beginning of the bootloader code are different. The
user software (or via JTAG/SWD) reads 0x1FFFE945 at address 0x1FFFB004 for
bootloader V2.0 0x1FFFE9A1 for bootloader V2.1, and 0x1FFFE9C1 for bootloader
V2.2.
 The DFU version is the following:
– V2.1 in bootloader V2.1
– V2.2 in bootloader V2.2.
It can be read through the bcdDevice field of the DFU Device Descriptor.

14.3.2 Bootloader unavailability on STM32F105xx/STM32F107xx devices

with date code lower than 937
Description
The bootloader cannot be used if the USART1_RX (PA10), USART2_RX (PD6, remapped),
CAN2_Rx (PB5, remapped), OTG_FS_DM (PA11), and/or OTG_FS_DP (PA12) pin(s) are
held low or left floating during the bootloader activation phase.
The bootloader cannot be connected through CAN2 (remapped), DFU (OTG FS in Device
mode), USART1 or USART2 (remapped).
On 64-pin packages, the USART2_RX signal remapped PD6 pin is not available and it is
internally grounded. In this case, the bootloader cannot be used at all.

Workaround
 For 64-pin packages
None. The bootloader cannot be used.
 For 100-pin packages
Depending on the used peripheral, the pins for the unused peripherals have to be kept
at a high level during the bootloader activation phase as described below:
– If USART1 is used to connect to the bootloader, PD6 and PB5 have to be kept at a
high level.
– If USART2 is used to connect to the bootloader, PA10, PB5, PA11 and PA12 have
to be kept at a high level.
– If CAN2 is used to connect to the bootloader, PA10, PD6, PA11 and PA12 have to
be kept at a high level.
– If DFU is used to connect to the bootloader, PA10, PB5 and PD6 have to be kept
at a high level.
Note: This limitation applies only to STM32F105xx and STM32F107xx devices with a date code
below 937. STM32F105xx and STM32F107xx devices with a date code higher or equal to
937 are not impacted. See STM32F105xx and STM32F107xx datasheets for where to find
the date code on the device marking.

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14.3.3 USART bootloader Get-Version command returns 0x20

instead of 0x22
Description
In USART mode, the Get-Version command (defined in AN3155) returns 0x20 instead of
0x22.
This limitation is present on bootloader versions V1.0 and V2.0, while it is fixed in bootloader
version 2.1.

Workaround
None.

14.3.4 PA9 excessive power consumption when USB cable is plugged

in bootloader V2.0
Description
When connecting a USB cable after booting from System-Memory mode, PA9 pin
(connected to VBUS=5 V) is also shared with USART TX pin which is configured as alternate
push-pull and forced to 0 since the USART peripheral is not yet clocked. As a consequence,
a current higher than 25 mA is drained by PA9 I/O and may affect the I/O pad reliability.
This limitation is fixed in bootloader version 2.1 by configuring PA9 as alternate function
push-pull when a correct 0x7F is received on RX pin and the USART is clocked. Otherwise,
PA9 is configured as alternate input floating.

Workaround
None.

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15 STM32F10xxx XL-density devices bootloader

15.1 Bootloader configuration

The STM32F10xxx XL-density bootloader is activated by applying Pattern 3 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 29. STM32F10xxx XL-density configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

RCC HSI enabled
using the PLL.
2 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
6 Kbyte starting from address 0x1FFFE000
Common to all System memory -
contain the bootloader firmware.
bootloaders
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output push-pull PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled
is: 8 bits, even parity and 1 Stop bit.
PD6 pin: USART2 receives (remapped
USART2 bootloader USART2_RX pin Input
pins).
PD5 pin: USART2 transmits (remapped
USART2_TX pin Output push-pull
pins).
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

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15.2 Bootloader selection

Figure 18 shows the bootloader selection mechanism.

Figure 18. Bootloader selection for STM32F10xxx XL-density devices

System Reset

BFB2 bit reset

(BFB2 = 0)

yes

If Value
@0x08080000 is
yes
within int. SRAM
address Jump to user code
in Bank2
no no

If Value
@0x08000000 is
yes
within int. SRAM
address Jump to user code
in Bank1
no

Continue Bootloader execution

Disable all
interrupt sources

System Init (Clock, GPIOs,

IWDG, SysTick)
yes Configure
USARTx

0x7F received on Execute

USARTx BL_USART_Loop
for USARTx

no
MS35006V1

15.3 Bootloader version

Table 30 lists the STM32F10xxx XL-density devices bootloader versions.

Table 30. STM32F10xxx XL-density bootloader versions

Bootloader version number Description

V2.1 Initial bootloader version

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Note: The bootloader ID format is applied to all STM32 devices families except the STM32F1xx
family. The bootloader version for the STM32F1xx applies only to the embedded device
bootloader version and not to its supported protocols.

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AN2606 STM32F2xxxx devices bootloader

16 STM32F2xxxx devices bootloader

Two bootloader versions are available on STM32F2xxxx devices:

 V2.x supporting USART1 and USART3
This version is embedded in revisions A, Z and B
 V3.x supporting USART1, USART3, CAN2 and DFU (USB FS device)
This version is embedded in all other revisions (Y, X, W, 1, V, 2, 3 and 4)

16.1 Bootloader V2.x

16.1.1 Bootloader configuration

The STM32F2xxxx bootloader is activated by applying Pattern 1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 31. STM32F2xxxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

RCC HSI enabled The system clock frequency is 24 MHz.

RAM - 8 Kbyte starting from address 0x20000000.
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
Common to all IWDG -
prevent watchdog reset (in case the
bootloaders
hardware IWDG option was previously
enabled by the user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART3 configuration
USART3 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART3 bootloader
(on PC10/PC11) USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode

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Table 31. STM32F2xxxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized, the USART3 configuration

USART3 Enabled
is: 8 bits, even parity and 1 Stop bit
USART3 bootloader
(on PB10/PB11) USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host.

The system clock is derived from the embedded internal high-speed RC. No external quartz
is required for the bootloader code.

16.1.2 Bootloader selection

Figure 19 shows the bootloader selection mechanism.

Figure 19. Bootloader V2.x selection for STM32F2xxxx devices

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

0x7F received on
USARTx

no
yes

Disable all
interrupt sources

Configure
USARTx

Execute
BL_USART_Loop
for USARTx

MS35010V1

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16.1.3 Bootloader version

This following table lists the STM32F2xxxx devices V2.x bootloader versions:

Table 32. STM32F2xxxx bootloader V2.x versions

Bootloader
version Description Known limitations
number

When a Read Memory command or Write Memory

command is issued with an unsupported memory
address and a correct address checksum (i.e.
address 0x6000 0000), the command is aborted by
the bootloader device, but the NACK (0x1F) is not
sent to the host. As a result, the next 2 bytes (which
V2.0 Initial bootloader version are the number of bytes to be read/written and its
checksum) are considered as a new command and
its checksum.
For the CAN interface, the Write Unprotect
command is not functional. Use Write Memory
command and write directly to the option bytes in
order to disable the write protection.(1)
1. If the “number of data - 1” (N-1) to be read/written is not equal to a valid command code (0x00, 0x01, 0x02,
0x11, 0x21, 0x31, 0x43, 0x44, 0x63, 0x73, 0x82 or 0x92), then the limitation is not perceived from the host
since the command is NACKed anyway (as an unsupported new command).

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16.2 Bootloader V3.x

16.2.1 Bootloader configuration

The STM32F2xxxx bootloader is activated by applying Pattern 1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 33. STM32F2xxxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

using the PLL.
The HSI clock source is used at startup
HSI enabled (interface detection phase) and when
USARTx interfaces are selected (once CAN
or DFU bootloader is selected, the clock
source is derived from the external crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the CAN or the DFU (USB FS Device)
HSE enabled interfaces are selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
Common to all external clock generates system reset.
bootloaders 8 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
29 Kbyte starting from address
System memory - 0x1FF00000 contain the bootloader
firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.

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Table 33. STM32F2xxxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized, the USART1 configuration

USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART3 configuration
USART3 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART3 bootloader
(on PB10/PB11) USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized, the USART3 configuration
USART3 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART3 bootloader
(on PC10/PC11) USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized, the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
USB OTG FS configured in forced device
USB Enabled
mode
DFU bootloader USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required
This timer is used to determine the value of
CAN2 and DFU the HSE. Once the HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx
bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but only for
the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.

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16.2.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 20. Bootloader V3.x selection for STM32F2xxxx devices

System Reset

yes Disable all

System Init (Clock, GPIOs,
interrupt sources
IWDG, SysTick)

Configure
Configure USB OTG FS
USARTx
device

Execute
0x7F received on BL_USART_Loop
USARTx for USARTx

yes
no

Frame detected HSE detected

no
on CANx pin yes

yes

no no HSE detected no Disable all

interrupt sources
Generate System
USB cable
Yes reset Reconfigure System
Detected
clock to 60MHz
Reconfigure System
clock to 60MHz and
Configure CAN
USB clock to 48 MHz

Execute
Execute DFU BL_CAN_Loop for
bootloader using USB CANx
interrupts

MS35011V1

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16.2.3 Bootloader version

The following table lists the STM32F2xxxx devices V3.x bootloader versions:

Table 34. STM32F2xxxx bootloader V3.x versions

Bootloader
version Description Known limitations
number

– When a Read Memory command or Write

Memory command is issued with an unsupported
memory address and a correct address
checksum (i.e. address 0x6000 0000), the
command is aborted by the bootloader device,
but the NACK (0x1F) is not sent to the host. As a
V3.2 Initial bootloader version. result, the next 2 bytes (which are the number of
bytes to be read/written and its checksum) are
considered as a new command and its
checksum(1).
– Option bytes, OTP and Device Feature
descriptors (in DFU interface) are set to “g”
instead of “e” (not erasable memory areas).
– For the USART interface, two consecutive
NACKs (instead of 1 NACK) are sent when a
Read Memory or Write Memory command is sent
Fix V3.2 limitations. DFU
and the RDP level is active.
V3.3 interface robustness
enhancement. – For the CAN interface, the Write Unprotect
command is not functional. Use Write Memory
command and write directly to the option bytes in
order to disable the write protection.
1. If the “number of data - 1” (N-1) to be read/written is not equal to a valid command code (0x00, 0x01, 0x02,
0x11, 0x21, 0x31, 0x43, 0x44, 0x63, 0x73, 0x82 or 0x92), then the limitation is not perceived from the host
since the command is NACKed anyway (as an unsupported new command).

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17 STM32F301xx/302x4(6/8) devices bootloader

17.1 Bootloader configuration

The STM32F301xx/302x4(6/8) bootloader is activated by applying Pattern 2 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.
Table 35. STM32F301xx/302x4(6/8) configuration in system memory boot mode
Bootloader Feature/Peripheral State Comment

The system clock frequency is 48 MHz with

HSI enabled
HSI48 48 MHz as clock source.
The external clock can be used for all
bootloader interfaces and must have one
the following values [24,18,16,12,9,8,6,4,3]
HSE enabled MHz.
RCC The PLL is used to generate the USB48
MHz clock and the 48 MHz clock for the
system clock.
The Clock Security System (CSS) interrupt
is enabled for the DFU bootloader. Any
-
Common to all failure (or removal) of the external clock
bootloaders generates system reset.
6 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
8 Kbyte starting from address
System memory - 0x1FFFD800, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.

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Table 35. STM32F301xx/302x4(6/8) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB Enabled USB used in FS mode

USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin An external pull-up resistor 1.5 KΩ must be
connected to USB_DP pin.

The bootloader has two case of operation depending on the presence of the external clock
(HSE) at bootloader startup:
 If HSE is present and has a value of 24, 18, 16, 12, 9, 8, 6, 4 or 3 MHz, the system
clock is configured to 48 MHz with HSE as clock source. The DFU interface, USART1
and USART2 are functional and can be used to communicate with the bootloader
device.
 If HSE is not present, the HSI is kept as default clock source and only USART1 and
USART2 are functional.
The external clock (HSE) must be kept if it is connected at bootloader startup because it is
used as system clock source.

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17.2 Bootloader selection

Figure 21 shows the bootloader selection mechanism.

Figure 21. Bootloader selection for STM32F301xx/302x4(6/8)

System Reset

Configure System clock to

48 MHz using HSI

HSE= 24,
18, 16, 12, 9, 8, 6, 4, no
3 MHz ?

Yes

Reconfigure System clock to

48 MHz using HSE

System Init (Clock, GPIOs,

IWDG, SysTick) System Init (Clock, GPIOs,
IWDG, SysTick)

Configure USB FS device

yes
USB cable
Detected & USB
configured Disable all interrupt
yes
sources and other
interfaces clock’s Disable other
no interfaces clock’s
Configure
USARTx
0x7F received on
Execute DFU
USARTx
no Execute bootloader using USB
BL_USART_Loop interrupts
for USARTx
MS35027V1

17.3 Bootloader version

The following table lists the STM32F301xx/302x4(6/8) devices bootloader versions:

Table 36. STM32F301xx/302x4(6/8) bootloader versions

Bootloader
version Description Known limitations
number

V4.0 Initial bootloader version None

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18 STM32F302xB(C)/303xB(C) devices bootloader

18.1 Bootloader configuration

The STM32F302xB(C)/303xB(C) bootloader is activated by applying Pattern 2 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 37. STM32F302xB(C)/303xB(C) configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

At startup, the system clock frequency is

configured to 48 MHz using the HSI. If an
HSI enabled
external clock (HSE) is not present, the
system is kept clocked from the HSI.
The external clock can be used for all
bootloader interfaces and must have one
the following values [24, 18,16, 12, 9, 8, 6,
RCC HSE enabled 4, 3] MHz.
The PLL is used to generate the USB
48 MHz clock and the 48 MHz clock for the
system clock.
The Clock Security System (CSS) interrupt
Common to all is enabled for the DFU bootloader. Any
-
bootloaders failure (or removal) of the external clock
generates system reset.
5 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address
System memory - 0x1FFFD800, contains the bootloader
firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.

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Table 37. STM32F302xB(C)/303xB(C) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB Enabled USB used in FS mode

USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin An external pull-up resistor 1.5 KΩ must be
connected to USB_DP pin.

The bootloader has two case of operation depending on the presence of the external clock
(HSE) at bootloader startup:
 If HSE is present and has a value of 24, 18, 16, 12, 9, 8, 6, 4 or 3 MHz, the system
clock is configured to 48 MHz with HSE as clock source. The DFU interface, USART1
and USART2 are functional and can be used to communicate with the bootloader
device.
 If HSE is not present, the HSI is kept as default clock source and only USART1 and
USART2 are functional.
The external clock (HSE) must be kept if it is connected at bootloader startup because it is
used as system clock source.

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18.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 22. Bootloader selection for STM32F302xB(C)/303xB(C) devices

System Reset

Configure System clock to

48MHz using HSI

HSE = 24, 18, 16, 12, 9,

8, 6, 4, 3 MHz
no

yes

Reconfigure System clock

to 48MHz using HSE

System Init (Clock, GPIOs,

System Init (Clock, GPIOs, IWDG, SysTick)
IWDG, SysTick)

Configure USB

yes

USB configured
and cable Detected yes Execute DFU
Disable all bootloader using USB
interrupt sources interrupts
no
Configure
0x7F received USARTx
no on USARTx

Execute
BL_USART_Loop
for USARTx

MS35016V3

18.3 Bootloader version

The following table lists the STM32F302xB(C)/303xB(C) devices bootloader versions.

Table 38. STM32F302xB(C)/303xB(C) bootloader versions

Bootloader version number Description Known limitations

V4.1 Initial bootloader version None

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19 STM32F302xD(E)/303xD(E) devices bootloader

19.1 Bootloader configuration

The STM32F302xD(E)/303xD(E) bootloader is activated by applying Pattern 2 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 39.STM32F302xD(E)/303xD(E) configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
The system clock frequency is 48 MHz with HSI48 48 MHz
HSI enabled
as clock source.
The external clock can be used for all bootloader
interfaces and must have one the following values
HSE enabled [24,18,16, 12, 9, 8, 6, 4, 3] MHz.
RCC
The PLL is used to generate the USB 48 MHz clock and
the 48 MHz clock for the system clock.
The Clock Security System (CSS) interrupt is enabled for
Common to all - the DFU bootloader. Any failure (or removal) of the
bootloaders external clock generates system reset.
6 Kbyte starting from address 0x20000000 are used by the
RAM -
bootloader firmware
8 Kbyte starting from address 0x1FFFD800, contain the
System memory -
bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG -
refreshed to prevent watchdog reset (in case the hardware
IWDG option was previously enabled by the user).
Once initialized the USART1 configuration is: 8-bit, even
USART1 Enabled
USART1 parity and 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bit, even
USART2 Enabled
USART2 parity and 1 Stop bit
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
USARTx Used to automatically detect the serial baud rate from the
SysTick timer Enabled
bootloaders host for USARTx bootloaders.
USB FS configured in forced device mode. USB FS
USB Enabled interrupt vector is enabled and used for USB DFU
communications.
DFU bootloader
USB_DM pin PA11 pin: USB FS DM line.
Input/Output PA12 pin: USB FS DP line. An external pull-up resistor
USB_DP pin
1.5 KΩ must be connected to USB_DP pin.

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The bootloader has two cases of operation depending on the presence of the external clock
(HSE) at bootloader startup:
 If HSE is present and has a value of 24, 18, 16, 12, 9, 8, 6, 4 or 3 MHz, the system
clock is configured to 48 MHz with HSE as clock source. The DFU interface, USART1
and USART2 are functional and can be used to communicate with the bootloader
device.
 If HSE is not present, the HSI is kept as default clock source and only USART1 and
USART2 are functional.
The external clock (HSE) must be kept if it is connected at bootloader startup because it is
used as system clock source.

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19.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 23. Bootloader selection for STM32F302xD(E)/303xD(E)

System Reset

Configure System clock to

48 MHz using HSI

HSE = 24, 18, 16,

12, 9, 8, 6, 4, 3 no
MHz?

yes
Reconfigure System clock to
48 MHz using HSE
System Init (Clock, GPIOs,
IWDG, SysTick)

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB FS device

USB cable
detected & USB yes
configured yes

Disable all interrupt

no sources and other
interfaces clock’s

Disable other
Configure USARTx interfaces clock’s
0x7F received on
no USARTx
Execute Execute DFU
BL_USART_Loop for bootloader using USB
USARTx interrupts

MSv36790V1

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19.3 Bootloader version

The following table lists the STM32F302xD(E)/303xD(E) devices bootloader versions.

Table 40. STM32F302xD(E)/303xD(E) bootloader versions

Bootloader
version Description Known limitations
number

V4.0 Initial bootloader version None

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20 STM32F303x4(6/8)/334xx/328xx devices bootloader

20.1 Bootloader configuration

The STM32F303x4(6/8)/334xx/328xx bootloader is activated by applying Pattern 2
(described in Table 2: Bootloader activation patterns). The following table shows the
hardware resources used by this bootloader.

Table 41. STM32F303x4(6/8)/334xx/328xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz with

RCC HSI enabled
HSI 8 MHz as clock source.
6 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
8 Kbyte starting from address
Common to all System memory - 0x1FFFD800, contain the bootloader
bootloaders firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111111x (where x = 0 for write
and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

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20.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 24. Bootloader selection for STM32F303x4(6/8)/334xx/328xx

System Reset

Disable all
interrupt sources

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure I2Cx

yes

I2C Address
detected yes Execute
BL_I2C_Loop for
Configure
I2Cx
USARTx
no

Execute
0x7F received on BL_USART_Loop
USARTx for USARTx
no

MS35029V2

20.3 Bootloader version

The following table lists the STM32F303x4(6/8)/334xx/328xx devices bootloader versions:

Table 42. STM32F303x4(6/8)/334xx/328xx bootloader versions

Bootloader
version Description Known limitations
number

V5.0 Initial bootloader version None

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21 STM32F318xx devices bootloader

21.1 Bootloader configuration

The STM32F318xx bootloader is activated by applying Pattern 2 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 43. STM32F318xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz with

RCC HSI enabled
HSI 8 MHz as clock source.
6 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
8 Kbyte starting from address
Common to all System memory - 0x1FFFD800, contain the bootloader
bootloaders firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111101x (where x = 0 for write
and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

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Table 43. STM32F318xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 kHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111101x (where x = 0 for write
and x = 1 for read) and digital filter disabled.
I2C3 bootloader
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PB5 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

21.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 25. Bootloader selection for STM32F318xx

System Reset

Disable all
interrupt sources

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure I2Cx

yes

I2C Address
detected yes Execute
BL_I2C_Loop for
Configure
I2Cx
USARTx
no

Execute
0x7F received on BL_USART_Loop
USARTx for USARTx
no

MS35028V2

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21.3 Bootloader version

The following table lists the STM32F318xx devices bootloader versions:

Table 44. STM32F318xx bootloader versions

Bootloader
version Description Known limitations
number

V5.0 Initial bootloader version None

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22 STM32F358xx devices bootloader

22.1 Bootloader configuration

The STM32F358xx bootloader is activated by applying Pattern 2 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 45. STM32F358xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 8 MHz using

RCC HSI enabled
the HSI.
5 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address
System memory - 0x1FFFD800, contains the bootloader
Common to all firmware.
bootloaders
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG - prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user). Window feature is
disabled.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode.
USART1_TX pin Output PA9 pin: USART1 in transmission mode.
Once initialized, the USART2 configuration
USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode.
USART2_TX pin Output PD5 pin: USART2 in transmission mode.
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0110111x (where x = 0 for write
and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

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The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

22.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 26. Bootloader selection for STM32F358xx devices

System Reset

Disable all
interrupt sources

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure I2Cx

yes

I2C Address
detected yes Execute
BL_I2C_Loop for
Configure
I2Cx
USARTx
no

Execute
0x7F received BL_USART_Loop
on USARTx for USARTx
no

MS35019V2

22.3 Bootloader version

The following table lists the STM32F358xx devices bootloader versions.
Table 46. STM32F358xx bootloader versions
Bootloader version
Description Known limitations
number

For USART1 and USART2 interfaces,

V5.0 Initial bootloader version the maximum baudrate supported by
the bootloader is 57600 baud.

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23 STM32F373xx devices bootloader

23.1 Bootloader configuration

The STM32F373xx bootloader is activated by applying Pattern 2 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 47. STM32F373xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

At startup, the system clock frequency is

configured to 48 MHz using the HSI. If an
HSI enabled
external clock (HSE) is not present, the
system is kept clocked from the HSI.
The external clock can be used for all
bootloader interfaces and must have one
the following values [24,18,16,12,9,8,6,4,3]
RCC HSE enabled MHz.
The PLL is used to generate the USB
48 MHz clock and the 48 MHz clock for the
system clock.
The Clock Security System (CSS) interrupt
Common to all is enabled for the DFU bootloader. Any
-
bootloaders failure (or removal) of the external clock
generates system reset.
5 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address
System memory - 0x1FFFD800, contains the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.

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Table 47. STM32F373xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB Enabled USB used in FS mode

USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin An external pull-up resistor 1.5 KΩ must be
connected to USB_DP pin.

The bootloader has two case of operation depending on the presence of the external clock
(HSE) at bootloader startup:
 If HSE is present and has a value of 24, 18, 16, 12, 9, 8, 6, 4 or 3 MHz, the system
clock is configured to 48 MHz with HSE as clock source. The DFU interface, USART1
and USART2 are functional and can be used to communicate with the bootloader
device.
 If HSE is not present, the HSI is kept as default clock source and only USART1 and
USART2 are functional.
Note: The external clock (HSE) must be kept if it is connected at bootloader startup because it is
used as system clock source.

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23.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 27. Bootloader selection for STM32F373xx devices

System Reset

Configure System clock to

48MHz using HSI

HSE = 24,
18, 16, 12, 9, 8, 6, 4,
3 MHz
no

yes

Reconfigure System clock

to 48MHz using HSE

System Init (Clock, GPIOs,

System Init (Clock, GPIOs, IWDG, SysTick)
IWDG, SysTick)

Configure USB

yes

USB configured
and cable Detected Execute DFU
yes Disable all bootloader using USB
interrupt sources interrupts
no
Configure
0x7F received USARTx
no on USARTx

Execute
BL_USART_Loop
for USARTx

MS35016V4

23.3 Bootloader version

The following table lists the STM32F373xx devices bootloader versions.

Table 48. STM32F373xx bootloader versions

Bootloader version number Description Known limitations

V4.1 Initial bootloader version None

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24 STM32F378xx devices bootloader

24.1 Bootloader configuration

The STM32F378xx bootloader is activated by applying Pattern 2 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 49. STM32F378xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 8 MHz using

RCC HSI enabled
the HSI.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address
System memory - 0x1FFFD800, contains the bootloader
Common to all firmware
bootloaders
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG - prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user). Window feature is
disabled.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode.
USART1_TX pin Output PA9 pin: USART1 in transmission mode.
Once initialized, the USART2 configuration
USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode.
USART2_TX pin Output PD5 pin: USART2 in transmission mode.
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0110111x (where x = 0 for write
and x = 1 for read).
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

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The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

24.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 28. Bootloader selection for STM32F378xx devices

System Reset

Disable all
interrupt sources

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure I2Cx

yes

I2C Address
detected yes Execute
BL_I2C_Loop for
Configure
I2Cx
USARTx
no

Execute
0x7F received BL_USART_Loop
on USARTx for USARTx
no

MS35018V2

24.3 Bootloader version

The following table lists the STM32F378xx devices bootloader versions.
Table 50. STM32F378xx bootloader versions
Bootloader version
Description Known limitations
number

For USART1 and USART2 interfaces, the

V5.0 Initial bootloader version maximum baudrate supported by the
bootloader is 57600 baud.

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25 STM32F398xx devices bootloader

25.1 Bootloader configuration

The STM32F398xx bootloader is activated by applying Pattern 2 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 51.STM32F398xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
The system clock frequency is 60 MHz with HSI 8
RCC HSI enabled
MHz as clock source.
6 Kbyte starting from address 0x20000000 are
RAM -
used by the bootloader firmware

Common to all 7 Kbyte starting from address 0x1FFFD800,

System memory -
bootloaders contain the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Once initialized the USART1 configuration is: 8-
USART1 Enabled
bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-
USART2 Enabled
bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
USARTx Used to automatically detect the serial baud rate
SysTick timer Enabled
bootloaders from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave
I2C1 Enabled mode, analog filter ON. Slave 7-bit address:
I2C1 bootloader 0b1000000x (where x = 0 for write and x = 1 for
read).
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave
I2C3 Enabled mode, analog filter ON. Slave 7-bit address:
I2C3 bootloader 0b1000000x (where x = 0 for write and x = 1 for
read).
I2C3_SCL pin Input/Output PA8 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PB5 pin: data line is used in open-drain mode.

The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.

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25.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 29.Bootloader selection for STM32F398xx

System Reset

Disable all
interrupt sources

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure I2Cx

0x7F received yes

on USARTx

Disable all interrupt

sources and other
yes
no interfaces clock’s
Disable other
interfaces clock’s Configure USARTx
I2Cx Address
no Detected
Execute
Execute BL_I2C_Loop
BL_USART_Loop
for I2Cx
for USARTx

MSv36791V1

25.3 Bootloader version

The following table lists the STM32F398xx devices bootloader versions.

Table 52. STM32F398xx bootloader versions

Bootloader
version Description Known limitations
number

V5.0 Initial bootloader version None

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26 STM32F40xxx/41xxx devices bootloader

26.1 Bootloader V3.x

26.1.1 Bootloader configuration

The STM32F40xxx/41xxx bootloader is activated by applying Pattern 1 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 53. STM32F40xxx/41xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

using the PLL.
The HSI clock source is used at startup
HSI enabled (interface detection phase) and when
USARTx interfaces are selected (once CAN
or DFU bootloader is selected, the clock
source is derived from the external crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the CAN or the DFU (USB FS Device)
HSE enabled interfaces are selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
Common to all external clock generates system reset.
bootloaders
8 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
29 Kbyte starting from address 0x1FFF
System memory -
0000 contain the bootloader firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.

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Table 53. STM32F40xxx/41xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized, the USART1 configuration

USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART3 configuration
USART3 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART3 bootloader
(on PB10/PB11) USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized, the USART3 configuration
USART3 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART3 bootloader
(on PC10/PC11) USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized, the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
USB OTG FS configured in forced device
USB Enabled
mode
DFU bootloader USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required
This timer is used to determine the value of
CAN2 and DFU the HSE. Once the HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx
bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but only for
the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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26.1.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 30. Bootloader V3.x selection for STM32F40xxx/41xxx devices

System Reset

yes Disable all

System Init (Clock, GPIOs,
interrupt sources
IWDG, SysTick)

Configure
Configure USB OTG FS
USARTx
device

Execute
0x7F received on BL_USART_Loop
USARTx for USARTx

yes
no

Frame detected HSE detected

no
on CANx pin yes

yes

no no HSE detected no Disable all

interrupt sources
Generate System
USB cable
yes reset Reconfigure System
Detected
clock to 60MHz
Reconfigure System
clock to 60MHz and
Configure CAN
USB clock to 48 MHz

Execute
Execute DFU BL_CAN_Loop for
bootloader using USB CANx
interrupts

MS35012V3

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26.1.3 Bootloader version

The following table lists the STM32F40xxx/41xxx devices V3.x bootloader versions:

Table 54. STM32F40xxx/41xxx bootloader V3.x versions

Bootloader
version Description Known limitations
number

– When a Read Memory command or Write

Memory command is issued with an unsupported
memory address and a correct address
checksum (i.e. address 0x6000 0000), the
command is aborted by the bootloader device,
but the NACK (0x1F) is not sent to the host. As a
result, the next 2 bytes (which are the number of
bytes to be read/written and its checksum) are
V3.0 Initial bootloader version considered as a new command and its
checksum(1).
– Option bytes, OTP and Device Feature
descriptors (in DFU interface) are set to “g”
instead of “e” (not erasable memory areas).
After executing Go command (jump to user code)
the bootloader resets AHB1ENR value to 0x0000
0000 and thus CCM RAM, when present, is not
active (must be re-enabled by user code at startup)
– For the USART interface, two consecutive
NACKs (instead of 1 NACK) are sent when a
Read Memory or Write Memory command is sent
and the RDP level is active.
– For the CAN interface, the Write Unprotect
Fix V3.0 limitations. DFU
command is not functional. Use Write Memory
V3.1 interface robustness
command and write directly to the option bytes in
enhancement.
order to disable the write protection.
After executing Go command (jump to user code)
the bootloader resets AHB1ENR value to 0x0000
0000 and thus CCM RAM, when present, is not
active (must be re-enabled by user code at startup)
1. If the “number of data - 1” (N-1) to be read/written is not equal to a valid command code (0x00, 0x01, 0x02,
0x11, 0x21, 0x31, 0x43, 0x44, 0x63, 0x73, 0x82 or 0x92), then the limitation is not perceived from the host
since the command is NACKed anyway (as an unsupported new command).

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26.2 Bootloader V9.x

26.2.1 Bootloader configuration

The STM32F40xxx/41xxx bootloader is activated by applying Pattern 1 (described in
Table 2: Bootloader activation patterns). Table 55 shows the hardware resources used by
this bootloader.
Note: The bootloader version V9.x is embedded only in STM32F405xx/415xx devices in
WLCSP90 package.

Table 55. STM32F40xxx/41xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz

using the PLL.
The HSI clock source is used at startup
HSI enabled (interface detection phase) and when
USART or SPI or I2C interfaces are
selected (once CAN or DFU bootloader is
selected, the clock source is derived from
the external crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the CAN or the DFU (USB FS Device)
HSE enabled interfaces are selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
Common to all external clock generates system reset.
bootloaders 12 Kbyte starting from address
RAM - 0x20000000 are used by the bootloader
firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.

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Table 55. STM32F40xxx/41xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8-bit, even parity and 1 Stop bit
USART3 bootloader
(on PB10/PB11) USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8-bit, even parity and 1 Stop bit
USART3 bootloader
(on PC10/PC11) USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111010x (where x = 0 for write
and x = 1 for read).
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111010x (where x = 0 for write
and x = 1 for read).
I2C2 bootloader
PF1 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PF0 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.

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Table 55. STM32F40xxx/41xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 kHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111010x (where x = 0 for write
and x = 1 for read).
I2C3 bootloader
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC9 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The SPI1 configuration is: 
slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in push-
SPI1_NSS pin Input
pull pull-down mode.
The SPI2 configuration is: 
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PI3 pin: Slave data Input line, used in push-
SPI2_MOSI pin Input
pull pull-down mode
SPI2 bootloader
PI2 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PI1 pin: Slave clock line, used in push-pull
SPI2_SCK pin Input
pull-down mode
PI0 pin: slave chip select pin used in push-
SPI2_NSS pin Input
pull pull-down mode.
USB OTG FS configured in forced device
USB Enabled
mode

DFU bootloader USB_DM pin PA11: USB DM line.

Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required
This timer is used to determine the value of
CAN2 and DFU the HSE. Once the HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

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The system clock is derived from the embedded internal high-speed RC for USARTx, I2Cx
and SPIx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device)
but only for the selection phase. An external clock multiple of 1 MHz (between 4 and
26 MHz) is required for CAN and DFU bootloader execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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26.2.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 31. Bootloader V9.x selection for STM32F40xxx/41xxx

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB OTG FS

device

Configure I2Cx Disable all

interrupt sources

Configure SPIx yes Configure

USARTx

Execute
0x7F received on
USARTx BL_USART_Loo
p for USARTx

no yes

Frame detected
on CANx no HSE detected

yes
no HSE detected no

Generate System
yes
Yes reset
USB cable
Detected
Reconfigure System
clock to 60MHz and Disable all
Disable all interrupt USB clock to 48 MHz interrupt sources
no sources
no
yes
Reconfigure System
Execute DFU clock to 60MHz
Execute
I2Cx Address BL_I2C_Loop for bootloader using
Detected I2Cx USB interrupts
Configure CAN

yes
no Execute
Disable all BL_CAN_Loop for
interrupt sources CANx
SPIx detects
Synchro
mechanism Execute
BL_SPI_Loop for
SPIx
MS35012V2

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26.2.3 Bootloader version

The following table lists the STM32F40xxx/41xxx devices V9.x bootloader versions.

Table 56. STM32F40xxx/41xxx bootloader V9.x versions

Bootloader
version Description Known limitations
number

– For the USART interface, two consecutive

This bootloader is an updated NACKs (instead of 1 NACK) are sent when a
version of bootloader v3.1. Read Memory or Write Memory command is sent
and the RDP level is active.
This new version of bootloader
supports I2C1, I2C2, I2C3, SPI1 – For the CAN interface, the Write Unprotect
and SPI2 interfaces. command is not functional. Use Write Memory
V9.0
command and write directly to the option bytes in
The RAM used by this bootloader
order to disable the write protection.
is increased from 8Kb to 12Kb.
After executing Go command (jump to user code)
The ID of this bootloader is 0x90.
the bootloader resets AHB1ENR value to 0x0000
The connection time is increased. 0000 and thus CCM RAM, when present, is not
active (must be re-enabled by user code at startup)

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27 STM32F401xB(C) devices bootloader

27.1 Bootloader configuration

The STM32F401xB(C) bootloader is activated by applying Pattern 1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 57. STM32F401xB(C) configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz

using the PLL.
The HSI clock source is used at startup
HSI enabled (interface detection phase) and when
USART or SPI or I2C interface is selected
(once DFU bootloader is selected, the clock
source is derived from the external crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the DFU (USB FS Device) interface is
HSE enabled selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
Common to all external clock generates system reset.
bootloaders 12 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.

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Table 57. STM32F401xB(C) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
and x = 1 for read)
I2C2 bootloader
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB3 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
and x = 1 for read)
I2C3 bootloader
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PB4 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.

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Table 57. STM32F401xB(C) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in push-
SPI1_NSS pin Input
pull pull-down mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
push-pull pull-down mode
SPI2 bootloader
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PB13 pin: Slave clock line, used in push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
SPI2_NSS pin Input
push-pull pull-down mode.
The SPI3 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI3 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PC12 pin: Slave data Input line, used in
SPI3_MOSI pin Input
push-pull pull-down mode
SPI3 bootloader
PC11 pin: Slave data output line, used in
SPI3_MISO pin Output
push-pull pull-down mode
PC10 pin: Slave clock line, used in push-
SPI3_SCK pin Input
pull pull-down mode
PA15 pin: slave chip select pin used in
SPI3_NSS pin Input
push-pull pull-down mode.

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Table 57. STM32F401xB(C) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB OTG FS configured in forced device

USB Enabled
mode
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
DFU bootloader USB_DP pin
No external pull-up resistor is required
This timer is used to determine the value of
the HSE. Once the HSE frequency is
TIM11 Enabled
determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx, I2Cx
and SPIx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device)
but only for the selection phase. An external clock multiple of 1 MHz (between 4 and
26 MHz) is required for CAN and DFU bootloader execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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27.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 32. Bootloader selection for STM32F401xB(C)

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB OTG FS

device
Disable all
interrupt sources
Configure I2Cx
Configure
USARTx
yes
Configure SPIx
Execute
BL_USART_Loop
for USARTx
0x7F received on
USARTx

no

USB cable HSE detected no

yes
Detected
yes Generate System
yes reset
no Disable all
interrupt sources
Reconfigure System
clock to 60MHz and
I2Cx Address USB clock to 48 MHz
Execute
Detected BL_I2C_Loop for
no I2Cx
Execute DFU
yes bootloader using USB
no
interrupts
Disable all
interrupt sources
SPIx detects
Synchro
mechanism Execute
BL_SPI_Loop for
SPIx
MS35030V1

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27.3 Bootloader version

The following table lists the STM32F401xB(C) devices bootloader version.

Table 58. STM32F401xB(C) bootloader versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code)

the bootloader resets AHB1ENR value to 0x0000
V13.0 Initial bootloader version
0000 and thus CCM RAM, when present, is not
active (must be re-enabled by user code at startup)

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28 STM32F401xD(E) devices bootloader

28.1 Bootloader configuration

The STM32F401xD(E) bootloader is activated by applying Pattern 1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 59. STM32F401xD(E) configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
The system clock frequency is 60 MHz
using the PLL.
The HSI clock source is used at startup
HSI enabled (interface detection phase) and when
USART or SPI or I2C interface is selected
(once DFU bootloader is selected, the clock
source is derived from the external crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the DFU (USB FS Device) interface is
HSE enabled selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the DFU bootloader. Any
-
failure (or removal) of the external clock
Common to all generates system reset.
bootloaders 12 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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Table 59. STM32F401xD(E) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
I2C1 bootloader and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
I2C2 bootloader and x = 1 for read)
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB3 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
I2C3 bootloader and x = 1 for read)
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PB4 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in push-
SPI1_NSS pin Input
pull pull-down mode.

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Table 59. STM32F401xD(E) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
push-pull pull-down mode
SPI2 bootloader
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PB13 pin: Slave clock line, used in push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
SPI2_NSS pin Input
push-pull pull-down mode.
The SPI3 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI3 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PC12 pin: Slave data Input line, used in
SPI3_MOSI pin Input
push-pull pull-down mode
SPI3 bootloader
PC11 pin: Slave data output line, used in
SPI3_MISO pin Output
push-pull pull-down mode
PC10 pin: Slave clock line, used in push-
SPI3_SCK pin Input
pull pull-down mode
PA15 pin: slave chip select pin used in
SPI3_NSS pin Input
push-pull pull-down mode.
USB OTG FS configured in forced device
USB Enabled
mode
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
DFU bootloader USB_DP pin
No external pull-up resistor is required
This timer is used to determine the value of
the HSE. Once the HSE frequency is
TIM11 Enabled
determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx, I2Cx
and SPIx bootloaders. This internal clock is also used for DFU (USB FS Device) but only for
the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for DFU bootloader execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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28.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 33. Bootloader selection for STM32F401xD(E)

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB OTG FS

device
Disable all
interrupt sources
Configure I2Cx
Configure
USARTx
yes
Configure SPIx
Execute
BL_USART_Loop
for USARTx
0x7F received
on USARTx

no

USB cable HSE detected no

yes
Detected
yes Generate System
yes reset
no Disable all
interrupt sources
Reconfigure System
clock to 60MHz and
I2Cx Address USB clock to 48 MHz
Execute
Detected BL_I2C_Loop for
no I2Cx
Execute DFU
yes bootloader using USB
no
interrupts
Disable all
interrupt sources
SPIx detects
Synchro
mechanism Execute
BL_SPI_Loop for
SPIx
MS35031V1

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28.3 Bootloader version

The following table lists the STM32F401xD(E) devices bootloader version.

Table 60. STM32F401xD(E) bootloader versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code)

the bootloader resets AHB1ENR value to 0x0000
V13.1 Initial bootloader version
0000 and thus CCM RAM, when present, is not
active (must be re-enabled by user code at startup)

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29 STM32F410xx devices bootloader

29.1 Bootloader configuration

The STM32F410xx bootloader is activated by applying Pattern 1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 61. STM32F410xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source

RCC HSI enabled for system clock configured to 60 MHz and
for USART and I2C bootloader operation.
5 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
Common to all value. It is periodically refreshed to
bootloaders IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
The voltage range is [1.8V, 3.6V]
In this range:
- Flash wait states: 3.
Power - - System clock frequency 60 MHz.
- ART Accelerator enabled.
- Flash write operation by byte (refer to
bootloader memory management section
for more information).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial
USARTx
SysTick timer Enabled baud rate from the host for USARTx
bootloaders
bootloaders.

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Table 61. STM32F410xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C1 configuration is:

I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b1000111x (where x = 0 for
write and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b1000111x (where x = 0 for
write and x = 1 for read)
I2C2 bootloader
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB11 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C4 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C4 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b1000111x (where x = 0 for
write and x = 1 for read)
PB15 pin: clock line is used in open-drain
I2C4 bootloader mode for STM32F410Cx/Rx devices.
I2C4_SCL pin Input/Output
PB10 pin: clock line is used in open-drain
mode for STM32F410Tx devices.
PB14 pin: data line is used in open-drain
mode for STM32F410Cx/Rx devices.
I2C4_SDA pin Input/Output
PB3 pin: data line is used in open-drain
mode for STM32F410Tx devices.

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Table 61. STM32F410xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

SPI1 Enabled Slave mode, Full Duplex, 8-bit MSB,
Speed up to 8 MHz, Polarity: CPOL Low,
CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in
push-pull pull-down mode for
STM32F410Cx/Rx devices.
SPI1_MOSI pin Input
PB5 pin: Slave data Input line, used in
push-pull pull-down mode for
STM32F410Tx devices.
PA6 pin: Slave data output line, used in
push-pull pull-down mode for
SPI1 bootloader
STM32F410Cx/Rx devices.
SPI1_MISO pin Output
PB4 pin: Slave data output line, used in
push-pull pull-down mode for
STM32F410Tx devices.
PA5 pin: Slave clock line, used in push-
SPI1_SCK pin Input
pull pull-down mode.
PA4 pin: slave chip select pin used in
push-pull pull-up mode for
STM32F410Cx/Rx devices.
SPI1_NSS pin Input
PA15 pin: slave chip select pin used in
push-pull pull-up mode for STM32F410Tx
devices.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI2 Enabled
Speed up to 8 MHz, Polarity: CPOL Low,
CPHA Low, NSS hardware.
PC3 pin: Slave data Input line, used in
SPI2_MOSI pin Input
push-pull pull-down mode
SPI2 bootloader
PC2 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PB13 pin: Slave clock line, used in push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
SPI2_NSS pin Input
push-pull pull-up mode.

The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.

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29.2 Bootloader selection

Figure 34 shows the bootloader selection mechanism.

Figure 34.Bootloader V11.x selection for STM32F410xx

System Reset

Disable all interrupt

sources

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure I2Cx

Configure SPIx

0x7F received
yes
on USARTx

no

I2Cx Address
yes
Detected

no Disable all other

Disable all other Disable all other interfaces clocks
interfaces clocks interfaces clocks

Configure USARTx
SPIx detects Synchro yes
mechanism

Execute Execute Execute

BL_SPI_Loop for BL_I2C_Loop for BL_USART_Loop
SPIx I2Cx for USARTx
no

MSv38431V2

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29.3 Bootloader version

The following table lists the STM32F410xx devices bootloader V11.x versions.

Table 62. STM32F410xx bootloader V11.x versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code)

the bootloader resets AHB1ENR value to 0x0000
V11.0 Initial bootloader version 0000 and thus CCM RAM, when present, is not
active (must be re-enabled by user code at
startup)
After executing Go command (jump to user code)
the bootloader resets AHB1ENR value to 0x0000
Support I2C4 and SPI1 for
V11.1 0000 and thus CCM RAM, when present, is not
STM32F410Tx devices.
active (must be re-enabled by user code at
startup)

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30 STM32F411xx devices bootloader

30.1 Bootloader configuration

The STM32F411xx bootloader is activated by applying Pattern 1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 63. STM32F411xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz

using the PLL.
The HSI clock source is used at startup
HSI enabled (interface detection phase) and when
USART or SPI or I2C interface is selected
(once DFU bootloader is selected, the clock
source is derived from the external crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the DFU (USB FS Device) interface is
HSE enabled selected.
The external clock must provide a fre-
quency multiple of 1 MHz and ranging from
4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the DFU bootloader. Any fail-
-
ure (or removal) of the external clock gener-
Common to all ates system reset.
bootoaders
12 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader firm-
ware
The independent watchdog (IWDG) pres-
caler is configured to its maximum value. It
IWDG - is periodically refreshed to prevent watch-
dog reset (in case the hardware IWDG
option was previously enabled by the user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be config-
ured in run time using bootloader com-
mands.

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Table 63. STM32F411xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
and x = 1 for read)
I2C2 bootloader
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB3 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
and x = 1 for read)
I2C3 bootloader
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PB4 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.

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Table 63. STM32F411xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in push-
SPI1_NSS pin Input
pull pull-down mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
push-pull pull-down mode
SPI2 bootloader
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PB13 pin: Slave clock line, used in push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
SPI2_NSS pin Input
push-pull pull-down mode.
The SPI3 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI3 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PC12 pin: Slave data Input line, used in
SPI3_MOSI pin Input
push-pull pull-down mode
SPI3 bootloader
PC11 pin: Slave data output line, used in
SPI3_MISO pin Output
push-pull pull-down mode
PC10 pin: Slave clock line, used in push-
SPI3_SCK pin Input
pull pull-down mode
PA15 pin: slave chip select pin used in
SPI3_NSS pin Input
push-pull pull-down mode.

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Table 63. STM32F411xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB OTG FS configured in forced device

USB Enabled
mode
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
DFU bootloader USB_DP pin
No external pull-up resistor is required
This timer is used to determine the value of
the HSE. Once the HSE frequency is
TIM11 Enabled
determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx, I2Cx
and SPIx bootloaders. This internal clock is also used for DFU (USB FS Device) but only for
the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for DFU bootloader execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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30.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 35. Bootloader selection for STM32F411xx

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB OTG FS

device
Disable all
interrupt sources
Configure I2Cx
Configure
USARTx
yes
Configure SPIx
Execute
BL_USART_Loop
for USARTx
0x7F received on
USARTx

no

USB cable HSE detected no

yes
Detected
yes Generate System
Yes reset
no Disable all
interrupt sources
Reconfigure System
clock to 60MHz and
I2Cx Address USB clock to 48 MHz
Execute
Detected BL_I2C_Loop for
no I2Cx
Execute DFU
yes bootloader using USB
no
interrupts
Disable all
interrupt sources
SPIx detects
Synchro
mechanism Execute
BL_SPI_Loop for
SPIx MS35032V1

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30.3 Bootloader version

The following table lists the STM32F411xx devices bootloader version.

Table 64. STM32F411xx bootloader versions

Bootloader
version num- Description Known limitations
ber

After executing Go command (jump to user code) the

bootloader resets AHB1ENR value to 0x0000 0000
V13.0 Initial bootloader version
and thus CCM RAM, when present, is not active
(must be re-enabled by user code at startup)

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31 STM32F412xx devices bootloader

31.1 Bootloader configuration

The STM32F412xx bootloader is activated by applying Pattern 1 (described in Table 2:
Bootloader activation patterns). The table shows the hardware resources used by this
bootloader.

Table 65.STM32F412xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source

HSI enabled for system clock configured to 60 MHz and
for USART and I2C bootloader operation.
The HSE is used only when the CAN or the
DFU (USB FS Device) interfaces are
selected. In this case the system clock
HSE enabled configured to 60 MHz with HSE as clock
RCC
source.
The HSE frequency must be multiple of 1
MHz and ranging from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
external clock generates system reset.
16 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
Common to all
bootloaders 29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
The voltage range is [1.8V, 3.6V] 
In this range:
- Flash wait states: 3.
- System clock frequency 60 MHz.
Power -
- ART Accelerator enabled.
- Flash write operation by byte (refer to
bootloader memory management section
for more information).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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Table 65.STM32F412xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART2 configuration

USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8-bit, even parity and 1 Stop bit
USART3 bootloader
USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000110x (where x =
I2C1 bootloader 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000110x (where x =
I2C2 bootloader 0 for write and x = 1 for read)
PF1 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PF0 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.

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Table 65.STM32F412xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 kHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000110x (where x =
I2C3 bootloader 0 for write and x = 1 for read)
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PB4 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The I2C4 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C4 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000110x (where x =
I2C4 bootloader 0 for write and x = 1 for read)
PB15 pin: clock line is used in open-drain
I2C4_SCL pin Input/Output
mode.
PB14 pin: data line is used in open-drain
I2C4_SDA pin Input/Output
mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in push-
SPI1_MOSI pin Input
pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in push-
SPI1_NSS pin Input
pull pull-up mode.
The SPI3 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI3 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PC12 pin: Slave data Input line, used in
SPI3_MOSI pin Input
push-pull pull-down mode
SPI3 bootloader
PC11 pin: Slave data output line, used in
SPI3_MISO pin Output
push-pull pull-down mode
PC10 pin: Slave clock line, used in push-
SPI3_SCK pin Input
pull pull-down mode
PA15 pin: slave chip select pin used in
SPI3_NSS pin Input
push-pull pull-up mode.

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Table 65.STM32F412xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI4 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI4 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PE14 pin: Slave data Input line, used in
SPI4_MOSI pin Input
push-pull pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used in
SPI4_MISO pin Output
push-pull pull-down mode
PE12 pin: Slave clock line, used in push-
SP4_SCK pin Input
pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
push-pull pull-up mode.
USB OTG FS configured in forced device
USB Enabled
mode

DFU bootloader USB_DM pin PA11 pin: USB DM line.

Input/Output PA12 pin: USB DP line
USB_DP pin
No external Pull-Up resistor is required.
This timer is used to determine the value of
CAN2 and DFU the HSE. Once HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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31.2 Bootloader selection

Figure 36 shows the bootloader selection mechanism.

Figure 36.Bootloader V9.x selection for STM32F412xx

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick) yes

Configure USB OTG FS

device yes
Disable all interrupt
yes sources and other
interfaces clocks
Configure I2Cx
Disable all interrupt Disable all interrupt
sources and other sources and other Configure
interfaces clocks interfaces clocks USARTx
Configure SPIx

Execute Execute Execute

BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx
0x7F received
on USARTx

no
yes

I2Cx Address
Detected

no
HSE detected no no HSE detected

Synchro mechanism Generate System

detected on SPIx yes reset yes

Disable all interrupt

Disable other
sources and other
no interfaces clocks
interfaces clocks
no

Frame detected Reconfigure System Reconfigure System

on CANx clock to 60MHz and clock to 60MHz
USB clock to 48 MHz

no Configure CANx
Execute DFU
bootloader using USB
USB cable interrupts Execute
yes
Detected BL_CAN_Loop for
CANx

MSv38454V2

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31.3 Bootloader version

The following table lists the STM32F412xx devices bootloader V9.x versions.

Table 66. STM32F412xx bootloader V9.x versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code)

the bootloader resets AHB1ENR value to 0x0000
V9.0 Initial bootloader version 0000 and thus CCM RAM, when present, is not
active (must be re-enabled by user code at
startup)
After executing Go command (jump to user code)
the bootloader resets AHB1ENR value to 0x0000
V9.1 Fix USART3 interface pinout 0000 and thus CCM RAM, when present, is not
active (must be re-enabled by user code at
startup)

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32 STM32F413xx/423xx devices bootloader

32.1 Bootloader configuration

The STM32F413xx/423xx bootloader is activated by applying Pattern 1 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 67. STM32F413xx/423xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock

source for system clock configured to
HSI enabled
60 MHz and for USART and I2C
bootloader operation.
The HSE is used only when the CAN
or the DFU (USB FS Device)
interfaces are selected. In this case
the system clock configured to 60 MHz
HSE enabled
RCC with HSE as clock source.
The HSE frequency must be multiple
of 1 MHz and ranging from 4 MHz to
26 MHz.
The Clock Security System (CSS)
interrupt is enabled for the CAN and
- DFU bootloaders. Any failure (or
removal) of the external clock
generates system reset.
16 Kbyte starting from address
Common to all bootloaders RAM - 0x20000000 are used by the
bootloader firmware
60 Kbyte starting from address
System memory - 0x1FF00000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
The voltage range is [1.8V, 3.6V]
In this range:
– Flash wait states 4.
Power - – System clock frequency 60 MHz.
– ART Accelerator enabled.
– Flash write operation by byte (refer
to Bootloader memory management
for more information).

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Table 67. STM32F413xx/423xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1

USART1 Enabled configuration is: 8-bit, even parity and
1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
PA9 pin: USART1 in transmission
USART1_TX pin Output
mode
Once initialized the USART2
USART2 Enabled configuration is: 8-bit, even parity and
1 Stop bit
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
PD5 pin: USART2 in transmission
USART2_TX pin Output
mode
Once initialized the USART3
USART3 Enabled configuration is: 8-bit, even parity and
1 Stop bit
USART3 bootloader
USART3_RX pin Input PB11 pin: USART3 in reception mode
PB10 pin: USART3 in transmission
USART3_TX pin Output
mode
Used to automatically detect the serial
USARTx bootloaders SysTick timer Enabled baud rate from the host for USARTx
bootloaders.
Once initialized the CAN2
configuration is: Baudrate 125 kbps,
11-bit identifier.
CAN2 Enabled Note: CAN1 is clocked during CAN2
CAN2 bootloader bootloader execution because CAN1
manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit
address, slave mode, analog filter ON.
I2C1 Enabled
Slave 7-bit address: 0b1001011x
(where x = 0 for write and x = 1 for
I2C1 bootloader read)
PB6 pin: clock line is used in open-
I2C1_SCL pin Input/Output
drain mode.
PB7 pin: data line is used in open-
I2C1_SDA pin Input/Output
drain mode.

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Table 67. STM32F413xx/423xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C2 configuration is:

I2C speed: up to 400 kHz, 7-bit
address, slave mode, analog filter ON.
I2C2 Enabled
Slave 7-bit address: 0b1001011x
(where x = 0 for write and x = 1 for
I2C2 bootloader read)
PF1 pin: clock line is used in open-
I2C2_SCL pin Input/Output
drain mode.
PF0 pin: data line is used in open-
I2C2_SDA pin Input/Output
drain mode.
The I2C3 configuration is:
I2C speed: up to 400 kHz, 7-bit
address, slave mode, analog filter ON.
I2C3 Enabled
Slave 7-bit address: 0b1001011x
(where x = 0 for write and x = 1 for
I2C3 bootloader read)
PA8 pin: clock line is used in open-
I2C3_SCL pin Input/Output
drain mode.
PB4 pin: data line is used in open-
I2C3_SDA pin Input/Output
drain mode.
The I2C4 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
slave mode, analog filter ON.
I2C4 Enabled
Slave 7-bit address: 0b1001011x
(where x = 0 for write and x = 1 for
I2C4 bootloader read)
PB15 pin: clock line is used in open-
I2C4_SCL pin Input/Output
drain mode.
PB14 pin: data line is used in open-
I2C4_SDA pin Input/Output
drain mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB, speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low,
NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1 bootloader SPI1_MOSI pin Input
push-pull pull-down mode
PA6 pin: Slave data output line, used
SPI1_MISO pin Output
in push-pull pull-down mode
PA5 pin: Slave clock line, used in
SPI1_SCK pin Input
push-pull pull-down mode
PA4 pin: slave chip select pin used in
SPI1_NSS pin Input
push-pull pull-up mode.

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Table 67. STM32F413xx/423xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI3 configuration is:

– Slave mode
– Full Duplex
SPI3 Enabled
– 8-bit MSB, speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low,
NSS hardware.
PC12 pin: Slave data Input line, used
SPI3 bootloader SPI3_MOSI pin Input
in push-pull pull-down mode
PC11 pin: Slave data output line, used
SPI3_MISO pin Output
in push-pull pull-down mode
PC10 pin: Slave clock line, used in
SPI3_SCK pin Input
push-pull pull-down mode
PA15 pin: slave chip select pin used in
SPI3_NSS pin Input
push-pull pull-up mode.
The SPI4 configuration is:
– Slave mode
– Full Duplex
SPI4 Enabled
– 8-bit MSB, speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low,
NSS hardware.
PE14 pin: Slave data Input line, used
SPI4 bootloader SPI4_MOSI pin Input
in push-pull pull-down mode
PE13 pin: Slave data output line, used
SPI4_MISO pin Output
in push-pull pull-down mode
PE12 pin: Slave clock line, used in
SP4_SCK pin Input
push-pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
push-pull pull-up mode.
USB OTG FS configured in forced
USB Enabled
device mode
USB_DM pin PA11 pin: USB DM line.
DFU bootloader
Input/Output PA12 pin: USB DP line
USB_DP pin No external Pull-Up resistor is
required.
This timer is used to determine the
value of the HSE. Once HSE
CAN2 and DFU
TIM11 Enabled frequency is determined, the system
bootloaders
clock is configured to 60 MHz using
PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.

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Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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32.2 Bootloader selection

Figure 37 shows the bootloader selection mechanism.

Figure 37.Bootloader V9.x selection for STM32F413xx/423xx

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick) yes

Configure USB OTG FS

device yes
Disable all interrupt
yes sources and other
interfaces clocks
Configure I2Cx
Disable all interrupt Disable all interrupt
sources and other sources and other Configure
interfaces clocks interfaces clocks USARTx
Configure SPIx

Execute Execute Execute

BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx
0x7F received on
USARTx

no
yes

I2C Address
Detected

no
HSE detected no no HSE detected

Synchro mechanism Generate System

detected on SPIx yes reset yes

Disable all interrupt

Disable other
sources and other
no interfaces clocks
interfaces clocks
no

Frame detected Reconfigure System Reconfigure System

on CANx clock to 60MHz and clock to 60MHz
USB clock to 48 MHz

no Configure CAN
Execute DFU
bootloader using USB
USB cable interrupts Execute
yes
Detected BL_CAN_Loop for
CAN2

MSv42229V1

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32.3 Bootloader version

The following table lists the STM32F413xx/423xx devices bootloader V9.x versions.

Table 68. STM32F413xx/423xx bootloader V9.x versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code)

the bootloader resets AHB1ENR value to 0x0000
V9.0 Initial bootloader version 0000 and thus CCM RAM, when present, is not
active (must be re-enabled by user code at
startup)

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33 STM32F42xxx/43xxx devices bootloader

33.1 Bootloader V7.x

33.1.1 Bootloader configuration

The STM32F42xxx/43xxx bootloader is activated by applying Pattern 5 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 69. STM32F42xxx/43xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

using the PLL.
The HSI clock source is used at startup
(interface detection phase) and when
HSI enabled
USART or I2C interfaces are selected
(once CAN or DFU bootloader is selected,
the clock source is derived from the
external crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the CAN or the DFU (USB FS Device)
HSE enabled interfaces are selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
Common to all external clock generates system reset.
bootloaders
8 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.

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Table 69. STM32F42xxx/43xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8 bits, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8 bits, even parity and 1 Stop bit
USART3 bootloader 
(on PB10/PB11) USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8 bits, even parity and 1 Stop bit
USART3 bootloader 
(on PC10/PC11) USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111000x (where x = 0 for write
and x = 1 for read).
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB9 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
USB OTG FS configured in forced device
USB Enabled
mode
DFU bootloader USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required
This timer is used to determine the value of
CAN2 and DFU the HSE. Once the HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

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The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

33.1.2 Bootloader selection

Figure 38 and Figure 39 show the bootloader selection mechanism.

Figure 38. Dual bank boot implementation for STM32F42xxx/43xxx Bootloader V7.x

System Reset

If Boot0 = 0

yes
no

If Value of first
address of Bank2 is
yes
within int. SRAM
address(1)
Protection level2 no
Set Bank Swap to
enabled
Bank2
no

Jump to user code yes Continue Bootloader

If Value of first in Bank2 execution
address of Bank1 is
within int. SRAM
address(1) If Value of first
yes address of Bank2 is
within int. SRAM yes
address(1)
no

Protection level2 no
yes
enabled
Set Bank Swap to Set Bank Swap to Set Bank Swap to
Bank1 Bank1 Bank2
no

Jump to user code Jump to user code Jump to user code

Continue Bootloader
in Bank1 in Bank1 in Bank2
execution

MS35021V1

1. CCM RAM is not considered valid as stack pointer address for the dual bank boot mechanism.

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Figure 39. Bootloader V7.x selection for STM32F42xxx/43xxx

Bootloader

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB OTG FS Disable all

yes
device interrupt sources

Configure
Configure I2Cx USARTx

Execute
0x7F received BL_USART_Loop
on USARTx for USARTx

yes
no
Execute
BL_I2C_Loop for
I2Cx
I2C Address
Detected yes

HSE detected
no no

yes yes
Frame detected
no on CANx HSE detected no Disable all
interrupt sources
Generate System
no yes reset
Reconfigure System
clock to 60MHz
Reconfigure System
USB cable clock to 60MHz and
Detected USB clock to 48 MHz Configure CAN

Execute DFU Execute

bootloader using USB BL_CAN_Loop for
interrupts CAN2

MS35022V1

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33.1.3 Bootloader version

The following table lists the STM32F42xxx/43xxx devices bootloader V7.x versions.
.

Table 70. STM32F42xxx/43xxx bootloader V7.x versions

Bootloader
version Description Known limitations
number

For the CAN interface, the Write Unprotect

command is not functional. Use Write Memory
command and write directly to the option bytes to
disable the write protection.
For the USB DFU interface, in Dual Bank mode, the
Erase operation is not functional for the second
V7.0 Initial bootloader version
bank. Return to Single Bank mode, erase desired
sector(s) and then reactivate the Dual Bank mode.
After executing Go command (jump to user code)
the bootloader resets AHB1ENR value to 0x0000
0000 and thus CCM RAM, when present, is not
active (must be re-enabled by user code at startup).

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33.2 Bootloader V9.x

33.2.1 Bootloader configuration

The STM32F42xxx/43xxx bootloader is activated by applying Pattern 5 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 71. STM32F42xxx/43xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz using the PLL.

The HSI clock source is used at startup (interface
detection phase) and when USART or SPI or I2C
HSI enabled
interfaces are selected (once CAN or DFU bootloader
is selected, the clock source is derived from the
external crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when the CAN or
HSE enabled the DFU (USB FS Device) interfaces are selected.
The external clock must provide a frequency multiple
of 1 MHz and ranging from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt is enabled
for the CAN and DFU bootloaders. Any failure (or
-
removal) of the external clock generates system
Common to all reset.
bootloaders 12 Kbyte starting from address 0x20000000 are used
RAM -
by the bootloader firmware
29 Kbyte starting from address 0x1FFF0000, contain
System memory -
the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Voltage range is set to [1.62 V, 2.1 V]. In this range
internal Flash write operations are allowed only in
byte format (Half-Word, Word and Double-Word
Power -
operations are not allowed). The voltage range can
be configured in run time using bootloader
commands.
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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Table 71. STM32F42xxx/43xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART3 configuration is: 8-bit,

USART3 Enabled
USART3 even parity and 1 Stop bit
bootloader 
USART3_RX pin Input PB11 pin: USART3 in reception mode
(on PB10/PB11)
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration is: 8-bit,
USART3 Enabled
USART3 even parity and 1 Stop bit
bootloader 
USART3_RX pin Input PC11 pin: USART3 in reception mode
(on PC10/PC11)
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud rate from
SysTick timer Enabled
bootloaders the host for USARTx bootloaders.
Once initialized the CAN2 configuration is: Baudrate
125 kbps, 11-bit identifier.
CAN2 Enabled Note: CAN1 is clocked during CAN2 bootloader
execution because CAN1 manages the
CAN2 bootloader
communication between CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave mode,
I2C1 Enabled
analog filter ON. Slave 7-bit address: 0b0111000x
I2C1 bootloader (where x = 0 for write and x = 1 for read).
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB9 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave mode,
I2C2 Enabled
analog filter ON. Slave 7-bit address: 0b0111000x
I2C2 bootloader (where x = 0 for write and x = 1 for read).
I2C2_SCL pin Input/Output PF1 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PF0 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave mode,
I2C3 Enabled
analog filter ON. Slave 7-bit address: 0b0111000x
I2C3 bootloader (where x = 0 for write and x = 1 for read).
I2C3_SCL pin Input/Output PA8 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC9 pin: data line is used in open-drain mode.

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Table 71. STM32F42xxx/43xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

Slave mode, Full Duplex, -bit MSB, Speed up to 8
SPI1 Enabled
MHz, Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in push-pull pull-
SPI1_MOSI pin Input
down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in push-pull
SPI1_MISO pin Output
pull-down mode
PA5 pin: Slave clock line, used in push-pull pull-down
SPI1_SCK pin Input
mode
PA4 pin: slave chip select pin used in push-pull pull-
SPI1_NSS pin Input
down mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed up to 8
SPI2 Enabled
MHz, Polarity: CPOL Low, CPHA Low, NSS
hardware.
PI3 pin: Slave data Input line, used in push-pull pull-
SPI2_MOSI pin Input
down mode
SPI2 bootloader
PI2 pin: Slave data output line, used in push-pull pull-
SPI2_MISO pin Output
down mode
PI1 pin: Slave clock line, used in push-pull pull-down
SPI2_SCK pin Input
mode
PI0 pin: slave chip select pin used in push-pull pull-
SPI2_NSS pin Input
down mode.
The SPI4 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed up to 8
SPI4 Enabled
MHz, Polarity: CPOL Low, CPHA Low, NSS
hardware.
PE14 pin: Slave data Input line, used in push-pull
SPI4_MOSI pin Input
pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used in push-pull
SPI4_MISO pin Output
pull-down mode
PE12 pin: Slave clock line, used in push-pull pull-
SP4_SCK pin Input
down mode
PE11 pin: slave chip select pin used in push-pull pull-
SPI4_NSS pin Input
down mode.
USB Enabled USB OTG FS configured in forced device mode
USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required
This timer is used to determine the value of the HSE.
CAN2 and DFU
TIM11 Enabled Once the HSE frequency is determined, the system
bootloaders
clock is configured to 60 MHz using PLL and HSE.

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The system clock is derived from the embedded internal high-speed RC for USARTx, I2Cx
and SPIx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device)
but only for the selection phase. An external clock multiple of 1 MHz (between 4 and
26 MHz) is required for CAN and DFU bootloader execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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33.2.2 Bootloader selection

Figure 40 and Figure 41 show the bootloader selection mechanism.

Figure 40. Dual bank boot implementation for STM32F42xxx/43xxx bootloader V9.x

System Reset

If Boot0 = 0

yes
no

If Value of first
address of Bank2 is
yes
within int. SRAM
address(1) Protection level2
no
Set Bank Swap to enabled
Bank2
no

Jump to user code yes Continue Bootloader

If Value of first in Bank2 execution
address of Bank1 is
within int. SRAM
address(1) If Value of first
yes address of Bank2 is
within int. SRAM yes
address(1)
no

Protection level2 no
yes
enabled
Set Bank Swap to Set Bank Swap to Set Bank Swap to
Bank1 Bank1 Bank2
no

Jump to user code Jump to user code Jump to user code

Continue Bootloader
in Bank1 in Bank1 in Bank2
execution

MS35023V1

1. CCM RAM is not considered valid as stack pointer address for the dual bank boot mechanism.

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Figure 41. Bootloader V9.x selection for STM32F42xxx/43xxx

Bootloader

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB OTG FS

device

Disable all interrupt

sources
Configure I2Cx
yes
Configure USARTx
Configure SPIx

Execute
BL_USART_Loop for
0x7F received USARTx
on USARTx

no Execute
BL_I2C_Loop for
yes
I2Cx
I2C Address
Detected

Execute
no
yes BL_SPI_Loop for
SPIx
Synchro
mechanism detected
on SPIx yes

no HSE detected
no
HSE detected
Frame detected yes
no yes no
on CANx
Disable all interrupt
sources
yes
no Generate System
reset
Reconfigure System clock
Reconfigure System to 60MHz
USB cable clock to 60MHz and
Detected USB clock to 48 MHz
Configure CAN

Execute DFU Execute

bootloader using USB BL_CAN_Loop for
interrupts CAN2

MS35024V1

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33.2.3 Bootloader version

Table 72 lists the STM32F42xxx/43xxx devices bootloader V9.x versions.

Table 72. STM32F42xxx/43xxx bootloader V9.x versions

Bootloader
version Description Known limitations
number

For the USB DFU interface, in Dual Bank mode,

This bootloader is an updated
the Erase operation is not functional for the
version of bootloader v7.0. 
second bank. Return to Single Bank mode, erase
This new version of bootloader
desired sector(s) and then reactivate the Dual
supports I2C2, I2C3, SPI1, SPI2
Bank mode.
V9.0 and SPI4 interfaces. 
The RAM used by this bootloader After executing Go command (jump to user code)
is increased from 8 Kb to 12 Kb. the bootloader resets AHB1ENR value to 0x0000
The ID of this bootloader is 0x90 0000 and thus CCM RAM, when present, is not
The connection time is increased. active (must be re-enabled by user code at
startup)
For the CAN interface, the Write Unprotect
command is not functional. Use Write Memory
This bootloader is an updated command and write directly to the option bytes in
version of bootloader v9.0. This order to disable the write protection.
new version implements the new
For the USB DFU interface, in Dual Bank mode,
I2C No-stretch commands (I2C
the Erase operation is not functional for the
protocol v1.1) and the capability
second bank. Return to Single Bank mode, erase
V9.1 of disabling PcROP when RDP1
desired sector(s) and then reactivate the Dual
is enabled with
Bank mode.
ReadOutUnprotect command for
all protocols(USB, USART, CAN, After executing Go command (jump to user code)
I2C and SPI). The ID of this the bootloader resets AHB1ENR value to 0x0000
bootloader is 0x91 0000 and thus CCM RAM, when present, is not
active (must be re-enabled by user code at
startup)

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34 STM32F446xx devices bootloader

34.1 Bootloader configuration

The STM32F446xx bootloader is activated by applying Pattern 1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 73.STM32F446xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source

for system clock configured to 60 MHz and
HSI enabled
for USART, I2C and SPI bootloader
operation.
The HSE is used only when the CAN or the
DFU (USB FS Device) interfaces are
selected. In this case the system clock
RCC HSE enabled configured to 60 MHz with HSE as clock
source.
The HSE frequency must be multiple of
1 MHz and ranging from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
external clock generates system reset.
12 Kbyte starting from address
RAM - 0x20000000 are used by the bootloader
Common to all firmware
bootloaders
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
The voltage range is [1.71 V, 3.6 V].
In this range:
- Flash wait states: 3.
- System Clock 60 MHz.
Power -
- Prefetch disabled.
- Flash write operation by byte (refer to
section bootloader memory management
for more information).

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Table 73.STM32F446xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8-bit, even parity and 1 Stop bit
USART3 bootloader
(on PB10/PB11) USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8-bit, even parity and 1 Stop bit
USART3 bootloader
(on PC10/PC11) USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because in CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b0111100x
I2C1 bootloader (where x = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB9 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b0111100x
I2C2 bootloader (where x = 0 for write and x = 1 for read)
PF1 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PF0 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.

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Table 73.STM32F446xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 kHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b0111100x
I2C3 bootloader (where x = 0 for write and x = 1 for read)
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC9 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in push-
SPI1_NSS pin Input
pull pull-up mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
push-pull pull-down mode
SPI2 bootloader
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PC7 pin: Slave clock line, used in push-pull
SPI2_SCK pin Input
pull-down mode
PB12 pin: slave chip select pin used in
SPI2_NSS pin Input
push-pull pull-up mode.

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Table 73.STM32F446xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI4 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI4 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PE14 pin: Slave data Input line, used in
SPI4_MOSI pin Input
push-pull pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used in
SPI4_MISO pin Output
push-pull pull-down mode
PE12 pin: Slave clock line, used in push-
SPI4_SCK pin Input
pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
push-pull pull-up mode.
USB OTG FS configured in forced device
USB Enabled
mode

DFU bootloader USB_DM pin PA11: USB DM line.

Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required
This timer is used to determine the value of
CAN2 and DFU the HSE. Once the HSE frequency is
TIM17 Enabled
bootloaders determinated, the system clock is
configured to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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34.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 42.Bootloader V9.x selection for STM32F446xx

System Reset

Disable all
System Init (Clock, GPIOs,
interrupt sources
IWDG, SysTick)
yes
Configure
Configure USB OTG FS
USARTx
device

Execute
Configure I2Cx BL_USART_Loop
for USARTx

0x7F received
on USARTx
Disable all
yes interrupt sources
no

Execute
I2C Address BL_I2C_Loop for
Detected I2Cx

yes Disable all

no interrupt sources

Execute
Synchro mechanism BL_SPI_Loop for
detected on SPIx SPIx
yes

no HSE detected
no
no

yes yes
Frame detected
on CANx HSE detected no Disable all
interrupt sources
Generate System
yes reset
no Reconfigure System
clock to 60MHz
Reconfigure System
clock to 60MHz and
USB cable USB clock to 48 MHz Configure CAN
Detected

Execute DFU Execute

bootloader using USB BL_CAN_Loop for
interrupts CAN2

MSv36763V1

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34.3 Bootloader version

The following table lists the STM32F446xx devices bootloader V9.x versions:

Table 74. STM32F446xx bootloader V9.x versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code)

the bootloader resets AHB1ENR value to 0x0000
V9.0 Initial bootloader version 0000 and thus CCM RAM, when present, is not
active (must be re-enabled by user code at
startup)

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35 STM32F469xx/479xx devices bootloader

35.1 Bootloader configuration

The STM32F469xx/479xx bootloader is activated by applying Pattern 5 (described in
Table 2: Bootloader activation patterns). Table 75 shows the hardware resources used by
this bootloader.

Table 75. STM32F469xx/479xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz

using the PLL.
The HSI clock source is used at startup
HSI enabled (interface detection phase) and when
USART or SPI or I2C interfaces are
selected (once CAN or DFU bootloader is
selected, the clock source is derived from
external crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the CAN or the DFU (USB FS Device)
HSE enabled interfaces are selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS)
interrupt is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of
Common to all the external clock generates system reset.
bootloaders 12 Kbyte starting from address
RAM - 0x20000000 are used by the bootloader
firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-
Power - Word, Word and Double-Word operations
are not allowed). The voltage range can
be configured in run time using bootloader
commands.

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Table 75. STM32F469xx/479xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8-bit, even parity and 1 Stop bit
USART3 bootloader
(on PB10/PB11) USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8-bit, even parity and 1 Stop bit
USART3 bootloader
(on PC10/PC11) USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial
USARTx bootloaders SysTick timer Enabled baud rate from the host for USARTx
bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB05 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b1000100x (where x = 0 for
write and x = 1 for read).
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB9 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b1000100x (where x = 0 for
write and x = 1 for read).
I2C2 bootloader
PF0 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PF1 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.

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Table 75. STM32F469xx/479xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 kHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b1000100x (where x = 0 for
write and x = 1 for read).
I2C3 bootloader
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC9 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI1 Enabled
Speed up to 8 MHz, Polarity: CPOL Low,
CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-
SPI1_SCK pin Input
pull pull-down mode
PA4 pin: slave chip select pin used in
SPI1_NSS pin Input
push-pull pull-up mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI2 Enabled
Speed up to 8 MHz, Polarity: CPOL Low,
CPHA Low, NSS hardware.
PI3 pin: Slave data Input line, used in
SPI2_MOSI pin Input
push-pull pull-down mode
SPI2 bootloader
PI2 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PI1pin: Slave clock line, used in push-pull
SPI2_SCK pin Input
pull-down mode
PI0 pin: slave chip select pin used in push-
SPI2_NSS pin Input
pull pull-up mode.

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Table 75. STM32F469xx/479xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI4 configuration is:

Slave mode, Full Duplex, 8-bit MSB,
SPI4 Enabled
Speed up to 8 MHz, Polarity: CPOL Low,
CPHA Low, NSS hardware.
PE14 pin: Slave data Input line, used in
SPI4_MOSI pin Input
push-pull pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used in
SPI4_MISO pin Output
push-pull pull-down mode
PE12 pin: Slave clock line, used in push-
SP4_SCK pin Input
pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
push-pull pull-up mode.
USB OTG FS configured in forced device
mode. USB_OTG_FS interrupt vector is
USB Enabled
enabled and used for USB DFU
communications.
DFU bootloader
USB_DM pin PA11 pin: USB DM line.
Input/Output PA12 pin: USB DP line.
USB_DP pin
No external Pull-Up resistor is required.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 48 MHz) is
required for CAN and DFU bootloaders execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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35.2 Bootloader selection

Figure 43 and Figure 44 show the bootloader selection mechanism.

Figure 43. Dual bank boot implementation for STM32F469xx/479xx Bootloader V9.x

System Reset

If Boot = 0 no

yes

If value of
first address of Bank2
yes
is within int. SRAM
address
Set Bank Swap to
Bank2

no
Jump to user code Protection
no
in Bank2 level2 enabled

Continue Bootloader
If value of
execution
first address of Bank1
yes
is within int. SRAM yes
address

no If value of
first address of Bank2
yes
is within int. SRAM
Protection address
yes
level2 enabled

no

no Set Bank Swap to Set Bank Swap to Set Bank Swap to

Bank1 Bank1 Bank2

Continue Bootloader Jump to user code Jump to user code Jump to user code
execution in Bank1 in Bank1 in Bank2

MSv38429V1

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Figure 44.Bootloader V9.x selection for STM32F469xx/479xx

Bootloader

System Init (Clock, GPIOs,

IWDG, SysTick)

Disable all interrupt

Configure USB OTG FS
Disable all interrupt Disable all interrupt sources and other
device
sources and other sources and other interfaces clocks
interfaces clocks interfaces clocks
Configure I2Cx Configure USARTx

Configure SPIx Execute Execute Execute

BL_SPI_Loop for BL_I2C_Loop for BL_USART_Loop
SPIx I2Cx for USARTx

0x7F received
yes
on USARTx

no

I2C Address
yes
Detected

no

no HSE detected

Synchro mechanism HSE detected no

yes
detected on SPIx
Generate System yes
reset
yes
Disable all interrupt
no Disable other sources and other
interfaces clocks interfaces clocks

Frame detected
yes
on CANx Reconfigure
Reconfigure System System clock to
clock to 60MHz and 60MHz
USB clock to 48 MHz
no

Configure CAN
Execute DFU
USB cable bootloader using USB
yes
Detected interrupts
Execute
BL_CAN_Loop for
CAN2
no
MSv38430V2

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35.3 Bootloader version

Table 76 lists the STM32F469xx/479xx devices V9.x bootloader versions:

Table 76. STM32F469xx/479xx bootloader V9.x versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code) the

bootloader resets AHB1ENR value to 0x0000 0000
V9.0 Initial bootloader version
and thus CCM RAM, when present, is not active
(must be re-enabled by user code at startup).

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36 STM32F72xxx/73xxx devices bootloader

36.1 Bootloader configuration

The STM32F72xxx/73xxx bootloader is activated by applying Pattern 8 (described in
Table 2: Bootloader activation patterns). Table 77 shows the hardware resources used by
this bootloader.

Table 77. STM32F72xxx/73xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock

source for system clock configured to
HSI enabled
60 MHz and for USART and I2C
bootloader operation.
The HSE is used only when the CAN
or the DFU (USB FS Device)
interfaces are selected. In this case the
system clock configured to 60 MHz
HSE enabled
RCC with HSE as clock source.
The HSE frequency must be multiple
of 1 MHz and ranging from 4 MHz to
26 MHz.
The Clock Security System (CSS)
interrupt is enabled for the CAN and
- DFU bootloaders. Any failure (or
removal) of the external clock
generates system reset.
16 Kbyte starting from address
Common to all RAM - 0x20000000 are used by the
bootloaders bootloader firmware
59 Kbyte starting from address
System memory - 0x1FF00000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
The voltage range is [1.8V, 3.6V]
In this range:
- Flash wait states: 3.
Power - - System clock frequency 60 MHz.
- ART Accelerator enabled.
- Flash write operation by byte (refer to
bootloader memory management
section for more information).

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Table 77. STM32F72xxx/73xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1

USART1 Enabled configuration is: 8-bit, even parity and
1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
PA9 pin: USART1 in transmission
USART1_TX pin Output
mode
Once initialized the USART3
USART3 Enabled configuration is: 8-bit, even parity and
USART3 1 Stop bit
bootloader 
USART3_RX pin Input PB11 pin: USART3 in reception mode
(on PB11/PB10)
PB10 pin: USART3 in transmission
USART3_TX pin Output
mode
Once initialized the USART3
USART3 Enabled configuration is: 8-bit, even parity and
USART3 1 Stop bit
bootloader 
USART3_RX pin Input PC11 pin: USART3 in reception mode
(on PC11/PC10)
PC10 pin: USART3 in transmission
USART3_TX pin Output
mode
Used to automatically detect the serial
USARTx
SysTick timer Enabled baud rate from the host for USARTx
bootloaders
bootloaders.
Once initialized the CAN1
CAN1 Enabled configuration is: Baudrate 125 kbps,
11-bit identifier.
CAN1 bootloader
CAN1_RX pin Input PD0 pin: CAN1 in reception mode
CAN1_TX pin Output PD1 pin: CAN1 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit
address, slave mode, analog filter ON.
I2C1 Enabled
Slave 7-bit address: 0b1001001x
(where x = 0 for write and x = 1 for
I2C1 bootloader read)
PB6 pin: clock line is used in open-
I2C1_SCL pin Input/Output
drain mode.
PB9 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

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Table 77. STM32F72xxx/73xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C2 configuration is:

I2C speed: up to 400 kHz, 7-bit
address, slave mode, analog filter ON.
I2C2 Enabled
Slave 7-bit address: 0b1001101x
(where x = 0 for write and x = 1 for
I2C2 bootloader read)
PF1 pin: clock line is used in open-
I2C2_SCL pin Input/Output
drain mode.
PF0 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 400 kHz, 7-bit
address, slave mode, analog filter ON.
I2C3 Enabled
Slave 7-bit address: 0b1001001x
(where x = 0 for write and x = 1 for
I2C3 bootloader read)
PA8 pin: clock line is used in open-
I2C3_SCL pin Input/Output
drain mode.
PC9 pin: data line is used in open-
I2C3_SDA pin Input/Output
drain mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI1 Enabled
Speed up to 8 MHz, Polarity: CPOL
Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in
SPI1_SCK pin Input
push-pull pull-down mode
PA4 pin: slave chip select pin used in
SPI1_NSS pin Input
push-pull pull-up mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI2 Enabled
Speed up to 8 MHz, Polarity: CPOL
Low, CPHA Low, NSS hardware.
PI3 pin: Slave data Input line, used in
SPI2_MOSI pin Input
push-pull pull-down mode
SPI2 bootloader
PI2 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PI1 pin: Slave clock line, used in push-
SPI2_SCK pin Input
pull pull-down mode
PI0 pin: slave chip select pin used in
SPI2_NSS pin Input
push-pull pull-up mode.

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Table 77. STM32F72xxx/73xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI4 configuration is:

Slave mode, Full Duplex, 8-bit MSB,
SPI4 Enabled
Speed up to 8 MHz, Polarity: CPOL
Low, CPHA Low, NSS hardware.
PE14 pin: Slave data Input line, used
SPI4_MOSI pin Input
in push-pull pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used
SPI4_MISO pin Output
in push-pull pull-down mode
PE12 pin: Slave clock line, used in
SP4_SCK pin Input
push-pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
push-pull pull-up mode.
USB OTG FS configured in forced
USB Enabled
device mode
USB_DM pin PA11 pin: USB DM line.
DFU bootloader
Input/Output PA12 pin: USB DP line
USB_DP pin No external Pull-Up resistor is
required.
This timer is used to determine the
value of the HSE. Once HSE
CAN1 and DFU
TIM11 Enabled frequency is determined, the system
bootloaders
clock is configured to 60 MHz using
PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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36.2 Bootloader selection

Figure 45 shows the bootloader selection mechanism.

Figure 45. Bootloader V9.x selection for STM32F72xxx/73xxx

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36.3 Bootloader version

Table 78 lists the STM32F72xxx/73xxx devices bootloader V9.x versions.

Table 78. STM32F72xxx/73xxx bootloader V9.x versions

Bootloader
version Description Known limitations
number

At high UART baudrates (115200 bps) connection

may fail due to software jitter leading to wrong
baudrate calculation.
V9.0 Initial bootloader version In that case bootloader may respond with a baudrate
up to ± 5% different from host baudrate.
Workaround: use baudrates lower than 57600 bps if
host tolerance to baudrate error is lower than ± 5%

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371
STM32F74xxx/75xxx devices bootloader AN2606

37 STM32F74xxx/75xxx devices bootloader

Two bootloader versions are available on STM32F74xxx/75xxx:

 V7.x supporting USART1, USART3, CAN2, I2C1, I2C2, I2C3 and DFU (USB FS
Device). This version is embedded in STM32F74xxx/75xxx rev. A devices.
 V9.x supporting USART1, USART3, CAN2, I2C1, I2C2, I2C3, SPI1, SPI2, SPI4 and
DFU (USB FS Device). This version is embedded in STM32F74xxx/75xxx rev. Z and
rev. 1 devices.
Note: When readout protection Level2 is activated, STM32F74xxx/75xxx devices can boot also on
system memory and all commands are not accessible except Get, GetID, and GetVersion.

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37.1 Bootloader V7.x

37.1.1 Bootloader configuration

The STM32F74xxx/75xxx bootloader is activated by applying Pattern 8 (described in
Table 2: Bootloader activation patterns). Table 79 shows the hardware resources used by
this bootloader.

Table 79. STM32F74xxx/75xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
The HSI is used at startup as clock source for system
HSI enabled clock configured to 60 MHz and for USART and I2C
bootloader operation.
The HSE is used only when the CAN or the DFU (USB
FS Device) interfaces are selected. In this case the
system clock configured to 60 MHz with HSE as clock
HSE enabled
RCC source.
The HSE frequency must be multiple of 1 MHz and
ranging from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
external clock generates system reset.
Common to all 16 Kbyte starting from address 0x20000000 are used
RAM -
bootloaders by the bootloader firmware
60 Kbyte starting from address 0x1FF00000, contain
System memory -
the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by the
user).
The voltage range is [1.8V, 3.6V]. In this range:
- Flash wait states: 3.
- System clock frequency 60 MHz.
Power -
- ART Accelerator enabled.
- Flash write operation by byte (refer to bootloader
memory management section for more information).
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
USART1 even parity and 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration is: 8-bit,
USART3 USART3 Enabled
even parity and 1 Stop bit
bootloader 
USART3_RX pin Input PB11 pin: USART3 in reception mode
(on PB10/PB11)
USART3_TX pin Output PB10 pin: USART3 in transmission mode

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Table 79. STM32F74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
Once initialized the USART3 configuration is: 8-bit,
USART3 USART3 Enabled
even parity and 1 Stop bit
bootloader 
USART3_RX pin Input PC11 pin: USART3 in reception mode
(on PC10/PC11)
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud rate from
SysTick timer Enabled
bootloaders the host for USARTx bootloaders.
Once initialized the CAN2 configuration is: Baudrate
125 kbps, 11-bit identifier.
CAN2 Enabled Note: CAN1 is clocked during CAN2 bootloader
CAN2 execution because CAN1 manages the
bootloader communication between CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
I2C1 bootloader Slave 7-bit address: 0b1000101x
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB9 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
I2C2 bootloader Slave 7-bit address: 0b1000101x
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PF1 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PF0 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave mode,
I2C3 Enabled analog filter ON.
I2C3 bootloader Slave 7-bit address: 0b1000101x
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PA8 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC9 pin: data line is used in open-drain mode.
USB Enabled USB OTG FS configured in forced device mode.
USB_DM pin PA11 pin: USB DM line.
DFU bootloader
Input/Output PA12 pin: USB DP line
USB_DP pin
No external Pull-Up resistor is required.
This timer is used to determine the value of the HSE.
CAN2 and DFU
TIM11 Enabled Once HSE frequency is determined, the system clock
bootloaders
is configured to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but

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only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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37.1.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 46.Bootloader V7.x selection for STM32F74xxx/75xxx

System Reset
yes

System Init (Clock, GPIOs,

IWDG, SysTick) yes
Disable all interrupt
sources and other
Configure USB OTG FS interfaces clocks
device
Disable all interrupt
sources and other Configure
interfaces clocks USARTx
Configure I2Cx

Execute Execute
BL_I2C_Loop BL_USART_Loop
0x7F received on for I2Cx for USARTx
USARTx
yes

no

I2C Address
Detected HSE detected no no HSE detected

no Generate System
yes reset yes

Disable all interrupt

Frame detected Disable other
sources and other
on CANx interfaces clocks
interfaces clocks
no

no Reconfigure System Reconfigure System

clock to 60MHz and clock to 60MHz
USB clock to 48 MHz
USB cable
yes
Detected
Configure CAN
Execute DFU
bootloader using USB
interrupts Execute
BL_CAN_Loop for
CAN2

MSv37792V1

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37.1.3 Bootloader version

The following table lists the STM32F74xxx/75xxx devices bootloader V7.x versions:

Table 80. STM32F74xxx/75xxx bootloader V7.x versions

Bootloader
version Description Known limitations
number

At high UART baudrates (115200 bps)

connection may fail due to software jitter
leading to wrong baudrate calculation.
In that case bootloader may respond with a
V7.0 Initial bootloader version baudrate up to ± 5% different from host
baudrate.
Workaround: use baudrates lower than
57600 bps if host tolerance to baudrate error
is lower than ± 5%

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37.2 Bootloader V9.x

37.2.1 Bootloader configuration

The STM32F74xxx/75xxx bootloader is activated by applying Pattern 8 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 81. STM32F74xxx/75xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source

for system clock configured to 60 MHz and
HSI enabled
for USART, I2C and SPI bootloader
operation.
The HSE is used only when the CAN or the
DFU (USB FS Device) interfaces are
selected. In this case the system clock
RCC HSE enabled configured to 60 MHz with HSE as clock
source.
The HSE frequency must be multiple of 1
MHz and ranging from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
external clock generates system reset.
16 Kbyte starting from address
RAM - 0x20000000 are used by the bootloader
Common to all
firmware
bootloaders
60 Kbyte starting from address
System memory - 0x1FF00000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
The voltage range is [1.8V, 3.6V]
In this range:
- Flash wait states: 3.
Power - - System clock frequency 60 MHz.
- ART Accelerator enabled.
- Flash write operation by byte (refer to
bootloader memory management section
for more information).

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Table 81. STM32F74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8-bit, even parity and 1 Stop bit
USART3 bootloader
(on PB10/PB11) USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8-bit, even parity and 1 Stop bit
USART3 bootloader
(on PC10/PC11) USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000101x
I2C1 bootloader (where x = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/output
mode.
PB9 pin: data line is used in open-drain
I2C1_SDA pin Input/output
mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000101x
I2C2 bootloader (where x = 0 for write and x = 1 for read)
PF1 pin: clock line is used in open-drain
I2C2_SCL pin Input/output
mode.
PF0 pin: data line is used in open-drain
I2C2_SDA pin Input/output
mode.

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Table 81. STM32F74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 kHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000101x
I2C3 bootloader (where x = 0 for write and x = 1 for read)
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/output
mode.
PC9 pin: data line is used in open-drain
I2C3_SDA pin Input/output
mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in push-
SPI1_NSS pin Input
pull pull-up mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PI3 pin: Slave data Input line, used in push-
SPI2_MOSI pin Input
pull pull-down mode
SPI2 bootloader
PI2 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PI1 pin: Slave clock line, used in push-pull
SPI2_SCK pin Input
pull-down mode
PI0 pin: slave chip select pin used in push-
SPI2_NSS pin Input
pull pull-up mode.

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Table 81. STM32F74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI4 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI4 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PE14 pin: Slave data Input line, used in
SPI4_MOSI pin Input
push-pull pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used in
SPI4_MISO pin Output
push-pull pull-down mode
PE12 pin: Slave clock line, used in push-
SP4_SCK pin Input
pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
push-pull pull-up mode.
USB OTG FS configured in forced device
USB Enabled
mode.

DFU bootloader USB_DM pin PA11 pin: USB DM line.

Input/Output PA12 pin: USB DP line
USB_DP pin
No external Pull-Up resistor is required.
This timer is used to determine the value of
CAN2 and DFU the HSE. Once HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx, I2Cx
and SPIx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device)
but only for the selection phase. An external clock multiple of 1 MHz (between 4 and
26 MHz) is required for CAN and DFU bootloader execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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37.2.2 Bootloader selection

Figure 47 shows the bootloader selection mechanism.

Figure 47.Bootloader V9.x selection for STM32F74xxx/75xxx

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick) yes

Configure USB OTG FS

device yes
Disable all interrupt
yes sources and other
interfaces clocks
Configure I2Cx
Disable all interrupt Disable all interrupt
sources and other sources and other Configure
interfaces clocks interfaces clocks USARTx
Configure SPIx

Execute Execute Execute

BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx
0x7F received on
USARTx

no
yes

I2C Address
Detected

no
HSE detected no no HSE detected

Synchro mechanism Generate System

detected on SPIx yes reset yes

Disable all interrupt

Disable other
sources and other
no interfaces clocks
interfaces clocks
no

Frame detected Reconfigure System Reconfigure System

on CANx clock to 60MHz and clock to 60MHz
USB clock to 48 MHz

no Configure CAN
Execute DFU
bootloader using USB
USB cable interrupts Execute
yes
Detected BL_CAN_Loop for
CAN2

MSv36793V1

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37.2.3 Bootloader version

The following table lists the STM32F74xxx/75xxx bootloader V9.x versions:

Table 82. STM32F74xxx/75xxx bootloader V9.x versions

Bootloader
version Description Known limitations
number

At high UART baudrates (115200 bps)

connection may fail due to software jitter
leading to wrong baudrate calculation.
In that case bootloader may respond with a
V9.0 Initial bootloader version baudrate up to ± 5% different from host
baudrate.
Workaround: use baudrates lower than
57600 bps if host tolerance to baudrate
error is lower than ± 5%

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38 STM32F76xxx/77xxx devices bootloader

38.1 Bootloader configuration

The STM32F76xxx/77xxx bootloader is activated by applying Pattern 9 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 83. STM32F76xxx/77xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source

HSI enabled for system clock configured to 60 MHz and
for USART and I2C bootloader operation.
The HSE is used only when the CAN or the
DFU (USB FS Device) interfaces are
selected. In this case the system clock
HSE enabled configured to 60 MHz with HSE as clock
RCC source.
The HSE frequency must be multiple of 1
MHz and ranging from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
external clock generates system reset.
16 Kbyte starting from address
RAM - 0x20000000 are used by the bootloader
Common to all firmware
bootloaders
59 Kbyte starting from address
System memory - 0x1FF00000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
The voltage range is [1.8V, 3.6V]
In this range:
- Flash wait states: 3.
Power - - System clock frequency 60 MHz.
- ART Accelerator enabled.
- Flash write operation by byte (refer to
bootloader memory management section
for more information).

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Table 83. STM32F76xxx/77xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8-bit, even parity and 1 Stop bit
USART3 bootloader
(on PB11/PB10) USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8-bit, even parity and 1 Stop bit
USART3 bootloader
(on PC11/PC10) USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001001x (where x
I2C1 bootloader = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB9 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001001x (where x
I2C2 bootloader = 0 for write and x = 1 for read)
PF1 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PF0 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.

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Table 83. STM32F76xxx/77xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 kHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001001x (where x
I2C3 bootloader = 0 for write and x = 1 for read)
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC9 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in push-
SPI1_NSS pin Input
pull pull-up mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PI3 pin: Slave data Input line, used in push-
SPI2_MOSI pin Input
pull pull-down mode
SPI2 bootloader
PI2 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PI1 pin: Slave clock line, used in push-pull
SPI2_SCK pin Input
pull-down mode
PI0 pin: slave chip select pin used in push-
SPI2_NSS pin Input
pull pull-up mode.

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Table 83. STM32F76xxx/77xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI4 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI4 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PE14 pin: Slave data Input line, used in
SPI4_MOSI pin Input
push-pull pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used in
SPI4_MISO pin Output
push-pull pull-down mode
PE12 pin: Slave clock line, used in push-
SP4_SCK pin Input
pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
push-pull pull-up mode.
USB OTG FS configured in forced device
USB Enabled
mode

DFU bootloader USB_DM pin PA11 pin: USB DM line.

Input/Output PA12 pin: USB DP line
USB_DP pin
No external Pull-Up resistor is required.
This timer is used to determine the value of
CAN2 and DFU the HSE. Once HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.
Note: Due to HSI deviation and since HSI is used to detect HSE value, the user must use low
frequency rather than high frequency HSE crystal values (low frequency values are better
detected due to larger error margin). For example, it is better to use 8 MHz instead of
25 MHz.

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38.2 Bootloader selection

Figure 48 and Figure 49 show the bootloader selection mechanism.

Figure 48. Dual bank boot implementation for STM32F76xxx/77xxx Bootloader V9.x

System Reset

nDBANK = 0 &
yes
nDBOOT = 0

Select BOOT_ADDx by BOOT0

no Pin(1)

Compute entire boot address from

BOOT_ADDx
Protection level2
enabled yes

no If boot address is out of Protection level2

yes yes
memory range or in ICP enabled
Jump to AXIM-Flash
Continue Bootloader
base address 0x0800
execution
0000 no
no
Continue Bootloader
execution
If boot address is in
RAM memory (SRAM1, yes
SRAM2, DTCM RAM)

no

If the code in boot

address is valid(2)
yes

If boot address is in
yes
Bank2

Set Bank Swap to

Bank2

no
Jump to address
defined by
BOOT_ADDx
If boot address is in
no yes
Bank1
Set Bank Swap to
Bank1

no
Jump to address
defined by
BOOT_ADDx

Protection level2
yes
enabled

no

Jump to AXIM-Flash
Continue Bootloader
base address 0x0800
execution
0000

MSv38482V2

1. Only BOOT_ADD0 value is considered whatever the BOOT0 pin state, as described in Known limitation under Table 84.
2. ITCM RAM is not considered valid as stack pointer address for the dual bank boot mechanism.

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Figure 49. Bootloader V9.x selection for STM32F76xxx/77xxx

Bootloader

System Init (Clock, GPIOs,

IWDG, SysTick) yes

Configure USB OTG FS

device yes
Disable all interrupt
yes sources and other
interfaces clocks
Configure I2Cx
Disable all interrupt Disable all interrupt
sources and other sources and other Configure
interfaces clocks interfaces clocks USARTx
Configure SPIx

Execute Execute Execute

BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx
0x7F received on
USARTx
yes
no

I2C Address
Detected HSE detected no no HSE detected

Generate System
no reset
yes yes

Disable all interrupt

Disable other
Synchro mechanism sources and other
interfaces clocks
detected on SPIx interfaces clocks

no Reconfigure System Reconfigure System

no clock to 60 MHz and clock to 60 MHz
USB clock to 48 MHz
Frame detected
on CANx Configure CAN
Execute DFU
bootloader using USB
no interrupts Execute
BL_CAN_Loop for
CANx
USB cable
yes
Detected

MSv38483V2

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38.3 Bootloader version

The following table lists the STM32F76xxx/77xxx devices bootloader V9.x versions.

Table 84. STM32F76xxx/77xxx bootloader V9.x versions

Bootloader
version Description Known limitations
number

When the Flash memory is configured to the dual

bank boot mode (nDBANK=nDBOOT=0),
whatever the BOOT0 Pin state only
BOOT_ADD0 value is considered (when BOOT0
Pin=1, BOOT_ADD0 value is considered not the
BOOT_ADD1).
Workaround: in order to manage dual bank boot
with BOOT_ADD0 only, refer to the AN4826:
"STM32F7 Series Flash memory dual bank
V9.3 Initial bootloader version mode”
At high UART baudrates (115200 bps)
connection may fail due to software jitter leading
to wrong baudrate calculation.
In that case bootloader may respond with a
baudrate up to ± 5% different from host baudrate.
Workaround: use baudrates lower than
57600 bps if host tolerance to baudrate error is
lower than ± 5%

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AN2606 STM32G03xxx/ STM32G04xxx devices bootloader

39 STM32G03xxx/ STM32G04xxx devices bootloader

39.1 Bootloader configuration

The STM32G03xxx/G04xxx bootloader is activated by applying Pattern 11 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 85. STM32G03xxx/G04xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz (using PLL

RCC HSI enabled
clocked by HSI).
4 Kbytes starting from address 0x20000000 are
RAM -
used by the bootloader firmware
Common to all System memory - 8 Kbytes starting from address 0x1FFF0000
bootloaders
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Securable memory The Address to jump to for the securable memory
- -
area area: @0x1FFF1D00
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bit,
USART2 Enabled
even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial baud rate
USARTx bootloader SysTick timer Enabled
from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
Slave 7-bit address: 0b1010001x
I2C1 bootloader
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.

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Table 85. STM32G03xxx/G04xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C2 configuration is:

I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
Slave 7-bit address: 0b1010001x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PB10 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PB11 pin: data line is used in open-drain mode.

Note: On SO8, WLCSP18, TSSOP20 and UFQFN28 packages USART1 PA9/PA10 IOs are
remapped on PA11/PA12.

39.2 Bootloader selection

Figure 50 shows the bootloader selection mechanism.

Figure 50. Bootloader V5.x selection for STM32G03xxx/G04xxx

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure I2Cx

0x7F received on
yes
USARTx
yes
no
Disable all interrupt
Disable all interrupt
sources and other
sources and other
no I2Cx Address
Detected interfaces clock’s interfaces clock’s

Execute Configure
BL_I2C_Loop for USARTx
I2Cx

Execute
BL_USART_Loop
for USARTx

MS52813V1

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39.3 Bootloader version

Table 86 lists the STM32G03xxx/G4xxx devices bootloader versions.

Table 86. STM32G03xx/04xxx bootloader versions

Bootloader version number Description Known limitations

– Supports only 48- and 32-pin

packages
– Issue is seen for both
packages, if PA3 stays to low
V5.1 Initial bootloader version
level, system is stuck in the
USART2 detection sequence
and no other interface is
detected.
Issue is seen for all packages
(except SO8, no PA3 pin), if PA3
Add support to small packages stays to low level, system is
V5.2
8/20 and 28 pins stuck in the USART2 detection
sequence and no other interface
is detected.
V5.3 Fix V5.2 limitations None

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40 STM32G07xxx/08xxx device bootloader

40.1 Bootloader configuration

The STM32G07xxx/G08xxx bootloader is activated by applying Pattern 11 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 87. STM32G07xxx/8xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz (using PLL

RCC HSI enabled
clocked by HSI).
12 Kbytes starting from address 0x20000000 are
RAM -
used by the bootloader firmware

Common to all 28 Kbytes starting from address 0x1FFF0000,

System memory -
bootloaders contain the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
The Address to jump to for the secrable memory
Securable memory
- - area:
area
@0x1FFF6800
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bit,
USART2 Enabled
even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-bit,
USART3 Enabled
even parity and 1 Stop bit
USART3 bootloader
USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
The I2C1 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
Slave 7-bit address: 0b1010001x
I2C1 bootloader
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.

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Table 87. STM32G07xxx/8xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C2 configuration is:

I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
Slave 7-bit address: 0b1010001x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PB10 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PB11 pin: data line is used in open-drain mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in push-pull,
SPI1_MOSI pin Input
pull-down mode.
SPI1 bootloader
PA6 pin: Slave data output line, used in push-pull,
SPI1_MISO pin Output
pull-down mode.
PA5 pin: Slave clock line, used in push-pull, pull-
SPI1_SCK pin Input
down mode.
PA4 pin: slave chip select pin used in push-pull, pull-
up mode. 
SPI1_NSS pin Input
Note: This IO can be tied to GND if the SPI Master
does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PB15 pin: Slave data Input line, used in push-pull,
SPI2_MOSI pin Input
pull-down mode.
SPI2 bootloader
PB14 pin: Slave data output line, used in push-pull,
SPI2_MISO pin Output
pull-down mode.
PB13 pin: Slave clock line, used in push-pull, pull-
SPI2_SCK pin Input
down mode.
PB12 pin: slave chip select pin used in push-pull,
pull-up. 
SPI2_NSS pin Input
Note: This IO can be tied to GND if the SPI master
does not use it.

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40.2 Bootloader selection

Figure 51 shows the bootloader selection mechanism.

Figure 51. Bootloader V11.0 selection for STM32G07xxx/G08xxx

Bootloader

Disable all interrupt sources

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure I2Cx
yes

Configure SPIx
yes

0x7F received
on USARTx yes
Disable all other
no interfaces clocks

I2C Address Disable all other Disable all other

Detected Configure
interfaces clocks interfaces clocks USARTx

no
Execute Execute Execute
BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
no for SPIx for I2Cx for USARTx
Synchro mechanism
detected on SPIx

MS51450V1

40.3 Bootloader version

Table 88 lists the STM32G07xxx/8xxx devices bootloader versions.

Table 88. STM32G07xx/08xxx bootloader versions

Bootloader version number Description Known limitations

Not supporting packages

V11.0 Initial bootloader version
smaller then LQFP64
V11.1 Supporting all packages None
Add securable memory area
V11.2 None
feature

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41 STM32G431xx/441xx devices bootloader

41.1 Bootloader configuration

The STM32G431xx/441xx bootloader is activated by applying Pattern 15 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 89. STM32G431xx/441xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 72 MHz (using the

HSI enabled
PLL clocked by HSI)
RCC The clock recovery system (CRS) is enabled for the
- DFU bootloader to allow USB to be clocked by
HSI48 48 MHz
16 Kbyte starting from address 0x20000000 are
RAM -
Common to all used by the bootloader firmware
bootloaders
28 Kbyte starting from address 0x1FFF0000,
System memory -
contain the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Securable memory The address to jump to the exit securable memory
- -
area area @0x1FFF6800
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bit,
USART2 Enabled
even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-bit,
USART3 Enabled
even parity and 1 Stop bit
USART3 bootloader
USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode

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Table 89. STM32G431xx/441xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C2 configuration is:

I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
Slave 7-bit address: 0b1010100x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PC4 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PA8 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C3 Enabled analog filter ON.
Slave 7-bit address: 0b1010100x
I2C3 bootloader
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PC8 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC9 pin: data line is used in open-drain mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in push-pull, no
SPI1 bootloader SPI1_MOSI pin Input
pull-up no pull-down mode.
PA6 pin: Slave data output line, used in push-pull,
SPI1_MISO pin Output
no pull-up no pull-down mode.
PA5 pin: Slave clock line, used in push-pull no pull-
SPI1_SCK pin Input
up, no pull-up no pull-down mode.
PA4 pin: slave chip select pin used in push-pull, no
SPI1_NSS pin Input
pull-up no pull-down mode.

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Table 89. STM32G431xx/441xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI2 configuration is:

– Slave mode
– Full Duplex
SPI2 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PB15 pin: Slave data Input line, used in push-pull,
SPI2_MOSI pin Input
no pull-up no pull-down mode.
SPI2 bootloader
PB14 pin: Slave data output line, used in push-pull,
SPI2_MISO pin Output
no pull-up no pull-down mode.
PB13 pin: Slave clock line, used in push-pull, no
SPI2_SCK pin Input
pull-up no pull-down mode.
PB12 pin: slave chip select pin used in push-pull, no
pull-up no pull-down mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the SPI Master
does not use it.
USB FS configured in forced device mode.
USB Enabled USB FS interrupt vector is enabled and used for
USB DFU communications.
DFU bootloader
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required

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41.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 52. Bootloader selection for STM32G431xx/441xx

System Reset

Configure System clock to

72 MHz with HSI

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB Device FS

using CRS and HSI48 as
clock source Disable all interrupt
sources and other
interfaces clocks
Configure I2Cx
Disable all interrupt Disable all interrupt
sources and other sources and other Configure
interfaces clocks interfaces clocks USARTx
Configure SPIx
Execute Execute Execute
BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx
0x7F received
on USARTx yes

no

I2C Address
yes
Detected

no

Disable other
Synchro mechanism interfaces clocks
yes
detected on SPIx
Execute DFU
bootloader using USB
no
interrupts
no

USB cable yes

Detected

MS51432V1

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41.3 Bootloader version

Table 90. STM32G431xx/441xx bootloader version
Bootloader
version Description Known limitations
number

V13.3 Initial bootloader version None

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42 STM32G47xxx/48xxx devices bootloader

42.1 Bootloader configuration

The STM32G47xxx/48xxx bootloader is activated by applying Pattern 14 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 91. STM32G47xxx/48xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 72 MHz (using the

HSI enabled
PLL clocked by HSI)
RCC The clock recovery system (CRS) is enabled for the
- DFU bootloader to allow USB to be clocked by
HSI48 48 MHz
16 Kbyte starting from address 0x20000000 are
RAM -
Common to all used by the bootloader firmware
bootloaders
28 Kbyte starting from address 0x1FFF0000,
System memory -
contain the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Securable memory The address to jump to the exit securable memory
- -
area area @0x1FFF6800
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bit,
USART2 Enabled
even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-bit,
USART3 Enabled
even parity and 1 Stop bit
USART3 bootloader
USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode

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Table 91. STM32G47xxx/48xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C2 configuration is:

I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
Slave 7-bit address: 0b1010011x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PC4 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PA8 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C3 Enabled analog filter ON.
Slave 7-bit address: 0b1010011x
I2C3 bootloader
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PC8 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC9 pin: data line is used in open-drain mode.
The I2C4 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C4 Enabled analog filter ON.
Slave 7-bit address: 0b1010011x
I2C4 bootloader
(where x = 0 for write and x = 1 for read)
I2C4_SCL pin Input/Output PC6 pin: clock line is used in open-drain mode.
I2C4_SDA pin Input/Output PC7 pin: data line is used in open-drain mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in push-pull, no
SPI1 bootloader SPI1_MOSI pin Input
pull-up no pull-down mode.
PA6 pin: Slave data output line, used in push-pull,
SPI1_MISO pin Output
no pull-up no pull-down mode.
PA5 pin: Slave clock line, used in push-pull no pull-
SPI1_SCK pin Input
up, no pull-up no pull-down mode.
PA4 pin: slave chip select pin used in push-pull, no
SPI1_NSS pin Input
pull-up no pull-down mode.

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Table 91. STM32G47xxx/48xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI2 configuration is:

– Slave mode
– Full Duplex
SPI2 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PB15 pin: Slave data Input line, used in push-pull,
SPI2_MOSI pin Input
no pull-up no pull-down mode.
SPI2 bootloader
PB14 pin: Slave data output line, used in push-pull,
SPI2_MISO pin Output
no pull-up no pull-down mode.
PB13 pin: Slave clock line, used in push-pull, no
SPI2_SCK pin Input
pull-up no pull-down mode.
PB12 pin: slave chip select pin used in push-pull, no
pull-up no pull-down mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the SPI Master
does not use it.
USB FS configured in forced device mode.
USB FS interrupt vector is enabled and used for
USB Enabled USB DFU communications.
Note: VDDUSB IO must be connected to 3.3 V for
DFU bootloader USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required

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42.2 Bootloader selection

The figures below show the bootloader selection mechanism.

Figure 53. Bootloader selection for STM32G47xxx/48xxx

System Reset

Configure System clock to

72 MHz with HSI

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB Device FS

using CRS and HSI48 as
clock source Disable all interrupt
sources and other
interfaces clocks
Configure I2Cx
Disable all interrupt Disable all interrupt
sources and other sources and other Configure
interfaces clocks interfaces clocks USARTx
Configure SPIx
Execute Execute Execute
BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx
0x7F received
on USARTx yes

no

I2C Address
yes
Detected

no

Disable other
Synchro mechanism interfaces clocks
yes
detected on SPIx
Execute DFU
bootloader using USB
no
interrupts
no

USB cable yes

Detected

MS51432V1

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Figure 54. Dual bank boot implementation for STM32G47xxx/48xxx bootloader V13.x

System Reset

If Boot from
FLASH
no

yes

If Value of first Protection level2 no

address of Bank2 is yes enabled
within int. SRAM
address
Set Bank Swap to
Bank2 yes
no
Continue Bootloader executio
Jump to user code
in Bank2 If Value of first
If Value of first address of Bank2 is
within int. SRAM yes
address of Bank1 is
within int. SRAM address
address
yes
no
no
Set Bank Swap to Set Bank Swap to
Bank1 Bank2
Protection
level2 enabled yes
Jump to user code Jump to user code
in Bank1 in Bank2
Set Bank Swap to
no Bank1

Continue Bootloader Jump to user code

execution in Bank1
MS52833V1

42.3 Bootloader version

Table 92. STM32G47xxx/48xxx bootloader version
Bootloader
Description Known limitations
version number

V13.3 (0xD3) Initial bootloader version Boot from bank2 is not working
V13.4 (0xD4) Fix V13.3 limitations None

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43 STM32H72xxx/73xxx devices bootloader

43.1 Bootloader configuration

The STM32H72xxx/73xxx bootloader is activated by applying Pattern 10 (described in
Table 2: Bootloader activation patterns). Table 93 shows the hardware resources used by
this bootloader.

Table 93. STM32H72xxx/73xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 66 MHz (using PLL

HSI enabled
clocked by the HSI)
The clock recovery system (CRS) is enabled for the
RCC
- DFU bootloader to allow USB to be clocked by
HSI48 48 MHz
- 20 MHz derived from the PLLQ is used for FDCAN
16 Kbyte starting from address 0x24000000 are
RAM -
Common to all used by the bootloader firmware
bootloaders
84 Kbyte starting from address 0x1FFF9800 contain
System memory -
the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Power - Voltage range is set to Voltage Range 3.
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bit,
USART2 Enabled
even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-bit,
USART3 Enabled
even parity and 1 Stop bit
USART3 bootloader
(on PB10/PB11) USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration is: 8-bit,
USART3 Enabled
even parity and 1 Stop bit
USART3 bootloader
(on PD8/PD9) USART3_RX pin Input PD9 pin: USART3 in reception mode
USART3_TX pin Output PD8 pin: USART3 in transmission mode

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Table 93. STM32H72xxx/73xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C1 configuration is:

I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
Slave 7-bit address: 0b1010111x
I2C1 bootloader
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB9 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
Slave 7-bit address: 0b1010111x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PF1 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PF0 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C3 Enabled analog filter ON.
Slave 7-bit address: 0b1010111x
I2C3 bootloader
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PA8 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC9 pin: data line is used in open-drain mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in push-pull
SPI1 bootloader SPI1_MOSI pin Input
pull-down mode.
PA6 pin: Slave data output line, used in push-pull
SPI1_MISO pin Output
pull-down mode.
PA5 pin: Slave clock line, used in push-pull pull-
SPI1_SCK pin Input
down mode.
PA4 pin: slave chip select pin used in push-pull pull-
SPI1_NSS pin Input
down mode.

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Table 93. STM32H72xxx/73xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI3 configuration is:

– Slave mode
– Full Duplex
SPI3 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PC12 pin: Slave data Input line, used in push-pull
SPI3 bootloader SPI3_MOSI pin Input
pull down mode
PC11 pin: Slave data output line, used in push-pull
SPI3_MISO pin Output
pull down mode.
PC10 pin: Slave clock line, used in push-pull pull
SPI3_SCK pin Input
down mode.
PA15 pin: slave chip select pin used in push-pull,
SPI3_NSS pin Input
pull-down mode.
USB FS configured in forced device mode.
USB Enabled USB FS interrupt vector is enabled and used for
USB DFU communications.
DFU bootloader
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required
Once initialized the FDCAN1 configuration is: 
bit-rate 0.5 Mbps
FrameFormat = FDCAN_FRAME_FD_BRS
FDCAN1 Enabled Mode = FDCAN_MODE_NORMAL
FDCAN bootloader AutoRetransmission = ENABLE
(on PH13/PH14) TransmitPause = DISABLE
ProtocolException = ENABLE
FDCAN1_Rx pin Input PH14 pin: FDCAN1 in reception mode
FDCAN1_Tx pin Output PH13 pin: FDCAN1 in transmission mode
Once initialized the FDCAN1 configuration is: 
bit-rate 0.5 Mbps
FrameFormat = FDCAN_FRAME_FD_BRS
FDCAN1 Enabled Mode = FDCAN_MODE_NORMAL
FDCAN bootloader AutoRetransmission = ENABLE
(onPD1/PD0) TransmitPause = DISABLE
ProtocolException = ENABLE
FDCAN1_Rx pin Input PD0 pin: FDCAN1 in reception mode
FDCAN1_Tx pin Output PD1 pin: FDCAN1 in transmission mode

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43.2 Bootloader selection

Figure 55 shows the bootloader selection mechanism.

Figure 55. Bootloader V9.0 selection for STM32H72xxx/73xxx

System Reset

Configure System clock to

66 MHz with HSI

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure
USB OTG FS Device

Configure I2Cx

Configure SPIx Disable all interrupt

Exexute
sources and other
BL_FDCAN loop
interfaces clocks

Disable all interrupt Disable all interrupt

FD-CAN frame Configure
yes sources and other sources and other
detected USARTx
interfaces clocks interfaces clocks
no
Execute Execute Execute
BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
0x7F received
yes for SPIx for I2Cx for USARTx
on USARTx

no

I2Cx address
yes
detected

no

SPIx detects
Synchro yes
mechanism
no

no

USB cable Execute DFU

yes bootloader using
detected
USB interrupts

MS54027V1

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43.3 Bootloader version

Table 96 lists the STM32H72xxx/73xxx devices bootloader versions.

Table 94. STM32H72xxx/73xxx bootloader version

Bootloader
version Description Known limitations
number

– TCM_AXI OB cannot be modified using all BL interfaces

V9.1 Initial bootloader version – String returned describing the memory size when using
USB is wrong
Fix all issues of previous
V9.2 None
release

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44 STM32H74xxx/75xxx devices bootloader

44.1 Bootloader configuration

The STM32H74xxx/75xxx bootloader is activated by applying Pattern 10 (described in
Table 2: Bootloader activation patterns). Table 95 shows the hardware resources used by
this bootloader.

Table 95. STM32H74xxx/75xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 64 MHz using the

HSI.
HSI enabled The HSI clock source is used at startup (interface
detection phase) and when USART or SPI or I2C
interface is selected.
RCC
The clock recovery system (CRS) is enabled for the
- DFU bootloader to allow USB to be clocked by
HSI48 48 MHz
Clock used for the FDCAN is fixed to 20 MHz and is
-
derived from PLLQ
Common to all
16 Kbyte starting from address 0x20000000, and
bootloaders
RAM - 208 Kbyte starting from address 0x24000000 are
used by the bootloader firmware
122 Kbyte starting from address 0x1FFF0000,
System memory -
contain the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Power - Voltage range is set to Voltage Range 3.
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
even parity and 1 Stop bit
USART1 bootloader
(on PA9/PA10) USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
even parity and 1 Stop bit
USART1 bootloader
(on PB14/PB15) USART1_RX pin Input PB15 pin: USART1 in reception mode
USART1_TX pin Output PB14 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bit,
USART2 Enabled
even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode

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Table 95. STM32H74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART3 configuration is: 8-bit,

USART3 Enabled
even parity and 1 Stop bit
USART3 bootloader
USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave
I2C1 Enabled mode, analog filter ON.
Slave 7-bit address: 0b1001110x
I2C1 bootloader
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB9 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave
I2C2 Enabled mode, analog filter ON.
Slave 7-bit address: 0b1001110x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PF1 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PF0 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave
I2C3 Enabled mode, analog filter ON.
Slave 7-bit address: 0b1001110x
I2C3 bootloader
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PA8 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC9 pin: data line is used in open-drain mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in push-pull, no
SPI1 bootloader SPI1_MOSI pin Input
pull-up no pull-down mode.
PA6 pin: Slave data output line, used in push-pull,
SPI1_MISO pin Output
no pull-up no pull-down mode.
PA5 pin: Slave clock line, used in push-pull no pull-
SPI1_SCK pin Input
up, no pull-up no pull-down mode.
PA4 pin: slave chip select pin used in push-pull, no
SPI1_NSS pin Input
pull-up no pull-down mode.

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Table 95. STM32H74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI2 configuration is:

– Slave mode
– Full Duplex
SPI2 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PI3 pin: Slave data Input line, used in push-pull, no
SPI2 bootloader SPI2_MOSI pin Input
pull-up no pull-down mode.
PI2 pin: Slave data output line, used in push-pull, no
SPI2_MISO pin Output
pull-up no pull-down mode.
PI1 pin: Slave clock line, used in push-pull, no pull-
SPI2_SCK pin Input
up no pull-down mode.
PI0 pin: slave chip select pin used in push-pull, no
SPI2_NSS pin Input
pull-up no pull-down mode.
The SPI3 configuration is:
– Slave mode
– Full Duplex
SPI3 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PC12 pin: Slave data Input line, used in push-pull,
SPI3 bootloader SPI3_MOSI pin Input
no pull-up no-pull down mode
PC11 pin: Slave data output line, used in push-pull,
SPI3_MISO pin Output
no pull-up no-pull down mode.
PC10 pin: Slave clock line, used in push-pull, no
SPI3_SCK pin Input
pull-up no-pull down mode.
PA15 pin: slave chip select pin used in push-pull, no
SPI3_NSS pin Input
pull-up no pull-down mode.
The SPI4 configuration is:
– Slave mode
– Full Duplex
SPI4 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PE14 pin: Slave data Input line, used in push-pull,
SPI4 bootloader SPI4_MOSI pin Input
no pull-up no pull-down mode.
PE13 pin: Slave data output line, used in push-pull,
SPI4_MISO pin Output
no pull-up no pull-down mode.
PE12 pin: Slave clock line, used in push-pull, no
SPI4_SCK pin Input
pull-up no pull-down mode.
PE11 pin: slave chip select pin used in push-pull, no
SPI4_NSS pin Input
pull-up no pull-down mode.

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Table 95. STM32H74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB FS configured in forced device mode.

USB Enabled USB FS interrupt vector is enabled and used for
USB DFU communications.
DFU bootloader
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required
Once initialized the FDCAN1 configuration is: 
bit-rate 0.5 Mbps
FrameFormat = FDCAN_FRAME_FD_BRS
FDCAN1 Enabled Mode = FDCAN_MODE_NORMAL
AutoRetransmission = ENABLE
FDCAN bootloader
TransmitPause = DISABLE
ProtocolException = ENABLE
FDCAN1_Rx pin Input PH14 pin: FDCAN1 in reception mode
FDCAN1_Tx pin Output PH13 pin: FDCAN1 in transmission mode

Note: To connect to the bootloader USART1 using PB14/PB15 pins, user must send two
synchronization bytes.
DFU mode does not support USBREGEN mode. If STM32 is powered by 1.8 V source, it is
not possible to use the BL DFU unless 3.3 V is provided

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44.2 Bootloader selection

Figure 56 shows the bootloader selection mechanism.

Figure 56. Bootloader V9.x selection for STM32H74xxx/75xxx

System Reset

Configure System clock to

64 MHz with HSI

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure
USB OTG FS Device

Configure I2Cx

Configure SPIx Disable all interrupt

Exexute
sources and other
BL_FDCAN loop
interfaces clocks

Disable all interrupt Disable all interrupt

FD-CAN frame Configure
yes sources and other sources and other
detected USARTx
interfaces clocks interfaces clocks
no
Execute Execute Execute
BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
0x7F received
yes for SPIx for I2Cx for USARTx
on USARTx

no

I2Cx address
yes
detected

no

SPIx detects
Synchro yes
mechanism
no

no

USB cable Execute DFU

yes bootloader using
detected
USB interrupts

MSv45966V3

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44.3 Bootloader version

Table 96 lists the STM32H74xxx/75xxx devices bootloader versions.

Table 96. STM32H74xxx/75xxx bootloader version

Bootloader
version Description Known limitations
number

– “Go” Command is not working

– USART2 connection is not working
V13.2
Initial bootloader version – SPI1 connection is not working
(0xD2)
– Mass erase is not working well on I2C (only Bank2
is erased in this command)
– Switch USB clock input from
V13.3 HSE to HSI48 with CRS – Bank erase is not working on USART/SPI and I2C
(0xD3) – Fix known limitations on the – DFU bootloader mass-erase not working
V13.2
– First ACK not received on “Go” Command when
using USART or SPI
– Limitation on the FDCAN write memory, write of
– Add support of FDCAN data with length > 63 bytes is failing
interface – If PB15 is set to GND, user will not be able to
V9.0 – Fix V13.3 limitations connect to BL interfaces. Only the USB is able to
(0x90) – V9.0 is the latest version in connect as it uses interrupt for detection.
production and replaces PB15 must not be pulled down if USART1 on
V13.2 and V13.3 PB14/PB15 is not used
– Jump issue on some application.
Application stack pointer must be lower than 
(RAM end @ - 16 bytes) to guarantee it is working

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45 STM32H7A3xx/B3xx devices bootloader

45.1 Bootloader configuration

The STM32H7A3xx/7B3xx bootloader is activated by applying Pattern 10 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 97. STM32H7A3xx/7B3xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 64 MHz using the

HSI enabled
HSI.
The clock recovery system (CRS) is enabled for the
RCC - DFU bootloader to allow USB to be clocked by
HSI48 48 MHz
Clock used for the FDCAN is fixed to 20 MHz and is
-
derived from PLLQ
Common to all 16 Kbyte starting from address 0x24000000 are
bootloaders RAM -
used by the bootloader firmware
40 Kbytes starting from address 0x1FFFA000,
System memory -
contain the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bit,
USART2 Enabled
even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-bit,
USART3 Enabled
even parity and 1 Stop bit
USART3 bootloader
on (PB10/PB11) USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration is: 8-bit,
USART3 Enabled
even parity and 1 Stop bit
USART3 bootloader
on (PD8/PD9) USART3_RX pin Input PD9 pin: USART3 in reception mode
USART3_TX pin Output PD8 pin: USART3 in transmission mode

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Table 97. STM32H7A3xx/7B3xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C1 configuration is:

I2C speed: up to 400 kHz, 7-bit address, slave
I2C1 Enabled mode, analog filter ON.
Slave 7-bit address: 0b10101111x
I2C1 bootloader
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB9 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave
I2C2 Enabled mode, analog filter ON.
Slave 7-bit address: 0b10101111x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PF1 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PF0 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave
I2C3 Enabled mode, analog filter ON.
Slave 7-bit address: 0b10101111x
I2C3 bootloader
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PA8 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC9 pin: data line is used in open-drain mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in push-pull, no
SPI1 bootloader SPI1_MOSI pin Input
pull-up no pull-down mode.
PA6 pin: Slave data output line, used in push-pull,
SPI1_MISO pin Output
no pull-up no pull-down mode.
PA5 pin: Slave clock line, used in push-pull no pull-
SPI1_SCK pin Input
up, no pull-up no pull-down mode.
PA4 pin: slave chip select pin used in push-pull, no
SPI1_NSS pin Input
pull-up no pull-down mode.

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Table 97. STM32H7A3xx/7B3xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI2 configuration is:

– Slave mode
– Full Duplex
SPI2 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PB15 pin: Slave data Input line, used in push-pull,
SPI2 bootloader SPI2_MOSI pin Input
no pull-up no pull-down mode.
PB14 pin: Slave data output line, used in push-pull,
SPI2_MISO pin Output
no pull-up no pull-down mode.
PB13 pin: Slave clock line, used in push-pull, no
SPI2_SCK pin Input
pull-up no pull-down mode.
PB12 pin: slave chip select pin used in push-pull, no
SPI2_NSS pin Input
pull-up no pull-down mode.
The SPI3 configuration is:
– Slave mode
– Full Duplex
SPI3 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PC12 pin: Slave data Input line, used in push-pull,
SPI3 bootloader SPI3_MOSI pin Input
no pull-up no-pull down mode
PC11 pin: Slave data output line, used in push-pull,
SPI3_MISO pin Output
no pull-up no-pull down mode.
PC10 pin: Slave clock line, used in push-pull, no
SPI3_SCK pin Input
pull-up no-pull down mode.
PA15 pin: slave chip select pin used in push-pull, no
SPI3_NSS pin Input
pull-up no pull-down mode.
USB FS configured in forced device mode.
USB Enabled USB FS interrupt vector is enabled and used for
USB DFU communications.
DFU bootloader
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required

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Table 97. STM32H7A3xx/7B3xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the FDCAN1 configuration is: bit-

rate 0.5 Mbps
FrameFormat = FDCAN_FRAME_FD_BRS
FDCAN1 Enabled Mode = FDCAN_MODE_NORMAL
FDCAN bootloader AutoRetransmission = ENABLE
on (PH13/PH14) TransmitPause = DISABLE
ProtocolException = ENABLE
FDCAN1_Rx pin Input PH14 pin: FDCAN1 in reception mode
FDCAN1_Tx pin Output PH13 pin: FDCAN1 in transmission mode
Once initialized the FDCAN1 configuration is: bit-
rate 0.5 Mbps
FrameFormat = FDCAN_FRAME_FD_BRS
FDCAN1 Enabled Mode = FDCAN_MODE_NORMAL
FDCAN bootloader AutoRetransmission = ENABLE
on (PD1/PD0) TransmitPause = DISABLE
ProtocolException = ENABLE
FDCAN1_Rx pin Input PD0 pin: FDCAN1 in reception mode
FDCAN1_Tx pin Output PD1 pin: FDCAN1 in transmission mode

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45.2 Bootloader selection

Figure 56 shows the bootloader selection mechanism.

Figure 57. Bootloader V9.x selection for STM32H7A3xx/7B3xx

System Reset

Configure System clock to 64

MHz with HSI

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB OTG FS

Device

Configure I2Cx

Configure SPIx Disable all interrupt

Exexute
sources and other
BL_FDCAN loop
interfaces clocks

Disable all interrupt Disable all interrupt

FD-CAN frame Configure
sources and other sources and other
detected USARTx
interfaces clocks interfaces clocks

Execute Execute Execute

BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
0x7F received
yes for SPIx for I2Cx for USARTx
on USARTx

no

I2Cx Address
yes
Detected

no

SPIx detects
Synchro yes
mechanism
no
Execute DFU
bootloader using
no
USB interrupts

USB cable
Detected

MSv45966V2

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45.3 Bootloader version

Table 96 lists the STM32H7A3xx/7B3xx devices bootloader versions.

Table 98. STM32H7A3xx/7B3xx bootloader version

Bootloader
version Description Known limitations
number

– String returned describing the Flash memory size

Initial bootloader version on when using USB is wrong (expected value 256 x 8 KB,
V9.0
cut 1.1 samples but returns 256 x 2 KB)
– OTP memory is not supported by the bootloader
Release supported only in
cut1.3.
V9.1 None
Fixes all issues of previous
release.

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46 STM32L01xxx/02xxx devices bootloader

46.1 Bootloader configuration

The STM32L01xxx/02xxx bootloader is activated by applying Pattern 6 (described in
Table 2: Bootloader activation patterns). Table 99 shows the hardware resources used by
this bootloader.

Table 99. STM32L01xxx/02xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 32 MHz with HSI 16

RCC HSI enabled
MHz as clock source.
2 Kbyte starting from address 0x20000000 are used
RAM -
by the bootloader firmware

Common to all 4 Kbyte starting from address 0x1FF00000, contain

System memory -
bootloaders the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
even parity and 1 Stop bit
USART1 bootloader
(on PA9/PA10) USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bit,
USART2 Enabled
even parity and 1 Stop bit
USART2 bootloader
(on PA2/PA3) USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial baud rate
USART2 bootloader SysTick timer Enabled
from the host for USARTx bootloaders.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed up to 8
SPI1 Enabled
MHz, Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in push-pull
SPI1_MOSI pin Input
pull-down mode
SPI1 bootloader (for
PA6 pin: Slave data output line, used in push-pull
all device packages SPI1_MISO pin Output
pull-down mode
except TSSOP14)
PA5 pin: Slave clock line, used in push-pull pull-
SPI1_SCK pin Input
down mode
PA4 pin: slave chip select pin used in push-pull pull-
up mode.
SPI1_NSS pin Input
Note: This IO can be tied to GND if the SPI Master
does not use it.

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Table 99. STM32L01xxx/02xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed up to
SPI1 Enabled
8 MHz, Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in push-pull
SPI1_MOSI pin Input
pull-down mode
PA14 pin: Slave data output line, used in push-pull
pull-down mode.
SPI1 bootloader Note: This IO is also used as SWCLK for debug
SPI1_MISO pin Output
(only for devices on interface, as a consequence debugger cannot
TSSOP14 package) connect to the device in "on-the-fly" mode when the
bootloader is running.
PA13 pin: Slave clock line, used in push-pull pull-
SPI1_SCK pin Input
down mode
PA4 pin: slave chip select pin used in push-pull pull-
up mode.
SPI1_NSS pin Input Note: NSS pin synchronization is required on
bootloader with SPI1 interface for devices on
TSSOP14 package.

The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.
Note: Due to empty check mechanism present on this product, it is not possible to jump from user
code to system bootloader. Such jump results in a jump back to user Flash memory space.
But if the first 4 bytes of user lash memory (at 0x0800 0000) are empty at the moment of the
jump (i.e. erase first sector before jump or execute code from SRAM while Flash is empty),
then system bootloader is executed when jumped to.

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46.2 Bootloader selection

The Table 58 shows the bootloader selection mechanism.

Figure 58. Bootloader selection for STM32L01xxx/02xxx

System Reset

Disable all
interrupt sources

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure SPIx

0x7F received
yes
on USARTx

Disable all other

yes interfaces clocks
no

Disable all other Configure

interfaces clocks USARTx
SPIx detects
no Synchro
mechanism Execute Execute
BL_SPI_Loop BL_USART_Loop
for SPIx for USARTx

MSv38476V1

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46.3 Bootloader version

The following table lists the STM32L01xxx/02xxx devices bootloader versions.

Table 100. STM32L01xxx/02xxx bootloader versions

Bootloader
version Description Known limitations
number

Bootloader not functional with SPI1 interface for

V12.2 Initial bootloader version
devices on TSSOP14 package.
For the SPI1 interface for devices in TSSOP14, a
This bootloader is an updated falling edge on NSS pin is required before staring
version of bootloader V12.2. communication, to properly synchronize the SPI
V12.3 This new version add support interface. If the NSS pin is grounded (all time from
of SPI interface for devices on device reset) the SPI communication is not
TSSOP14 package. synchronized and bootloader does not work
properly with the SPI interface.

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47 STM32L031xx/041xx devices bootloader

47.1 Bootloader configuration

The STM32L031xx/041xx bootloader is activated by applying Pattern 2 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 101. STM32L031xx/041xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 32 MHz with HSI 16

RCC HSI enabled
MHz as clock source.
4 Kbyte starting from address 0x20000000 are
RAM -
used by the bootloader firmware

Common to all 4 Kbyte starting from address 0x1FF00000, contain

System memory -
bootloaders the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Once initialized the USART2 configuration is: 8-bit,
USART2 Enabled
even parity and 1 Stop bit
USART2 bootloader
(on PA9/PA10) USART2_RX pin Input PA10 pin: USART2 in reception mode
USART2_TX pin Output PA9 pin: USART2 in transmission mode
Once initialized the USART2 configuration is: 8-bit,
USART2 Enabled
even parity and 1 Stop bit
USART2 bootloader
(on PA2/PA3) USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial baud rate
USART2 bootloader SysTick timer Enabled
from the host for USARTx bootloaders.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed up to
SPI1 Enabled
8 MHz, Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in push-pull
SPI1_MOSI pin Input
pull-down mode
PA6 pin: Slave data output line, used in push-pull
SPI1 bootloader SPI1_MISO pin Output
pull-down mode
PA5 pin: Slave clock line, used in push-pull pull-
SPI1_SCK pin Input
down mode
PA4 pin: slave chip select pin used in push-pull pull-
up mode.
SPI1_NSS pin Input
Note: This IO can be tied to GND if the SPI Master
does not use it.

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The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.
The bootloader Read/Write commands do not support SRAM space for this product.

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47.2 Bootloader selection

Figure 59 shows the bootloader selection mechanism.

Figure 59. Bootloader selection for STM32L031xx/041xx

System Reset

Disable all
interrupt sources

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure SPIx

0x7F received on
yes
USARTx
Disable all other
interfaces clocks

no
yes Configure
Disable all other USARTx
interfaces clocks
SPIx detects
no Execute
Synchro
BL_USART_Loop
mechanism Execute for USARTx
BL_SPI_Loop for
SPIx
MS35035V1

47.3 Bootloader version

Table 102 lists the STM32L031xx/041xx devices bootloader versions.

Table 102. STM32L031xx/041xx bootloader versions

Bootloader version number Description Known limitations

V12.0 Initial bootloader version None

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AN2606 STM32L05xxx/06xxx devices bootloader

48 STM32L05xxx/06xxx devices bootloader

48.1 Bootloader configuration

The STM32L05xxx/06xxx bootloader is activated by applying Pattern 1 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 103. STM32L05xxx/06xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 32 MHz with

RCC HSI enabled
HSI 16 MHz as clock source.
Power - Voltage range is set to Voltage Range 1.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
Common to all 4 Kbyte starting from address 0x1FF00000,
System memory -
bootloaders contain the bootloader firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.

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Table 103. STM32L05xxx/06xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in push-
SPI1_NSS pin Input
pull pull-down mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
push-pull pull-down mode
SPI2 bootloader
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PB13 pin: Slave clock line, used in push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
SPI2_NSS pin Input
push-pull pull-down mode.

The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.

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48.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 60. Bootloader selection for STM32L05xxx/06xxx

System Reset

Disable all
interrupt sources

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure SPIx

0x7F received on
yes
USARTx
Disable all other
interfaces clocks

no
yes Configure
Disable all other USARTx
interfaces clocks
SPIx detects
no Execute
Synchro
BL_USART_Loop
mechanism Execute for USARTx
BL_SPI_Loop for
SPIx
MS35035V1

48.3 Bootloader version

The following table lists the STM32L05xxx/06xxx devices bootloader versions:

Table 104. STM32L05xxx/06xxx bootloader versions

Bootloader
version Description Known limitations
number

V12.0 Initial bootloader version None

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49 STM32L07xxx/08xxx devices bootloader

Two bootloader versions are available on STM32L07xxx/08xxx devices:

 V4.x supporting USART1, USART2 and DFU (USB FS Device).
This version is embedded in STM32L072xx/73xx and STM32L082xx/83xx devices.
 V11.x supporting USART1, USART2, I2C1, I2C2, SPI1 and SPI2.
This version is embedded in other STM32L071xx/081xx devices.

49.1 Bootloader V4.x

49.1.1 Bootloader configuration

The STM32L07xxx/08xxx bootloader is activated by applying Pattern 2 or Pattern 7 when
dual bank boot feature is available (described in Table 2: Bootloader activation patterns).
Table 105 shows the hardware resources used by this bootloader.

Table 105. STM32L07xxx/08xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 32 MHz with

RCC HSI enabled
HSI 16 MHz as clock source.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address 0x1FF00000,
Common to all System memory -
contain the bootloader firmware.
bootloaders
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bit, even parity and 1 Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART2 in reception mode
USART1_TX pin Output PA9 pin: USART2 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bit, even parity and 1 Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.

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Table 105. STM32L07xxx/08xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB FS configured in forced device mode.

USB Enabled USB FS interrupt vector is enabled and
used for USB DFU communications.
DFU bootloader USB_DM pin PA11 pin: USB FS DM line
Input/Output PA12 pin: USB FS DP line.
USB_DP pin
No external pull-up resistor is required.

The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.

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49.1.2 Bootloader selection

Figure 61 and Figure 62 show the bootloader selection mechanism.

Figure 61. Dual bank boot implementation for STM32L07xxx/08xxx bootloader V4.x

System Reset

If Boot0 = 0 no

yes

If Value of first
address of Bank2 is Protection
within int. SRAM
yes no
level2 enabled
address
Set Bank Swap to
Bank2
Continue Bootloader
no Jump to user yes
execution
code in Bank2

If Value of first If Value of first

address of Bank1 is address of Bank2 is
within int. SRAM within int. SRAM
address address
yes yes

no

no
Protection
level2 enabled
yes

Set Bank Swap to Set Bank Swap to Set Bank Swap to

no Bank1 Bank1 Bank2

Continue Bootloader
Jump to user Jump to user Jump to user
execution
code in Bank1 code in Bank1 code in Bank2

MSv38477V1

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Figure 62. Bootloader V4.x selection for STM32L07xxx/08xxx

Bootloader

Configure System clock

to 32 MHz with HSI

Configure USB clock to 48

MHz with HSI as clock source

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB FS device

0x7F received on
yes
USARTx
Disable all
interrupt sources
no
Configure
USARTx
USB cable
yes
Detected
no Execute
Execute DFU bootloader BL_USART_Loop
using USB interrupts for USARTx

MSv38442V1

49.1.3 Bootloader version

Table 106 lists the STM32L07xxx/08xxx devices bootloader versions.

Table 106. STM32L07xxx/08xxx bootloader versions

Bootloader version number Description Known limitations

V4.0 Initial bootloader version None

This bootloader is an updated
version of bootloader V4.0. This
V4.1 None
new version implements the
Dual Bank Boot feature.

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49.2 Bootloader V11.x

49.2.1 Bootloader configuration

The STM32L07xxx/08xxx bootloader is activated by applying Pattern 2 or Pattern 7 when
dual bank boot feature is available (see in Table 2: Bootloader activation patterns).
Table 107 shows the hardware resources used by this bootloader.

Table 107. STM32L07xxx/08xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 32 MHz

RCC HSI enabled
with HSI 16 MHz as clock source.
5 Kbyte starting from address
RAM - 0x20000000 are used by the bootloader
firmware
8 Kbyte starting from address
Common to all bootloaders System memory - 0x1FF00000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized the USART1
USART1 Enabled configuration is: 8-bit, even parity and 1
Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART2 in reception mode
USART1_TX pin Output PA9 pin: USART2 in transmission mode
Once initialized the USART2
USART2 Enabled configuration is: 8-bit, even parity and 1
Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial
USARTx bootloaders SysTick timer Enabled baud rate from the host for USARTx
bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000010x
I2C1 bootloader (where x = 0 for write and x = 1 for read)
PB6 pin: I2C1 clock line is used in open-
I2C1_SCL pin Input/Output
drain mode.
PB7 pin: I2C1 data line is used in open-
I2C1_SDA pin Input/Output
drain mode.

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Table 107. STM32L07xxx/08xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C2 configuration is:

I2C speed: up to 400 kHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000010x
I2C2 bootloader (where x = 0 for write and x = 1 for read)
PB10 pin: I2C2 clock line is used in
I2C2_SCL pin Input/Output
open-drain mode.
PB11 pin: I2C2 data line is used in
I2C2_SDA pin Input/Output
open-drain mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI1 Enabled
Speed up to 8 MHz, Polarity: CPOL
Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
push-pull pull-down mode
PA6 pin: Slave data output line, used in
SPI1 bootloader SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-
SPI1_SCK pin Input
pull pull-down mode
PA4 pin: slave chip select pin used in
push-pull pull-up mode.
SPI1_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI2 Enabled
Speed up to 8 MHz, Polarity: CPOL
Low, CPHA Low, NSS hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
push-pull pull-down mode
PB14 pin: Slave data output line, used
SPI2 bootloader SPI2_MISO pin Output
in push-pull pull-down mode
PB13 pin: Slave clock line, used in
SPI2_SCK pin Input
push-pull pull-down mode
PB12 pin: slave chip select pin used in
push-pull pull-up mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.

The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.

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49.2.2 Bootloader selection

Figure 63 and Figure 64 show the bootloader selection mechanism.

Figure 63. Dual bank boot implementation for STM32L07xxx/08xxx bootloader V11.x

System Reset

If Boot0 = 0 no

yes

If Value of first
address of Bank2 is Protection
within int. SRAM
yes no
level2 enabled
address
Set Bank Swap to
Bank2
Continue Bootloader
no Jump to user yes
execution
code in Bank2

If Value of first If Value of first

address of Bank1 is address of Bank2 is
within int. SRAM within int. SRAM
address address
yes yes

no

no
Protection
level2 enabled
yes

Set Bank Swap to Set Bank Swap to Set Bank Swap to

no Bank1 Bank1 Bank2

Continue Bootloader
Jump to user Jump to user Jump to user
execution
code in Bank1 code in Bank1 code in Bank2

MSv38477V1

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Figure 64. Bootloader V11.x selection for STM32L07xxx/08xxx

Bootloader

Disable all
interrupt sources

System Init ( Clock, GPIOs,

IWDG, SysTick)

Configure I2Cx

Configure SPIx

0x7F received
yes
on USARTx

no

I2Cx Address
yes
detected

no
yes Disable all other
no interfaces clocks

Disable all other Disable all other Configure

interfaces clocks interfaces clocks USARTx
SPIx detects
Synchro
mechanism
Execute Execute Execute
BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx

MSv38443V2

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49.2.3 Bootloader version

The following table lists the STM32L07xxx/08xxx devices bootloader versions:

Table 108. STM32L07xxx/08xxx bootloader V11.x versions

Bootloader version number Description Known limitations

V11.1 Initial bootloader version None

This bootloader is an updated
version of bootloader V11.1.
V11.2 None
This new version implements
the Dual Bank Boot feature.

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AN2606 STM32L1xxx6(8/B)A devices bootloader

50 STM32L1xxx6(8/B)A devices bootloader

50.1 Bootloader configuration

The STM32L1xxx6(8/B)A bootloader is activated by applying Pattern 1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 109. STM32L1xxx6(8/B)A configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

RCC HSI enabled The system clock frequency is 16 MHz.

2 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
4 Kbyte starting from address 0x1FF00000
System memory -
contain the bootloader firmware.
Common to all
The independent watchdog (IWDG)
bootloaders
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Power - Voltage range is set to Voltage Range 1.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

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50.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 65. Bootloader selection for STM32L1xxx6(8/B)A devices

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

0x7F received on
USARTx

no yes

Disable all
interrupt sources

Configure
USARTx

Execute
BL_USART_Loop
for USARTx

MS35033V1

50.3 Bootloader version

The following table lists the STM32L1xxx6(8/B)A devices bootloader versions:

Table 110. STM32L1xxx6(8/B)A bootloader versions

Bootloader
version Description Known limitations
number

When a Read Memory command or Write Memory

command is issued with an unsupported memory
address and a correct address checksum (i.e. address
0x6000 0000), the command is aborted by the bootloader
V2.0 Initial bootloader version
device, but the NACK (0x1F) is not sent to the host. As a
result, the next 2 bytes (which are the number of bytes to
be read/written and its checksum) are considered as a
new command and its checksum.(1)
1. If the “number of data - 1” (N-1) to be read/written is not equal to a valid command code, then the limitation
is not perceived from the host since the command is NACKed anyway (as an unsupported new command).

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51 STM32L1xxx6(8/B) devices bootloader

51.1 Bootloader configuration

The STM32L1xxx6(8/B) bootloader is activated by applying Pattern 1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 111. STM32L1xxx6(8/B) configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

RCC HSI enabled The system clock frequency is 16 MHz.

2 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
4 Kbyte starting from address 0x1FF00000
System memory -
contain the bootloader firmware.
Common to all
The independent watchdog (IWDG)
bootloaders
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Power - Voltage range is set to Voltage Range 1.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

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51.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 66. Bootloader selection for STM32L1xxx6(8/B) devices

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

0x7F received on
USARTx

no yes

Disable all
interrupt sources

Configure
USARTx

Execute
BL_USART_Loop
for USARTx

MS35007V1

51.3 Bootloader version

The following table lists the STM32L1xxx6(8/B) devices bootloader versions:

Table 112. STM32L1xxx6(8/B) bootloader versions

Bootloader
version Description Known limitations
number

When a Read Memory command or Write Memory

command is issued with an unsupported memory
address and a correct address checksum (i.e. address
0x6000 0000), the command is aborted by the bootloader
V2.0 Initial bootloader version
device, but the NACK (0x1F) is not sent to the host. As a
result, the next 2 bytes (which are the number of bytes to
be read/written and its checksum) are considered as a
new command and its checksum.(1)
1. If the “number of data - 1” (N-1) to be read/written is not equal to a valid command code, then the limitation
is not perceived from the host since the command is NACKed anyway (as an unsupported new command).

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52 STM32L1xxxC devices bootloader

52.1 Bootloader configuration

The STM32L1xxxC bootloader is activated by applying Pattern 1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 113. STM32L1xxxC configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 16 MHz

using the HSI. This is used only for
USARTx bootloaders and during USB
HSI enabled
detection for DFU bootloader (once the
DFU bootloader is selected, the clock
source is derived from the external crystal).
The external clock is mandatory only for the
DFU bootloader and must be in the
RCC following range: 
HSE enabled [24, 16, 12, 8, 6, 4, 3, 2] MHz.
The PLL is used to generate the USB
48 MHz clock and the 32 MHz clock for the
system clock.
The Clock Security System (CSS) interrupt
Common to all
is enabled for the DFU bootloader. Any
bootloaders -
failure (or removal) of the external clock
generates a system reset.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address 0x1FF00000
System memory -
contains the bootloader firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog resets (in case the
hardware IWDG option was previously
enabled by the user).
Power - Voltage range is set to Voltage Range 1.
Once initialized, the USART1 configuration
USART1 Enabled
is 8 bits, even parity and 1 stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled is 8 bits, even parity and 1 stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode

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Table 113. STM32L1xxxC configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Used to automatically detect the serial baud

USARTx bootloaders SysTick timer Enabled rate from the host for the USARTx
bootloader.
USB Enabled USB used in FS mode
DFU bootloader USB_DM pin PA11: USB DM line.
Input/Output
USB_DP pin PA12: USB DP line

The system clock is derived from the embedded internal high-speed RC for the USARTx
bootloader. This internal clock is also used the for DFU bootloader but only for the selection
phase. An external clock in the range of [24, 16, 12, 8, 6, 4, 3, 2] MHz is required for the
execution of the DFU bootloader after the selection phase.

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52.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 67. Bootloader selection for STM32L1xxxC devices

System Reset

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB

USB cable
yes
Detected

no

HSE = 24, 16, 12, 8,

no
0x7F received on 6, 4, 3, 2 MHz
no USARTx

Generate System
yes yes reset

Reconfigure System
Disable all clock to 32MHz and
interrupt sources USB clock to 48 MHz

Configure
Execute DFU
USARTx
bootloader using USB
interrupts
Execute
BL_USART_Loop
for USARTx

MS35008V1

52.3 Bootloader version

The following table lists the STM32L1xxxC devices bootloader versions.

Table 114. STM32L1xxxC bootloader versions

Bootloader version
Description Known limitations
number

For the USART interface, two consecutive NACKs

Initial bootloader instead of 1 NACK are sent when a Read Memory
V4.0
version or Write Memory command is sent and the RDP
level is active.

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53 STM32L1xxxD devices bootloader

53.1 Bootloader configuration

The STM32L1xxxD bootloader is activated by applying pattern4 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 115. STM32L1xxxD configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 16 MHz

using the HSI. This is used only for
USARTx bootloaders and during USB
HSI enabled
detection for DFU bootloader (once the
DFU bootloader is selected, the clock
source is derived from the external crystal).
The external clock is mandatory only for
DFU bootloader and it must be in the
RCC following range: [24, 16, 12, 8, 6, 4, 3, 2]
HSE enabled MHz.
The PLL is used to generate the USB
48 MHz clock and the 32 MHz clock for the
system clock.
The Clock Security System (CSS) interrupt
Common to all
is enabled for the DFU bootloader. Any
bootloaders -
failure (or removal) of the external clock
generates system reset.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address 0x1FF00000
System memory -
contains the bootloader firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Power - Voltage range is set to Voltage Range 1.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode

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Table 115. STM32L1xxxD configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Used to automatically detect the serial baud

USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.
USB Enabled USB used in FS mode
DFU bootloader USB_DM pin PA11: USB DM line.
Input/Output
USB_DP pin PA12: USB DP line.

The system clock is derived from the embedded internal high-speed RC for USARTx
bootloader. This internal clock is used also for DFU bootloader but only for the selection
phase. An external clock in the range of [24, 16, 12, 8, 6, 4, 3, 2] MHz is required for DFU
bootloader execution after the selection phase.

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53.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 68. Bootloader selection for STM32L1xxxD devices

System Reset

BFB2 bit reset

(BFB2 = 0)

Protection
no yes
level2 enabled
If Value
@0x08030000 is
yes yes
within int. SRAM
address Jump to user code
in Bank2 If Value
no no @0x08030000 is
yes
within int. SRAM
If Value address
@0x08000000 is Jump to user code
yes in Bank2
within int. SRAM
address Jump to user code no
in Bank1
no If Value
@0x08000000 is
Continue Bootloader execution yes
within int. SRAM
address
Jump to user code
Disable all in Bank1
interrupt sources no

CPU blocked
System Init (Clock, GPIOs, (halted)
IWDG, SysTick)

Configure USB
yes

USB cable Generate System

Detected HSE detected no
reset

yes
no yes

Configure Reconfigure System

0x7F received on USARTx clock to 32MHz and
USARTx USB clock to 48 MHz
no
Execute
BL_USART_Loop
for USARTx
Execute DFU
bootloader using USB
interrupts MS35009V2

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53.3 Bootloader version

The following table lists the STM32L1xxxD devices bootloader versions:

Table 116. STM32L1xxxD bootloader versions

Bootloader
version Description Known limitations
number

– In the bootloader code the PA13

(JTMS/SWDIO) I/O output speed is
configured to 400 kHz, as a
consequence some debugger cannot
connect to the device in Serial Wire
mode when the bootloader is running.
V4.1 Initial bootloader version – When the DFU bootloader is selected,
the RTC is reset and thus all RTC
information (such as calendar, alarm)
are lost including backup registers.
Note: When the USART bootloader is
selected there is no change on the RTC
configuration (including backup
registers).
– Stack overflow by 8 bytes when jumping
to Bank1/Bank2 if BFB2=0 or when
Read Protection level is set to 2. 
Workaround: the user code must force in
the startup file the top of stack address
before to jump to the main program. This
can be done in the “Reset_Handler”
routine.
Fix V4.1 limitations (available on Rev.Z – When the Stack of the user code is
V4.2
devices only) placed outside the SRAM (i.e. @
0x2000C000) the bootloader cannot
jump to that user code which is
considered invalid. This might happen
when using compilers which place the
stack at a non-physical address at the
top of the SRAM (i,e. @ 0x2000C000). 
Workaround: place manually the stack at
a physical address.
– For the USART interface, two
Fix V4.2 limitations. consecutive NACKs (instead of 1 NACK)
V4.5 DFU interface robustness enhancements are sent when a Read Memory or Write
(available on Rev.Y devices only). Memory command is sent and the RDP
level is active.

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54 STM32L1xxxE devices bootloader

54.1 Bootloader configuration

The STM32L1xxxE bootloader is activated by applying pattern 4 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 117. STM32L1xxxE configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 16 MHz

using the HSI. This is used only for
USARTx bootloaders and during USB
HSI enabled
detection for DFU bootloader (once the
DFU bootloader is selected, the clock
source is derived from the external crystal).
The external clock is mandatory only for
DFU bootloader and it must be in the
RCC following range: [24, 16, 12, 8, 6, 4, 3, 2]
HSE enabled MHz.
The PLL is used to generate the USB
48 MHz clock and the 32 MHz clock for the
system clock.
The Clock Security System (CSS) interrupt
Common to all
is enabled for the DFU bootloader. Any
bootloaders -
failure (or removal) of the external clock
generates system reset.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address 0x1FF00000
System memory -
contains the bootloader firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Power - Voltage range is set to Voltage Range 1.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode

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Table 117. STM32L1xxxE configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Used to automatically detect the serial baud

USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.
USB Enabled USB used in FS mode
DFU bootloader USB_DM pin PA11: USB DM line.
Input/Output
USB_DP pin PA12: USB DP line.

The system clock is derived from the embedded internal high-speed RC for USARTx
bootloader. This internal clock is used also for DFU bootloader but only for the selection
phase. An external clock in the range of [24, 16, 12, 8, 6, 4, 3, 2] MHz is required for DFU
bootloader execution after the selection phase.

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54.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 69. Bootloader selection for STM32L1xxxE devices

System Reset
no

BFB2 bit reset Protection level2

(BFB2 = 0) enabled

yes yes

If Value
no If Value @0x08040000 is @0x08040000 is within yes
yes
within int. SRAM address int. SRAM address

Jump to user code Jump to user code

no in Bank2 no in Bank2

If Value @0x08000000 is If Value @0x08000000 is

yes yes
within int. SRAM address within int. SRAM address

Jump to user code

in Bank1
no Jump to user code
no
in Bank1
Continue Bootloader execution
CPU blocked
(halted)

Disable all interrupt sources

System Init (Clock, GPIOs, HSE Generate

no
IWDG, SysTick) detected System Reset

Configure USB
Reconfigure System
clock to 32MHz and
USB cable USB clock to 48 MHz
detected
yes

no yes
Execute DFU
bootloader using USB
0x7F received interrupts
Configure USARTx
on USARTx

Execute BL_USART_Loop
no for USARTx

MS35034V3

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54.3 Bootloader version

The following table lists the STM32L1xxxE devices bootloader versions:

Table 118. STM32L1xxxE bootloader versions

Bootloader version
Description Known limitations
number

For the USART interface, two

consecutive NACKs (instead of 1
V4.0 Initial bootloader version NACK) are sent when a Read
Memory or Write Memory command
is sent and the RDP level is active.

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55 STM32L412xx/422xx devices bootloader

55.1 Bootloader configuration

The STM32L412xx/422xx bootloader is activated by applying Pattern 6 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 119. STM32L412xx/422xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source for

HSI enabled system clock configured to 72 MHz and for USART,
I2C, SPI and USB bootloader operation.
RCC
The clock recovery system (CRS) is enabled for the
- DFU bootloader to allow USB to be clocked by
HSI48 48 MHz.
12 Kbyte starting from address 0x20000000 are
RAM -
used by the bootloader firmware

Common to all 28 Kbyte starting from address 0x1FFF0000, contain

System memory -
bootloaders the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
The DFU cannot be used to communicate with
bootloader if the voltage scaling range 2 is selected.
Power -
Bootloader firmware does not configure voltage
scaling range value in PWR_CR1 register.
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bit,
USART2 Enabled
even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-bit,
USART3 Enabled
even parity and 1 Stop bit
USART3
bootloader USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud rate
SysTick timer Enabled
bootloaders from the host for USARTx bootloaders.

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Table 119. STM32L412xx/422xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C1 configuration is:

I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
Slave 7-bit address: 0b1010010x
I2C1 bootloader
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
Slave 7-bit address: 0b1010010x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PB10 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PB11 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C3 Enabled analog filter ON.
Slave 7-bit address: 0b1010010x
I2C3 bootloader
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PC0 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC1 pin: data line is used in open-drain mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in push-pull pull-
SPI1_MOSI pin Input
down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in push-pull
SPI1_MISO pin Output
pull-down mode
PA5 pin: Slave clock line, used in push-pull pull-
SPI1_SCK pin Input
down mode
PA4 pin: slave chip select pin used in push-pull pull-
up mode.
SPI1_NSS pin Input
Note: This IO can be tied to GND if the SPI Master
does not use it.

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Table 119. STM32L412xx/422xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI2 configuration is:

– Slave mode
– Full Duplex
SPI2 Enabled
– 8-bit MSB
– Speed up to 8 MHz
Polarity: CPOL Low, CPHA Low, NSS hardware
PB15 pin: Slave data Input line, used in push-pull
SPI2_MOSI pin Input
pull-down mode
SPI2 bootloader
PB14 pin: Slave data output line, used in push-pull
SPI2_MISO pin Output
pull-down mode
PB13 pin: Slave clock line, used in push-pull pull-
SPI2_SCK pin Input
down mode
PB12 pin: slave chip select pin used in push-pull
pull-up mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the SPI Master
does not use it.
USB FS configured in forced device mode.
USB FS interrupt vector is enabled and used for
USB Enabled USB DFU communications.
Note: VDDUSB IO must be connected to 3.3 V for
DFU bootloader USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required

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55.2 Bootloader selection

The figures below show the bootloader selection mechanism.

Figure 70. Dual bank boot Implementation for STM32L412xx/422xx bootloader V9.x

System Reset

If Boot0 = 0

yes
no

If Value of first
address of Bank2 is
yes
within int. SRAM
address(1)
Protection level2 no
Set Bank Swap to
enabled
Bank2
no

Jump to user code yes Continue Bootloader

If Value of first in Bank2 execution
address of Bank1 is
within int. SRAM
address(1) If Value of first
yes address of Bank2 is
within int. SRAM yes
address(1)
no

Protection level2 no
yes
enabled
Set Bank Swap to Set Bank Swap to Set Bank Swap to
Bank1 Bank1 Bank2
no

Jump to user code Jump to user code Jump to user code

Continue Bootloader
in Bank1 in Bank1 in Bank2
execution

MS35021V1

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Figure 71.Bootloader V13.x selection for STM32L412xx/422xx

System Reset

Configure System clock to

72 MHz with HSI

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB Device FS

using CRS and HSI48 as
clock source Disable all interrupt
sources and other
interfaces clocks
Configure I2Cx
Disable all interrupt Disable all interrupt
sources and other sources and other Configure
interfaces clocks interfaces clocks USARTx
Configure SPIx
Execute Execute Execute
BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx
0x7F received
on USARTx yes

no

I2C Address
yes
Detected

no

Disable other
Synchro mechanism interfaces clocks
yes
detected on SPIx
Execute DFU
bootloader using USB
no
interrupts
no

USB cable yes

Detected

MS51432V1

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AN2606 STM32L412xx/422xx devices bootloader

55.3 Bootloader version

Table 120 lists the STM32L412xx/422xx devices bootloader version.

Table 120. STM32L412xx/422xx bootloader versions

Bootloader
version Description Known limitations
number

– On connection phase, USART responds with

two ACK bytes (0x79) instead of only one.
– PcROP option bytes cannot be written as
V13.1 Initial bootloader version Bootloader uses Byte access while PcROP
must be accessed using Half-Word access. 
Workaround: load a code snippest in SRAM
using Bootloader interface then jump to it, and
that code would write PcROP value.

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56 STM32L43xxx/44xxx devices bootloader

56.1 Bootloader configuration

The bootloader V9.1 version is updated to fix known limitations relative to USB-DFU
interface, and is implemented on devices with version information ID equal to 0x10 (refer to
Table 122 for more details).
The STM32L43xxx/44xxx bootloader is activated by applying Pattern 6 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 121. STM32L43xxx/44xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source for

HSI enabled system clock configured to 60 MHz and for USART,
I2C, SPI and USB bootloader operation.
The clock recovery system (CRS) is enabled for the
- DFU bootloader to allow USB to be clocked by
HSI48 48 MHz.
RCC The HSE is used only when the CAN interface is
HSE enabled selected. The HSE must have one of the following
values [24,20,18,16,12,9,8,6,4] MHz.
The Clock Security System (CSS) interrupt is
enabled when HSE is enabled. Any failure (or
-
removal) of the external clock generates system
Common to all reset
bootloaders 12 Kbyte starting from address 0x20000000 are
RAM -
used by the bootloader firmware
28 Kbyte starting from address 0x1FFF0000, contain
System memory -
the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
The DFU cannot be used to communicate with
bootloader if the voltage scaling range 2 is selected.
Power -
Bootloader firmware does not configure voltage
scaling range value in PWR_CR1 register.
Once initialized the USART1 configuration is: 8-bit,
USART1 Enabled
even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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Table 121. STM32L43xxx/44xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART2 configuration is: 8-bit,

USART2 Enabled
even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-bit,
USART3 Enabled
even parity and 1 Stop bit
USART3
bootloader USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud rate
SysTick timer Enabled
bootloaders from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
Slave 7-bit address: 0b1001000x
I2C1 bootloader
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
Slave 7-bit address: 0b1001000x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PB10 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PB11 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C3 Enabled analog filter ON.
Slave 7-bit address: 0b1001000x
I2C3 bootloader
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PC0 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC1 pin: data line is used in open-drain mode.

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Table 121. STM32L43xxx/44xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in push-pull pull-
SPI1_MOSI pin Input
down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in push-pull
SPI1_MISO pin Output
pull-down mode
PA5 pin: Slave clock line, used in push-pull pull-
SPI1_SCK pin Input
down mode
PA4 pin: slave chip select pin used in push-pull pull-
down mode.
SPI1_NSS pin Input
Note: This IO can be tied to GND if the SPI Master
does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled
– 8-bit MSB
– Speed up to 8 MHz
Polarity: CPOL Low, CPHA Low, NSS hardware
PB15 pin: Slave data Input line, used in push-pull
SPI2_MOSI pin Input
pull-down mode
SPI2 bootloader
PB14 pin: Slave data output line, used in push-pull
SPI2_MISO pin Output
pull-down mode
PB13 pin: Slave clock line, used in push-pull pull-
SPI2_SCK pin Input
down mode
PB12 pin: slave chip select pin used in push-pull
pull-down mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the SPI Master
does not use it.
Once initialized the CAN1 configuration is:
CAN1 Enabled
Baudrate 125 kbps, 11 -bit identifier.
CAN1_RX pin Input PB8 pin: CAN1 in reception mode
CAN1 bootloader CAN1_TX pin Output PB9 pin: CAN1 in transmission mode
This timer is used to determine the value of the HSE.
TIM16 Enabled Once the HSE frequency is determined, the system
clock is configured to 60 MHz using PLL and HSE.

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Table 121. STM32L43xxx/44xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB FS configured in forced device mode.

USB FS interrupt vector is enabled and used for
USB Enabled USB DFU communications.
Note: VDDUSB IO must be connected to 3.3 V for
DFU bootloader USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required

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56.2 Bootloader selection

The figures below show the bootloader selection mechanism.

Figure 72. Dual bank boot Implementation for STM32L3x2xx/44xxx bootloader V9.x

System Reset

If Boot0 = 0

yes
no

If Value of first
address of Bank2 is
yes
within int. SRAM
address(1)
Protection level2 no
Set Bank Swap to
enabled
Bank2
no

Jump to user code yes Continue Bootloader

If Value of first in Bank2 execution
address of Bank1 is
within int. SRAM
address(1) If Value of first
yes address of Bank2 is
within int. SRAM yes
address(1)
no

Protection level2 no
yes
enabled
Set Bank Swap to Set Bank Swap to Set Bank Swap to
Bank1 Bank1 Bank2
no

Jump to user code Jump to user code Jump to user code

Continue Bootloader
in Bank1 in Bank1 in Bank2
execution

MS35021V1

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Figure 73. Bootloader V9.x selection for STM32L43xxx/44xxx

System Reset

Configure System clock to

60 MHz with HSI
Disable all interrupt
System Init (Clock, GPIOs, sources and other
IWDG, SysTick) interfaces clocks

Disable all interrupt Disable all interrupt

Configure USB Device FS sources and other sources and other Configure
using CRS and HSI48 as interfaces clocks interfaces clocks USARTx
clock source

Execute Execute Execute

Configure I2Cx BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx

Configure SPIx

0x7F received on
USARTx yes

HSE detected no
no
Generate System
I2C Address yes reset
yes
Detected
Disable all interrupt
sources and other
no
interfaces clocks

SPIx detects yes Reconfigure System

Synchro mechanism clock to 60 MHz

no
Disable other Configure CAN
no interfaces clocks
Frame detected
on CANx yes
Execute DFU Execute
bootloader using USB BL_CAN_Loop for
no interrupts CANx

USB cable
yes
Detected

MSv38484V1

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56.3 Bootloader version

Table 122 lists the STM32L43xxx/44xxx devices bootloader versions.

Table 122. STM32L43xxx/44xxx bootloader versions

Bootloader
version Description Known limitations
number

Check the Version Information ID of your

STM32L43xxx/44xxx device, which can be read
at 0x1FFF6FF2 address.
Version Information ID equal to 0xFF:
– For memory write operations using DFU
interface: If the buffer size is larger than 256
bytes and not multiple of 8 bytes, the write
memory operation result is corrupted.
Workaround: if the file size is larger than 256
bytes, add byte padding to align it on 8-bytes
multiple size.
– For the USB-DFU interface, the CRS (clock
recovery system) is not correctly configured
and this may lead to random USB
communication errors (depending on
V9.1 Initial bootloader version temperature and voltage). In most case
communication error will manifest by a "Stall"
response to setup packets.
– On the “Go” command, system bootloader de-
init clears the RTCAPBEN bit in the
RCC_APB1ENR register
Workaround: manually call
__HAL_RCC_RTC_CLK_ENABLE() in the
software which sets the RTCAPBEN bit.
Version Information ID equal to 0x10: None
– PcROP option bytes cannot be written as
Bootloader uses Byte access while PcROP
must be accessed using Half-Word access. 
Workaround: load a code snippiest in SRAM
using Bootloader interface then jump to it, and
that code would write PcROP value.

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AN2606 STM32L45xxx/46xxx devices bootloader

57 STM32L45xxx/46xxx devices bootloader

57.1 Bootloader configuration

The STM32L45xxx/46xxx bootloader is activated by applying Pattern 6 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 123. STM32L45xxx/46xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source for

system clock configured to 72 MHz and for
HSI enabled
USART, I2C, SPI and USB bootloader
operation.
The clock recovery system (CRS) is
- enabled for the DFU bootloader to allow
USB to be clocked by HSI48 48 MHz.
RCC The system clock frequency is 60 MHz.
The HSE is used only when the CAN interface is
HSE enabled
selected . The HSE must have one of the
following values [24,20,18,16,12,9,8,6,4] MHz.
The Clock Security System (CSS) interrupt is
enabled when HSE is enabled. Any failure (or
-
removal) of the external clock generates system
Common to all
reset
bootloaders
12 Kbyte starting from address 0x20000000 are
RAM -
used by the bootloader firmware
28 Kbyte starting from address 0x1FFF0000,
System memory -
contain the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is
IWDG - periodically refreshed to prevent watchdog reset
(in case the hardware IWDG option was
previously enabled by the user).
The DFU cannot be used to communicate with
bootloader if the voltage scaling range 2 is
Power - selected. Bootloader firmware does not
configure voltage scaling range value in
PWR_CR1 register.
Once initialized the USART1 configuration is: 8-
USART1 Enabled
bit, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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Table 123. STM32L45xxx/46xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART2 configuration is: 8-

USART2 Enabled
bit, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-
USART3 Enabled
bit, even parity and 1 Stop bit
USART3
bootloader USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud rate
SysTick timer Enabled
bootloaders from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave
I2C1 Enabled mode, analog filter ON.
Slave 7-bit address: 0b1001010x
I2C1 bootloader
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave
I2C2 Enabled mode, analog filter ON.
Slave 7-bit address: 0b1001010x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PB10 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PB11 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave
I2C3 Enabled mode, analog filter ON.
Slave 7-bit address: 0b1001010x
I2C3 bootloader
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PC0 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC1 pin: data line is used in open-drain mode.

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Table 123. STM32L45xxx/46xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

– Slave mode
– Full Duplex
SPI1 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in push-pull
SPI1_MOSI pin Input
SPI1 bootloader pull-down mode
PA6 pin: Slave data output line, used in push-
SPI1_MISO pin Output
pull pull-down mode
PA5 pin: Slave clock line, used in push-pull pull-
SPI1_SCK pin Input
down mode
PA4 pin: slave chip select pin used in push-pull
pull-down mode.
SPI1_NSS pin Input
Note: This IO can be tied to GND if the SPI
Master does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PB15 pin: Slave data Input line, used in push-
SPI2_MOSI pin Input
SPI2 bootloader pull pull-down mode
PB14 pin: Slave data output line, used in push-
SPI2_MISO pin Output
pull pull-down mode
PB13 pin: Slave clock line, used in push-pull
SPI2_SCK pin Input
pull-down mode
PB12 pin: slave chip select pin used in push-pull
pull-down mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the SPI
Master does not use it.
Once initialized the CAN1 configuration is:
CAN1 Enabled
Baudrate 125 kbps, 11 -bit identifier.
CAN1_RX pin Input PB8 pin: CAN1 in reception mode

CAN1 bootloader CAN1_TX pin Output PB9 pin: CAN1 in transmission mode
This timer is used to determine the value of the
HSE. Once the HSE frequency is determined,
TIM16 Enabled
the system clock is configured to 60 MHz using
PLL and HSE.

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Table 123. STM32L45xxx/46xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB FS configured in forced device mode.

USB FS interrupt vector is enabled and used for
USB Enabled USB DFU communications.
Note: VDDUSB IO must be connected to 3.3 V
DFU bootloader for USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required

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57.2 Bootloader selection

The figures below show the bootloader selection mechanism.

Figure 74. Dual bank boot Implementation for STM32L45xxx/46xxx bootloader V9.x

System Reset

If Boot0 = 0

yes
no

If Value of first
address of Bank2 is
yes
within int. SRAM
address(1)
Protection level2 no
Set Bank Swap to
enabled
Bank2
no

Jump to user code yes Continue Bootloader

If Value of first in Bank2 execution
address of Bank1 is
within int. SRAM
address(1) If Value of first
yes address of Bank2 is
within int. SRAM yes
address(1)
no

Protection level2 no
yes
enabled
Set Bank Swap to Set Bank Swap to Set Bank Swap to
Bank1 Bank1 Bank2
no

Jump to user code Jump to user code Jump to user code

Continue Bootloader
in Bank1 in Bank1 in Bank2
execution

MS35021V1

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Figure 75.Bootloader V9.x selection for STM32L45xxx/46xxx

System Reset

Configure System clock to

72 MHz with HSI

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB Device FS

using CRS and HSI48 as
clock source Disable all interrupt
sources and other
interfaces clocks
Configure I2Cx
Disable all interrupt Disable all interrupt
sources and other sources and other Configure
interfaces clocks interfaces clocks USARTx
Configure SPIx
Execute Execute Execute
BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx
0x7F received
yes
on USARTx

no

I2C Address
yes
Detected HSE detected no

Generate System
no reset
yes

Disable all interrupt

Synchro mechanism sources and other
yes interfaces clocks
detected on SPIx

Reconfigure System
no clock to 60 MHz
no

Frame detected Disable other Configure CAN

yes
on CANx interfaces clocks

Execute DFU Execute

no
bootloader using USB BL_CAN_Loop for
interrupts CANx
USB cable
yes
Detected

MSv45964V1

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57.3 Bootloader version

Table 124 lists the STM32L45xxx/46xxx devices bootloader versions.

Table 124. STM32L45xxx/46xxx bootloader versions

Bootloader version number Description Known limitations

– PcROP option bytes cannot

be written as Bootloader uses
Byte access while PcROP
must be accessed using Half-
Word access. 
V9.2 Initial bootloader version
Workaround: load a code
snippiest in SRAM using
Bootloader interface then
jump to it, and that code
would write PcROP value.

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58 STM32L47xxx/48xxx devices bootloader

Two bootloader versions are available on STM32L47xxx/48xxx:

 V10.x supporting USART, I2C and DFU (USB FS Device).
This version is embedded in STM32L47xxx/48xxx rev. 2 and rev. 3 devices.
 V9.x supporting USART, I2C, SPI, CAN and DFU (USB FS Device). 
This version is embedded in STM32L47xxx/48xxx rev. 4 devices.

58.1 Bootloader V10.x

58.1.1 Bootloader configuration

The STM32L47xxx/48xxx bootloader is activated by applying Pattern 7 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 125. STM32L47xxx/48xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
The HSI is used at startup as clock source for system clock
HSI enabled configured to 24 MHz and for USART and I2C bootloader
operation.
The HSE is used only when the USB interface is selected
HSE enabled and the LSE is not present. The HSE must have one of the
following values [24,20,18,16,12,9,8,6,4] MHz.
The LSE is used to trim the MSI which is configured to 48
MHz as USB clock source. The LSE must be equal to
RCC LSE enabled
32,768 kHz. If the LSE is not detected, the HSE is used
instead if USB is connected.
The MSI is configured to 48 MHz and is used as USB clock
MSI enabled source. The MSI is used only if LSE is detected, otherwise,
HSE is used if USB is connected.
Common to all The Clock Security System (CSS) interrupt is enabled
bootloaders - when LSE or HSE is enabled. Any failure (or removal) of
the external clock generates system reset.
12 Kbyte starting from address 0x20000000 are used by
RAM -
the bootloader firmware
28 Kbyte starting from address 0x1FFF0000, contain the
System memory -
bootloader firmware
The independent watchdog (IWDG) prescaler is configured
to its maximum value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware IWDG option was
previously enabled by the user).
The DFU cannot be used to communicate with bootloader if
the voltage scaling range 2 is selected. Bootloader
Power -
firmware does not configure voltage scaling range value in
PWR_CR1 register.

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Table 125. STM32L47xxx/48xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
Once initialized the USART1 configuration is: 8-bit, even
USART1 Enabled
USART1 parity and 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bit, even
USART2 Enabled
USART2 parity and 1 Stop bit
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-bit, even
USART3 Enabled
USART3 parity and 1 Stop bit
bootloader USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud rate from the
SysTick timer Enabled
bootloaders host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
I2C1 bootloader Slave 7-bit address: 0b1000011x
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
I2C2 bootloader Slave 7-bit address: 0b1000011x
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PB10 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PB11 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave mode,
I2C3 Enabled analog filter ON.
I2C3 bootloader Slave 7-bit address is 0b1000011x
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PC0 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC1 pin: data line is used in open-drain mode.
USB Enabled USB OTG FS configured in forced device mode
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
DFU bootloader USB_DP pin No external pull-up resistor is required
This timer is used to determine the value of the HSE. Once
TIM17 Enabled the HSE frequency is determined, the system clock is
configured to 24 MHz using PLL and HSE.

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For USARTx and I2Cx bootloaders no external clock is required.

USB bootloader (DFU) requires either an LSE (low-speed external clock) or a HSE (high-
speed external clock):
 In case, the LSE is present regardless the HSE presence, the MSI is configured and
trimmed by the LSE to provide an accurate clock equal to 48 MHz which is the clock
source of the USB. The system clock is kept clocked to 24 MHz by the HSI.
 In case, the HSE is present, the system clock and USB clock is configured respectively
to 24 MHz and 48 MHz with HSE as clock source.

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58.1.2 Bootloader selection

Figure 76 and Figure 77 show the bootloader selection mechanism.

Figure 76. Dual bank boot implementation for STM32L47xxx/48xxx bootloader V10.x

System Reset

If Boot0 = 0
no

yes

If Value of first Protection level2 no

address of Bank2 is yes enabled
within int. SRAM
address
Set Bank Swap to
Bank2 yes
no
Continue Bootloader execution
Jump to user code
in Bank2 If Value of first
If Value of first address of Bank2 is
within int. SRAM yes
address of Bank1 is
within int. SRAM address
address
yes
no
no
Set Bank Swap to Set Bank Swap to
Bank1 Bank2
Protection
level2 enabled yes
Jump to user code Jump to user code
in Bank1 in Bank2
Set Bank Swap to
no Bank1

Continue Bootloader Jump to user code

execution in Bank1
MSv36786V1

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Figure 77.Bootloader V10.x selection for STM32L47xxx/48xxx

Bootloader

Configure System clock

to 24 MHz with HSI

LSE detected no

yes
Configure USB clock to 48
MHz with HSI as clock source
Configure USB clock to 48
MHz with MSI as clock source

System Init (Clock, GPIOs,

IWDG, SysTick)
Disable all
interrupt sources
Configure USB OTG FS yes
device Configure
USARTx

Configure all I2Cs

Execute
BL_USART_Loop
for USARTx

0x7F received
on USARTx
Disable all
yes
interrupt sources
no

Execute
BL_I2C_Loop for
I2C Address I2Cx
Detected yes
MSI used as USB
no
clock source
no
yes HSE detected no

USB cable Generate System

Detected yes reset

yes Reconfigure System clock

to 24 MHz and USB clock
to 48 MHz with HSE

Execute DFU bootloader

using USB interrupts
MSv38432V2

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58.1.3 Bootloader version

The following table lists the STM32L47xxx/48xxx devices bootloader V10.x versions:

Table 126. STM32L47xxx/48xxx bootloader V10.x versions

Bootloader
version Description Known limitations
number

For memory write operations using DFU interface:

If the buffer size is larger than 256 bytes and not
multiple of 8 bytes, the write memory operation
result is corrupted.
V10.1 Initial bootloader version Workaround: if the file size is larger than 256
bytes, add byte padding to align it on 8-bytes
multiple size.
Write in SRAM is corrupted.
For memory write operations using DFU interface:
If the buffer size is larger than 256 bytes and not
multiple of 8 bytes, the write memory operation
V10.2 Fix write in SRAM issue result is corrupted.
Workaround: if the file size is larger than 256
bytes, add byte padding to align it on 8-bytes
multiple size.
– For memory write operations using DFU
interface: If the buffer size is larger than 256
bytes and not multiple of 8 bytes, the write
memory operation result is corrupted.
Add support of MSI as USB clock Workaround: if the file size is larger than 256
source (MSI is trimmed by LSE). bytes, add byte padding to align it on 8-bytes
V10.3 Update dual bank boot feature to multiple size.
support the case when user stack – PcROP option bytes cannot be written as
is mapped in SRAM2. Bootloader uses Byte access while PcROP
must be accessed using Half-Word access. 
Workaround: load a code snippiest in SRAM
using Bootloader interface then jump to it, and
that code would write PcROP value.

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58.2 Bootloader V9.x

58.2.1 Bootloader configuration

The STM32L47xxx/48xxx bootloader is activated by applying Pattern 7 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 127. STM32L47xxx/48xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
The HSI is used at startup as clock source for
HSI enabled system clock configured to 72 MHz and for
USART and I2C bootloader operation.
The HSE is used only when the USB interface
is selected and the LSE is not present. The
HSE must have one of the following values
HSE enabled
[24,20,18,16,12,8,6,4] MHz. 
System is clocked at 72 MHz if USB is used or
60 MHz if CAN is used.
The LSE is used to trim the MSI which is
configured to 48 MHz as USB clock source.
RCC
LSE enabled The LSE must be equal to 32,768 kHz. If the
LSE is not detected, the HSE is used instead if
USB is connected.
The MSI is configured to 48 MHz and is used
as USB clock source. The MSI is used only if
MSI enabled
LSE is detected, otherwise, HSE is used if
Common to all USB is connected.
bootloaders The Clock Security System (CSS) interrupt is
enabled when LSE or HSE is enabled. Any
CSS
failure (or removal) of the external clock
generates system reset.
13 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
28 Kbyte starting from address 0x1FFF0000,
System memory -
contain the bootloader firmware
The independent watchdog (IWDG) prescaler
is configured to its maximum value. It is
IWDG - periodically refreshed to prevent watchdog
reset (in case the hardware IWDG option was
previously enabled by the user).
The DFU cannot be used to communicate with
bootloader if the voltage scaling range 2 is
Power - selected. Bootloader firmware does not
configure voltage scaling range value in
PWR_CR1 register.
Once initialized the USART1 configuration is:
USART1 Enabled
USART1 8-bit, even parity and 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART2 in reception mode
USART1_TX pin Output PA9 pin: USART2 in transmission mode

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Table 127. STM32L47xxx/48xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
Once initialized the USART2 configuration is:
USART2 Enabled
USART2 8-bit, even parity and 1 Stop bit
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is:
USART3 Enabled
USART3 8-bit, even parity and 1 Stop bit
bootloader USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud
SysTick timer Enabled
bootloaders rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave
I2C1 Enabled mode, analog filter ON. Slave 7-bit address:
I2C1 bootloader 0b1000011x (where x = 0 for write and x = 1 for
read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave
I2C2 Enabled mode, analog filter ON. Slave 7-bit address:
0b1000011x (where x = 0 for write and x = 1 for
I2C2 bootloader read)
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB11 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 400 kHz, 7-bit address, slave
I2C3 Enabled mode, analog filter ON. Slave 7-bit address:
I2C3 bootloader 0b1000011x (where x = 0 for write and x = 1 for
read)
I2C3_SCL pin Input/Output PC0 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC1 pin: data line is used in open-drain mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed up
SPI1 Enabled
to 8 MHz, Polarity: CPOL Low, CPHA Low,
NSS hardware.
PA7 pin: Slave data Input line, used in push-
SPI1_MOSI pin Input
pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in push-
SPI1_MISO pin Output
pull pull-down mode
PA5 pin: Slave clock line, used in push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in push-pull
SPI1_NSS pin Input
pull-down mode.

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Table 127. STM32L47xxx/48xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed up
SPI2 Enabled
to 8 MHz, Polarity: CPOL Low, CPHA Low,
NSS hardware
PB15 pin: Slave data Input line, used in push-
SPI2_MOSI pin Input
pull pull-down mode
SPI2 bootloader
PB14 pin: Slave data output line, used in push-
SPI2_MISO pin Output
pull pull-down mode
PB13 pin: Slave clock line, used in push-pull
SPI2_SCK pin Input
pull-down mode
PB12 pin: slave chip select pin used in push-
SPI2_NSS pin Input
pull pull-down mode.
Once initialized the CAN1 configuration is:
CAN1 Enabled
Baudrate 125 kbps, 11-bit identifier.
CAN1 bootloader
CAN1_RX pin Input PB8 pin: CAN1 in reception mode
CAN1_TX pin Output PB9 pin: CAN1 in transmission mode
USB FS configured in forced device mode.
USB FS interrupt vector is enabled and used
USB Enabled for USB DFU communications.
Note: VDDUSB IO must be connected to 3.3 V
DFU bootloader for USB to be operational.
USB_DM pin PA11 pin: USB FS DM line
Input/Output PA12 pin: USB FS DP line.
USB_DP pin
No external pull-up resistor is required.

In case, the HSE is present, the system clock and USB clock is configured respectively to
72 MHz and 48 MHz with PLL (clocked by HSE) as a clock source.

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58.2.2 Bootloader selection

Figure 78 and Figure 79 show the bootloader selection mechanism.

Figure 78. Dual bank boot implementation for STM32L47xxx/48xxx bootloader V9.x

System Reset

If Boot0 = 0
no

yes

If Value of first Protection level2 no

address of Bank2 is yes enabled
within int. SRAM
address
Set Bank Swap to
Bank2 yes
no
Continue Bootloader execution
Jump to user code
in Bank2 If Value of first
If Value of first address of Bank2 is
within int. SRAM yes
address of Bank1 is
within int. SRAM address
address
yes
no
no
Set Bank Swap to Set Bank Swap to
Bank1 Bank2
Protection
level2 enabled yes
Jump to user code Jump to user code
in Bank1 in Bank2
Set Bank Swap to
no Bank1

Continue Bootloader Jump to user code

execution in Bank1
MSv36786V1

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Figure 79.Bootloader V9.x selection for STM32L47xxx/48xxx

Bootloader

Configure System clock to 72 MHz

with HSI

LSE detected no

yes

Configure USB clock to 48 MHz

with MSI as clock source
Configure USB clock to 48 MHz with HSI
as clock source

System Init(Clock,
GPIOs,IWDG,Systick)

Configure USB OTG FS device Disable all interrupt Disable all interrupt sources
Disable all interrupt sources
sources and other and other interfaces clocks
and other interfaces clocks
interfaces clocks

Configure I2Cx Execute BL_SPI_Loop Execute BL_I2C_Loop

Configure USARTx
for SPIx for I2Cx

Configure SPIx Execute

BL_USART_Loop
for USARTx

0x7F received on
yes
USARTx
MSI used as USB clock
no source
yes
I2C Address
yes no
Detected
no
HSE detected no no HSE detected
Synchro mechanism yes
detected on SPIx yes
yes
no yes Generate System yes
Reconfigure System reset
no USB cable clock to 60 MHz
Detected Reconfigure System clock
to 72 MHz and USB clock
no Configure CAN to 48 MHz

Frame yes
detected on Execute
CANx BL_CAN_Loop Execute DFU bootloader
for CANx using USB interrupts

MSv38404V1

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58.2.3 Bootloader version

The following table lists the STM32L47xxx/48xxx devices bootloader V9.x versions:

Table 128. STM32L47xxx/48xxx bootloader V9.x versions

Bootloader
version Description Known limitations
number

For memory write operations using DFU interface:

If the buffer size is larger than 256 bytes and not
multiple of 8 bytes, the write memory operation
result is corrupted.
V9.0 Initial bootloader version Workaround: if the file size is larger than 256
bytes, add byte padding to align it on 8-bytes
multiple size.
Write in SRAM is corrupted
V9.1 Deprecated version (not used) None
– For memory write operations using DFU
interface: If the buffer size is larger than 256
bytes and not multiple of 8 bytes, the write
memory operation result is corrupted.
Workaround: if the file size is larger than 256
bytes, add byte padding to align it on 8-bytes
V9.2 Fix write in SRAM issue multiple size.
– PcROP option bytes cannot be written as
Bootloader uses Byte access while PcROP
must be accessed using Half-Word access. 
Workaround: load a code snippiest in SRAM
using Bootloader interface then jump to it, and
that code would write PcROP value.

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59 STM32L496xx/4A6xx devices bootloader

59.1 Bootloader configuration

The STM32L496xx/4A6xx bootloader is activated by applying Pattern 6 (described in
Table 2: Bootloader activation patterns). Table 129 shows the hardware resources used by
this bootloader.

Table 129. STM32L496xx/4A6xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source

for system clock configured to 72 MHz
HSI enabled
and for USART, I2C and SPI bootloader
operation.
The clock recovery system (CRS) is
- enabled for the DFU bootloader to allow
USB to be clocked by HSI 48 MHz.
RCC The HSE is used only when the CAN
interface is selected . The HSE must have
HSE enabled
one of the following value
[24,20,18,16,12,9,8,6,4] MHz.
The Clock Security System (CSS)
interrupt is enabled when HSE is enabled.
-
Any failure (or removal) of the external
clock generates system reset
Common to all 12 Kbyte starting from address
bootloaders RAM - 0x20000000 are used by the bootloader
firmware
28 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
The DFU cannot be used to communicate
with bootloader if the voltage scaling
Power - range 2 is selected. Bootloader firmware
does not configure voltage scaling range
value in PWR_CR1 register.
Once initialized the USART1
USART1 Enabled configuration is: 8-bit, even parity and 1
Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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Table 129. STM32L496xx/4A6xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART2

USART2 Enabled configuration is: 8-bit, even parity and 1
Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3
USART3 Enabled configuration is: 8-bit, even parity and 1
Stop bit
USART3 bootloader
USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial
USARTx
SysTick timer Enabled baud rate from the host for USARTx
bootloaders
bootloaders.
The I2C1 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001100x (where x
I2C1 bootloader = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001100x (where x
I2C2 bootloader = 0 for write and x = 1 for read)
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB11 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001100x (where x
I2C3 bootloader = 0 for write and x = 1 for read)
PC0 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC1 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.

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Table 129. STM32L496xx/4A6xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

– Slave mode
– Full Duplex
SPI1 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
SPI1 bootloader push-pull pull-down mode
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-
SPI1_SCK pin Input
pull pull-down mode
PA4 pin: slave chip select pin used in
push-pull pull-down mode.
SPI1_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
SPI2 bootloader push-pull pull-down mode
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PB13 pin: Slave clock line, used in push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
push-pull pull-down mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.
Once initialized the CAN1 configuration
CAN1 Enabled
is:Baudrate 125 kbps, 11 -bit identifier.
CAN1_RX pin Input PB8 pin: CAN1 in reception mode
CAN1_TX pin Output PB9 pin: CAN1 in transmission mode
CAN1 bootloader
This timer is used to determine the value
of the HSE. Once the HSE frequency is
TIM16 Enabled determined, the system clock is
configured to 60 MHz using PLL and
HSE.

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Table 129. STM32L496xx/4A6xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB OTG FS configured in forced device

mode.
USB OTG FS interrupt vector is enabled
USB Enabled
and used for USB DFU communications.
Note: VDDUSB IO must be connected to
DFU bootloader
3.3 V for USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required

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59.2 Bootloader selection

The figures below show the bootloader selection mechanism.

Figure 80. Dual bank boot Implementation for STM32L496xx/4A6xx bootloader V9.x

System Reset

If Boot0 = 0

yes
no

If Value of first
address of Bank2 is
yes
within int. SRAM
address(1)
Protection level2 no
Set Bank Swap to
enabled
Bank2
no

Jump to user code yes Continue Bootloader

If Value of first in Bank2 execution
address of Bank1 is
within int. SRAM
address(1) If Value of first
yes address of Bank2 is
within int. SRAM yes
address(1)
no

Protection level2 no
yes
enabled
Set Bank Swap to Set Bank Swap to Set Bank Swap to
Bank1 Bank1 Bank2
no

Jump to user code Jump to user code Jump to user code

Continue Bootloader
in Bank1 in Bank1 in Bank2
execution

MS35021V1

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Figure 81.Bootloader V9.x selection for STM32L496xx/4A6xx

System Reset

Configure System clock to

72 MHz with HSI

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB OTG FS using

CRS and HSI48 as clock
source Disable all interrupt
sources and other
interfaces clocks
Configure I2Cx
Disable all interrupt Disable all interrupt
sources and other sources and other Configure
interfaces clocks interfaces clocks USARTx
Configure SPIx
Execute Execute Execute
BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx
0x7F received
on USARTx yes

no

I2C Address
yes HSE detected no
Detected

Generate System
no reset
yes

Disable all interrupt

Synchro mechanism yes sources and other
detected on SPIx interfaces clocks

Reconfigure System
no clock to 60 MHz
no

Frame detected Disable other Configure CAN

on CANx yes
interfaces clocks

Execute DFU Execute

no
bootloader using USB BL_CAN_Loop for
interrupts CANx
USB cable yes
Detected

MSv44808V1

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59.3 Bootloader version

Table 130 lists the STM32L496xx/4A6xx devices bootloader versions.

Table 130. STM32L496xx/4A6xx bootloader version

Bootloader
version Description Known limitations
number

– The Bank Erase command is aborted by the bootloader device, and

the NACK (0x1F) is sent to the host. Workaround: Perform Bank
erase operation through page erase using the Erase command
(0x44).
– SPI write operation fail
Limitation:
a. During Bootloader SPI write Flash memory operation, some
random 64-bits (2 double-words) may be left blank at 0xFF.
Root cause:
a. Bootloader uses 64-bits cast write operation which is interrupted
by SPI DMA and it leads to double access on same Flash memory
address and the 64-bits are not written
Workarounds:
a. WA1: add a delay between sending write command and its ACK
request. Its duration must be the duration of the 256-Bytes Flash
memory write time.
V9.3 Initial bootloader version b. WA2: read back after write and in case of error start write again.
c. WA3: Patch in RAM to write in Flash memory that implements
write memory without 64-bits cast.
WA1 and WA3 are more efficient than WA2 in terms of total
programming time
How critical is the limitation:
a. The limitation leads to a modification in customer SPI host
software by adding 3-4 ms delay to each write operation.
b. The delay is not waste because it is anyway the Flash memory
write period of time that host has to wait anyway (so instead of
waiting by sending ACK requests, host will wait by delay).
c. Limitation has been seen only on SPI and cannot impact
USART/I2C/CAN.
– PcROP option bytes cannot be written as Bootloader uses Byte
access while PcROP must be accessed using Half-Word access.
Workaround: load a code snippiest in SRAM using Bootloader
interface then jump to it, and that code would write PcROP value.

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AN2606 STM32L4P5xx/4Q5xx devices bootloader

60 STM32L4P5xx/4Q5xx devices bootloader

60.1 Bootloader configuration

The STM32L4P5xx/4Q5xx bootloader is activated by applying Pattern 7 (described in
Table 2: Bootloader activation patterns). Table 133 shows the hardware resources used by
this bootloader.

Table 131. STM32L4P5xx/4Q5xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock

source for system clock configured to 60
HSI enabled
MHz and for USART, I2C, SPI and USB
bootloader operation.
The clock recovery system (CRS) is
- enabled for the DFU bootloader to allow
USB to be clocked by HSI 48 MHz.
RCC The HSE is used only when the CAN
interface is selected . The HSE must
HSE enabled
have one of the following value
[24,20,18,16,12,9,8,6,4] MHz.
The Clock Security System (CSS)
interrupt is enabled when HSE is
-
enabled. Any failure (or removal) of the
external clock generates system reset
Common to all 16 Kbytes starting from address
bootloaders RAM - 0x20000000 are used by the bootloader
firmware
28 Kbytes starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
The DFU cannot be used to communicate
with bootloader if the voltage scaling
Power - range 2 is selected. Bootloader firmware
does not configure voltage scaling range
value in PWR_CR1 register.
Once initialized the USART1
USART1 Enabled configuration is: 8-bit, even parity and 1
USART1 Stop bit
bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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Table 131. STM32L4P5xx/4Q5xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART2

USART2 Enabled configuration is: 8-bit, even parity and 1
USART2 Stop bit
bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3
USART3 Enabled configuration is: 8-bit, even parity and 1
USART3 Stop bit
bootloader
USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
The I2C1 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1011011x
I2C1 bootloader (where x = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1011011x
I2C2 bootloader (where x = 0 for write and x = 1 for read)
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB11 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1011011x
I2C3 bootloader (where x = 0 for write and x = 1 for read)
PC0 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC1 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.

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Table 131. STM32L4P5xx/4Q5xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

– Slave mode
– Full Duplex
SPI1 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
SPI1 bootloader push-pull pull-down mode
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-
SPI1_SCK pin Input
pull pull-down mode
PA4 pin: slave chip select pin used in
push-pull pull-up mode.
SPI1_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
SPI2 bootloader push-pull pull-down mode
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PB13 pin: Slave clock line, used in push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
push-pull pull-up mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.
Once initialized the CAN1 configuration
CAN1 Enabled is:
Baudrate 125 kbps, 11 -bit identifier.
CAN1 bootloader
CAN1_RX pin Input PB8 pin: CAN1 in reception mode
CAN1_TX pin Output PB9 pin: CAN1 in transmission mode

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Table 131. STM32L4P5xx/4Q5xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB FS configured in forced device

mode.
USB FS interrupt vector is enabled and
USB Enabled
used for USB DFU communications.
Note: VDDUSB IO must be connected to
DFU bootloader
3.3 V for USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required

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60.2 Bootloader selection

Figure 84 and Figure 85 show the bootloader selection mechanisms.

Figure 82. Dual bank boot implementation for STM32L4P5xx/4Q5xx bootloader V9.x

System Reset

If Boot0 = 0
no

yes

If Value of first Protection level2 no

address of Bank2 is yes enabled
within int. SRAM
address
Set Bank Swap to
Bank2 yes
no
Continue Bootloader execution
Jump to user code
in Bank2 If Value of first
If Value of first address of Bank2 is
within int. SRAM yes
address of Bank1 is
within int. SRAM address
address
yes
no
no
Set Bank Swap to Set Bank Swap to
Bank1 Bank2
Protection
level2 enabled yes
Jump to user code Jump to user code
in Bank1 in Bank2
Set Bank Swap to
no Bank1

Continue Bootloader Jump to user code

execution in Bank1
MSv36786V1

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Figure 83.Bootloader V9.x selection for STM32L4P5xx/4Q5xx

System Reset

Configure System clock to 60

MHz with HSI

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB Device FS

using CRS and HSI48 as
clock source

Configure I2Cx

Configure SPIx

Disable all interrupt

0x7F received on sources and other
yes interfaces clocks
USARTx Disable all Disable all
interrupt sources interrupt sources
and other and other
no interfaces clocks interfaces clocks Configure USARTx

I2C Address Execute Execute Execute

yes
Detected BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx

no

HSE detected no
Synchro mechanism
yes
detected on SPIx
Generate
yes System reset

no Disable all interrupt

yes sources and other
no interfaces clocks

Frame detected on
Reconfigure System
CANx
clock to 60 MHz

Disable other
no interfaces clocks Configure CAN

USB cable Execute DFU Execute

yes bootloader using BL_CAN_Loop
Detected
USB interrupts for CANx

MS49689V1

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60.3 Bootloader version

Table 132 lists the STM32L4P5xx/4Q5xx devices bootloader versions.

Table 132. STM32L4P5xx/4Q5xx bootloader versions

Bootloader
version Description Known limitations
number

– PcROP option bytes cannot be written as

bootloader uses byte access while PcROP must
Initial bootloader version on cut be accessed using half-word access.
V9.0
1.0 samples Workaround: load a code snippet in SRAM using
bootloader interface then jump to it, and that code
writes PcROP value.

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61 STM32L4Rxxx/4Sxxx devices bootloader

61.1 Bootloader configuration

The STM32L4Rxx/4Sxx bootloader is activated by applying Pattern 6 (described in Table 2:
Bootloader activation patterns). Table 133 shows the hardware resources used by this
bootloader.

Table 133. STM32L4Rxxx/4Sxxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source

for system clock configured to 60 MHz
HSI enabled
and for USART, I2C, SPI and USB
bootloader operation.
The clock recovery system (CRS) is
- enabled for the DFU bootloader to allow
USB to be clocked by HSI 48 MHz.
RCC The HSE is used only when the CAN
interface is selected . The HSE must have
HSE enabled
one of the following values
[24,20,18,16,12,9,8,6,4] MHz.
The Clock Security System (CSS)
interrupt is enabled when HSE is enabled.
-
Any failure (or removal) of the external
clock generates system reset
Common to all 12 Kbytes starting from address
bootloaders RAM - 0x20000000 are used by the bootloader
firmware
28672 bytes starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
The DFU cannot be used to communicate
with bootloader if the voltage scaling
Power - range 2 is selected. Bootloader firmware
does not configure voltage scaling range
value in PWR_CR1 register.
Once initialized the USART1
USART1 Enabled configuration is: 8-bit, even parity and 1
Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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Table 133. STM32L4Rxxx/4Sxxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART2

USART2 Enabled configuration is: 8-bit, even parity and 1
Stop bit
USART2 bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3
USART3 Enabled configuration is: 8-bit, even parity and 1
Stop bit
USART3 bootloader
USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial
USARTx
SysTick timer Enabled baud rate from the host for USARTx
bootloaders
bootloaders.
The I2C1 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1010000x
I2C1 bootloader (where x = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1010000x
I2C2 bootloader (where x = 0 for write and x = 1 for read)
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB11 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1010000x
I2C3 bootloader (where x = 0 for write and x = 1 for read)
PC0 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC1 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.

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Table 133. STM32L4Rxxx/4Sxxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

– Slave mode
– Full Duplex
SPI1 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
SPI1 bootloader push-pull pull-down mode
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-
SPI1_SCK pin Input
pull pull-down mode
PA4 pin: slave chip select pin used in
push-pull pull-up mode.
SPI1_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
SPI2 bootloader push-pull pull-down mode
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PB13 pin: Slave clock line, used in push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
push-pull pull-up mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.
Once initialized the CAN1 configuration
CAN1 Enabled is:
Baudrate 125 kbps, 11 -bit identifier.
CAN1_RX pin Input PB8 pin: CAN1 in reception mode

CAN1 bootloader CAN1_TX pin Output PB9 pin: CAN1 in transmission mode
This timer is used to determine the value
of the HSE. Once the HSE frequency is
TIM16 Enabled determined, the system clock is
configured to 60 MHz using PLL and
HSE.

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Table 133. STM32L4Rxxx/4Sxxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB FS configured in forced device

mode.
USB FS interrupt vector is enabled and
USB Enabled
used for USB DFU communications.
Note: VDDUSB IO must be connected to
DFU bootloader
3.3 V for USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required

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61.2 Bootloader selection

Figure 84 and Figure 85 show the bootloader selection mechanisms.

Figure 84. Dual bank boot implementation for STM32L4Rxxx/STM32L4Sxxx bootloader V9.x

System Reset

If Boot0 = 0
no

yes

If Value of first Protection level2 no

address of Bank2 is yes enabled
within int. SRAM
address
Set Bank Swap to
Bank2 yes
no
Continue Bootloader execution
Jump to user code
in Bank2 If Value of first
If Value of first address of Bank2 is
within int. SRAM yes
address of Bank1 is
within int. SRAM address
address
yes
no
no
Set Bank Swap to Set Bank Swap to
Bank1 Bank2
Protection
level2 enabled yes
Jump to user code Jump to user code
in Bank1 in Bank2
Set Bank Swap to
no Bank1

Continue Bootloader Jump to user code

execution in Bank1
MSv36786V1

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Figure 85.Bootloader V9.x selection for STM32L4Rxx/4Sxx

System Reset

Configure System clock to 60

MHz with HSI

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB Device FS

using CRS and HSI48 as
clock source

Configure I2Cx

Configure SPIx

Disable all interrupt

0x7F received on sources and other
yes interfaces clocks
USARTx Disable all Disable all
interrupt sources interrupt sources
and other and other
no interfaces clocks interfaces clocks Configure USARTx

I2C Address Execute Execute Execute

yes
Detected BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx

no

HSE detected no
Synchro mechanism
yes
detected on SPIx
Generate
yes System reset

no Disable all interrupt

yes sources and other
no interfaces clocks

Frame detected on
Reconfigure System
CANx
clock to 60 MHz

Disable other
no interfaces clocks Configure CAN

USB cable Execute DFU Execute

yes bootloader using BL_CAN_Loop
Detected
USB interrupts for CANx

MS49689V1

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61.3 Bootloader version

Table 134 lists the STM32L4Rxx/4Sxx devices bootloader versions.

Table 134. STM32L4Rxx/4Sxx bootloader versions

Bootloader
version Description Known limitations
number

V9.0 Initial bootloader version on cut 1.0 samples – None

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62 STM32L552xx/STM32L562xx devices bootloader

62.1 Bootloader configuration

The STM32L552xx/562xx bootloader is activated by applying Pattern 12 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 135. STM32L552xx/562xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz (using

HSI enabled
PLL clocked by HSI).
The clock recovery system (CRS) is enabled
RCC - for the DFU bootloader to allow USB to be
clocked by HSI 48 MHz.
20 MHZ derived from the PLLQ is used for
-
FDCAN
Common to all 16 Kbytes starting from address 0x20000000
bootloaders RAM -
are used by the bootloader firmware
32 Kbytes starting from address
System memory -
0x0BF90000.
The independent watchdog (IWDG) prescaler
is configured to its maximum value. It is
IWDG - periodically refreshed to prevent watchdog
reset (in case the hardware IWDG option was
previously enabled by the user).
Once initialized the USART1 configuration is:
USART1 Enabled
8-bit, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is:
USART2 Enabled
8-bit, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is:
USART3 Enabled
8-bit, even parity and 1 Stop bit
USART3
bootloader USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode

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Table 135. STM32L552xx/562xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C1 configuration is:

I2C speed: up to 1 MHz, 7-bit address, slave
I2C1 Enabled mode, analog filter ON.
Slave 7-bit address: 0b0101100x
I2C1 bootloader (where x = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave
I2C2 Enabled mode, analog filter ON.
Slave 7-bit address: 0b0101100x
I2C2 bootloader (where x = 0 for write and x = 1 for read)
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB11 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave
I2C3 Enabled mode, analog filter ON.
Slave 7-bit address: 0b0101100x (where x =
I2C3 bootloader 0 for write and x = 1 for read)
PC0 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC1 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in push-
SPI1_MOSI pin Input
SPI1 bootloader pull pull-down mode
PA6 pin: Slave data output line, used in push-
SPI1_MISO pin Output
pull pull-down mode
PA5 pin: Slave clock line, used in push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in push-
pull pull-up mode.
SPI1_NSS pin Input
Note: This IO can be tied to GND if the SPI
Master does not use it.

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Table 135. STM32L552xx/562xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI2 configuration is:

– Slave mode
– Full Duplex
SPI2 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PB15 pin: Slave data Input line, used in push-
SPI2_MOSI pin Input
SPI2 bootloader pull pull-down mode
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PB13 pin: Slave clock line, used in push-pull
SPI2_SCK pin Input
pull-down mode
PB12 pin: slave chip select pin used in push-
pull pull-up mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the SPI
Master does not use it.
The SPI configuration is:
– Slave mode
– Full Duplex
SPI3 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PB5 pin: Slave data Input line, used in push-
SPI3_MOSI pin Input
SPI3 bootloader pull pull-down mode
PG10 pin: Slave data output line, used in
SPI3_MISO pin Output
push-pull pull-down mode
PG9 pin: Slave clock line, used in push-pull
SPI3_SCK pin Input
pull-down mode
PG12 pin: slave chip select pin used in push-
pull pull-up mode.
SPI3_NSS pin Input
Note: This IO can be tied to GND if the SPI
Master does not use it.
Once initialized the FDCAN1 configuration is:
Bitrate 0.5 Mbps
FrameFormat = FDCAN_FRAME_FD_BRS
FDCAN1 Enabled Mode = FDCAN_MODE_NORMAL
FDCAN bootloader AutoRetransmission = ENABLE
TransmitPause = DISABLE
ProtocolException = ENABLE
FDCAN1_Rx pin Input/ PB9 pin: FDCAN1 in reception mode
FDCAN1_Tx pin Output PB8 pin: FDCAN1 in transmission mode

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Table 135. STM32L552xx/562xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB FS configured in forced device mode.

USB FS interrupt vector is enabled and used
USB Enabled for USB DFU communications.
Note: VDDUSB IO must be connected to
DFU bootloader 3.3 V for USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required

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62.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 86. Bootloader V9.x selection for STM32L552xx/562xx

System Reset

Configure System clock to

60 MHz with HSI

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB OTG FS

Device
Execute
BL_FDCAN loop

Configure I2Cx

Configure SPIx Disable all interrupt

sources and other
interfaces clocks
FDCAN frame Disable all interrupt Disable all interrupt
detected yes sources and other Configure
sources and other
interfaces clocks interfaces clocks USARTx
no
Execute Execute Execute
0x7F received BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
on USARTx yes for SPIx for I2Cx for USARTx

no

I2C Address
yes
Detected

no

no
Execute DFU
Synchro mechanism yes bootloader using USB
detected on SPIx
interrupts

no

USB cable yes

Detected

MS52834V1

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62.3 Bootloader version

Table 136 lists the STM32L552xx/562xx devices bootloader versions.

Table 136. STM32L552xx/562xx bootloader versions

Bootloader
version Description Known limitations
number

– USART3 not working

– SPI3 not working
– OB launch not working on USB-DFU
Initial bootloader version on – No read/write SRAM2 in all protocols
V13.0
cut1.0 samples – Read Secure Option bytes only implemented on
USART/I2C
– Regression from TZen = 1 to TZen = 0 is done
automatically on RDP regression
– Not able to set TZen to 1 option byte using all
interfaces of the BL
No WA available
Release supported only in cut2.0 – Cannot set RDP level 0.5 nor option bytes in
– Fix all issues on previous RDP level 0.5 using BL interfaces
release No WA available
V9.0 – Add FDCAN support – Multiple reset seen when enabling HW IWDG
– New command added for TZen option byte in TZen = 1
disable No WA available
– Support of sales type 256KB – Not able to set secure option bytes setting when
TZen = 1 and RDP level is 0
No WA available
– “Go” Command on USB is not working
– Fix all known limitations of
previous release Option byte programming is not working properly
– Add enable BOOT_LOCK BL when using FDCAN interface
V9.1
command This makes the change of the Option byte not
– Add support of RDP L1 to 0.5 effective until a power off power on.
regression
– Fix all known limitations of
V9.2 previous release None
– Version for silicon revision Z

Note: When jumping to the BL the cache must be disabled.

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AN2606 STM32WB50xx/55xx devices bootloader

63 STM32WB50xx/55xx devices bootloader

63.1 Bootloader configuration

The STM32WBxxx bootloader is activated by applying Pattern 16 (described in Table 2:
Bootloader activation patterns). Table 137 shows the hardware resources used by this
bootloader.

Table 137. STM32WB50xx/55xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 64 MHz

MSI enabled
(using PLL clocked by MSI).
RCC The clock recovery system (CRS) is
- enabled for the DFU bootloader to allow
USB to be clocked by HSI 48 MHz.
20 Kbytes starting from address
RAM - 0x20000000 are used by the bootloader
firmware
Common to all
bootloaders 28 Kbytes starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized the USART1
USART1 Enabled configuration is: 8-bit, even parity and 1
Stop bit
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
The I2C1 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001111x (where x
I2C1 bootloader = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

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Table 137. STM32WB50xx/55xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 1 MHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001111x (where x
I2C3 bootloader = 0 for write and x = 1 for read)
PC0 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC1 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
SPI1 bootloader push-pull pull-down mode
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-
SPI1_SCK pin Input
pull pull-down mode
PA4 pin: slave chip select pin used in
push-pull pull-up mode.
SPI1_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
SPI2 bootloader push-pull pull-down mode
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PB13 pin: Slave clock line, used in push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
push-pull pull-up mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.

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Table 137. STM32WB50xx/55xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB FS configured in forced device

mode.
USB FS interrupt vector is enabled and
USB Enabled
used for USB DFU communications.
Note: VDDUSB IO must be connected to
DFU bootloader
3.3 V for USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required

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63.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 87. Bootloader V13.0 selection for STM32WB50xx/55xx

System Reset

Configure System clock to 64

MHz with MSI

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure USB Device FS

using CRS and HSI48 as
clock source

Configure I2Cx

Configure SPIx

Disable all interrupt

0x7F received on sources and other
yes interfaces clocks
USARTx Disable all Disable all
interrupt sources interrupt sources
and other and other
no interfaces clocks interfaces clocks Configure USARTx

I2C Address Execute Execute Execute

yes
Detected BL_SPI_Loop BL_I2C_Loop BL_USART_Loop
for SPIx for I2Cx for USARTx

no

Synchro mechanism
yes
detected on SPIx
no
Disable other
interfaces clocks
no

Execute DFU
USB cable bootloader using
yes
Detected USB interrupts

MS51473V1

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63.3 Bootloader version

Table 138. STM32WB50xx/55xx bootloader versions
Bootloader
version Description Known limitations
number

– Readout Unprotect Command is not working

properly as at the end of the command an
NVIC_SystemReset is done instead of a Flash
V13.5 Initial bootloader version
option bytes reload.
This makes the change of the RDP level not
effective until a power off power on.

Note: Instability when performing multiple resets during operations ongoing causing Overrun or
FrameError errors on USART Bootloader and not recoverable unless Hardware Reset is
performed. Fixed by workaround in FUS V1.0.1 and V1.0.2.

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64 STM32WLE5xx devices bootloader

64.1 Bootloader configuration

The STM32WLE5xx bootloader is activated by applying Pattern 13 (described in Table 2:
Bootloader activation patterns). Table 139 shows the hardware resources used by this
bootloader.

Table 139. STM32WLE5xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 48 MHz

RCC HSI enabled
(using PLL clocked by HSI).
8 Kbytes starting from address
RAM - 0x20000000 are used by the bootloader
firmware
16 Kbytes starting from address
Common to all System memory - 0x1FFF0000, contain the bootloader
bootloaders firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized the USART1
USART1 Enabled configuration is: 8-bit, even parity and 1
USART1 Stop bit
bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART1
USART2 Enabled configuration is: 8-bit, even parity and 1
USART2 Stop bit
bootloader
USART2_RX pin Input PA3 pin: USART1 in reception mode
USART2_TX pin Output PA2 pin: USART1 in transmission mode

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Table 139. STM32WLE5xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

– Slave mode
– Full Duplex
SPI1 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
SPI1 bootloader push-pull pull-down mode
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
push-pull pull-down mode
PA5 pin: Slave clock line, used in push-
SPI1_SCK pin Input
pull pull-down mode
PA4 pin: slave chip select pin used in
push-pull pull-up mode.
SPI1_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
SPI2 bootloader push-pull pull-down mode
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
push-pull pull-down mode
PB13 pin: Slave clock line, used in push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
push-pull pull-up mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.

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64.2 Bootloader selection

Figure 88 shows the bootloader selection mechanism.

Figure 88. Bootloader V12.x selection for STM32WLE5xx

System Reset

Disable all
interrupt sources

System Init (Clock, GPIOs,

IWDG, SysTick)

Configure SPIx

0x7F received
yes
on USARTx

Disable all other

yes interfaces clocks
no

Disable all other Configure

interfaces clocks USARTx
SPIx detects
no Synchro
mechanism Execute Execute
BL_SPI_Loop BL_USART_Loop
for SPIx for USARTx

MSv38476V1

64.3 Bootloader version

Table 140. STM32WLE5xx bootloader versions
Bootloader
version Description Known limitations
number

V12.2 Initial bootloader version on cut 1.1 samples None

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65 Device-dependent bootloader parameters

The bootloader protocol command set and sequences for each serial peripheral are the
same for all STM32 devices. However, some parameters depend on device and bootloader
version:
 PID (Product ID)
 Valid RAM memory addresses (RAM area used during bootloader execution is not
accessible) accepted by the bootloader when the Read Memory, Go and Write Memory
commands are requested.
 System Memory area.
Table 141 shows the values of these parameters for each STM32 device.

Table 141. Bootloader device-dependent parameters

STM32 System
Device PID BL ID RAM
Series memory

0x20000800 -
STM32F05xxx and STM32F030x8 0x440 0x21
0x20001FFF 0x1FFFEC00 -
0x20000800 - 0x1FFFF7FF
STM32F03xx4/6 0x444 0x10
0x20000FFF
0x20001800 - 0x1FFFD800 -
STM32F030xC 0x442 0x52
0x20007FFF 0x1FFFF7FF
0x1FFFC400 -
STM32F04xxx 0x445 0xA1 NA
0x1FFFF7FF
F0
0x1FFFC400 -
STM32F070x6 0x445 0xA2 NA
0x1FFFF7FF
0x1FFFC800 -
STM32F070xB 0x448 0xA2 NA
0x1FFFF7FF
0x20001800 - 0x1FFFC800 -
STM32F071xx/072xx 0x448 0xA1
0x20003FFF 0x1FFFF7FF
0x1FFFD800 -
STM32F09xxx 0x442 0x50 NA
0x1FFFF7FF

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Table 141. Bootloader device-dependent parameters (continued)

STM32 System
Device PID BL ID RAM
Series memory

0x20000200 -
Low-density 0x412 NA
0x200027FF
0x20000200 -
Medium-density 0x410 NA
0x20004FFF
0x20000200 - 0x1FFFF000 -
STM32F10xxx High-density 0x414 NA
0x2000FFFF 0x1FFFF7FF
Medium-density value 0x20000200 -
F1 0x420 0x10
line 0x20001FFF
0x20000200 -
High-density value line 0x428 0x10
0x20007FFF
0x20001000 - 0x1FFFB000 -
STM32F105xx/107xx 0x418 NA
0x2000FFFF 0x1FFFF7FF
0x20000800 - 0x1FFFE000 -
STM32F10xxx XL-density 0x430 0x21
0x20017FFF 0x1FFFF7FF
0x20 0x20002000 - 0x1FFF0000 -
F2 STM32F2xxxx 0x411
0x33 0x2001FFFF 0x1FFF77FF

0x20001400 -
STM32F373xx 0x41
0x20007FFF
0x432
0x20001000 -
STM32F378xx 0x50
0x20007FFF
STM32F302xB(C)/303xB(C) 0x41 0x20001400 -
0x422
STM32F358xx 0x50 0x20009FFF

STM32F301xx/302x4(6/8) 0x40 0x20001800 - 0x1FFFD800 -

F3 0x439
0x20003FFF 0x1FFFF7FF
STM32F318xx 0x50
STM32F303x4(6/8)/ 0x20001800 -
0x438 0x50
334xx/328xx 0x20002FFF
0x20001800 -
STM32F302xD(E)/303xD(E) 0x446 0x40
0x2000FFFF
0x20001800 -
STM32F398xx 0x446 0x50
0x2000FFFF

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Table 141. Bootloader device-dependent parameters (continued)

STM32 System
Device PID BL ID RAM
Series memory

0x20002000 -
0x31
0x2001FFFF
STM32F40xxx/41xxx 0x413
0x20003000 -
0x90
0x2001FFFF
0x70 0x20003000 -
STM32F42xxx/43xxx 0x419
0x91 0x2002FFFF

0x20003000 -
STM32F401xB(C) 0x423 0xD1
0x2000FFFF
0x20003000 -
STM32F401xD(E) 0x433 0xD1
0x20017FFF
0x20003000 - 0x1FFF0000 -
F4 STM32F410xx 0x458 0xB1
0x20007FFF 0x1FFF77FF

0x20003000 -
STM32F411xx 0x431 0xD0
0x2001FFFF
0x20003000 -
STM32F412xx 0x441 0x90
0x2003FFFF
0x20003000 -
STM32F446xx 0x421 0x90
0x2001FFFF
0x20003000 -
STM32F469xx/479xx 0x434 0x90
0x2005FFFF
0x20003000 -
STM32F413xx/423xx 0x463 0x90
0x2004FFFF
0x20004000 - 0x1FF00000 -
STM32F72xxx/73xxx 0x452 0x90
0x2003FFFF 0x1FF0EDBF
0x20004000 - 0x1FF00000 -
0x70
0x2004FFFF 0x1FF0EDBF
F7 STM32F74xxx/75xxx 0x449
0x20004000 - 0x1FF00000 -
0x90
0x2004FFFF 0x1FF0EDBF
0x20004000 - 0x1FF00000 -
STM32F76xxx/77xxx 0x451 0x93
0x2007FFFF 0x1FF0EDBF
0x20000000 - 0x1FFF0000 -
STM32G03xxx/04xxx 0x466 0x52
0x20000FFF 0x1FFF1FFF
G0
0x20000000 - 0x1FFF0000 -
STM32G07xxx/08xxx 0x460 0xB2
0x200026FF 0x1FFF6FFF
0x20000000 – 0x1FFF0000 -
STM32G431xx/441xx 0x468 0xD3
0x20004000 0x1FFF7000
G4
0x20000000 – 0x1FFF0000 -
STM32G47xxx/48xxx 0x469 0xD4
0x20004000 0x1FFF7000

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Table 141. Bootloader device-dependent parameters (continued)

STM32 System
Device PID BL ID RAM
Series memory

0x20004100 -
0x2001FFFF 0x1FF00000 -
STM32H72xxx/73xxx 0x483 0x91
0x24004000 - 0x1FF1E7FF
0x2404FFFF
0x20004100 -
0x2001FFFF 0x1FF00000 -
H7 STM32H74xxx/75xxx 0x450 0x90
0x24034000 - 0x1FF1E7FF
0x2407FFFF
0x20004100 -
0x2001FFFF 0x1FF00000 -
STM32H7A3xx/B3xx 0x480 0x90
0x24034000 - 0x1FF13FFF
0x2407FFFF
0x1FF00000 -
STM32L01xxx/02xxx 0x457 0xC3 NA
0x1FF00FFF
0x20001000 - 0x1FF00000 -
STM32L031xx/041xx 0x425 0xC0
0x20001FFF 0x1FF00FFF
0x20001000 - 0x1FF00000 -
L0 STM32L05xxx/06xxx 0x417 0xC0
0x20001FFF 0x1FF00FFF
0x20001000 -
0x41
0x20004FFF 0x1FF00000 -
STM32L07xxx/08xxx 0x447
0x20001400 - 0x1FF01FFF
0xB2
0x20004FFF
0x20000800 -
STM32L1xxx6(8/B) 0x416 0x20
0x20003FFF
STM32L1xxx6(8/B)A 0x429 0x20 0x20001000 -
STM32L1xxxC 0x427 0x40 0x20007FFF 0x1FF00000 -
L1
0x1FF01FFF
0x20001000 -
STM32L1xxxD 0x436 0x45
0x2000BFFF
0x20001000 -
STM32L1xxxE 0x437 0x40
0x20013FFF

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Table 141. Bootloader device-dependent parameters (continued)

STM32 System
Device PID BL ID RAM
Series memory

0x20000000 - 0x1FFF0000 -
STM32L412xx/422xx 0x464 0xD1
0x200020FF 0x1FFF6FFF
0x20003100 - 0x1FFF0000 -
STM32L43xxx/44xxx 0x435 0x91
0x2000BFFF 0x1FFF6FFF
0x20003100 - 0x1FFF0000 -
STM32L45xxx/46xxx 0x462 0x92
0x2001FFFF 0x1FFF6FFF
0x20003000 -
0xA3
0x20017FFF 0x1FFF0000 -
L4 STM32L47xxx/48xxx 0x415
0x20003100 - 0x1FFF6FFF
0x92
0x20017FFF
0x20003100 - 0x1FFF0000 -
STM32L496xx/4A6xx 0x461 0x93
0x2003FFFF 0x1FFF6FFF
0x20003200 - 0x1FFF0000 -
STM32L4Rxx/4Sxx 0x470 0x95
0x2009FFFF 0x1FFF6FFF
0x20004000 - 0x1FFF0000 -
STM32L4P5xx /Q5xx 0x471 0x90
0x2004FFFF 0x1FFF6FFF
0x20000000 - 0x0BF90000 -
L5 STM32L552xx/562xx 0x472 0x92
0x20004000 0x0BF97FFF
0x20000000 – 0x1FFF0000 -
WB STM32WB50xx/WB55xx 0x495 0xD5
0x20005000 0x1FFF7000
0x20000000 – 0x1FFF0000 -
WL STM32WLE5xx 0x497 0xC2
0x20001FFF 0x1FFF3FFF

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66 Bootloader timings

This section presents the typical timings of the bootloader firmware to be used to ensure
correct synchronization between host and STM32 device.
Two types of timings are described:
 STM32 device bootloader resources initialization duration.
 Communication interface selection duration.
After these timings the bootloader is ready to receive and execute host commands.

66.1 Bootloader startup timing

After bootloader reset, the host must wait until the STM32 bootloader is ready to start
detection phase with a specific interface communication. This time corresponds to
bootloader startup timing, during which resources used by bootloader are initialized.

Figure 89. Bootloader Startup timing description

Table 142. Bootloader startup timings (ms) for STM32 devices

Minimum bootloader
Device HSE timeout
startup

STM32F03xx4/6 1.612 NA
STM32F05xxx and STM32F030x8 devices 1.612 NA
STM32F04xxx 0.058 NA
STM32F071xx/072xx 0.058 NA
HSE connected 3
STM32F070x6 200
HSE not connected 230
HSE connected 6
STM32F070xB 200
HSE not connected 230

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Table 142. Bootloader startup timings (ms) for STM32 devices (continued)
Minimum bootloader
Device HSE timeout
startup

STM32F09xxx 2 NA
STM32F030xC 2 NA
STM32F10xxx 1.227 NA
PA9 pin low 1.396
STM32F105xx/107xx NA
PA9 pin high 524.376
STM32F10xxx XL-density 1.227 NA
V2.x 134 NA
STM32F2xxxx
V3.x 84.59 0.790
HSE connected 45
STM32F301xx/302x4(6/8) 560.5
HSE not connected 560.8
HSE connected 43.4
STM32F302xB(C)/303xB(C) 2.236
HSE not connected 2.36
HSE connected 7.53 NA
STM32F302xD(E)/303xD
HSE not connected 146.71 NA
STM32F303x4(6/8)/334xx/328xx 0.155 NA
STM32F318xx 0.182 NA
STM32F358xx 1.542 NA
HSE connected 43.4
STM32F373xx 2.236
HSE not connected 2.36
STM32F378xx 1.542 NA
STM32F398xx 1.72 NA
V3.x 84.59 0.790
STM32F40xxx/41xxx
V9.x 74 96
STM32F401xB(C) 74.5 85
STM32F401xD(E) 74.5 85
STM32F410xx 0.614 NA
STM32F411xx 74.5 85
STM32F412xx 0.614 180
STM32F413xx/423xx 0.642 165
V7.x 82 97
STM32F429xx/439xx
V9.x 74 97
STM32F446xx 73.61 96
STM32F469xx/479xx 73.68 230
STM32F72xxx/73xxx 17.93 50

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Table 142. Bootloader startup timings (ms) for STM32 devices (continued)
Minimum bootloader
Device HSE timeout
startup

STM32F74xxx/75xxx 16.63 50
STM32G03xxx/04xxx 0.390 NA
STM32G07xxx/08xxx 0.390 NA
STM32G4xxxx 0.390 NA
STM32H72xxx/73xxx 53.975 NA
STM32H74xxx/75xxx 53.975 2
STM32H7A3xx/B3xx 53.975 NA
STM32L01xxx/02xxx 0.63 NA
STM32L031xx/041xx 0.62 NA
STM32L05xxx/06xxx 0.22 NA
V4.x 0.61 NA
STM32L07xxx/08xxx
V11.x 0.71 NA
STM32L1xxx6(8/B)A 0.542 NA
STM32L1xxx6(8/B) 0.542 NA
STM32L1xxxC 0.708 80
STM32L1xxxD 0.708 80
STM32L1xxxE 0.708 200
STM32L43xxx/44xxx 0.3335 100
STM32L45xxx/46xxx 50.93 NA
LSE connected 55
V10.x 100
LSE not connected 2560
STM32L47xxx/48xxx
LSE connected 55.40
V9.x 100
LSE not connected 2560.51
STM32L412xx/422xx 0.12 NA
STM32L496xx/4A6xx 76.93 100
STM32L4P5xx /Q5xx NA NA
STM32L4Rxx/4Sxx NA NA
STM32L552xx/562xx 0.390 NA
STM32WB50xx/55xx 0.390 NA
STM32WLE5xx 0.390 NA

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66.2 USART connection timing

USART connection timing is the time that the host must wait for between sending the
synchronization data (0x7F) and receiving the first acknowledge response (0x79).

Figure 90. USART connection timing description

Host Host
sends receives
0x7F 0x79 (ACK)

a b a
Bootloader
execution time

Device Device Bootloader

receives sends ACK ready to receive
0x7F byte 0x79 and execute
commands

a Duration of 1 byte sending through USART (depends on Baudrate)

b Duration of USART peripheral configuration MS35041V1

1. Receiving any other character different from 0x7F (or line glitches) will cause bootloader to start
communication using a wrong baudrate. Bootloader measures the signal length between rising edge of first
1 bit in 0x7F to the falling edge of the last 1 bit in 0x7F to deduce the baudrate value
2. Bootloader does not re-align the calculated baudrate to standard baudrate values (i.e. 1200, 9600,
115200..).
Note: For STM32F105xx/107xx line devices, PA9 pin (USB_VBUS) is used to detect the USB host
connection. The initialization of USB peripheral is performed only if PA9 is high at detection
phase which means that a host is connected to the port and delivering 5 V on the USB bus.
When PA9 level is high at detection phase, more time is required to initialize and shutdown
the USB peripheral. To minimize bootloader detection time when PA9 pin is not used, keep
PA9 state low during USART detection phase from the moment the device is reset until a
device ACK is sent.

Table 143. USART bootloader minimum timings (ms) for STM32 devices
One USART USART USART
Device
byte sending configuration connection

STM32F03xx4/6 0.078125 0.0064 0.16265

STM32F05xxx and STM32F030x8 devices 0.078125 0.0095 0.16575
STM32F04xxx 0.078125 0.007 0.16325
STM32F071xx/072xx 0.078125 0.007 0.16325
STM32F070x6 0.078125 0.014 0.17
STM32F070xB 0.078125 0.08 0.23
STM32F09xxx 0.078125 0.07 0.22
STM32F030xC 0.078125 0.07 0.22

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Table 143. USART bootloader minimum timings (ms) for STM32 devices (continued)
One USART USART USART
Device
byte sending configuration connection

STM32F10xxx 0.078125 0.002 0.15825

PA9 pin low 0.007 0.16325
STM32F105xx/107xx 0.078125
PA9 pin High 105 105.15625
STM32F10xxx XL-density 0.078125 0.006 0.16225
V2.x
STM32F2xxxx 0.078125 0.009 0.16525
V3.x
HSE connected
STM32F301xx/302x4(6/8) 0.078125 0.002 0.15825
HSE not connected
HSE connected
STM32F302xB(C)/303xB(C) 0.078125 0.002 0.15825
HSE not connected
STM32F302xD(E)/303xD 0.078125 0.002 0.15885
STM32F303x4(6/8)/334xx/328xx 0.078125 0.002 0.15825
STM32F318xx 0.078125 0.002 0.15825
STM32F358xx 0.15625 0.001 0.3135
HSE connected
STM32F373xx 0.078125 0.002 0.15825
HSE not connected
STM32F378xx 0.15625 0.001 0.3135
STM32F398xx 0.078125 0.002 0.15885
V3.x 0.009 0.16525
STM32F40xxx/41xxx 0.078125
V9.x 0.0035 0.15975
STM32F401xB(C) 0.078125 0.00326 0.15951
STM32F401xD(E) 0.078125 0.00326 0.15951
STM32F410xx 0.078125 0.002 0.158
STM32F411xx 0.078125 0.00326 0.15951
STM32F412xx 0.078125 0.002 0.158
STM32F413xx/423xx 0.078125 0.002 0.158
V7.x 0.007 0.16325
STM32F429xx/439xx 0.078125
V9.x 0.00326 0.15951
STM32F446xx 0.078125 0.004 0.16
STM32F469xx/479xx 0.078125 0.003 0.159
STM32F72xxx/73xxx 0.078125 0.070 0.22
STM32F74xxx/75xxx 0.078125 0.065 0.22
STM32G03xxx/04xxx 0.078125 0.01 0.11
STM32G07xxx/08xxx 0.078125 0.01 0.11

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Table 143. USART bootloader minimum timings (ms) for STM32 devices (continued)
One USART USART USART
Device
byte sending configuration connection

STM32G4xxxx 0.078125 0.003 0.159

STM32H72xxx/73xxx 0.078125 0.072 0.22825
STM32H74xxx/75xxx 0.078125 0.072 0.22825
STM32H7A3xx/B3xx 0.078125 0.072 0.22825
STM32L01xxx/02xxx 0.078125 0.016 0.17
STM32L031xx/041xx 0.078125 0.018 0.174
STM32L05xxx/06xxx 0.078125 0.018 0.17425
V4.x 0.078125 0.017 0.173
STM32L07xxx/08xxx
V11.x 0.078125 0.017 0.158
STM32L1xxx6(8/B)A 0.078125 0.008 0.16425
STM32L1xxx6(8/B) 0.078125 0.008 0.16425
STM32L1xxxC 0.078125 0.008 0.16425
STM32L1xxxD 0.078125 0.008 0.16425
STM32L1xxxE 0.078125 0.008 0.16425
STM32L412xx/422xx 0.078125 0.005 0.2
STM32L43xxx/44xxx 0.078125 0.003 0.159
STM32L45xxx/46xxx 0.078125 0.07 0.22
V10.x 0.078125 0.003 0.159
STM32L47xxx/48xxx
V9.x 0.078125 0.003 0.159
STM32L496xx/4A6xx 0.078125 0.003 0.159
STM32L4Rxx/4Sxx NA NA NA
STM32L4P5xx/4Q5xx NA NA NA
STM32L552xx/562xx 0.078125 0.01 0.11
STM32WB50xx/55xx 0.078125 0.003 0.159
STM32WLE5xx 0.078125 0.001 0.110

66.3 USB connection timing

USB connection timing is the time that the host must wait for between plugging the USB
cable and establishing a correct connection with the device. This timing includes
enumeration and DFU components configuration. USB connection depends on the host.

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Figure 91. USB connection timing description

Device
reset

a
Bootloader
execution time

Bootloader
ready to start
detection phase

a Duration of Bootloader resources initialization

MSv35042V1

Note: For STM32F105xx/107xx devices, if the external HSE crystal frequency is different from
25 MHz (14.7456 MHz or 8 MHz), the device performs several unsuccessful enumerations
(with connect / disconnect sequences) before being able to establish a correct connection
with the host. This is due to the HSE automatic detection mechanism based on Start Of
Frame (SOF) detection.

Table 144. USB bootloader minimum timings (ms) for STM32 devices
Device USB connection

STM32F04xxx 350
STM32F070x6 TBD
STM32F070xB 320
HSE = 25 MHz 460
STM32F105xx/107xx HSE = 14.7465 MHz 4500
HSE = 8 MHz 13700
STM32F2xxxx 270
STM32F301xx/302x4(6/8) 300
STM32F302xB(C)/303xB(C) 300
STM32F302xD(E)/303xD 100
STM32F373xx 300
V3.x 270
STM32F40xxx/41xxx
V9.x 250
STM32F401xB(C) 250
STM32F401xD(E) 250
STM32F411xx 250
STM32F412xx 380
STM32F413xx/423xx 350

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Table 144. USB bootloader minimum timings (ms) for STM32 devices (continued)
Device USB connection

V7.x
STM32F429xx/439xx 250
V9.x
STM32F446xx 200
STM32F469xx/479xx 270
STM32F72xxx/73xxx 320
STM32F74xxx/75xxx 230
STM32G4xxxx 300
STM32H72xxx/73xxx 53.9764
STM32H74xxx/75xxx 53.9764
STM32H7A3xx/B3xx 53.9764
STM32L07xxx/08xxx 140
STM32L1xxxC 849
STM32L1xxxD 849
STM32L412xx/422xx 820
STM32L43xxx/44xxx 820
STM32L45xxx/46xxx 330
V10.x
STM32L47xxx/48xxx 300
V9.x
STM32L496xx/4A6xx 430
STM32L4P5xx/4Q5xx NA
STM32L4Rxx/4Sxx NA
STM32L552xx/L562xx 300
STM32WB50xx/55xx 300

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66.4 I2C connection timing

I2C connection timing is the time that the host must wait for between sending I2C device
address and sending command code. This timing includes I2C line stretching duration.

Figure 92. I2C connection timing description

Host sends start Host receives

condition + acknowledge
device address

a b
Bootloader
execution time

Device Bootloader
acknowledges its ready to receive
address and and execute
stretch line commands

a
Duration of start + 1 byte sending through I2C (depends on communication speed)
b Duration of I2C line stretching
MS35043V1

Note: For I2C communication, a timeout mechanism is implemented and it must be respected to
execute bootloader commands correctly. This timeout is implemented between two I2C
frames in the same command (eg: for Write memory command a timeout is inserted
between command sending frame and address memory sending frame). Also the same
timeout period is inserted between two successive data receptions or transmissions in the
same I2C frame. If the timeout period is elapsed a system reset is generated to avoid
bootloader crash.
In erase memory command and read-out unprotect command, the duration of the operation
must be taken into consideration when implementing the host side. After sending the code
of pages to be erased, the host must wait until the bootloader device performs page erasing
to complete the remaining steps of erase command.

Table 145. I2C bootloader minimum timings (ms) for STM32 devices
Start condition
I2C line
Device + one I2C byte I2C connection I2C timeout
stretching
sending

STM32F04xxx 0.0225 0.0025 0.0250 1000

STM32F070x6 0.0225 0.0025 0.0245 1000
STM32F070xB 0.0225 0.0025 0.0245 1000
STM32F071xx/072xx 0.0225 0.0025 0.0250 1000
STM32F09xxx 0.0225 0.0025 0.0245 1000
STM32F030xC 0.0225 0.0025 0.0250 1000
STM32F303x4(6/8)/334xx/328xx 0.0225 0.0027 0.0252 1000

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Table 145. I2C bootloader minimum timings (ms) for STM32 devices (continued)
Start condition
I2C line
Device + one I2C byte I2C connection I2C timeout
stretching
sending

STM32F318xx 0.0225 0.0027 0.0252 1000

STM32F358xx 0.0225 0.0055 0.0280 10
STM32F378xx 0.0225 0.0055 0.0280 10
STM32F398xx 0.0225 0.0020 0.0245 1500
STM32F40xxx/41xxx 0.0225 0.0022 0.0247 1000
STM32F401xB(C) 0.0225 0.0022 0.0247 1000
STM32F401xD(E) 0.0225 0.0022 0.0247 1000
STM32F410xx 0.0225 0.0020 0.0245 1000
STM32F411xx 0.0225 0.0022 0.0247 1000
STM32F412xx 0.0225 0.0020 0.0245 1000
STM32F413xx/423xx 0.0225 0.0020 0.0245 1000
V7.x 0.0225 0.0033 0.0258 1000
STM32F42xxx/43xxx
V9.x 0.0225 0.0022 0.0247 1000
STM32F446xx 0.0225 0.0020 0.0245 1000
STM32F469xx/479xx 0.0225 0.0020 0.0245 1000
STM32F72xxx/73xxx 0.0225 0.0020 0.0245 1000
STM32F74xxx/75xxx 0.0225 0.0020 0.0245 500
STM32G03xxx/04xxx 0.0225 0.0020 0.0245 1000
STM32G07xxx/08xxx 0.0225 0.0020 0.0245 1000
STM32G4xxxx 0.0225 0.0020 0.0245 1000
STM32H72xxx/73xxx 0.0225 0.05 0.0745 1000
STM32H74xxx/75xxx 0.0225 0.05 0.0725 1000
STM32H7A3xx/7B3xx 0.0225 0.05 0.0745 1000
STM32L07xxx/08xxx 0.0225 0.0020 0.0245 1000
STM32L412xx/422xx 0.0225 0.0020 0.o245 1000
STM32L43xxx/44xxx 0.0225 0.0020 0.0245 1000
STM32L45xxx/46xxx 0.0225 0.0020 0.0245 1000
V10.x 0.0225 0.0020 0.0245 1000
STM32L47xxx/48xxx
V9.x 0.0225 0.0020 0.0245 1000
STM32L496xx/4A6xx 0.0225 0.0020 0.0245 1000
STM32L4P5xx/4Q5xx NA NA NA NA
STM32L4Rxx/4Sxx NA NA NA NA

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Table 145. I2C bootloader minimum timings (ms) for STM32 devices (continued)
Start condition
I2C line
Device + one I2C byte I2C connection I2C timeout
stretching
sending

STM32L552xx/L562xx 0.0225 0.0020 0.0245 1000

STM32WB50xx/55xx 0.0225 0.0020 0.0245 1000

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66.5 SPI connection timing

SPI connection timing is the time that the host must wait for between sending the
synchronization data (0xA5) and receiving the first acknowledge response (0x79).

Figure 93. SPI connection timing description

Host Host receives

sends ACK byte
0x5A 0x79

a b a
Bootloader
execution time

Device Device Bootloader

receives sends ACK ready to receive
0x5A byte 0x79 and execute
commands

a Duration of 1 byte sending through SPI (depends on communication speed)

b Delay between two bytes MS35044V1

Table 146. SPI bootloader minimum timings (ms) for STM32 devices
Device One SPI byte sending Delay between two bytes SPI connection

All products 0.001 0.008 0.01

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Example of function to use the “ExitSecureMemory” function AN2606

Appendix A Example of function to use the

“ExitSecureMemory” function

/**
**************************************************************************
****
* @file main.c
**************************************************************************
****
*/

/* Includes ---------------------------------------------------------------
---*/
#include "main.h"

/* Private function prototypes --------------------------------------------

---*/
static void ConfigClock(void);

void JUMP_WITHOUT_PARAM(uint32_t jump_address);

void JUMP_WITH_PARAM(uint32_t jump_address, uint32_t magic, uint32_t
applicationVectorAddress);

/* Private functions ------------------------------------------------------

---*/

/**
* @brief Main program
* @param None
* @retval None
*/
int main(void)
{
ConfigClock();

uint32_t application_address = 0x08000800;

uint32_t exit_secure_memory_address = 0x1FFF1E00;
uint32_t magic_number = 0x08192A3C;
uint32_t exit_with_magic_number = 0x0;

if (exit_with_magic_number)
{
JUMP_WITH_PARAM(exit_secure_memory_address, magic_number,
application_address);
}

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else
{
JUMP_WITHOUT_PARAM(exit_secure_memory_address);
}
}

/**
* @brief ConfigClock
* @param None
* @retval None
*/
static void ConfigClock(void)
{
/* Will be developped as per the template of the needed project */
}

/**
* @brief JUMP_WITHOUT_PARAM
* @param jump_address
* @retval None
*/
void JUMP_WITHOUT_PARAM(uint32_t jump_address)
{
asm ("LDR R1, [R0]"); // jump_address
asm ("LDR R2, [R0,#4]");
asm ("MOV SP, R1");
asm ("BX R2");
}

/**
* @brief JUMP_WITH_PARAM
* @param jump_address, magic, applicationVectorAddress
* @retval None
*/
void JUMP_WITH_PARAM(uint32_t jump_address, uint32_t magic, uint32_t
applicationVectorAddress))
{
asm ("MOV R3, R0"); // jump_address
asm ("LDR R0, [R3]");
asm ("MOV SP, R0");
asm ("LDR R0, [R3,#4]");
asm ("BX R0");
}

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/************************ (C) COPYRIGHT STMicroelectronics *****END OF

FILE****/

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67 Revision history

Table 147. Document revision history

Date Revision Changes

22-Oct-2007 1 Initial release.

All STM32 in production (rev. B and rev. Z) include the bootloader described in this
application note.
Modified: Section 3.1: Bootloader activation and Section 1.4: Bootloader code
sequence.
Added: Section 1.3: Hardware requirements, Section 1.5: Choosing the USART baud
22-Jan-2008 2 rate, Section 1.6: Using the bootloader and Section:
Note 2 linked to Get, Get Version & Read Protection Status and Get ID commands in
Table 3: Bootloader commands, Note 3 added.
Notion of “permanent” (Permanent Write Unprotect/Readout Protect/Unprotect)
removed from document. Small text changes.
Bootloader version upgraded to 2.0.
Small text changes. RAM and System memory added to Table : The system clock is
derived from the embedded internal high-speed RC, no external quartz is required for
the bootloader execution.
Section 1.6: Using the bootloader on page 8 removed.
Erase modified, Note 3 modified and Note 1 added in Table 3: Bootloader commands
on page 9.
Byte 3: on page 11 modified.
Byte 2: on page 13 modified.
Byte 2:, Bytes 3-4: and Byte 5: on page 15 modified, Note 3 modified.
Byte 8: on page 18 modified.
Notes added to Section 2.5: Go command on page 18.
26-May-2008 3 Figure 11: Go command: device side on page 20 modified.
Note added in Section 2.6: Write Memory command on page 21.
Byte 8: on page 24 modified.
Figure 14: Erase Memory command: host side and Figure 15: Erase Memory
command: device side modified.
Byte 3: on page 26 modified.
Table 3: Bootloader commands on page 9.
Note modified and note added in Section 2.8: Write Protect command on page 27.
Figure 16: Write Protect command: host side, Figure 17: Write Protect command:
device side, Figure 19: Write Unprotect command: device side, Figure 21: Readout
Protect command: device side and Figure 23: Readout Unprotect command: device
side modified.
This application note also applies to the STM32F102xx microcontrollers.
29-Jan-2009 4
Bootloader version updated to V2.2 (see Table 4: Bootloader versions).

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371
Revision history AN2606

Table 147. Document revision history (continued)

Date Revision Changes

IWDG added to Table : The system clock is derived from the embedded internal high-
speed RC, no external quartz is required for the bootloader execution.. Note added.
BL changed bootloader in the entire document.
Go command description modified in Table : The system clock is derived from the
embedded internal high-speed RC, no external quartz is required for the bootloader
execution.
Number of bytes awaited by the bootloader corrected in Section 2.4: Read Memory
command.
Note modified below Figure 10: Go command: host side.
19-Nov-2009 5
Note removed in Section 2.5: Go command and note added.
Start RAM address specified and note added in Section 2.6: Write Memory command.
All options are erased when a Write Memory command is issued to the Option byte
area.
Figure 11: Go command: device side modified.
Figure 13: Write Memory command: device side modified.
Note added and bytes 3 and 4 sent by the host modified in Section 2.7: Erase Memory
command.
Note added to Section 2.8: Write Protect command.
Application note restructured. Value line and connectivity line device bootloader added
09-Mar-2010 6 (Replaces AN2662).
Introduction changed. Glossary added.
Related documents: added XL-density line datasheets and programming manual.
Glossary: added XL-density line devices.
Table 3: added information for XL-density line devices.
20-Apr-2010 7 Section 4.1: Bootloader configuration: updated first sentence.
Section 5.1: Bootloader configuration: updated first sentence.
Added Section 6: STM32F10xxx XL-density devices bootloader.
Table 65: added information for XL-density line devices.
08-Oct-2010 8 Added information for high-density value line devices in Table 3 and Table 65.
14-Oct-2010 9 Removed references to obsolete devices.
26-Nov-2010 10 Added information on ultralow power devices.
Added information related to STM32F205/215xx and STM32F207/217xx devices.
13-Apr-2011 11
Added Section 32: Bootloader timing
Updated:
– Table 12: STM32L1xxx6(8/B) bootloader versions
06-Jun-2011 12 – Table 17: STM32F2xxxx configuration in System memory boot mode
– Table 18: STM32F2xxxx bootloader V2.x versions
– Table 20: STM32F2xxxx bootloader V3.x versions
Added information related to STM32F405/415xx and STM32F407/417xx bootloader,
and STM32F105xx/107xx bootloader V2.1.
28-Nov-2011 13
Added value line devices in Section 4: STM32F10xxx devices bootloader title and
overview.

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Table 147. Document revision history (continued)

Date Revision Changes

Added information related to STM32F051x6/STM32F051x8 and to High-density

ultralow power STM32L151xx, STM32L152xx bootloader.
Added case of BOOT1 bit in Section 3.1: Bootloader activation.
Updated Connectivity line, High-density ultralow power line, STM32F2xx and
STM32F4xx in Table 3: Embedded bootloaders.
Added bootloader version V2.2 in Table 8: STM32F105xx/107xx bootloader versions.
Added bootloader V2.2 in Section 5.3.1: How to identify STM32F105xx/107xx
bootloader versions.
Added note related to DFU interface below Table 15: STM32L1xxxx high-density
configuration in System memory boot mode. Added V4.2 bootloader know limitations
and updated description, and added V4.5 bootloader in Table 16: STM32L1xxxx high-
density bootloader versions.
Added note related to DFU interface below Table 19: STM32F2xxxx configuration in
30-Jul-2012 14 System memory boot mode. Added V3.2 bootloader know limitations, and added V3.3
bootloader in Table 20: STM32F2xxxx bootloader V3.x versions. Updated STM32F2xx
and STM32F4xx system memory end address in Table 21: STM32F40xxx/41xxx
configuration in System memory boot mode.
Added note related to DFU interface below Table 21: STM32F40xxx/41xxx
configuration in System memory boot mode. Added V3.0 bootloader know limitations,
and added V3.1 bootloader in Table 22: STM32F40xxx/41xxx bootloader V3.x version.
Added bootloader V2.1 know limitations in Table 26: STM32F051xx bootloader
versions.
Updated STM32F051x6/x8 system memory end address in Table 65: Bootloader
device-dependent parameters.
Added Table 75: USART bootloader timings for high-density ultralow power devices,
and Table 78: USART bootloader timings for STM32F051xx devices.
Added Table 88: USB minimum timings for high-density ultralow power devices.
Updated generic product names throughout the document (see Glossary).
Added the following new sections:
– Section 8: STM32L1xxxC devices bootloader.
– Section 13: STM32F031xx devices bootloader.
– Section 14: STM32F373xx devices bootloader.
– Section 15: STM32F302xB(C)/303xB(C) devices bootloader.
– Section 16: STM32F378xx devices bootloader.
– Section 17: STM32F358xx devices bootloader.
– Section 18: STM32F427xx/437xx devices bootloader.
24-Jan-2013 15 – Section 34.3: I2C bootloader timing characteristics.
Updated Section 1: Related documents and Section 2: Glossary.
Added Table 79 to Table 85 (USART bootloader timings).
Replaced Figure 6 to Figure 16, and Figures 18, 19 and 42.
Modified Tables 3, 5, 9, 11, 17, 20, 21, 22 to 13, 27, 29, 31, 33, 35, 37 and 65.
Removed “X = 6: one USART is used” in Section 3.3: Hardware connection
requirement.
Replaced address 0x1FFFF 8002 with address 0x1FFF F802 in Section 12.1:
Bootloader configuration.
Modified procedure related to execution of the bootloader code in Note: on page 28, in
Section 6.2: Bootloader selection and in Section 9.2: Bootloader selection.

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Revision history AN2606

Table 147. Document revision history (continued)

Date Revision Changes

I2
Added information related to C throughout the document.
Streamlined Table 1: Applicable products and Section 1: Related documents.
Modified Table 3: Embedded bootloaders as follows:
– Replaced "V6.0" with "V1.0"
– Replaced "0x1FFFF7A6" with "0x1FFFF796" in row STM32F31xx
– Replaced "0x1FFF7FA6" with "0x1FFFF7A6" in row STM32F051xx
Updated figures 6, 9 and 11.
Added Note: in Glossary and Note: in Section 3.1: Bootloader activation.
Replaced:
06-Feb-2013 16 – "1.62 V" with "1.8 V" in tables17, 19, 19, 22, 21, 27, 37 and 59
– "5 Kbyte" with "4 Kbyte" in row RAM of Table 33
– "127 pages (2 KB each)" with "4 KB (2 pages of 2 KB each)" in rows F3 of Table 65
– "The bootloader ID is programmed in the last two bytes of the device system
memory" with "The bootloader ID is programmed in the last byte address - 1 of the
device system memory" in Section 3.3: Hardware connection requirement.
– "STM32F2xxxx devices revision Y" by "STM32F2xxxx devices revision X and Y" in
Section 10: STM32F2xxxx devices bootloader
– “Voltage Range 2” with “Voltage Range 1” in tables 11, 15 and 26.

Updated:
– Introduction
– Section 2: Glossary
– Section 3.3: Hardware connection requirement
– Section 7: STM32L1xxx6(8/B) devices bootloader to include STM32L100 value line
– Section 32.2: USART connection timing
– Section 34.2: USB bootloader timing characteristics
21-May-2013 17 – Section 34.3: I2C bootloader timing characteristics
– Table 1: Applicable products
– Table 3: Embedded bootloaders
– Table 25: STM32F051xx configuration in System memory boot mode
– Table 27: STM32F031xx configuration in System memory boot mode
– Table 65: Bootloader device-dependent parameters
– Figure 17: Bootloader selection for STM32F031xx devices
Added Section 19: STM32F429xx/439xx devices bootloader.

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Table 147. Document revision history (continued)

Date Revision Changes

Add:
– Figure 1 to Figure 5, Figure 69, Figure 8, Figure 27, Figure 28, Figure 26, from
Figure 40 to Figure 89, Figure 93
– Table 4, Table 117, Table 118, from Table 9 to Table 48, from Table 49 to Table 46,
from Table 71 to Table 72, from Table to Table 146
– Section 38.4, Section 33.2, Section 66.1, Section 66.5
– Section 5 ,Section 23, Section 24, Section 22, from Section 17 to Section 58
– note under Figure 1, Figure 2, Figure 3 and Figure 4
Updated:
19-May-2014 18 – Updated starting from Section 4 to Section 7 and Section 18, Section 33 and
Section 33 the chapter structure organized in three subsection: Bootloader
configuration, Bootloader selection and Bootloader version.
Updated Section 58 and Section 66
– Updated block diagram of Figure 27 and Figure 22.
– Fixed I2C address for STM32F429xx/439xx devices in Table 69
– Table 1, Table 2, Table 3, Table 27, Table 111, Table 113, Table 115, Table 31,
Table 33, Table 53, Table 141
– from Figure 16, to Figure 30, Figure 10, from Figure 89 to Figure 93
– note on Table 112
Updated:
– notes under Table 2
– Figure 68 and Figure 69
– Section 3: Glossary
– replaced any reference to STM32F427xx/437xx with STM32F42xxx/43xxx on
Section 33: STM32F42xxx/43xxx devices bootloader
– replace any occurrence of ‘STM32F072xx’ with ‘STM32F07xxx’
– replace any occurrence of ‘STM32F051xx’ with ‘STM32F051xx and STM32F030x8
devices’.
– comment field related to OTG_FS_DP and OTG_FS_DM on Table 27, Table 33,
Table 53, Table 117, Table 69, Table 71, Table 15, Table 21, Table 57, Table 59 and
29-Jul-2014 19 Table 63
– comment field related to USB_DM on Table 117.
– replace reference to "STM32F429xx/439xx" by "STM32F42xxx/43xxx” on Table 3
– comment field related to SPI2_MOSI, SPI2_MISO, SPI2_SCK and SPI2_NSS pins
on Table 71
Added:
– note under Table 2
– reference to STM32F411 on Table 1, Section 3: Glossary, Table 142, Table 143,
Table 144, Table 145
– Section 30: STM32F411xx devices bootloader
Removed reference to STM32F427xx/437xx on Table 3, Section 3: Glossary,
Table 141, Table 142, Table 143, Table 144
Updated:
– comment in “SPI1_NSS pin" and "SPI2_NSS pin" rows on Table 117 and Table 103
24-Nov-2014 20 – comment in "SPI1_NSS pin", "SPI2_NSS pin" and "SPI3_NSS pin" rows on Table 57,
Table 59 and Table 63
– Figure 1

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Table 147. Document revision history (continued)

Date Revision Changes

Updated:
– Table 1, Table 3, Table 25, Table 29, Table 111, Table 31, Table 33, Table 34,
Table 53, Table 117, Table 13, Table 14, Table 9, Table 37, Table 69, Table 71,
Table 15, Table 16, Table 21, Table 22,Table 35, Table 109, Table 125, Table 141,
Table 142, Table 143, Table 144 and Table 145
11-Mar-2015 21 – Figure 77
– Chapter 3: Glossary
– Section 4.1 and Section 4.4
Added:
– Section 58: STM32L47xxx/48xxx devices bootloader and Section 34: STM32F446xx
devices bootloader
Added:
– Section 9: STM32F070x6 devices bootloader
– Section 10: STM32F070xB devices bootloader
– Section 12: STM32F09xxx devices bootloader
– Section 19: STM32F302xD(E)/303xD(E) devices bootloaderSection 25:
STM32F398xx devices bootloader
– Section 36: STM32F72xxx/73xxx devices bootloader
– Section 58.2: Bootloader V9.x
09-Jun-2015 22
– Notes 1 and 2 on Figure 90
Updated:
– Table 1
– Section 3: Glossary
– Table 2
– Table 3
– Section 4.4: Bootloader memory management
– Table 141, Table 142, Table 143, Table 144 and Table 145
Added:
– Section 29: STM32F410xx devices bootloader
– Section 35: STM32F469xx/479xx devices bootloader
– Section 47: STM32L031xx/041xx devices bootloader
– Section 49: STM32L07xxx/08xxx devices bootloader
29-Sep-2015 23
Updated:
– Table 1
– Section 3: Glossary
– Table 3
– Figure 77, Table 127, Table 142, Table 143, Table 144, Table 145
Updated:
– Table 1, Table 3, Table 141, Table 142, Table 143, Table 144, Table 145
– Section 35
02-Nov-2015 24
Added:
– Note on Section 26.2.1
– Section 31

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Table 147. Document revision history (continued)

Date Revision Changes

Updated:
01-Dec-2015 25 – Section 4.1, Section 49
– Table 141
Updated:
– Table 1, Table 3, Table 66, Table 106, Table 108, Table 141
– Section 3, Section 49.1.1, Section 49.2.1, Section 58
03-Mar-2016 26
Added:
– Section 46: STM32L01xxx/02xxx devices bootloader
– Figure 61, Figure 63
Added:
– Section 38: STM32F76xxx/77xxx devices bootloader, Section 56:
STM32L43xxx/44xxx devices bootloader.
– Note on: Section 4.1: Bootloader activation, Section 8.1: Bootloader configuration,
Section 9.1: Bootloader configuration, Figure 38: Dual bank boot implementation for
STM32F42xxx/43xxx Bootloader V7.x, Figure 40: Dual bank boot implementation for
STM32F42xxx/43xxx bootloader V9.x
Updated:
– Table 1: Applicable products, Table 2: Bootloader activation patterns, Table 11:
STM32F030xC configuration in system memory boot mode, Table 17: STM32F070x6
21-Apr-2016 27 configuration in system memory boot mode, Table 19: STM32F070xB configuration
in system memory boot mode, Table 23: STM32F09xxx configuration in system
memory boot mode, Table 35: STM32F301xx/302x4(6/8) configuration in system
memory boot mode, Table 37: STM32F302xB(C)/303xB(C) configuration in system
memory boot mode, Table 39: STM32F302xD(E)/303xD(E) configuration in system
memory boot mode, Table 47: STM32F373xx configuration in system memory boot
mode, Table 57: STM32F401xB(C) configuration in system memory boot mode,
Table 59: STM32F401xD(E) configuration in system memory boot mode, Table 63:
STM32F411xx configuration in system memory boot mode, Table 126:
STM32L47xxx/48xxx bootloader V10.x versions, Table 128: STM32L47xxx/48xxx
bootloader V9.x versions, Table 141: Bootloader device-dependent parameters
– Section 3: Glossary,

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Revision history AN2606

Table 147. Document revision history (continued)

Date Revision Changes

Updated:
– Table 1: Applicable products, Table 11: STM32F030xC configuration in system
memory boot mode, Table 13: STM32F05xxx and STM32F030x8 devices
configuration in system memory boot mode, Table 15: STM32F04xxx configuration in
system memory boot mode, Table 17: STM32F070x6 configuration in system
memory boot mode, Table 19: STM32F070xB configuration in system memory boot
mode, Table 21: STM32F071xx/072xx configuration in system memory boot mode,
Table 23: STM32F09xxx configuration in system memory boot mode, Table 27:
STM32F105xx/107xx configuration in system memory boot mode, Table 29:
STM32F10xxx XL-density configuration in system memory boot mode, Table 31:
STM32F2xxxx configuration in system memory boot mode, Table 33: STM32F2xxxx
configuration in system memory boot mode, Table 35: STM32F301xx/302x4(6/8)
configuration in system memory boot mode, Table 37: STM32F302xB(C)/303xB(C)
configuration in system memory boot mode, Table 39: STM32F302xD(E)/303xD(E)
configuration in system memory boot mode, Table 41:
STM32F303x4(6/8)/334xx/328xx configuration in system memory boot mode,
Table 43: STM32F318xx configuration in system memory boot mode, Table 45:
STM32F358xx configuration in system memory boot mode, Table 47: STM32F373xx
configuration in system memory boot mode, Table 49: STM32F378xx configuration in
system memory boot mode, Table 51: STM32F398xx configuration in system
memory boot mode, Table 53: STM32F40xxx/41xxx configuration in system memory
boot mode, Table 55: STM32F40xxx/41xxx configuration in system memory boot
mode, Table 57: STM32F401xB(C) configuration in system memory boot mode,
Table 59: STM32F401xD(E) configuration in system memory boot mode, Table 63:
STM32F411xx configuration in system memory boot mode, Table 69:
05-Sep-2016 28
STM32F42xxx/43xxx configuration in system memory boot mode, Table 71:
STM32F42xxx/43xxx configuration in system memory boot modeTable 73:
STM32F446xx configuration in system memory boot mode, Table 75:
STM32F469xx/479xx configuration in system memory boot mode, Table 79:
STM32F74xxx/75xxx configuration in system memory boot mode, Table 81:
STM32F74xxx/75xxx configuration in system memory boot mode, Table 103:
STM32L05xxx/06xxx configuration in system memory boot mode, Table 109:
STM32L1xxx6(8/B)A configuration in system memory boot mode, Table 111:
STM32L1xxx6(8/B) configuration in system memory boot mode, Table 113:
STM32L1xxxC configuration in system memory boot mode, Table 115:
STM32L1xxxD configuration in system memory boot mode, Table 117:
STM32L1xxxE configuration in system memory boot mode, Table 122:
STM32L43xxx/44xxx bootloader versions, Table 125: STM32L47xxx/48xxx
configuration in system memory boot mode, Table 141: Bootloader device-dependent
parameters
– Section 56.1: Bootloader configuration
– Figure 24: Bootloader selection for STM32F303x4(6/8)/334xx/328xx, Figure 25:
Bootloader selection for STM32F318xx, Figure 27: Bootloader selection for
STM32F373xx devices, Figure 28: Bootloader selection for STM32F378xx devices,
Figure 31: Bootloader V9.x selection for STM32F40xxx/41xxx, Figure 34: Bootloader
V11.x selection for STM32F410xx, Figure 36: Bootloader V9.x selection for
STM32F412xx, Figure 44: Bootloader V9.x selection for STM32F469xx/479xx,
Figure 49: Bootloader V9.x selection for STM32F76xxx/77xxx, Figure 64: Bootloader
V11.x selection for STM32L07xxx/08xxx, Figure 77: Bootloader V10.x selection for
STM32L47xxx/48xxx

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Table 147. Document revision history (continued)

Date Revision Changes

Updated:
– Table 1: Applicable products, Section 3: Glossary, Section 4.1: Bootloader activation,
Table 3: Embedded bootloaders, Table 12: STM32F09xxx devices bootloader,
Table 14: STM32F105xx/107xx devices bootloader, Table 15: STM32F10xxx XL-
density devices bootloader, Table 16: STM32F2xxxx devices bootloader, Table 17:
STM32F301xx/302x4(6/8) devices bootloader, Table 18:
STM32F302xB(C)/303xB(C) devices bootloader, Table 20:
STM32F303x4(6/8)/334xx/328xx devices bootloader, Table 22: STM32F358xx
devices bootloader, Table 25: STM32F398xx devices bootloader, Table 29:
STM32F410xx devices bootloader, Table 32: STM32F413xx/423xx devices
bootloader, Table 59: STM32F401xD(E) configuration in system memory boot mode,
Section 14.3.1: How to identify STM32F105xx/107xx bootloader versions,
Section 28.1: Bootloader configuration, Table 61: STM32F410xx configuration in
system memory boot mode, Table 63: STM32F411xx configuration in system
07-Dec-2016 29 memory boot mode, Table 65: STM32F412xx configuration in system memory boot
mode, Section 30.1: Bootloader configuration, Table 70: STM32F42xxx/43xxx
bootloader V7.x versions, Table 72: STM32F42xxx/43xxx bootloader V9.x versions,
Table 83: STM32F76xxx/77xxx configuration in system memory boot mode,
Table 84: STM32F76xxx/77xxx bootloader V9.x versions, Table 100:
STM32L01xxx/02xxx bootloader versions, Table 108: STM32L07xxx/08xxx
bootloader V11.x versions, Table 121: STM32L43xxx/44xxx configuration in system
memory boot mode, Table 122: STM32L43xxx/44xxx bootloader versions, Table 126:
STM32L47xxx/48xxx bootloader V10.x versions, Table 141: Bootloader device-
dependent parameters, Table 142: Bootloader startup timings (ms) for STM32
devices, Table 144: USB bootloader minimum timings (ms) for STM32 devices,
Table 144: USB bootloader minimum timings (ms) for STM32 devices, Table 145: I2C
bootloader minimum timings (ms) for STM32 devices
Added:
– Section 32: STM32F413xx/423xx devices bootloader

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Table 147. Document revision history (continued)

Date Revision Changes

Updated:
– Table 1: Applicable products, Table 3: Embedded bootloaders, Table 14:
STM32F05xxx and STM32F030x8 devices bootloader versions, Table 15:
STM32F04xxx configuration in system memory boot mode, Table 16: STM32F04xxx
bootloader versions, Table 18: STM32F070x6 bootloader versions, Table 20:
STM32F070xB bootloader versions, Table 21: STM32F071xx/072xx configuration in
system memory boot mode, Table 22: STM32F071xx/072xx bootloader versions,
Table 23: STM32F09xxx configuration in system memory boot mode, Table 24:
STM32F09xxx bootloader versions, Table 35: STM32F301xx/302x4(6/8)
configuration in system memory boot mode, Table 38: STM32F302xB(C)/303xB(C)
bootloader versions, Table 84: STM32F76xxx/77xxx bootloader V9.x versions,
Table 99: STM32L01xxx/02xxx configuration in system memory boot mode,
13-Mar-2017 30 Table 122: STM32L43xxx/44xxx bootloader versions, Table 141: Bootloader device-
dependent parameters, Table 127: STM32L47xxx/48xxx configuration in system
memory boot mode, Table 142: Bootloader startup timings (ms) for STM32 devices,
Table 143: USART bootloader minimum timings (ms) for STM32 devices, Table 144:
USB bootloader minimum timings (ms) for STM32 devices, Table 145: I2C
bootloader minimum timings (ms) for STM32 devices, Table 146: SPI bootloader
minimum timings (ms) for STM32 devices
– Section 3: Glossary, Section 6.1: Bootloader configuration, Section 14.3.3: USART
bootloader Get-Version command returns 0x20 instead of 0x22, RPN reference in
Section 56: STM32L43xxx/44xxx devices bootloader and in Section 58:
STM32L47xxx/48xxx devices bootloader
Added Section 36: STM32F72xxx/73xxx devices bootloader and Section 59:
STM32L496xx/4A6xx devices bootloader

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Table 147. Document revision history (continued)

Date Revision Changes

Updated:
– Table 1: Applicable products, Table 2: Bootloader activation patterns, Table 3:
Embedded bootloaders, Table 28: STM32F105xx/107xx bootloader versions,
Table 33: STM32F2xxxx configuration in system memory boot mode, Table 37:
STM32F302xB(C)/303xB(C) configuration in system memory boot mode, Table 45:
STM32F358xx configuration in system memory boot mode, Table 47: STM32F373xx
configuration in system memory boot mode, Table 49: STM32F378xx configuration in
system memory boot mode, Table 55: STM32F40xxx/41xxx configuration in system
memory boot mode, Table 57: STM32F401xB(C) configuration in system memory
boot mode, Table 59: STM32F401xD(E) configuration in system memory boot mode,
Table 63: STM32F411xx configuration in system memory boot mode, Table 69:
STM32F42xxx/43xxx configuration in system memory boot mode, Table 73:
STM32F446xx configuration in system memory boot mode, Table 75:
STM32F469xx/479xx configuration in system memory boot mode, Table 77:
STM32F72xxx/73xxx configuration in system memory boot mode, Table 79:
04-Jul-2017 31 STM32F74xxx/75xxx configuration in system memory boot mode, Table 81:
STM32F74xxx/75xxx configuration in system memory boot mode, Table 95:
STM32H74xxx/75xxx configuration in system memory boot mode, Table 113:
STM32L1xxxC configuration in system memory boot mode, Table 115:
STM32L1xxxD configuration in system memory boot mode, Table 117:
STM32L1xxxE configuration in system memory boot mode, Table 123:
STM32L45xxx/46xxx configuration in system memory boot mode, Table 141:
Bootloader device-dependent parameters, Table 142: Bootloader startup timings
(ms) for STM32 devices, Table 143: USART bootloader minimum timings (ms) for
STM32 devices, Table 144: USB bootloader minimum timings (ms) for STM32
devices, Table 145: I2C bootloader minimum timings (ms) for STM32 devices
– Introduction, Section 3: Glossary
– Figure 73: Bootloader V9.x selection for STM32L43xxx/44xxx
Added:
– Section 44: STM32H74xxx/75xxx devices bootloader, Section 57:
STM32L45xxx/46xxx devices bootloader
Updated Table 3: Embedded bootloaders, Table 96: STM32H74xxx/75xxx bootloader
version, Table 129: STM32L496xx/4A6xx configuration in system memory boot mode,
Table 130: STM32L496xx/4A6xx bootloader version, Table 141: Bootloader device-
dependent parameters, Table 142: Bootloader startup timings (ms) for STM32 devices,
16-Feb-2018 32 Table 143: USART bootloader minimum timings (ms) for STM32 devices, Table 144:
USB bootloader minimum timings (ms) for STM32 devices, Table 145: I2C bootloader
minimum timings (ms) for STM32 devices.
Added Section 61: STM32L4Rxxx/4Sxxx devices bootloader
Updated Note: in Section 8.1: Bootloader configuration, Note: in Section 9.1:
07-Aug-2018 33
Bootloader configuration

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Table 147. Document revision history (continued)

Date Revision Changes

Updated Table 1: Applicable products, Table 54: STM32F40xxx/41xxx bootloader V3.x

versions, Table 56: STM32F40xxx/41xxx bootloader V9.x versions, Table 58:
STM32F401xB(C) bootloader versions, Table 60: STM32F401xD(E) bootloader
versions, Table 62: STM32F410xx bootloader V11.x versions, Table 64: STM32F411xx
bootloader versions, Table 66: STM32F412xx bootloader V9.x versions, Table 68:
STM32F413xx/423xx bootloader V9.x versions, Table 70: STM32F42xxx/43xxx
bootloader V7.x versions, Table 72: STM32F42xxx/43xxx bootloader V9.x versions,
Table 74: STM32F446xx bootloader V9.x versions, Table 76: STM32F469xx/479xx
05-Nov-2018 34
bootloader V9.x versions, Table 78: STM32F72xxx/73xxx bootloader V9.x versions,
Table 80: STM32F74xxx/75xxx bootloader V7.x versions, Table 82:
STM32F74xxx/75xxx bootloader V9.x versions, Table 84: STM32F76xxx/77xxx
bootloader V9.x versions, Table 141: Bootloader device-dependent parameters,
Table 142: Bootloader startup timings (ms) for STM32 devices, Table 143: USART
bootloader minimum timings (ms) for STM32 devices, Table 144: USB bootloader
minimum timings (ms) for STM32 devices.
Added Section 55: STM32L412xx/422xx devices bootloader
Updated Table 1: Applicable products, Section 3: Glossary, Table 142: Bootloader
startup timings (ms) for STM32 devices, Table 143: USART bootloader minimum
06-Dec-2018 35 timings (ms) for STM32 devices, Table 145: I2C bootloader minimum timings (ms) for
STM32 devices.
Added Section 40: STM32G07xxx/08xxx device bootloader
Updated Table 1: Applicable products, Section 3: Glossary, Table 3: Embedded
bootloaders, Table 141: Bootloader device-dependent parameters, Table 142:
Bootloader startup timings (ms) for STM32 devices, Table 143: USART bootloader
21-Feb-2019 36 minimum timings (ms) for STM32 devices, Table 144: USB bootloader minimum
timings (ms) for STM32 devices, Table 145: I2C bootloader minimum timings (ms) for
STM32 devices.
Added Section 63: STM32WB50xx/55xx devices bootloader
Updated Table 1: Applicable products, Section 3: Glossary, Table 141: Bootloader
device-dependent parameters, Table 142: Bootloader startup timings (ms) for STM32
devices, Table 143: USART bootloader minimum timings (ms) for STM32 devices,
06-May-2019 37 Table 144: USB bootloader minimum timings (ms) for STM32 devices, Table 145: I2C
bootloader minimum timings (ms) for STM32 devices.
Added Section 41: STM32G431xx/441xx devices bootloader, Section 42:
STM32G47xxx/48xxx devices bootloader

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Table 147. Document revision history (continued)

Date Revision Changes

Updated:
– Table 1: Applicable products, Table 2: Bootloader activation patterns, Table 3:
Embedded bootloaders, Table 67: STM32F413xx/423xx configuration in system
memory boot mode, Table 95: STM32H74xxx/75xxx configuration in system memory
boot mode, Table 96: STM32H74xxx/75xxx bootloader version, Table 101:
STM32L031xx/041xx configuration in system memory boot mode, Table 122:
STM32L43xxx/44xxx bootloader versions, Table 123: STM32L45xxx/46xxx
configuration in system memory boot mode, Table 130: STM32L496xx/4A6xx
bootloader version, Table 138: STM32WB50xx/55xx bootloader versions, Table 141:
08-Jul-2019 38 Bootloader device-dependent parameters, Table 142: Bootloader startup timings
(ms) for STM32 devices, Table 143: USART bootloader minimum timings (ms) for
STM32 devices, Table 144: USB bootloader minimum timings (ms) for STM32
devices, Table 145: I2C bootloader minimum timings (ms) for STM32 devices
– Section 3: Glossary, Section 4.1: Bootloader activation, Section 39.1: Bootloader
configuration, Section 41.1: Bootloader configuration
– Figure 56: Bootloader V9.x selection for STM32H74xxx/75xxx, Figure 84: Dual bank
boot implementation for STM32L4Rxxx/STM32L4Sxxx bootloader V9.x
Added Note: in Section 4.2, Note: in Section 13.3, Note: in Section 44.1, Note: in
Section 46.1, Section 39: STM32G03xxx/ STM32G04xxx devices bootloader
Updated:
– Table 1: Applicable products, Table 2: Bootloader activation patterns, Table 3:
Embedded bootloaders, Table 86: STM32G03xx/04xxx bootloader versions,
Table 120: STM32L412xx/422xx bootloader versions, Table 122:
STM32L43xxx/44xxx bootloader versions, Table 124: STM32L45xxx/46xxx
bootloader versions, Table 126: STM32L47xxx/48xxx bootloader V10.x versions,
Table 128: STM32L47xxx/48xxx bootloader V9.x versions, Table 130:
STM32L496xx/4A6xx bootloader version, Table 132: STM32L4P5xx/4Q5xx
16-Sep-2019 39 bootloader versions, Table 141: Bootloader device-dependent parameters,
Table 142: Bootloader startup timings (ms) for STM32 devices, Table 143: USART
bootloader minimum timings (ms) for STM32 devices, Table 144: USB bootloader
minimum timings (ms) for STM32 devices, Table 145: I2C bootloader minimum
timings (ms) for STM32 devices
– Section 3: Glossary, Section 4.2: Bootloader identification
Added Figure 54: Dual bank boot implementation for STM32G47xxx/48xxx bootloader
V13.x, Section 62: STM32L552xx/STM32L562xx devices bootloader, note in
Section 63.3: Bootloader version
Updated Table 3: Embedded bootloaders, Table 136: STM32L552xx/562xx bootloader
03-Oct-2019 40
versions, Table 138: STM32WB50xx/55xx bootloader versions
Updated:
– Table 78: STM32F72xxx/73xxx bootloader V9.x versions, Table 80:
STM32F74xxx/75xxx bootloader V7.x versions, Table 82: STM32F74xxx/75xxx
bootloader V9.x versions, Table 84: STM32F76xxx/77xxx bootloader V9.x versions,
Table 85: STM32G03xxx/G04xxx configuration in system memory boot mode,
25-Oct-2019 41 Table 96: STM32H74xxx/75xxx bootloader version, Table 132: STM32L4P5xx/4Q5xx
bootloader versions, Table 135: STM32L552xx/562xx configuration in system
memory boot mode, Table 142: Bootloader startup timings (ms) for STM32 devices,
Table 143: USART bootloader minimum timings (ms) for STM32 devices, Table 145:
I2C bootloader minimum timings (ms) for STM32 devices
– Section 16: STM32F2xxxx devices bootloader

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Table 147. Document revision history (continued)

Date Revision Changes

Updated:
– Table 1: Applicable products, Table 2: Bootloader activation patterns, Table 3:
Embedded bootloaders, Table 141: Bootloader device-dependent parameters,
Table 142: Bootloader startup timings (ms) for STM32 devices, Table 143: USART
bootloader minimum timings (ms) for STM32 devices, Table 144: USB bootloader
05-Dec-2019 42 minimum timings (ms) for STM32 devices, Table 145: I2C bootloader minimum
timings (ms) for STM32 devices
– Section 3: Glossary
Added: Section 45: STM32H7A3xx/B3xx devices bootloader, Section 60:
STM32L4P5xx/4Q5xx devices bootloader, Section 64: STM32WLE5xx devices
bootloader
Updated:
– Table 1: Applicable products, Table 2: Bootloader activation patterns, Table 3:
Embedded bootloaders, Table 89: STM32G431xx/441xx configuration in system
memory boot mode, Table 91: STM32G47xxx/48xxx configuration in system memory
boot mode, Table 92: STM32G47xxx/48xxx bootloader version, Table 96:
STM32H74xxx/75xxx bootloader version, Table 98: STM32H7A3xx/7B3xx
bootloader version, Table 132: STM32L4P5xx/4Q5xx bootloader versions, Table 135:
STM32L552xx/562xx configuration in system memory boot mode, Table 136:
STM32L552xx/562xx bootloader versions, Table 137: STM32WB50xx/55xx
configuration in system memory boot mode, Table 141: Bootloader device-dependent
parameters
– Section 3: Glossary, Section 37: STM32F74xxx/75xxx devices bootloader,
Section 39.1: Bootloader configuration, Section 40.1: Bootloader configuration,
Section 41.1: Bootloader configuration, Section 42.1: Bootloader configuration,
Section 44.1: Bootloader configuration
Added:
– Section 4.5: Bootloader UART baudrate detection, Section 4.6: Programming
04-Jun-2020 43
constraints, Section 4.7: ExitSecureMemory feature
– Note: in: Section 26.1.1: Bootloader configuration, Section 26.2.1: Bootloader
configuration, Section 27.1: Bootloader configuration, Section 28.1: Bootloader
configuration, Section 30.1: Bootloader configuration, Section 31.1: Bootloader
configuration, Section 32.1: Bootloader configuration, Section 33.1.1: Bootloader
configuration, Section 33.2.1: Bootloader configurationSection 34.1: Bootloader
configuration, Section 35.1: Bootloader configuration, Section 36.1: Bootloader
configuration, Section 37.1.1: Bootloader configuration, Section 37.2.1: Bootloader
configuration, Section 38.1: Bootloader configuration
– Figure 72: Dual bank boot Implementation for STM32L3x2xx/44xxx bootloader V9.x,
Figure 74: Dual bank boot Implementation for STM32L45xxx/46xxx bootloader V9.x,
Figure 80: Dual bank boot Implementation for STM32L496xx/4A6xx bootloader V9.x
– Appendix A: Example of function to use the “ExitSecureMemory” function
Deleted Figure 48. Access to securable memory area from the bootloader for
STM32G03xxx/G04xxx, Figure 50. Access to securable memory area from the
bootloader for STM32G07xxx/G08xxx, Figure 52. Access to securable memory area,
Figure 54. Access to securable memory area

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Table 147. Document revision history (continued)

Date Revision Changes

Introduced STM32H72xxx/73xxx devices, hence added Section 43:

STM32H72xxx/73xxx devices bootloader and its subsections.
Updated Section 3: Glossary, note in Section 39.1: Bootloader configuration and
Section 63.1: Bootloader configuration.
Updated Table 1: Applicable products, Table 2: Bootloader activation patterns, Table 3:
Embedded bootloaders, Table 8: ExitSecureMemory entry address, Table 91:
STM32G47xxx/48xxx configuration in system memory boot mode, Table 98:
STM32H7A3xx/7B3xx bootloader version, Table 113: STM32L1xxxC configuration in
29-Jul-2020 44 system memory boot mode, Table 115: STM32L1xxxD configuration in system memory
boot mode, Table 117: STM32L1xxxE configuration in system memory boot mode,
Table 135: STM32L552xx/562xx configuration in system memory boot mode,
Table 141: Bootloader device-dependent parameters, Table 142: Bootloader startup
timings (ms) for STM32 devices, Table 143: USART bootloader minimum timings (ms)
for STM32 devices, Table 144: USB bootloader minimum timings (ms) for STM32
devices and Table 145: I2C bootloader minimum timings (ms) for STM32 devices.
Updated Figure 56: Bootloader V9.x selection for STM32H74xxx/75xxx.
Minor text edits across the whole document.

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